WO2019140693A1 - 基于阻变器件交叉阵列结构实现逻辑计算的方法 - Google Patents

基于阻变器件交叉阵列结构实现逻辑计算的方法 Download PDF

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WO2019140693A1
WO2019140693A1 PCT/CN2018/073641 CN2018073641W WO2019140693A1 WO 2019140693 A1 WO2019140693 A1 WO 2019140693A1 CN 2018073641 W CN2018073641 W CN 2018073641W WO 2019140693 A1 WO2019140693 A1 WO 2019140693A1
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resistive
input
resistive unit
unit
output
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PCT/CN2018/073641
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French (fr)
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刘琦
王伟
刘森
张峰
吕杭炳
龙世兵
刘明
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中国科学院微电子研究所
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Priority to US16/959,225 priority Critical patent/US11189345B2/en
Priority to PCT/CN2018/073641 priority patent/WO2019140693A1/zh
Publication of WO2019140693A1 publication Critical patent/WO2019140693A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

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  • the invention belongs to the field of microelectronics, and particularly relates to a computation-storage fusion method based on a cross-array structure of a resistive device.
  • the traditional computing system adopts the von Neumann architecture.
  • the memory and the computing unit are spatially separated, and frequent data exchange between them consumes a large amount of energy and time, and the processing efficiency of the massive information is extremely low. Therefore, the development of new information devices and technologies integrating logic computing and data storage has become a research hotspot in the field of microelectronics.
  • the non-volatile resistive memory has the advantages of small size, low power consumption, and easy large-scale integration. It is expected to break through the bottleneck of von Neumann architecture and realize a new efficient computing system for computing-storage fusion.
  • Embodiments of the present invention provide a method for implementing logic calculation based on a cross-array structure of a resistive device, including the steps of:
  • One of the resistive units is an output resistive unit, and the remaining resistive units are input resistive units;
  • the end of the word line or the bit line shared by the resistive change unit is not applied with voltage, and the non-shared end of the output resistive unit is connected to the high level or the low level, and the non-shared end of the input resistive unit is not shared with the output resistive unit.
  • the opposite level of one end realizes that the information of each input resistive unit is logically operated and stored in the output resistive unit.
  • the input resistive unit includes a first input resistive unit and a second input resistive unit, and initializes an output resistive unit to “1”, a first input resistive unit, and a second
  • the input resistive unit and the output resistive unit share one word line or bit line at one end, and the word line or the bit line is not leveled; the other end of the first input resistive unit and the second input resistive unit are connected Level or low level, the other end of an output resistive unit is connected to a level opposite to the other end of a first input resistive unit and a second input resistive unit, and the current direction of an output resistive unit is guaranteed to be Negative, realize NAND logic, that is, a first input resistive unit stores data as A, and a second input resistive unit stores data as B, then an output resistive unit stores data after implementing NAND logic. for
  • the input resistive unit includes a first input resistive unit and a second input resistive unit, and the data stored by the first input resistive unit and the second input resistive unit are respectively represented as “A” and “B”, the output resistance unit stores the result as “R”, the output resistive unit positive terminal is grounded, the negative terminal voltage is pre-initialized to “0”; the first input resistive unit, the second input resistive unit and The positive or negative terminals of the output resistive unit are connected; when the positive ends of the first input resistive unit, the second input resistive unit and the output resistive unit are connected, the first input resistive unit and the second input resistive unit Negative termination voltage, the negative terminal of the output resistive unit is grounded; or the first input resistive unit, the second input resistive unit and the negative terminal of the output resistive unit are connected, the first input resistive unit and the second input resistance
  • the positive terminal of the variable unit is grounded, and the positive terminal of the output resistive unit is connected to the voltage; the pulse is applied to ensure that the current direction of
  • the data stored by the first input resistive unit and the second input resistive unit connected to the same word line or the same bit line are "A” and "B", connected to the word line or bit
  • the input resistive unit includes a first input resistive unit and a second input resistive unit, and is connected to the first input resistive unit and the second input resistive unit of the same word line or the same bit line.
  • the data is "A” and "B”
  • the data initially stored by the output resistive unit connected to the word line or the bit line is "C”
  • the three resistive units connected to the same bit line or word line have two In either case, the positive terminals are connected together or the negative terminals are connected together. If the positive terminals are connected together, the two ends of the first input resistive unit and the second input resistive unit that are not connected are grounded through a word line or a bit line.
  • the voltage V NAND is applied to the end of the output resistive unit not connected to the first and second input resistive units. If the negative terminals are connected together, the voltage V NAND is connected to the ground in reverse, and the final result is stored in the output.
  • the resistance R is the result of the NAND NAND operation and the C phase is AND, indicating
  • the data stored by the first input resistive unit is “A”, and is connected to the word line or bit.
  • the data stored by the output resistive unit of the line is “C”.
  • the invention provides a method for implementing logic calculation based on a cross-array structure of a resistive device, and 16 kinds of binary Boolean logic operations are realized by combining or reconstructing at least two logical calculation methods.
  • the above method solves the defects that a large number of resistive change units are required based on the logic calculation of the resistive variable device, and the operation steps are complicated and lengthy.
  • the present invention proposes an implementation method of computation-storage integration based on the cross-array structure of the resistive change device.
  • the resistive unit forms a different string structure by designing the position at which the pulse sequence is applied in the cross lattice.
  • FIG. 1 is a schematic diagram of a cross dot matrix memory array according to an embodiment of the present invention.
  • FIGS. 2A and 2B are respectively schematic diagrams of setting and resetting a resistive device according to an embodiment of the present invention.
  • FIG. 3A and FIG. 3B are respectively schematic diagrams showing two operation modes of “or” logic according to an embodiment of the present invention.
  • 4A and 4B are respectively schematic diagrams showing two operation modes of "NAND" logic according to an embodiment of the present invention.
  • FIG. 5A and FIG. 5B are respectively schematic diagrams showing two operation modes of “copy” logic according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an operation of implementing a full adder according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of parallel operation for implementing “copy” according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of operations of implementing a partial parallel full adder according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a combination of eight Boolean operations according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a combination of eight other Boolean operations according to an embodiment of the present invention.
  • the novel computation-storage integration method based on the cross-array structure of the resistive unit includes applying a pulse sequence to the basic unit of the bit line or the word line through the controller, and configuring the basic unit of the resistive device to form different serial-parallel structures, thereby realizing The three basic logical operations of "NAND”, “or”, and “copy” are combined with each other to implement all binary Boolean logic operations.
  • FIG. 1 is a schematic diagram of a cross-lattice memory array.
  • the logic computing operation method of the present invention does not need to change its structure, and does not change the original data reading and writing method, so the reading and setting mode of the basic resistive unit and the periphery thereof are The read and write circuits are not described here.
  • the resistive unit that needs to participate in the calculation of the same word line or bit line and the result storage unit apply corresponding pulses to perform operations, and the operation result is directly stored in the result storage unit. Can be used for the next step of the operation or output.
  • the different types of operations implemented are determined by the manner in which the pulses are applied.
  • All the resistive units in the array can participate in the operation or store the operation results, and the calculation and storage are completed at the same time, saving the data transmission time, and does not need to make any changes to the storage structure and the read/write circuit of the cross lattice, and realizes Computation and storage process and architectural integration.
  • the implemented arithmetic functions cover 16 kinds of Boolean logic, and further combinations can implement complex operations such as addition and multiplication, which will be described in detail below.
  • FIGS. 2A and 2B are respectively schematic diagrams of setting and resetting a resistive device according to an embodiment of the present invention.
  • the high-profile and low-resistance devices of the resistive device correspond to logic “0” and “1” respectively.
  • FIG. 2A the process of setting the device from “0” to “1” is set, and the device is positively terminated.
  • V the negative terminal is grounded, the current flows from the positive terminal to the negative terminal, and the device changes from a high resistance state to a low resistance state;
  • FIG. 2B the process from "1" to "0” is reset, and the positive terminal of the device is grounded.
  • the negative terminal voltage V the current flows from the negative terminal to the positive terminal, and the device changes from a low resistance state to a high resistance state.
  • FIG. 3A and 3B show an implementation of an OR operation of an embodiment of the present invention.
  • the information stored by the first input resistive device, the second input resistive device, and the result storage device are A, B, and R, respectively, and are referred to by A, B, and R for convenience of description.
  • the three resistive cells connected to the same bit line or word line have the two cases shown in the figure, that is, the positive terminals are connected together or the negative terminals are connected together, and the result memory device R is first set to “0”, pulse is applied to ensure that the direction of R current is positive, that is, when the opposite ends of A, B and R are connected (see Figure 3A), the positive terminals of A and B are grounded, and the positive terminal of R is connected with voltage V; A, B and R are positive When the terminals are connected (see Figure 3B), the positive terminals of A and B are grounded, and the positive terminal of R is connected to voltage V.
  • FIGS. 3A and 3B show an implementation of an embodiment of the invention or a logical operation.
  • the information stored by the first input resistive device, the second input resistive device, and the resulting memory device are A, B, and R, respectively, and three resistives connected to the same bit line or word line.
  • the positive terminals are connected together or the negative terminals are connected together, and a pulse is applied to ensure that the R current direction is positive, that is, when the opposite ends of A, B and R are connected, the positive ends of A and B are grounded.
  • R positive terminal voltage V; when A, B and R positive terminals are connected, A and B positive terminals are grounded, R positive terminal is connected to voltage V, and A, B and R OR logic can be obtained in the resistive unit R
  • FIGS. 4A and 4B show an implementation method of a NAND logic operation in an embodiment of the present invention.
  • the information stored in the first input resistive device, the second input resistive device, and the result storage device are A, B, and R, respectively, and the three resistive units connected to the same bit line or word line have the two types shown in the figure.
  • the result storage device R is first set to "1", and a pulse is applied to ensure that the R current direction is negative, that is, when the opposite ends of A, B and R are connected, A and B positive terminal voltage V, R positive terminal grounding (see Figure 4A); when A, B and R positive terminals are connected, A and B positive terminal voltage V, R positive terminal ground, can be in the resistive unit R
  • the result of the NAND logical operation of A and B see Figure 4B
  • FIG. 4A and 4B show an implementation method of a NAND logic operation in an embodiment of the present invention.
  • the information stored in the first input resistive device, the second input resistive device, and the result storage device are A, B, and R, respectively, and three resistive units connected to the same bit line or word line exist.
  • the positive terminals are connected together or the negative terminals are connected together, and a pulse is applied to ensure that the R current direction is negative, that is, when the opposite ends of A, B and R are connected, the positive voltages of A and B are terminated.
  • R positive terminal is grounded; when A, B and R positive terminals are connected, A and B are positively connected to voltage V, and R positive terminal is grounded, so that A and B can be obtained in the resistive unit R, and NAND and R
  • the result of the logical operation with "R" is expressed as
  • FIG. 5A and 5B show an implementation of the "copy" logic operation of the embodiment of the present invention.
  • the information stored by the first input resistive device and the result storage device are A and R, respectively, and the two resistive units connected to the same bit line or word line have two cases as shown in the figure, that is, The positive terminals are connected together or the negative terminals are connected together.
  • 5A and 5B show an implementation of an OR operation derived from an embodiment of the present invention.
  • the information stored by the first input resistive device and the result storage device are A and R, respectively, and the two resistive units connected to the same bit line or word line have two cases as shown in the figure, that is, The positive terminals are connected together or the negative terminals are connected together, and a pulse is applied to ensure that the R current direction is positive, that is, when the A and R terminals are connected, the A positive terminal is grounded, and the R positive terminal is connected to the voltage V; as shown in FIG.
  • the full addition operation is a one-bit operation in the full adder, which takes into account the carry compared to the half-add operation.
  • the input includes Ai, Bi and the carry Ci-1 of the previous bit, and the output includes the home bit and Si and the generated carry Ci.
  • a total of six resistive units on the same word line or bit line are required to implement full logic, and two addends Ai and Bi and a previous carry Ci-1 are respectively stored in three of them.
  • the other three resistive units are used to store the results of the intermediate process and the final calculation results.
  • Ai and Bi are ORed, and the result is that Ai+Bi is stored in the resistive unit 1; in the second step, Ai, Bi, and Ai+Bi are subjected to multiple input logic operations.
  • the result is Stored in the resistive unit 1 to overwrite the original stored data; the third step will be Do NAND logic with Ci-1, the result Stored in the resistive unit 2; the fourth step will be Do "or" logical operation with Ci-1, the result Saved in the resistive unit 3; the fifth step, will Ci-1 and Do more input logic operations, the result is The result is stored in the resistive change unit 3; in the sixth step, Ai and Bi perform a NAND operation, and the result Stored in the resistive unit 2; the seventh step, versus A NAND operation is performed, and as a result, Ci is stored at the position of the original Ci-1.
  • a logic calculation implementation method based on a cross-lattice memory structure of a resistive-change device is proposed.
  • the calculation and storage are based on the same hardware architecture, and the data storage is completed while calculating, and the computational storage fusion is realized.
  • the calculation result of each step is stored in the output unit, and is used as the input unit of the next calculation in the cascade, which avoids the transmission and invocation of data, and effectively reduces the number of the resistive devices and the operation steps required to implement the calculation function.
  • the logic operation method set forth in the present invention can be simultaneously executed to implement parallel calculation.
  • the information stored by the first input resistive device and the first result storage device are A and R, respectively, and the information stored by the second input resistive device and the second result storage device are respectively
  • A' and R' first set the result memory devices R and R' to "0"
  • the various logic operations designed above and the complex logic functions implemented based on basic logic calculations can be performed in parallel in this way.
  • Combining the parallel operation implemented by the present invention with a one-bit full adder can implement a partial parallel multi-bit full adder.
  • a total of two sets of six resistive units on the same word line or bit line are required to implement two-bit all-addition logic.
  • Two addends Ai and Bi and one high one are two by copy logic.
  • the addendum Ai+1 and Bi+1 are aligned, Ci-1 is the carry of the previous bit, and the other resistive unit is used to store the result of the intermediate process and the final calculation result.
  • the result is Stored in the resistive unit 1-1, covering the original storage data, the same Also obtained at the same time, saved in 2-1; the third step, connect the word line or bit line connected to Ai+1 and Bi+1 to 1/2VNAND, and then Do NAND logic with Ci-1, the result Stored in the resistive change unit 1-3; in the fourth step, the word line or bit line connected to Ai+1 and Bi+1 is connected to 1/2VOR, and then Do "or" logical operation with Ci-1, the result Stored in the resistive unit 1-4; in the fifth step, Ai and Bi, Ai+1 and Bi+1 perform a NAND operation, and the result is Stored in the resistive unit 1-5, the result Stored in the resistive change unit 2-5; in the sixth step, the word line or bit line connected to Ai+1 and Bi+1 is connected to 1/2VNAND, versus The NAND operation is performed, and the result is that Ci is stored in the original Ci-1 position; in the seventh step, Ci is moved to the a
  • the multi-bit full adder can be simplified in this way, and the n-bit full adder needs 3+4n steps to complete the operation.
  • FIG. 9 is a schematic diagram of a combination of eight Boolean operations according to an embodiment of the present invention
  • FIG. 10 is a schematic diagram of a combination of eight other Boolean operations according to an embodiment of the present invention.
  • any of 16 Boolean logic calculations can be realized in up to three steps.
  • the above embodiment realizes the integration of logic calculation and data storage, solves the defect that a large number of resistive units are required in the logic calculation of the resistive variable device, and the operation steps are complicated and tedious.
  • the present invention proposes a calculation based on the cross array structure of the resistive variable device. -
  • the implementation method of storage integration by designing the position where the pulse sequence is applied in the cross lattice, the resistive unit forms different serial and parallel structures, realizes three basic logical operations of NAND, OR, and copy, and combines them on the basis of , implement 16 basic Boolean logics, effectively reducing the number of resistive units and operating steps required for logic operations.

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Abstract

一种基于阻变器件交叉阵列结构的逻辑计算与数据存储一体化的操作方法，该方法的计算和存储功能基于相同的硬件架构，且在计算的同时完成数据的存储，实现了计算存储融合。所述方法包括通过控制器向指定字线或位线施加脉冲序列，配置阻变器件基本单元形成不同的串并结构，实现与非、或、复制3种基本逻辑运算并在此基础上相互组合，实现16种二值布尔逻辑和全加运算，并在此基础上提出了并行逻辑和全加器的实现方法。

Description

基于阻变器件交叉阵列结构实现逻辑计算的方法 技术领域
本发明属于微电子技术领域，具体涉及一种基于阻变器件交叉阵列结构的计算-存储融合方法。
背景技术
传统计算系统采用冯诺依曼架构，存储器与计算单元在空间上分离，它们之间的频繁数据交换，消耗大量的能量和时间，对于海量信息的处理效率极低。因此，发展逻辑计算和数据存储一体化的新型信息器件及技术成为微电子领域的研究热点。非易失性阻变存储器具有体积小，功耗低，易于大规模集成的优点，有望突破冯诺依曼架构瓶颈，实现计算-存储融合的新型高效计算系统。
目前，基于阻变器件的逻辑操作在实现复杂逻辑时需要庞大数量的计算单元，而且操作步骤复杂冗长，不符合实际运用的需求。
发明内容
有鉴于此，本发明的目的在于提供一种基于阻变器件交叉阵列结构实现逻辑计算的方法，以解决以上所述的至少部分技术问题。
(二)技术方案
本发明实施例提供一种基于阻变器件交叉阵列结构实现逻辑计算的方法，其中包括步骤：
选择共用一条字线或位线的两个或三个阻变单元；
其中一个阻变单元，为输出阻变单元，其余的阻变单元为输入阻变单元；
阻变单元共用的字线或位线的一端不加电压，输出阻变单元非共用的一端接高电平或低电平，输入阻变单元非共用的一端接与输出阻变单元非共用的一端相反的电平，实现各输入阻变单元的信息经逻辑运算后到存入输出阻变单元。
在进一步的方案中，输入阻变单元包括一第一输入阻变单元和一第二输入阻变单元，初始化将一输出阻变单元置“1”，一第一输入阻变单元，一第二输入阻变单元和一输出阻变单元有一端共用一条字线或位线，字线或位线不加电平；一第一输入阻变单元和一第二输入阻变单元的另一端接高电平或低电平，一输出阻变单元的另一端接与一第一输入阻变单元和一第二输入阻变单元的另一端相反的电平，并保证一输出阻变单元电流方向为负，实现“与非”逻辑，即一第一输入阻变单元存储数据为A、一第二输入阻变单元存储数据为B，则一输出阻变单元在实现“与非”逻辑后存储数据为
Figure PCTCN2018073641-appb-000001
在进一步的方案中，输入阻变单元包括一第一输入阻变单元，初始化将一输出阻变单元置“0”，一第一输入阻变单元和一输出阻变单元有一端共用一条字线或位线，字线或位线不加电平；一第一输入阻变单元的另一端接高电平或低电平，一输出阻变单元的另一端接与一第一输入阻变单元的另一端相反的电平，并保证一输出阻变单元电流方向为正，实现“复制”逻辑，即一第一输入阻变单元存储数据为A，则一输出阻变单元在实现“复制”逻辑后存储数据为R＝A。
在进一步的方案中，输入阻变单元包括一第一输入阻变单元和一第二输入阻变单元，第一输入阻变单元和第二输入阻变单元存储的数据分别表示为“A”和“B”，输出阻变单元存储结果表示为“R”，输出阻变单元正端接地，负端接电压，预先初始化为“0”；第一输入阻变单元、第二输入阻变单元和输出阻变单元的正端或负端相连；第一输入阻变单元、第二输入阻变单元和输出阻变单元的正端相连时，第一输入阻变单元和第二输入阻变单元的负端接电压，输出阻变单元的负端接地；或第一输入阻变单元、第二输入阻变单元和输出阻变单元的负端相连时，第一输入阻变单元和第二输入阻变单元的正端接地，输出阻变单元的正 端接电压；施加脉冲，保证输出阻变单元电流方向为正，实现“或”运算，结果存储在输出阻变单元中，运算的结果表示为R＝A+B。
在进一步的方案中，其中连接到同一字线或者同一位线的第一输入阻变单元和第二输入阻变单元存储的数据为“A”和“B”，连接到所述字线或者位线的输出阻变单元初始存储的数据为“C”，所连接到同一位线或者字线的三个阻变单元存在两种情况，即正端连接在一起或负端连接在一起，如果正端连在一起，通过字线或者位线向第一输入阻变单元和第二输入阻变单元不互连的那两端施加电压V OR，同时将与第一、第二输入阻变单元不相连的输出阻变单元的那端接地，如果负端连在一起，接电压V OR和接地的方式相反，最终结果存储在输出阻变单元中，其阻值R为A、B和C“或”运算的结果，表示为R＝A+B+C。
在进一步的方案中，输入阻变单元包括第一输入阻变单元和第二输入阻变单元，连接到同一字线或者同一位线的第一输入阻变单元和第二输入阻变单元存储的数据为“A”和“B”，连接到所述字线或者位线的输出阻变单元初始存储的数据为“C”，所连接到同一位线或者字线的三个阻变单元存在两种情况，即正端连接在一起或负端连接在一起，如果正端连在一起，通过字线或者位线将第一输入阻变单元和第二输入阻变单元不相连的那两端接地，同时将与第一、第二输入阻变单元不相连的输出阻变单元的那端施加电压V NAND，如果负端连在一起，接电压V NAND和接地的方式相反，最终结果存储在输出阻变单元中，其阻值R为A和B“与非”运算的结果再和C相“与”，表示
Figure PCTCN2018073641-appb-000002
在进一步的方案中，其中第一输入阻变单元和输出阻变单元连接到同一字线或者同一位线，第一输入阻变单元存储的数据为“A”，连接到所述字线或者位线的输出阻变单元初始存储的数据为“C”，所连接到同一位线或者字线的两个阻变单元存在两种情况，即正端连接在一起或负端连接在一起，如果正端连在一起，通过字线或者位线向第一输入阻变单元不互连的那端施加电压V COPY，同时将与第一输入阻变单元不互连的输出阻变单元的那端接地，如果负端连在一起，接电压V COPY和接地的方式相反，最终结果存储在输出阻变单元中，其阻值R为A和 C“或”运算的结果，表示为R＝A+C。
本发明提供一种基于阻变器件交叉阵列结构实现逻辑计算的方法，通过以上至少两种以上逻辑计算方法的组合或重构，实现16种二值布尔逻辑运算。
(三)有益效果
通过上述方法，解决现有基于阻变器件逻辑计算时需要大量阻变单元，操作步骤复杂冗长的缺陷，本发明提出了一种基于阻变器件交叉阵列结构的计算-存储一体化的实现方法，通过设计脉冲序列在交叉点阵中施加的位置，阻变单元形成不同的串并结构。
附图说明
图1为本发明实施例交叉点阵存储阵列示意图。
图2A和图2B分别为本发明实施例阻变器件置位和复位示意图。
图3A和图3B分别为本发明实施例“或”逻辑的两种运算方式示意图。
图4A和图4B分别为本发明实施例“与非”逻辑的两种运算方式示意图。
图5A和图5B分别为本发明实施例“复制”逻辑的两种运算方式示意图。
图6为本发明实施例实现一位全加器的运算示意图。
图7为本发明实施例实现“复制”的并行运算示意图。
图8为本发明实施例实现部分并行全加器的运算示意图。
图9为本发明实施例实现8种布尔运算的组合示意图；
图10为本发明实施例实现另8种布尔运算的组合示意图。
具体实施方式
在下文中，将提供一些实施例以详细说明本公开的实施方案。本公 开的优点以及功效将通过本公开下述内容而更为显著。在此说明所附附图简化过且做为例示用。附图中所示的组件数量、形状及尺寸可依据实际情况而进行修改，且组件的配置可能更为复杂。本公开中也可进行其他方面的实践或应用，且不偏离本公开所定义的精神及范畴的条件下，可进行各种变化以及调整。
所述基于阻变单元的交叉阵列结构的新型计算-存储一体化的方法包括通过控制器向位线或者字线的基本单元施加脉冲序列，配置阻变器件基本单元形成不同的串并结构，实现“与非”、“或”、“复制”3种基本逻辑运算并在此基础上相互组合，能实现全部的二值布尔逻辑运算。
图1为交叉点阵存储阵列示意图，本发明的逻辑计算操作方法不用对其结构进行改变，不改变原有的数据读写方法，所以对基本阻变单元的读取和置位方式及外围的读写电路不做赘述。
根据本发明的实施例，依据不同逻辑计算的需要，将处于同一字线或位线的需要参与计算的阻变单元与结果存储单元施加相应的脉冲进行运算，运算结果直接存储在结果存储单元中，可用于下步的运算或输出。实现的不同的类型的运算，是由施加脉冲的方式决定的，通过施加不同方式的脉冲形成阻变单元不同的串并结构，完成相应的逻辑计算功能。阵列中所有的阻变单元都可以参与运算或存储运算结果，计算和存储是同时完成的，节省了数据传输时间，且不需要对交叉点阵的存储结构和读写电路做任何改变，实现了计算与存储过程上和架构上的融合。实现的运算功能涵盖16种布尔逻辑，进一步组合可实现加法、乘法等复杂运算，这将在下面相详细描述。
图2A和图2B分别为本发明实施例阻变器件置位和复位示意图。阻变器件处于高组态和低阻态分别对应了逻辑“0”和“1”，如图2A所示，器件由“0”变为“1”的过程为置位，器件正端接电压V，负端接地，电流从正端流向负端，器件由高阻态变为低阻态；如图2B所示，器件由“1”变为“0”的过程为复位，器件正端接地，负端接电压V，电流从负端流向正端，器件由低阻态变为高阻态。
“或”逻辑操作
图3A和图3B给出了本发明实施例“或”逻辑运算的实现方法。如图3A和图3B所示，第一输入阻变器件、第二输入阻变器件和结果存储器件存储的信息分别为A、B和R，为了方便表述，后面用A、B和R指代这三种器件，所连接到同一位线或者字线的三个阻变单元存在图中所示两种情况，即正端连接在一起或负端连接在一起，首先将结果存储器件R置为“0”，施加脉冲，保证R电流方向为正，即A、B和R反端相连时(参见图3A)，A和B正端接地，R正端接电压V；A、B和R正端相连时(参见图3B)，A和B正端接地，R正端接电压V，即可在阻变单元R中得到A和B“或”逻辑运算的结果，表示为R＝A+B。
多输入逻辑操作R’＝A+B+R
图3A和图3B给出了本发明实施例或逻辑运算的实现方法。如图3A和3B所示，第一输入阻变器件、第二输入阻变器件和结果存储器件存储的信息分别为A、B和R，所连接到同一位线或者字线的三个阻变单元存在图中所示两种情况，即正端连接在一起或负端连接在一起，施加脉冲，保证R电流方向为正，即A、B和R反端相连时，A和B正端接地，R正端接电压V；A、B和R正端相连时，A和B正端接地，R正端接电压V，即可在阻变单元R中得到A、B和R“或”逻辑运算的结果R’，表示为R’＝A+B+R，阻变单元R中存储的初始信息被覆盖。
“与非”逻辑操作
图4A和图4B给出了本发明实施例“与非”逻辑运算的实现方法。第一输入阻变器件、第二输入阻变器件和结果存储器件存储的信息分别为A、B和R，所连接到同一位线或者字线的三个阻变单元存在图中所示两种情况，即正端连接在一起或负端连接在一起，首先将结果存储器件R置为“1”，施加脉冲，保证R电流方向为负，即A、B和R反端相连时，A和B正端接电压V，R正端接地(参见图4A所示)；A、B和R正端相连时，A和B正端接电压V，R正端接地，即可在阻变单元R中得到A和B“与非”逻辑运算的结果(参见图4B所示)，表示
Figure PCTCN2018073641-appb-000003
多输入逻辑操作为
Figure PCTCN2018073641-appb-000004
图4A和图4B给出了本发明实施例“与非”逻辑运算的实现方法。如 图4所示，第一输入阻变器件、第二输入阻变器件和结果存储器件存储的信息分别为A、B和R，所连接到同一位线或者字线的三个阻变单元存在图中所示两种情况，即正端连接在一起或负端连接在一起，施加脉冲，保证R电流方向为负，即A、B和R反端相连时，A和B正端接电压V，R正端接地；A、B和R正端相连时，A和B正端接电压V，R正端接地，即可在阻变单元R中得到A和B“与非”再和R“与”的逻辑运算的结果R’，表示为
Figure PCTCN2018073641-appb-000005
“复制”逻辑操作
图5A和图5B给出了本发明实施例“复制”逻辑运算的实现方法。如图5A所示，第一输入阻变器件和结果存储器件存储的信息分别为A和R，所连接到同一位线或者字线的两个阻变单元存在图中所示两种情况，即正端连接在一起或负端连接在一起，首先将结果存储器件R置为“0”，施加脉冲，保证R电流方向为正，即A、和R反端相连时，A正端接地，R正端接电压V；A和R正端相连时，A正端接地，R正端接电压V，即可在阻变单元R中得到A的“复制”逻辑运算的结果，表示为R＝A。
衍生的“或”逻辑操作
图5A和5B给出了本发明实施例衍生的“或”逻辑运算的实现方法。如图5A所示，第一输入阻变器件和结果存储器件存储的信息分别为A和R，所连接到同一位线或者字线的两个阻变单元存在图中所示两种情况，即正端连接在一起或负端连接在一起，施加脉冲，保证R电流方向为正，即A、和R反端相连时，A正端接地，R正端接电压V；图5B所示，A和R正端相连时，A正端接地，R正端接电压V，即可在阻变单元R中得到A和R的“或”逻辑运算的结果，表示为R’＝A+R,其中R’为运算完之后阻变单元R中存储的信息，R的初始值将被覆盖。
“全加”运算
全加运算为全加器中的一位运算，相较于半加运算它将进位考虑在内。输入包括Ai、Bi和前一位的进位Ci-1，输出包括本位和Si和产生的进位Ci。通过将上述基本逻辑运算和衍生逻辑运算合理组合，实现全加功能，只需6个阻变单元，7步操作即可。全加器逻辑表达式如下：
Figure PCTCN2018073641-appb-000006
Figure PCTCN2018073641-appb-000007
Figure PCTCN2018073641-appb-000008
如图6所示，实现全加逻辑一共需要6个处在同一字线或位线上的阻变单元，两个加数Ai和Bi以及上一位的进位Ci-1分别存储在其中3个阻变单元中，另外3个阻变单元用来存储中间过程的结果和最终的计算结果。
全加运算时，首先Ai和Bi进行“或”运算，结果为Ai+Bi保存在阻变单元1中；第二步，将Ai、Bi和Ai+Bi进行多输入逻辑操作
Figure PCTCN2018073641-appb-000009
(Ai+Bi)，结果为
Figure PCTCN2018073641-appb-000010
保存在阻变单元1中，将原存储数据覆盖；第三步，将
Figure PCTCN2018073641-appb-000011
和Ci-1做“与非”逻辑运算，结果
Figure PCTCN2018073641-appb-000012
保存在阻变单元2中；第四步，将
Figure PCTCN2018073641-appb-000013
和Ci-1做“或”逻辑运算，结果
Figure PCTCN2018073641-appb-000014
Figure PCTCN2018073641-appb-000015
保存在阻变单元3中；第五步，将
Figure PCTCN2018073641-appb-000016
Ci-1和
Figure PCTCN2018073641-appb-000017
做多输入逻辑运算，结果为
Figure PCTCN2018073641-appb-000018
结果保存在阻变单元3中；第六步，Ai和Bi进行“与非”运算，结果
Figure PCTCN2018073641-appb-000019
保存在阻变单元2中；第七步，
Figure PCTCN2018073641-appb-000020
与
Figure PCTCN2018073641-appb-000021
进行“与非”运算，结果为Ci保存在原Ci-1的位置。
根据本公开的实施例，提出了一种基于阻变器件交叉点阵存储结构的逻辑计算实现方法，计算和存储基于相同的硬件架构，且在计算的同时完成数据的存储，实现了计算存储融合，每步的计算结果存储在输出单元中，在级联中作为下一个计算的输入单元，避免了数据的传输和调用，有效的减少了实现计算功能所需的阻变器件数量和操作步骤。
并行运算
本发明所阐述的逻辑运算方法可以同时执行，实现并行计算。以复制逻辑的并行计算为例，如图7，第一输入阻变器件和第一结果存储器件存储的信息分别为A和R，第二输入阻变器件和第二结果存储器件存储的信息分别为A’和R’，首先将结果存储器件R和R’置为“0”，施加脉冲，保证R’电流方向为正，即A和A’负端接电压V，R和R’负端接地，即可在阻变单元R中得到A的“复制”逻辑运算的结果，表示为 R＝A，同时，在阻变单元R’中得到A’的“复制”逻辑运算的结果，表示为R’＝A’。以上所设计的各种逻辑运算及基于基本逻辑计算所实现的复杂逻辑功能都可以运用这种方式并行完成。
部分并行多位全加器
将本发明实现的并行运算与一位全加器相结合可以实现部分并行多位全加器。如图8所示，实现两位全加逻辑一共需要两组6个处在同一字线或位线上的阻变单元，通过复制逻辑将两个加数Ai和Bi以及高一位的两个加数Ai+1和Bi+1对齐，Ci-1为上一位的进位，另外的阻变单元用来存储中间过程的结果和最终的计算结果。
全加运算时，首先Ai和Bi进行“或”运算，将Ai和Bi正端接地，负端接VOR，结果为Ai+Bi保存在阻变单元1-1中，根据电路分析结果，在此激励下Ai+1和Bi+1也进行了进行“或”运算，结果Ai+1+Bi+1保存在阻变单元2-1中；第二步，将Ai、Bi和Ai+Bi进行多输入逻辑操作
Figure PCTCN2018073641-appb-000022
Figure PCTCN2018073641-appb-000023
(Ai+Bi)，结果为
Figure PCTCN2018073641-appb-000024
保存在阻变单元1-1中，将原存储数据覆盖，同样的
Figure PCTCN2018073641-appb-000025
也同时得到，保存在2-1中；第三步，将Ai+1和Bi+1所连接的字线或位线接1/2VNAND，再将
Figure PCTCN2018073641-appb-000026
和Ci-1做“与非”逻辑运算，结果
Figure PCTCN2018073641-appb-000027
保存在阻变单元1-3中；第四步，将Ai+1和Bi+1所连接的字线或位线接1/2VOR，再将
Figure PCTCN2018073641-appb-000028
和Ci-1做“或”逻辑运算，结果
Figure PCTCN2018073641-appb-000029
保存在阻变单元1-4中；第五步，Ai和Bi，Ai+1和Bi+1进行“与非”运算，结果
Figure PCTCN2018073641-appb-000030
保存在阻变单元1-5中，结果
Figure PCTCN2018073641-appb-000031
保存在阻变单元2-5中；第六步，将Ai+1和Bi+1所连接的字线或位线接1/2VNAND，
Figure PCTCN2018073641-appb-000032
与
Figure PCTCN2018073641-appb-000033
进行“与非”运算，结果为Ci保存在原Ci-1的位置；第七步，将Ci通过复制逻辑移到2-1处；第八步，将Ai和Bi所连接的字线或位线接1/2VNAND，再将
Figure PCTCN2018073641-appb-000034
Figure PCTCN2018073641-appb-000035
和Ci做“与非”逻辑运算，结果
Figure PCTCN2018073641-appb-000036
保存在阻变单元2-3中；第九步，将Ai和Bi所连接的字线或位线接1/2VOR，再将
Figure PCTCN2018073641-appb-000037
Figure PCTCN2018073641-appb-000038
和Ci做“或”逻辑运算，结果
Figure PCTCN2018073641-appb-000039
保存在阻变单元2-4中；第十步，将Ai和Bi所连接的字线或位线接1/2VNAND，
Figure PCTCN2018073641-appb-000040
Figure PCTCN2018073641-appb-000041
与
Figure PCTCN2018073641-appb-000042
进行“与非”运算，结果为Ci+1保存在原Ci的位置； 第十一步，将
Figure PCTCN2018073641-appb-000043
Ci-1和
Figure PCTCN2018073641-appb-000044
Ci和
Figure PCTCN2018073641-appb-000045
Figure PCTCN2018073641-appb-000046
做多输入逻辑运算，结果分别为Si和Si+1，结果保存在阻变单元1-4和2-4中.
多位全加器均可按照这种方法进行步骤简化，n位全加器需要3+4n步能运算完毕。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
图9为本发明实施例实现8种布尔运算的组合示意图；图10为本发明实施例实现另8种布尔运算的组合示意图。如图9和图10所示，通过对上述实施例中的逻辑运算方法进行组合，最多三步就可以实现16种布尔逻辑计算的任意一种。
以上实施例实现逻辑计算和数据存储一体化，解决现有基于阻变器件逻辑计算时需要大量阻变单元，操作步骤复杂冗长的缺陷，本发明提出了一种基于阻变器件交叉阵列结构的计算-存储一体化的实现方法，通过设计脉冲序列在交叉点阵中施加的位置，阻变单元形成不同的串并结构，实现与非、或、复制3种基本逻辑运算并在此基础上相互组合，实现16种基本布尔逻辑，有效的减少了逻辑运算所需的阻变单元数量和操作步骤。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种基于阻变器件交叉阵列结构实现逻辑计算的方法，其中，包括
    步骤：
    选择共用一条字线或位线的两个或三个阻变单元；
    其中一个阻变单元为输出阻变单元，其余的阻变单元为输入阻变单元；
    阻变单元共用的字线或位线的一端不加电压，输出阻变单元非共用的一端接高电平或低电平，输入阻变单元非共用的一端接与输出阻变单元非共用的一端相反的电平，实现各输入阻变单元的信息在逻辑运算地同时存入到输出阻变单元。
  2. 根据权利要求1所述的一种基于阻变器件交叉阵列结构实现逻辑计算的方法，其中，输入阻变单元包括一第一输入阻变单元和一第二输入阻变单元，初始化将输出阻变单元置“1”，一第一输入阻变单元，一第二输入阻变单元和一输出阻变单元有一端共用一条字线或位线，这条字线或位线不加电平；一第一输入阻变单元和一第二输入阻变单元的另一端接高电平或低电平，一输出阻变单元的另一端接与一第一输入阻变单元和一第二输入阻变单元的另一端相反的电平，并保证一输出阻变单元电流方向为负，实现“与非”逻辑，即一第一输入阻变单元存储数据为A、一第二输入阻变单元存储数据为B，则一输出阻变单元在实现“与非”逻辑后存储数据为
    Figure PCTCN2018073641-appb-100001
  3. 根据权利要求1所述的基于阻变器件交叉阵列结构实现逻辑计算的方法，其中，包括：输入阻变单元包括一第一输入阻变单元时，初始化将一输出阻变单元置“0”，一第一输入阻变单元和一输出阻变单元有一端共用一条字线或位线，字线或位线不加电平；一第一输入阻变单元的另一端接高电平或低电平，一输出阻变单元的另一端接与一第一输入阻变单元的另一端相反的电平，并保证一输出阻变单元电流方向为正，实现“复制”逻辑，即一第一输入阻变单元存储数据为A，则一输出阻变单元在实现“复制”逻辑后存储数据为R＝A。
  4. 根据权利要求1所述的基于阻变器件交叉阵列结构实现逻辑计算的方法，其中，输入阻变单元包括一第一输入阻变单元和一第二输入阻变单元，第一输入阻变单元和第二输入阻变单元存储的数据分别表示为“A”和“B”，输出阻变单元存储结果表示为“R”，输出阻变单元正端接地，负端接电压，预先初始化为“0”；第一输入阻变单元、第二输入阻变单元和输出阻变单元的正端或负端相连；第一输入阻变单元、第二输入阻变单元和输出阻变单元的正端相连时，第一输入阻变单元和第二输入阻变单元的负端接电压，输出阻变单元的负端接地；或第一输入阻变单元、第二输入阻变单元和输出阻变单元的负端相连时，第一输入阻变单元和第二输入阻变单元的正端接地，输出阻变单元的正端接电压；施加脉冲，保证输出阻变单元电流方向为正，实现“或”运算，结果存储在输出阻变单元中，运算的结果表示为R＝A+B。
  5. 根据权利要求1所述的基于阻变器件交叉阵列结构实现逻辑计算的方法，其中连接到同一字线或者同一位线的第一输入阻变单元和第二输入阻变单元存储的数据为“A”和“B”，连接到所述字线或者位线的输出阻变单元初始存储的数据为“C”，所连接到同一位线或者字线的三个阻变单元存在两种情况，即正端连接在一起或负端连接在一起，如果正端连在一起，通过字线或者位线向第一输入阻变单元和第二输入阻变单元不互连的那两端施加电压V OR，同时将与第一、第二输入阻变单元不相连的输出阻变单元的那端接地，如果负端连在一起，接电压V OR和接地的方式相反，最终结果存储在输出阻变单元中，其阻值R为A、B和C“或”运算的结果，表示为R＝A+B+C。
  6. 根据权利要求1所述的基于阻变器件交叉阵列结构实现逻辑计算的方法，其中，输入阻变单元包括第一输入阻变单元和第二输入阻变单元，连接到同一字线或者同一位线的第一输入阻变单元和第二输入阻变单元存储的数据为“A”和“B”，连接到所述字线或者位线的输出阻变单元初始存储的数据为“C”，所连接到同一位线或者字线的三个阻变单元存在两种情况，即正端连接在一起或负端连接在一起，如果正端连在一起，通过字线或者位线将第一输入阻变单元和第二输入阻变单元不相连 的那两端接地，同时将与第一、第二输入阻变单元不相连的输出阻变单元的那端施加电压V NAND，如果负端连在一起，接电压V NAND和接地的方式相反，最终结果存储在输出阻变单元中，其阻值R为A和B“与非”运算的结果再和C相“与”，表示
    Figure PCTCN2018073641-appb-100002
  7. 根据权利要求1所述的基于阻变器件交叉阵列结构实现逻辑计算的方法，其中第一输入阻变单元和输出阻变单元连接到同一字线或者同一位线，第一输入阻变单元存储的数据为“A”，连接到所述字线或者位线的输出阻变单元初始存储的数据为“C”，所连接到同一位线或者字线的两个阻变单元存在两种情况，即正端连接在一起或负端连接在一起，如果正端连在一起，通过字线或者位线向第一输入阻变单元不互连的那端施加电压V COPY，同时将与第一输入阻变单元不互连的输出阻变单元的那端接地，如果负端连在一起，接电压V COPY和接地的方式相反，最终结果存储在输出阻变单元中，其阻值R为A和C“或”运算的结果，表示为R＝A+C。
  8. 一种基于阻变器件交叉阵列结构实现逻辑计算的方法，为根据权利要求2-7项中任意两种以上逻辑计算方法的组合或重构，实现逻辑与、逻辑等值、以及或非中任一种逻辑运算。
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