Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
  • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
  • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/02—General constructional details
  • G01R1/06—Measuring leads; Measuring probes
  • G01R1/067—Measuring probes
  • G01R1/06766—Input circuits therefor
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/26—Testing of individual semiconductor devices
  • G01R31/2607—Circuits therefor
  • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
  • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
  • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
  • H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
  • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
  • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
  • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
  • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/16—Modifications for eliminating interference voltages or currents
  • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches

Definitions

• This relates generally to power switches, and more particularly to adaptive voltage clamps and related methods.
• MOSFET metal oxide semiconductor field-effect transistor
• SOA safe operating area
• An example apparatus includes: a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage; and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to- source voltage to a second voltage different from the first voltage based on a fault signal.
• FIG. 1 is a schematic illustration of an example power switching system including an example adaptive drain-to-source voltage (VDS) clamp to implement the examples described herein.
• VDS adaptive drain-to-source voltage
• FIG. 2 is an example graph depicting example operations of the V DS clamp of FIG. 1.
• FIG. 3 is a schematic illustration of an example implementation of the adaptive V DS clamp of FIG. 1.
• FIG. 4 is a schematic illustration of an alternative example implementation of the adaptive VDS clamp of FIG. 1.
• FIG. 5 depicts an example graph corresponding to a safe operating area of the power switching system of FIG. 1.
• FIG. 6 depicts an example graph corresponding to a thermal instability limit of the power switching system of FIG. 1.
• FIG. 7 depicts electrical parameters of the power switching system of FIG. 1 when an example transistor is experiencing a fault condition.
• FIG. 8 depicts electrical parameters of the power switching system of FIG. 1 when the example transistor of FIG. 7 is experiencing a non-fault regular load condition.
• FIG. 9 depicts an example timing diagram corresponding to an operation of the example power switching system of FIG. 1.
• FIG. 10 is a flowchart representative of machine readable instructions which may be executed to implement an example controller to control the example adaptive VDS clamp of FIG. 1.
• FIG. 11 is a schematic illustration of an example system implementation including the example adaptive VDS clamp of FIG. 1 to implement the examples described herein.
• FIG. 12 depicts an example timing diagram corresponding to an operation of the example system of FIG. 11.
• FIG. 13 is a block diagram of an example processing platform structured to execute the instructions of FIG. 10 to implement the example controller.
• Power MOSFETs are commonly used power devices because of their fast-switching speed, low gate drive power, and superior paralleling capability.
• I D s drain-source current
• V DS drain-source voltage
• a power MOSFET included in an integrated circuit (IC) package operates safely when limited to a maximum current flowing between the source and drain (e.g., loss) and/or a maximum BV DSS
• a load dump can occur when a load to which a power source is delivering power to is abruptly disconnected.
• a load to which a power source is delivering power to is abruptly disconnected.
• other loads connected to the vehicle alternator see a surge in supply voltage (e.g., 60 V, 80 V, 100 V, etc.) and/or a substantially high transient current (e.g., 80 amps (A), 90 A, 100 A, etc.).
• a device such as a light bulb (e.g., in cold weather) becomes problematic because of its high in-rush current.
• a 65-Watt (W) bulb can require approximately 80 Amps (A) to turn on within a specified time period.
• A Amps
• a drain-to-source clamp must not clamp supply voltage due to the high voltage and relatively long duration during which the high voltage persists.
• the power accumulation on the power MOSFET can exceed the SOA due to the high V D s and the corresponding I DS during the time duration.
• an in-rush current of a light indicator e.g., a headlight light bulb
• a current limit of the high-side switch must be set at a fixed level higher than the light indicator in-rush current to energize and turn on the light indicator within a desired tum-on time specification limit.
• an adaptive voltage clamp controller dynamically controls a clamp voltage (Vc) (e.g., a clamp voltage level, a clamp voltage threshold, etc.) for a drain-source voltage (VDS) of one or more MOSFETs based on an operating condition of the one or more MOSFETs.
• Vc clamp voltage
• VDS drain-source voltage
• the adaptive voltage clamp controller maintains a substantially high (e.g., 40V, 45V, 50V, etc.) clamp voltage during a non-fault condition, or a non-fault regular load condition.
• the adaptive voltage clamp controller reduces the clamp voltage from a normal operation state to a folded state (e.g., 25V, 30V, 35V, etc.) when the one or more MOSFETs are experiencing a fault condition.
• a MOSFET providing power to a device electrically coupled to the power switching system may experience a fault condition and quickly turn off during a thermal shutdown and/or when the MOSFET exceeds a current limit (e.g., activating short-circuit protection measures).
• a current limit e.g., activating short-circuit protection measures.
• FIG. 1 is a schematic illustration of an example power switching system 100 including an example voltage clamp 102, or an example adaptive drain-source voltage (VDS) clamp 102, to dynamically control a VDS clamp level, or a clamp voltage, based on an operating condition of an example transistor 124 providing power to an example device 104.
• the adaptive VDS clamp 102 is an improvement over prior fixed VDS clamps and example implementations of the adaptive VDS clamp 102 are described below.
• the power switching system 100 includes an example controller die 106 to determine when to provide power (e.g., a current, a voltage, etc.) from an example power source 108 to the device 104 via an example power switching die 110.
• the controller die 106 is an integrated circuit (IC) chip including one or more electrical circuits.
• the controller die 106 may be implemented using hardware logic, machine readable instructions, hardware implemented state machines, etc., and/or any combination thereof.
• the device 104 is a light indicator (e.g., a halogen bulb, a light-emitting diode, a xenon bulb, etc.) of a vehicle (e.g., an aircraft, an automobile, a marine vehicle, etc.).
• a vehicle e.g., an aircraft, an automobile, a marine vehicle, etc.
• the device 104 can be a headlight of an automobile corresponding to vehicle exterior lighting.
• the device 104 may be any other device requiring power from a switchable power source.
• the device 104 of FIG. 1 is electrically coupled to the power switching die 110 at an output node 112 to receive an output voltage (VOUT) 113.
• VOUT output voltage
• the power switching die 110 is coupled to the output node 112 via a first example inductor (Ll) 114 and a first example resistor (Rl) 116.
• first inductor 114 and the first resistor 116 are depicted as separate elements, they are not physical elements, but a representation of an equivalent inductance and resistance of the coupling between the device 104 and the power switching die 110 (e.g., wiring inductance and resistance).
• the power switching die 110 is electrically coupled to the power source 108 via a second example inductor (L2) 118 and a second example resistor (R2) 120 at a power input node 122.
• the power switching die 110 includes the example transistor 124 to alternately provide an example supply voltage (V B B) (e.g., a source voltage) 126 to the device 104 based on an example gate voltage 128 of the transistor 124.
• V B B example supply voltage
• the power source 108 is a vehicle battery.
• the power source 108 may be any other supply of electrical power.
• the transistor 124 is a first transistor 124.
• the first transistor 124 of FIG. 1 is an N-channel MOSFET.
• the first transistor 124 can be a power transistor.
• the power switching die 110 may be implemented utilizing more than one transistor 124.
• the power switching die 110 may be implemented utilizing one or more P-channel MOSFETs.
• the controller die 106 includes the V D s clamp 102, an example controller 130, an example gate driver 132, and a third example resistor (R3) 134.
• a first example threshold voltage (VTHI) 135 builds up across the third resistor 134 to turn on the first transistor 124.
• the gate driver 132 includes an example gate-pull up driver 136 and an example gate-pull down driver 138.
• each of the gate-pull up driver 136 and the gate-pull down driver 138 can correspond to one or more resistors.
• gate-pull up driver 136, the gate-pull down driver 138, and/or, the gate driver 132 may be implemented using hardware logic, machine readable instructions, hardware implemented state machines, etc., and/or any combination thereof.
• the gate-pull up driver 136 pulls the gate voltage 128 up to an example pull-up voltage (VCP) 140.
• the gate-pull down driver 138 pulls the gate voltage 128 down to the supply voltage 126.
• the controller die 106 may include more than one of the VDS clamp 102, the controller 130, and/or the gate driver 132.
• the controller 130 is an IC chip including one or more electrical circuits.
• the controller 130 may be implemented using hardware logic, machine readable instructions, hardware implemented state machines, etc., and/or any combination thereof.
• the controller 130 of FIG. 1 obtains an example enable signal (EN PAD) 142 from a first example input node 144 at a second example input node 146, or a controller die input node 146.
• EN PAD example enable signal
• a high value of the enable signal 142 triggers the controller 130 to initialize the power switching system 100.
• a low value of the enable signal 142 triggers the controller 130 to idle, pause, and/or otherwise suspend an operation of the power switching system 100.
• the first input node 144 is electrically coupled to the second input node 146 on an example circuit interface 148.
• the second input node 146 can be electrically coupled to one or more electrical circuits, controllers, and/or hardware disposed on the circuit interface 148.
• the circuit interface 148 is a silicon substrate.
• the circuit interface 148 may be a gallium arsenide substrate or any other type of semiconductor substrate.
• the circuit interface 148 is depicted as a separation between different circuit or electrical interfaces.
• the output node 112, the power input node 122, and the first input node 144 are not directly coupled to each other.
• the output node 112, the power input node 122, and the first input node 144 are not electrically shorted to each other.
• the circuit interface 148 is a multi-chip module (MCM) package including the controller die 106 and/or the power switching die 110.
• MCM multi-chip module
• the controller 130 generates a first example control signal (VDS_Clamp_Fold) 150 and a second example control signal (EN_GATE) 152 based on a condition of the first transistor 124.
• the controller 130 can obtain information associated with an operating condition of the first transistor 124 (e.g., an example fault signal 302 described in connection with FIGS. 3-4).
• the controller 130 can generate a first value of the first control signal 150 and a second value of the second control signal 152 when the first transistor 124 is in the non-fault regular load condition.
• the first value of the first control signal 150 can control the V D s clamp 102 to clamp an example VDS 154 of the first transistor 124 to a first voltage (e.g., a first threshold, a first voltage clamp level, a first voltage threshold, etc.) to prevent the VDS clamp 102 from prematurely clamping the supply voltage 126.
• the second value of the second control signal 152 can control the gate driver 132 to activate and/or otherwise enable the gate-pull up driver 136 and deactivate and/or otherwise disable the gate-pull down driver 138 to switch on the first transistor 124.
• the controller 130 generates a third value of the first control signal 150 and a fourth value of the second control signal 152 when the first transistor 124 is in the fault condition.
• the third value of the first control signal 150 can control the V D s clamp 102 to clamp the VDS 154 to a second voltage (e.g., a second threshold, a second voltage clamp level, a second voltage threshold, etc.) to enable the VDS clamp 102 to clamp VOUT 113 when the VDS 154 of the first transistor 124 extends to and/or otherwise operates at an unsafe operating level.
• the fourth value of the second control signal 152 can control the gate driver 132 to disable the gate-pull up driver 136 and activate the gate-pull down driver 138 to switch off the first transistor 124.
• FIG. 1 While an example manner of implementing the controller die 106 and the power switching die 110 is illustrated in FIG. 1, one or more of the elements, processes, and/or devices illustrated in FIG. lmay be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example VDS clamp 102, the example controller 130, the example gate driver 132, and/or, more generally, the example controller die 106 of FIG. 1 and/or the example transistor 124, and/or, more generally the example power switching die 110 of FIG. 1 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware.
• any of the example VDS clamp 102, the example controller 130, the example gate driver 132, and/or, more generally, the example controller die 106 and/or the first transistor 124, and/or, more generally, the example power switching die 110 could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)).
• At least one of the example, VDS clamp 102, the example transistor 124, the example controller 130, and/or the example gate driver 132 is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including the software and/or firmware.
• the example controller die 106 and/or the power switching die 110 may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated in FIG. 1, and/or may include more than one of any or all of the illustrated elements, processes, and devices.
• the phrase“in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
• FIG. 2 is an example graph 200 depicting example operations of the VDS clamp 102 of FIG. 1.
• the graph 200 depicts the supply voltage (VBB) 126 and the VDS 154 with respect to time.
• the supply voltage 126 is depicted using a solid line and the VDS 154 is depicted using a solid line with cross-hatches.
• the graph 200 illustrates the Vc of the VDS clamp 102 being adjusted from a first example threshold 202, or a first example clamp voltage 202, to a second example threshold 204, or a second example clamp voltage 204, based on a condition of the first transistor 124.
• the supply voltage 126 and the BVDSS are approximately 24 V during a non-fault regular load operation of the first transistor 124.
• the Vc of the VDS clamp 102 is at the first threshold 202.
• the first threshold 202 is 44 V.
• the first threshold 202 may be any other voltage.
• the VDS 154 is experiencing a voltage surge (e.g., a load dump).
• the controller 130 of FIG. 1 does not adjust the VDS clamp 102 to the second threshold because the first transistor 124 is not experiencing a fault condition.
• the supply voltage 126 would be clamped to 40 V and hamper the operation of the first transistor 124.
• the VDS clamp 102 does not clamp the VDS 154 as the Vc is at the first threshold 202 of 44 V and, thus, the VDS 154 correlates to the supply voltage 126 from the second time 208 until a third time (T 3 ) 210 when the VDS surge subsides.
• the VDS 154 surges to approximately 49 V at a fourth time (T 4 ) 212.
• the first transistor 124 is not experiencing a fault condition so the controller 130 does not generate the first control signal 150 to adjust the Vc of the VDS clamp 102.
• the VDS clamp 102 clamps the VDS 154 from 49 V to the first threshold of 44 V.
• the first transistor 124 experiences a fault condition at a sixth time (T 6 ) 216.
• the controller 130 determines the fault condition, the controller 130 generates the first control signal 150 to adjust the VDS clamp 102 from the first threshold 202 to the second threshold 204.
• the VDS clamp 102 clamps the VDS 154 of approximately 60 V to the second threshold 204 of 33 V.
• the controller 130 generates the first control signal 150 for a period of time defined by a VDS folding timer.
• the VDS folding timer represents a quantity of time for the output current to the device 104 to dissipate to approximately 0 A.
• the controller 130 generates the first control signal 150 to adjust the Vc of the VDS clamp 102 from the second threshold 204 back to the first threshold 202 after the VDS folding timer expires.
• the VDS folding timer can expire at a seventh time (T 7 ) 218 or any time before an eighth time (T 8 ) 220.
• the supply voltage 126 surges to approximately 40 V at the eighth time 220.
• the first transistor 124 is not experiencing a fault condition.
• the VDS clamp 102 does not clamp the VDS 154 as the Vc of the VDS clamp 102 returned to the first threshold 202 when the VDS folding timer expired.
• FIG. 3 is a schematic illustration of an example implementation of the VDS clamp 102 of FIG. 1.
• the VDS clamp l02a of FIG. 3 corresponds to the VDS clamp 102 of FIG. 1.
• the controller 130 of FIG. 1 controls the Vc of the VDS clamp l02a based on the example fault signal 302 (IN_FAULT) generated by an example fault condition detector 304.
• the fault condition detector 304 is a current limit circuit and/or a thermal protection circuit.
• a current limit circuit can detect whether an output current is higher than a current threshold.
• a thermal protection circuit can detect whether a temperature of a die (e.g., the power switching die 110 of FIG. 1) is higher than a temperature threshold.
• the current limit circuit and/or the thermal protection circuit is integrated with and/or otherwise included in the controller die 106 of FIG. 1. In other examples, the current limit circuit and/or the thermal protection circuit is not included in the controller die 106.
• the fault condition detector 304 generates a high value for the fault signal 302 when a fault condition is detected for the first transistor 124. For example, the fault condition detector 304 can generate the high value for the fault signal 302 when the first transistor 124 exceeds a current limit and/or experiences a thermal shutdown.
• the controller 130 generates the first control signal 150 based on the fault signal 302.
• the controller 130 generates the first control signal 150 to have a low value, or a first voltage (e.g., a digital 0, a logic value of 0, a signal of approximately 0 V, etc.), when the fault signal 302 does not indicate a fault condition associated with the first transistor 124.
• the controller 130 generates the first control signal 150 to have a high value, or a second voltage (e.g., a digital 1, a logic value of 1, a signal of approximately 5 V, etc.), when the fault signal 302 indicates a fault condition associated with the first transistor 124.
• the VDS clamp l02a includes an example inverter 306 coupled to the controller 130 to receive and invert the first control signal 150.
• the inverter 306 can invert the first voltage to the second voltage or invert the second voltage to the first voltage.
• the inverter 306 is coupled to a gate terminal of a second example transistor (MP1) 308.
• MP1 308 of FIG. 3 is coupled to a third example transistor (MP2) 310 in a back-to-back diode configuration.
• a drain of MP1 308 is coupled to a drain of MP2 310
• a body diode of MP1 308 is coupled to the drain of MP2 310
• the body diode of MP1 308 is coupled to a body diode of MP2 310
• MP2 310 is always turned off as MP2 310 provides a blocking diode for MP1 308.
• MP1 308 is turned on, a current will flow through an example body diode 309 of MP2 310.
• MP1 308 and MP2 310 provide a foldback of the VDS clamp l02a by reducing the VDS clamp voltage level by shorting a first example node 332 and a second example node 334 as described in further detail below.
• MP1 308 and MP2 310 are P-channel MOSFETs.
• MP1 308 and MP2 310 are substantially similar to each other (e.g., MP1 308 and MP2 310 are the same type, have the same electrical and/or mechanical parameters, structures, etc., within a tolerance).
• MP1 308 and MP2 310 may be different from each other.
• a fourth example transistor (MN1) 312 is coupled to the supply voltage 126, MP1 308, and a series-connected diode stack 314.
• MN1 312 is an N-channel MOSFET.
• the VDS clamp l02a may be implemented utilizing a P-channel MOSFET in place of MN1 312.
• a gate of MN1 312 is coupled to the supply voltage 126 and, thus, is always turned off.
• MN1 312 provides a blocking diode (e.g., the body diode of MN1 (VD,MNI)) for normal turn on in which the gate voltage 128 of the first transistor 124 goes above the supply voltage 126.
• the series-connected diode stack 314 includes a first example diode (Dl) 316, a second example diode (D2) 318, a third example diode (D3) 320, and a fourth example diode (D4) 322.
• the diode stack 314 includes two or more diodes.
• a fourth example resistor (R4) 324 is coupled between the first example diode 316 and the second example diode 318.
• the first, third, and fourth diodes 316, 318, 322 each have a break-down voltage of approximately 9.8 V.
• the first, third, and fourth diodes 316, 318, 322 may have different break-down voltages and/or may have different break-down voltages from each other.
• the second diode 318 of FIG. 3 is a Zener diode that has a break-down voltage of approximately 5.9 V.
• the second diode 318 may have a different break-down voltage.
• a current flows from the supply voltage 126 through VD,MNI of the MN1 312, the diode stack 314, and a fifth example resistor (R5) 326.
• the current is high enough to turn on a fifth example transistor (MN2) 328 by inducing a gate voltage of MN2 328 to be greater than a second example threshold voltage (V TH 2) 330 across the fifth resistor 326.
• MN2 328 turns on, MN1 312 and MN2 328 form a current path to facilitate a current to flow from the supply voltage 126 to the gate of the first transistor 124 of FIG. 1.
• the current builds up the first threshold voltage 135 across the third resistor 134 of FIG. 1 that turns on the first transistor 124 of FIG. 1.
• the VDS 154 of the first transistor 124 is clamped to the first voltage threshold 202 of FIG. 2 during a non-fault regular load condition (e.g., the fault signal 302 is a low value, the fault signal 302 indicates no fault condition, etc.).
• a non-fault regular load condition e.g., the fault signal 302 is a low value, the fault signal 302 indicates no fault condition, etc.
• the Vc of the YDS clamp l02a when the first transistor 124 is in a non-fault regular load condition can be approximated as described below in Equation (1):
• V D MN1 refers to the forward-bias body diode voltage of MN1 312 and V D1 .
• V D3 , and V DA refer to the reverse breakdown voltages of the first diode 316, the second diode 318, the third diode 320, and the fourth diode 322, respectively.
• V TH1 refers to the first threshold voltage 135
• V TH2 refers to the second threshold voltage 330
• R4 refers to the resistance of the fourth resistor 324
• RS refers to the resistance of the fifth resistor 326.
• the example of Equation (1) can be evaluated to approximately 44 V.
• the controller 130 when the first transistor 124 is in a fault condition, the controller 130 generates the second voltage for the first control signal 150 and the inverter 306 inverts the second voltage to the first voltage.
• the first voltage turns on MP1 308 by pulling a gate of MP1 308 low.
• MP1 308 When MP1 308 is enabled, a first example node 332 coupled to the supply voltage 126 is shunted to a second example node 334.
• the second node 334 is coupled to MP2 310, a cathode of the second diode 318, and the fourth resistor 324.
• MP1 308 and MP2 310 provide a current path from the supply voltage 126 to the cathode of the second diode 318 at the second node 334.
• the current path to the second diode 318 generates an early -break down of the VDS clamp l02a compared to when the first transistor 124 is in the non-fault regular load condition.
• Equation (2) the Vc of the VDS clamp l02a during a fault condition can be approximated as described below in Equation (2):
• V D MP2 refers to the forward-bias body diode voltage of MP2 310.
• the example of Equation (2) can be evaluated to approximately 33 V.
• FIG. 4 is a schematic illustration of an alternative example implementation of the adaptive V D s clamp 102 of FIG. 1 including a two-level clamp control structure 400.
• the VDS clamp l02b of FIG. 4 corresponds to the VDS clamp 102 of FIG. 1.
• the VDS clamp l02b includes the inverter 306 of FIG. 3, or a first inverter 306, MP1 308, and MP2 310 of FIG. 3.
• the VDS clamp l02b of FIG. 4 includes a second inverter 402 coupled to the controller 130 and a sixth example transistor (MP11) 404.
• MP11 404 is coupled to a seventh example transistor (MP22) 406.
• MP11 404 is coupled to a seventh example transistor (MP22) 406.
• MP11 404 is coupled to the supply voltage 126 via the first node 332.
• MP22 406 of FIG. 4 is coupled to the cathode of the second diode 318 and the fourth resistor 324 at a third example node 408.
• MP22 406 is always turned off as MP22 406 provides a blocking diode for MP11 404. For example, when MP11 404 is turned on, a current will flow through an example body diode 405 of MP22 406.
• MP11 404 and MP22 406 are P-channel MOSFETs. Alternatively, the VDS clamp l02b may be implemented utilizing N-channel MOSFETs in place of MP11 404 and MP22 406.
• MP11 404 and MP22 406 are substantially similar to each other (e.g., MP11 404 and MP22 406 are the same type, have the same electrical and/or mechanical parameters, structures, etc., within a tolerance). Alternatively, MP11 404 and MP22 406 may be different from each other.
• MP11 404 and MP22 406 are substantially similar to MP1 308 and MP2 310. Alternatively, MP11 404 and MP22 406 may be different from MP1 308 and MP2 310.
• the controller 130 of FIG. 1 can adjust Vc of the VDS clamp l02b to different clamp voltages based on at least one of the second control signal 152, the fault signal 302, a first example clamp control signal (VDS CLAMP FOLDl) 410, or a second example clamp control signal (VDS CLAMP FOLD2) 412.
• the first clamp control signal 410 can correspond to the first control signal 150 of FIG. 1.
• the controller 130 adjusts Vc of the VDS clamp l02b to a first clamp voltage, or a first threshold, by generating low values for and/or otherwise disabling the first and second clamp control signals 410, 412 during a non-fault regular load operation of the first transistor 124.
• the controller 130 can determine the non-fault regular load condition of the first transistor 124 based on the fault signal 302. For example, the controller 130 can generate low values for the first and second clamp control signals 410, 412 during the non-fault regular load operation based on a low value for the fault signal 302.
• the first inverter 306 obtains and inverts the low value of the first clamp control signal 410 to a high value that turns off MP1 308.
• the second inverter 402 obtains and inverts the low value of the second clamp control signal 412 to a high value that turns off MP11 404.
• the Vc of the VDS clamp l02b during the non-fault regular load operation can be evaluated as approximately 44 V as described above in Equation (1).
• the controller 130 adjusts Vc of the VDS clamp l02b to a second clamp voltage, or a second threshold, by generating a high value and/or otherwise enabling the first clamp control signal 410 and disabling the second clamp control signal 412 during a first fault condition of the first transistor 124.
• the first fault condition of the first transistor 124 may correspond to a full thermal shutdown and/or a full utilization of the current limiter monitoring the first transistor 124.
• the controller 130 can determine the first fault condition of the first transistor 124 based on the fault signal 302. For example, the controller 130 can generate a high value for the first clamp control signal 410 and a low value for the second clamp control signal 412 during the first fault condition.
• the first inverter 306 obtains and inverts the high value of the first clamp control signal 410 to a low value that turns on the MP1 308.
• the second inverter 402 obtains and inverts the low value of the second clamp control signal 412 to a high value that turns off MP11 404.
• Vc of the VDS clamp l02b during the first fault condition can be evaluated as approximately 27 V as described below in Equation (3):
• Vc VD,MP2 + ⁇ D3 + 4 + V TH1 + V TH2
• a current path can be formed through MP1 308 and the body diode 309 of MP2 310 by shunting the first node 332 and the second node 334.
• the controller 130 adjusts Vc of the VDS clamp l02b to a third clamp voltage, or a third threshold, by disabling the first clamp control signal 410 and enabling the second clamp control signal 412 during a second fault condition of the first transistor 124.
• the second fault condition of the first transistor 124 may correspond to a partial thermal shutdown and/or a partial utilization of the current limiter monitoring the first transistor 124.
• the controller 130 can determine the second fault condition of the first transistor 124 based on the fault signal 302. For example, the controller 130 can generate a low value for the first clamp control signal 410 and a high value for the second clamp control signal 412 during the second fault condition.
• the first inverter 306 obtains and inverts the low value of the first clamp control signal 410 to a high value that turns off MP1 308.
• the second inverter 402 obtains and inverts the high value of the second clamp control signal 412 to a low value that turns on MP11 404.
• Vc V D,MP22 + V D2 + V D3 + V D4 + V TH1 + V TH2
• a current path can be formed through MP11 404 and the body diode 405 of MP22 406 by shunting the first node 334 and the third node 408.
• Equation (4) may be used by turning on MP1 308 and turning on MP11 404 by generating high values for the first and second clamp control signals 410, 412 causing Vc of the V DS clamp l02b to become approximately 27 V.
• FIG. 5 depicts an example graph 500 corresponding to an example safe operating area (SOA) 502 of the first transistor 124 of FIG. 1.
• SOA 502 corresponds to voltage and current conditions over which the first transistor 124 of FIG. 1 can be expected to operate without self-damage.
• the graph 500 depicts an example thermal instability region 504 corresponding to voltage and current conditions over which the first transistor 124 may be damaged due to operation at such conditions.
• the first transistor 124 is operating on a first example thermal instability line 506 for an example time window.
• the first thermal instability line 506 is determined based on a quantity of power that can be dissipated for a given time window as described in connection with FIG. 6.
• FIG. 6 depicts an example thermal instability limit graph 600 as a function of VDS and drain current ID of the first transistor 124 of FIG. 1. As depicted in FIG. 6, the first transistor 124 can operate at higher VDS and ID limits with shorter pulse widths of the first transistor 124 being enabled.
• the first transistor 124 can operate at a higher VDS and ID limit when the pulse width of the first transistor 124 is 100 microseconds (us) compared to a pulse width of 100 milliseconds (ms). For example, the first transistor 124 can operate at higher limits for the shorter pulse width due to a shorter period of time because less energy will be accumulated on the first transistor 124.
• the controller 130 of FIG. 1 can enable the first transistor 124 of FIG. 1 to operate with a higher reliability margin and/or push a higher I D s (e.g., operate a higher I D s current limit) during a peak power dissipation time window.
• the controller 130 can direct the VDS clamp 102 of FIG. 1 to adjust to the first voltage threshold 202 of FIG. 2.
• the controller 130 may direct the VDS clamp 102 to adjust to the second voltage threshold 204 of FIG. 2.
• the controller 130 can enable the first transistor 124 to operate at a higher current limit by staying on the same thermal instability limit line 506 (e.g., by moving from position 1 to position 2 on the graph 500).
• the first transistor 124 can operate based on a first current limit (e.g., a first current limit of the I DS ) at a SOA margin when the Vc is the first voltage.
• the controller 130 can direct and/or otherwise enable the first transistor 124 to operate based on a second current limit (e.g., a second current limit of the I DS ) at the same SOA margin when the Vc is the second voltage, where the second current limit is higher than the first current limit.
• a second current limit e.g., a second current limit of the I DS
• the controller 130 can enable the first transistor 124 to operate at the same current limit but at a higher SOA margin by moving from the first thermal instability line 506 to a second example thermal instability line 508 (e.g., by moving from position 1 to position 2 on the graph 500).
• the first transistor 124 can operate based on a current limit (e.g., a current limit of the I DS ) at a first SOA margin when the Vc is the first voltage.
• the controller 130 can direct and/or otherwise enable the first transistor 124 to operate based on the same current limit at a second SOA margin when the Vc is the second voltage, where the second SOA margin is higher than the first SOA margin.
• FIG. 7 depicts electrical parameters of the first transistor 124 of FIG. 1 when the first transistor 124 of FIG. 1 is experiencing a fault condition.
• a first example curve 700 depicts V D s of the first transistor 124 of FIG. 1 as a function of time.
• a second example curve 702 depicts IDS of the first transistor 124 as a function of time.
• the first transistor 124 is turned off causing VDS to correspond to the supply voltage 126 of FIG. 1 (e.g., approximately 14 V from a vehicle alternator, a vehicle battery, etc.).
• the first transistor 124 is turned on causing VDS to approach approximately 0 V and causing I D s to increase.
• the first transistor 124 is turned off causing an impedance of the first transistor 124 to increase, the IDS to decrease, and the VDS to increase to the second voltage threshold 204 of FIG. 2.
• the VDS remains at the second voltage threshold 204 for a fold time t 710 until the IDS reaches approximately 0 A.
• a third example curve 712 depicts power dissipation of the first transistor 124 as a function of time. At the third time 708, the power dissipation reaches approximately 5.4 kilowatts (kW) and decreases to approximately 0 kW during the fold time 710.
• FIG. 8 depicts electrical parameters of the first transistor 124 of FIG. 1 when the first transistor 124 of FIG. 1 is experiencing a non-fault regular load condition.
• a first example curve 800 depicts VDS of the first transistor 124 of FIG. 1 as a function of time.
• a second example curve 802 depicts loss of the first transistor 124 as a function of time.
• the first transistor 124 is turned off causing V D s to correspond to the supply voltage 126 of FIG. 1 (e.g., approximately 14 V from a vehicle alternator, a vehicle battery, etc.).
• the first transistor 124 is turned on causing V D s to approach approximately 0 V and causing I D s to increase.
• the first transistor 124 is turned off causing an impedance of the first transistor 124 to increase, the IDS to decrease, and the VDS to increase to the first voltage threshold 202 of FIG. 2.
• the VDS remains at the first voltage threshold 202 for a fold time t 810 until the IDS reaches approximately 0 A.
• a third example curve 812 depicts power dissipation of the first transistor 124 as a function of time. At the third time 808, the power dissipation reaches approximately 7.0 kilowatts (kW) and decreases to approximately 0 kW during the fold time 810.
• FIG. 9 depicts an example timing diagram 900 corresponding to an operation of the VDS clamp 102 of FIG. 1.
• the controller 130 determines that the first transistor 124 of FIG. 1 is in a non-fault regular load condition based on receiving a low value for the fault signal 302 from the fault condition detector 304 of FIG. 3.
• the controller 130 In response to determining the non-fault regular load condition, the controller 130 generates a low value for the first control signal 150 to adjust the Vc of the VDS clamp 102 of FIG. 1 to the first voltage threshold 202 of FIG. 2 (e.g., 44 V).
• the controller 130 of FIG. 1 generates high values for the enable signal 142 and the second control signal 152 to turn on the first transistor 124 of FIG. 1.
• the controller 130 receives a high value for the fault signal 302.
• the controller 130 can determine that the first transistor 124 is in a fault condition (e.g., the first fault condition, the second fault condition, etc.).
• the controller 130 In response to determining the fault condition of the first transistor 124, the controller 130 generates a low value for the second control signal 152 to turn off the first transistor 124 and generates a high value for the first control signal 150 to adjust the Vc of the VDS clamp 102 to the second voltage threshold 204 of FIG. 2. For example, the controller 130 can turn on MP1 308 of FIG. 3 and shunt the first node 332 to the second node 334 to adjust the Vc of the V DS clamp 102 from 44 V to 33 V.
• the controller 130 adjusts the Vc of the VDS clamp 102 to the second voltage threshold 204 until a fourth time (T 4 ) 908 for a fold time r 912 defined by a VDS folding timer 910.
• the controller 130 outputs a high value for the first control signal 150 until the fold time 912 expires.
• the Vc of the VDS clamp 102 is adjusted from the first voltage threshold 202 to the second voltage threshold 204 until the fourth time 908 at which the Vc is adjusted back to the first voltage threshold 202.
• the fold time 912 can correspond to the fold time 710 of FIG. 7 or the fold time 810 of FIG. 8.
• the fold time 912 is defined by the controller 130 to ensure that the IDS of the first transistor 124 approaches approximately 0 A as described above in connection with FIGS. 7 and/or 8 before re-adjusting the Vc of the VDS clamp 102 to the first voltage threshold 202.
• the fold time 912 is the same for each instance of the first transistor 124 experiencing a fault condition.
• the controller 130 may adjust the fold time 912 to different time values between fault conditions of the first transistor 124.
• the controller 130 resumes normal operation of the first transistor 124 by generating a high value for the second control signal 152 to turn on the first transistor 124.
• the controller 130 determines that the first transistor 124 is experiencing a fault condition based on receiving a high value for the fault signal 302.
• the controller 130 outputs a low value for the second control signal 152 to turn off the first transistor 124 and outputs a high value for the first control signal 150 to adjust the Vc of the VDS clamp 102 from the first voltage threshold 202 to the second voltage threshold 204 spanning the fold time 912.
• the controller 130 In response to the fold time 912 expiring, the controller 130 generates a low value for the first control signal 150 to return the Vc to the first voltage threshold 202, but the first transistor 124 is still experiencing a fault condition. Therefore, the first transistor 124 does not resume normal operation until the fault signal 302 is lowered.
• FIG. 10 A flowchart representative of example hardware logic, machine readable instructions, hardware implemented state machines, and/or any combination thereof for implementing the controller 130 of FIGS. 1, 3, and/or 4 is shown in FIG. 10.
• the machine readable instructions may be an executable program or portion of an executable program for execution by a computer processor such as the processor 1312 shown in the example processor platform 1300 described below in connection with FIG. 13.
• the program may be embodied in software stored on a non-transitory computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a DVD, a Blu-ray disk, or a memory associated with the processor 1312, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 1312 and/or embodied in firmware or dedicated hardware.
• a non-transitory computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a DVD, a Blu-ray disk, or a memory associated with the processor 1312
• the entire program and/or parts thereof could alternatively be executed by a device other than the processor 1312 and/or embodied in firmware or dedicated hardware.
• the example program is described with reference to the flowchart illustrated in FIG. 10, many other methods of implementing the example controller 130 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed,
• any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware.
• hardware circuits e.g., discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.
• the example process of FIG.10 may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium such as a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random-access memory, and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information).
• a non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.
• the term“and/or” when used in a form such as A, B and/or C refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C.
• FIG. 10 is a flowchart representative of example machine readable instructions 1000 that may be executed to implement the controller 130 of FIGS. 1, 3, and/or 4 to control the VDS clamps 102, l02a, l02b of FIGS. 1, 3, and/or 4.
• the machine readable instructions 1000 begin at block 1002 when the controller 130 receives an enable signal.
• the controller 130 can receive the enable signal 142 of FIG. 1 to initialize the power switching system 100 of FIG. 1.
• the controller 130 In response to receiving the enable signal, the controller 130 generates a high signal for a gate driver at block 1004. For example, the controller 130 can generate a high value for the second control signal 152 of FIG. 1 to enable the gate-pull up driver 136 of FIG. 1 to switch on the first transistor 124. [0079] At block 1006, the controller 130 identifies a fault condition. For example, the controller 130 can determine that the first transistor 124 of FIG. 1 is experiencing a fault condition based on the fault signal 302 obtained from the fault condition detector 304 of FIG. 3.
• the controller 130 generates a low signal for the gate driver and a high signal for a voltage clamp.
• the controller 130 can generate a low value for the second control signal 152 to disable the gate-pull up driver 136 and to enable the gate-pull down driver 138 of FIG. 1 to switch off the first transistor 124.
• the controller 130 may generate a high value for the first control signal 150 to turn on MP1 308 to fold the Vc of the V DS clamp 102 from the first voltage threshold 202 (e.g., 44 V) to the second voltage threshold 204 (e.g., 33 V).
• the controller 130 determines whether a VDS folding timer has expired. For example, the controller 130 can determine whether the VDS folding timer 910 of FIG. 9 has expired. If, at block 1010, the controller 130 determines that the VDS folding timer has not expired, the controller 130 re-determines whether the VDS folding timer has expired at block 1010. If, at block 1010, the controller 130 determines that the VDS folding timer has expired, then, at block 1012, the controller generates a low signal for the voltage clamp. For example, the controller 130 can generate a low value for the first control signal 150 to turn off MP1 308 to return the Vc of the VDS clamp 102 to the first voltage threshold 202. In response to generating the low signal for the voltage clamp, the machine readable instructions 1000 conclude.
• FIG. 11 is a schematic illustration of an example system 1100 including the VDS clamp 102 of FIG. 1 to implement the examples described herein.
• the system 1100 includes an example power source 1102, a first example inductive load (L suppiy ) 1104, a first example resistive load (R SUppiy ) 1106, an example switching network 1108, a second example inductive load (L S h 0 rt) 1110, a second example resistive load (R S hort) 1112, an example device 1114, and an example control system 1116.
• the system 1100 is an example power switching system included in an example vehicle 1118.
• the vehicle 1118 is an automobile.
• the vehicle 1118 may be a marine vehicle (e.g., a boat, submarine, etc.), an aircraft (e.g., an unmanned aerial vehicle (UAV) (e.g., a drone), an airplane, etc.), etc.
• the system 1100 may correspond to the power switching system 100 of FIG. 1.
• the system 1100 is operative to monitor a condition (e.g., an operating condition) of at least one of the power source 1102 or the device 1114 and control the VDS clamp 102 via the control system 1116 based on the monitoring.
• a condition e.g., an operating condition
• the power source 1102 is a battery.
• the power source 1102 may correspond to the power source 108 of FIG. 1.
• the first inductive load 1104 and the first resistive load 1106 of FIG. 11 are discrete, physical elements.
• the first inductive load 1104 and/or the first resistive load 1106 may be representations of an equivalent inductance and resistance of the coupling between the power source 1102 and the switching network 1108.
• the first inductive load 1104 may correspond to the second inductor 118 of FIG. 1 and/or the first resistive load 1106 may correspond to the first resistor 116 of FIG. 1.
• the second inductive load 1110 and the second resistive load 1112 of FIG. 11 are discrete, physical elements (e.g., electrical devices that can be represented by an inductive and/or a resistive load).
• the second inductive load 1110 and/or the second resistive load 1112 may be representations of an equivalent inductance and resistance of the coupling between the switching network 1108 and the device 1114.
• the second inductive load 1110 may correspond to the first inductor 114 of FIG. 1 and/or the second resistive load 1112 may correspond to the first resistor 116 of FIG. 1.
• the system 1100 may include fewer than or more than the inductive loads 1104, 1110 and/or the resistive loads 1106, 1112 depicted in FIG. 11.
• the control system 1116 directs, instructs, and/or otherwise controls the switching network 1108 of FIG. 11.
• the control system 1116 includes one or more controllers such as the controller 130 of FIG. 1.
• the control system 1116 may correspond to one or more instances of the controller 130 of FIG. 1.
• the control system 1116 of FIG. 11 obtains a condition of the device 1114 and generates a control signal based on the condition.
• the condition may be a non-fault regular load condition (e.g., normal operation, typical operation, standard operation, etc.) or a fault condition.
• the control system 1116 of FIG. 11 controls the switching network 1108 based on a condition of the device 1114.
• the switching network 1108 includes an example transistor 1120 (e.g., an N-channel MOSFET, a P-channel MOSFET, etc.).
• the switching network 1108 may include more than one transistor and/or more than one type of transistor.
• the transistor 1120 is coupled either directly to or through one or more intervening electrical devices to the VDS clamp 102 of FIG. 1.
• the VDS clamp 102 may also be the VDS clamp l02a of FIG. 3 or the VDS clamp l02b of FIG. 4.
• the control system 1116 of FIG. 11 generates a control signal (e.g., the first control signal 150 of FIG. 1, the second control signal 152 of FIG. 1, etc.) to adjust the VDS clamp 102 from a first voltage to a second voltage based on the condition of the device 1114.
• the control system 1116 may instruct the VDS clamp 102 to adjust or fold back from a first voltage clamp level of 44 V during a non-fault regular load operation of the device 1114 to a second voltage clamp level of 33 V in response to determining that the device 1114 is experiencing a fault condition.
• control system 11 generates (e.g., iteratively generates, continuously generates, etc.) the control signal for a time period defined by a VDS folding timer.
• the control system 1116 In response to an expiration of the VDS folding timer, the control system 1116 generates another control signal to direct the VDS clamp 102 to adjust from the second voltage clamp level of 33 V back to the first voltage clamp level of 44 V.
• the VDS clamp 102 clamps the VDS of the transistor 1120 included in the switching network 1108 when a supply voltage (VBB) from the power source 1102 exceeds a voltage clamp level.
• VBB supply voltage
• the VDS clamp 102 during a non-fault regular load operation of the device 1114 may have a voltage clamp level of 44 V.
• the VDS clamp 102 may clamp a supply voltage of 50 V to 44 V when the device 1114 is not experiencing a fault condition.
• the VDS clamp 102 may clamp the supply voltage to a first voltage (e.g., 44 V) during a non-fault regular load operation of the device 1114 and clamp the supply voltage to a second voltage (e.g., 33 V) during a fault condition of the device 1114.
• the system 1100 of FIG. 11 supplies the necessary power and/or otherwise facilitates an operation of the device 1114 when the device 1114 is experiencing different operating conditions due to the adaptive nature of the V D s clamp 102 (e.g., the VDS clamp l02a of FIG. 3, the VDS clamp l02b of FIG. 4, etc.).
• FIG. 12 depicts an example timing diagram 1200 corresponding to an operation of the system 1100 of FIG. 11.
• the control system 1116 of FIG. 11 receives a high value for an example control signal 1204.
• the control signal 1204 may correspond to the enable signal 142 of FIG. 1.
• the control system 1116 may instruct a controller (e.g., the controller 130 of FIG. 1) to initialize the system 1100 of FIG. 11.
• the control system 1116 receives an example status feedback signal 1206.
• the status feedback signal 1206 may correspond to the fault signal 302 of FIG. 3.
• the status feedback signal 1206 may indicate a condition of the device 1114 of FIG. 11.
• the control system 1116 determines that the status feedback signal 1206 indicates that the device 1114 is in a non-fault regular load condition.
• T 2 the device 1114 of FIG. 11 is experiencing a fault condition evident by an increase in an example short circuit current 1210.
• the increase in the short circuit current 1210 causes the status feedback signal 1206 to change from a first voltage to a second voltage indicating that the device 1114 is experiencing a fault condition.
• the control system 1116 determines that the device 1114 is in a fault condition based on the status feedback signal 1206.
• control system 1116 In response to determining that the device 1114 is in the fault condition, the control system 1116 generates a control signal to adjust the VDS clamp 102 included in the switching network 1108 of FIG. 11 from a first clamp voltage to a second clamp voltage for a time period defined by a VDS folding timer.
• FIG. 13 is a block diagram of an example processor platform 1300 structured to execute the instructions of FIG. 10 to implement the controller 130 of FIGS. 1, 3 and/or 4.
• the processor platform 1300 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPadTM), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset or other wearable device, or any other type of computing device.
• a self-learning machine e.g., a neural network
• a mobile device e.g., a cell phone, a smart phone, a tablet such as an iPadTM
• PDA personal digital assistant
• an Internet appliance e.g., a DVD player
• the processor platform 1300 of the illustrated example includes a processor 1312.
• the processor 1312 of the illustrated example is hardware.
• the processor 1312 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer.
• the hardware processor may be a semiconductor based (e.g., silicon based) device. In this example, the processor 1312 implements the controller 130.
• the processor 1312 of the illustrated example includes a local memory 1313 (e.g., a cache).
• the processor 1312 of the illustrated example is in communication with a main memory including a volatile memory 1314 and a non-volatile memory 1316 via a bus 1318.
• the volatile memory 1314 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of random access memory device.
• the non-volatile memory 1316 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 1314, 1316 is controlled by a memory controller.
• the processor platform 1300 of the illustrated example also includes an interface circuit 1320.
• the interface circuit 1320 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth® interface, a near field communication (NFC) interface, and/or a PCI express interface.
• one or more input devices 1322 are connected to the interface circuit 1320.
• the input device(s) 1322 permit(s) a user to enter data and/or commands into the processor 1312.
• the input device(s) 1322 can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.
• One or more output devices 1324 are also connected to the interface circuit 1320 of the illustrated example.
• the output devices 1324 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker.
• the interface circuit 1320 of the illustrated example thus, usually includes a graphics driver card, a graphics driver chip, and/or a graphics driver processor.
• the interface circuit 1320 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 1326.
• the communication can be via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, etc.
• DSL digital subscriber line
• the processor platform 1300 of the illustrated example also includes one or more mass storage devices 1328 for storing software and/or data.
• mass storage devices 1328 include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital versatile disk (DVD) drives.
• the machine executable instructions 1332 of FIG. 10 may be stored in the mass storage device 1328, in the volatile memory 1314, in the non-volatile memory 1316, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.
• Example methods, apparatus, and articles of manufacture are described herein that provide a dynamic adjustment on drain-source voltage clamp levels. Such a dynamic adjustment improves a versatility of a power-switchable device under load dump and more robust under fault conditions without any significant silicon area impact.
• By adaptively adjusting the drain-source voltage clamp levels above-described examples can enable the power-switchable device to operate with an increased safe operating area margin at the same current limit or operate at a higher current limit for the same safe operating area margin.

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