WO2019136976A1 - Procédé permettant d'utiliser diverses combinaisons de codes de correction d'erreurs dans un système de codage et de décodage - Google Patents

Procédé permettant d'utiliser diverses combinaisons de codes de correction d'erreurs dans un système de codage et de décodage Download PDF

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Publication number
WO2019136976A1
WO2019136976A1 PCT/CN2018/099755 CN2018099755W WO2019136976A1 WO 2019136976 A1 WO2019136976 A1 WO 2019136976A1 CN 2018099755 W CN2018099755 W CN 2018099755W WO 2019136976 A1 WO2019136976 A1 WO 2019136976A1
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WO
WIPO (PCT)
Prior art keywords
error
parameters
decoder
encoder
codec
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Application number
PCT/CN2018/099755
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English (en)
Chinese (zh)
Inventor
陈育鸣
李庭育
魏智汎
洪振洲
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江苏华存电子科技有限公司
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Publication of WO2019136976A1 publication Critical patent/WO2019136976A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

Definitions

  • the present invention relates to the technical field of storage devices, and in particular, to a method in which a coding and decoding system uses a plurality of combinations of error correction codes.
  • An encoder/decoder or codec is often accompanied by a non-volatile memory device such as a flash memory, which presents a problem of error during memory access.
  • the flash memory has evolved into many different types of information lengths and parity lengths.
  • a flash controller that supports different types of flash memory in the same chip is required to ensure data correctness, regardless of the type involved. Flash.
  • the codec must be configurable for multiple error correcting codes.
  • a method for compiling a codec system using a plurality of error correction code combinations including a computer, a main control chip, and a plurality of storage components, wherein the computer is connected to the main control chip through a bus.
  • the main control chip is connected to a plurality of storage components through a bus, the main control chip is provided with an encoder and a decoder, and the encoder is bidirectionally connected with the decoder;
  • the plurality of storage components include a first storage component and a second storage
  • the component, the third storage component, and the Nth storage component, N is an integer greater than 3.
  • the storage component includes a codec core and a plurality of non-volatile memories; the compiled code core is provided with a read parameter; the codec core is connected to a plurality of non-volatile memories, and the plurality of non-volatile memories are The first non-volatile memory, the second non-volatile memory, the third non-volatile memory, and the M non-volatile memory, and M is an integer greater than 3.
  • said encoder, decoder is configured to selectively perform different error corrections having different parameters; at least one storage component is configured to store error-free parameters, wherein selected error-free parameters are stored from said Components are loaded into the encoder, decoder for initializing the encoder and decoder.
  • said encoder, decoder is configured to selectively perform different error corrections having different parameters;
  • the external storage component is configured to store different parameters,
  • the auxiliary encoder, the decoder being configured to be stored from an external component Select and load one of the stored parameters, and then modify the load parameters according to the built-in parameters to generate an error-free parameter to be provided for initializing the encoder and decoder.
  • the encoder and decoder are configured to selectively perform different error corrections with different parameters; an error-free storage device for storing error-free fixed parameters to be loaded to the encoder, the decoder to initialize the encoding And an external storage component configured to store different parameters, the encoder, the decoder selecting and loading one of the stored parameters from the storage component, and performing the loading parameter according to the fixed parameter Corrected to produce error-free parameters.
  • an error-free storage device for storing error-free fixed parameters to be loaded to the encoder, the decoder to initialize the encoding
  • an external storage component configured to store different parameters, the encoder, the decoder selecting and loading one of the stored parameters from the storage component, and performing the loading parameter according to the fixed parameter Corrected to produce error-free parameters.
  • the present invention provides a configurable encoding system and method for storing a plurality of error correcting codes of a device or device to provide error-free parameters efficiently and economically.
  • FIG. 1 is a block diagram of a configurable codec using multiple error correcting codes according to the present invention
  • FIG. 2 is a block diagram of a configurable codec for a plurality of error correcting codes for a memory device in accordance with FIG. 1;
  • FIG. 3 is a block diagram of a configurable encoding system of a plurality of error correcting codes
  • FIG. 4 is a flowchart of a configurable encoding method for a plurality of error correcting codes of a memory device according to the first embodiment
  • Figure 5 is a block diagram of a configurable encoding system for a plurality of error correcting codes for a memory device in accordance with the first embodiment of Figure 3;
  • FIG. 6 is a flow chart of a configurable encoding method for a plurality of error correcting codes for a memory device in accordance with FIG. 5;
  • Figure 7 is a block diagram of a configurable encoding system for a plurality of error correcting codes
  • FIG. 8 is a flowchart of a configurable encoding method for a plurality of error correcting codes of a memory device according to a second embodiment
  • Figure 9 is a block diagram of a configurable encoding system for a plurality of error correcting codes
  • Figure 10 is a flow chart for storing or updating parameters.
  • the present invention provides a technical solution: a method for compiling a codec system using a plurality of error correction code combinations, including a computer 1, a master chip 2, and a plurality of storage components, the computer 1 being connected by a bus Control chip 2, the main control chip 2 is connected to a plurality of storage components through a bus, the main control chip 1 is provided with an encoder 3 and a decoder 4, and the encoder 3 and the decoder 4 are bidirectionally connected;
  • the storage component includes a first storage component 5, a second storage component 6, a third storage component 7, and an Nth storage component, N is an integer greater than 3;
  • the storage component includes a compiled code core 8 and a plurality of non-volatile memories;
  • the compiled code core 8 is provided with a read parameter; the compiled code core 8 is connected to a plurality of non-volatile memories, and the plurality of non-volatile memories include a first non-volatile memory 9, a second non-volatile memory 10, and
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the encoder and the decoder are configured to selectively perform different error corrections having different parameters; the at least one storage component is configured to store the error-free parameters, wherein the selected error-free parameters are from the storage A component is loaded to the encoder, decoder for initializing the encoder and decoder; in this embodiment, the codec is configurable to correct the error using one of the plurality of error correcting codes.
  • the codec can be switched to the first set of error correcting codes of the first storage device at a time, and the same codec can be switched to the second set of error correcting codes of the second storage device at another time, the codec It may be part of the master chip controller or may be separate from the controller, for example, the controller or codec may be further controlled, in the embodiment the memory device may be a volatile memory device, For example, a flash memory device that relies on an error correction code to correct bits that fail during normal device operation.
  • the codec primarily comprises an encoder and/or a decoder
  • the codec may comprise an encoder and a decoder, or may comprise only an encoder, or may only comprise a decoder.
  • a memory device includes an array of non-volatile memory cells divided into a plurality of blocks, each of the plurality of pages including a plurality of pages.
  • the codec can be configured to use different error correction codes to separately correct errors for the corresponding page (or block).
  • the encoding system includes an error correction code codec that includes configurable to perform different error corrections on different non-volatile memories.
  • the encoding system further includes a plurality of error-free parameter storage devices for respectively storing parameters of different error correcting codes, thereby providing an error-free parameter to the error correcting code codec in an embodiment, and each error-free parameter storage device may be Static random access memory or read only memory in each error-free storage device for initializing the error correction code codec in this specification or the error correction code codec relative to the corresponding error correction code, without error
  • the storage device has an error probability that is substantially less than the error probability of the error correction code codec. In other words, in practical applications, the probability of an error in the error-free parameter storage device can be ignored.
  • the encoding system is similar to the foregoing encoding system, and uses an error-free storage device to store parameters of different error correcting codes.
  • parameters of the plurality of error correction code codes are stored in the storage device.
  • parameters corresponding to different error correction codes are stored at different addresses in the storage device.
  • a parameter in the error correcting code can be configured to load from the storage device SD by addressing the need to initialize the error correcting code selected in the error correcting code codec.
  • an error correction code codec is prepared to begin encoding and/or decoding the data of the corresponding non-volatile memory.
  • the parameters are stored in the storage devices SD1-SDn.
  • parameters may be stored in storage devices SD1-SDn, such as rom, before encoding system 20 is shipped out of the factory.
  • the parameters may be stored in the memory set 1-N, and then the user selects one of the configurable error correcting codes, and the parameters required to initialize the selected error correcting code in the error correcting codec are The corresponding storage device is loaded. After initialization is complete, an error correction code codec is prepared to begin encoding and/or decoding data for the corresponding non-volatile memory. Or corresponding non-volatile memory.
  • the parameters are loaded from the second storage device 2, and then the error correction code codec is prepared to begin encoding and/or decoding the data of the second non-volatile memory.
  • Another example is selecting a set of parameters of the error correcting code and then loading from one of the corresponding storage devices, then preparing the error correcting code codec to begin the encoding step and/or non-volatile to the at least one page The memory data is decoded.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the encoder, decoder are configured to selectively perform different error corrections with different parameters; at least one storage component is configured to store error-free parameters, wherein the selected error-free parameters are The storage component is loaded to the encoder, decoder for initializing the encoder and decoder.
  • the encoding system includes a first error correction code codec that includes configurable to perform different error corrections on different non-volatile memories.
  • the encoding system further includes a second error correction code codec for external storage for loading parameters required to initialize the first error correction code codec, the nonvolatile memory storing the parameters may be non-easy as described above One of the cryptographic memories, or may be another separate non-volatile memory; the second error correcting codec itself is capable of correcting errors in the loading parameters without initialization.
  • the second error correction code codec has built-in parameters and is therefore capable of error correction. Subsequently, the second error correction code codec outputs the corrected or error free parameters to the first error correction code codec.
  • the first error correction code codec is prepared to start encoding and/or decoding the data of the corresponding non-volatile memory. For example, if the loading parameter is associated with the second error correcting code, then the first error correcting code codec is prepared to begin encoding and/or decoding the data of the second non-volatile memory.
  • This second embodiment maintains the advantage of the first embodiment that the error correction code codec does not bear the burden of storing a large number of parameters.
  • the extra space of the nonvolatile memory is, for example, a nonvolatile memory.
  • the extra space note that the cost of storing parameters in non-volatile memory is much less than the cost of parameters stored in error-free storage devices.
  • the second embodiment has two error correction codecs.
  • the first error correction code codec can be a low density parity check codec and the second codec can be a BCH codec.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the encoder and decoder are configured to selectively perform different error corrections with different parameters; an error-free storage device for storing error-free fixed parameters to be loaded into the encoder, decoder Initializing an encoder, a decoder; the external storage component is configured to store different parameters, the encoder, the decoder selecting and loading one of the stored parameters from the storage component, and according to the fixed parameter Load parameters are corrected to produce error-free parameters.
  • the encoding system includes an error correction code codec that includes configurable to perform different error corrections on different non-volatile memories.
  • the encoding system also includes a storage device such as an SRAM or a ROM for storing fixed parameters. Based on the fixed parameter ROM, the error correction code codec can load and correct parameters, and the error correction code codec needs to be initialized by the external storage device; note that the error correction code codec can correct the loading parameters with fixed parameters.
  • the error, the non-volatile memory storing the parameters may be one of the above non-volatile memories, or may be another separate non-volatile memory; subsequently, the error-correcting codec is performed using fixed parameters. initialization.
  • the associated portion of the stored parameters is loaded, and from the non-volatile memory to the error correction code codec, the loading parameters are error corrected by the error parameter based codec based on the fixed parameters.
  • the correction parameters After initializing the error correction code codec by the correction parameters, preparing an error correction code codec to start data of the nonvolatile memory corresponding to the encoding and/or decoding step, for example, if the loading parameter is related to the second error correction code
  • the error code codec is then prepared to begin encoding and/or decoding the data of the second non-volatile memory.
  • the third embodiment maintains the advantage of the first embodiment that the error correction code codec does not bear the burden of storing a large number of parameters. Moreover, this third embodiment maintains the advantage of the second embodiment that the cost of storing parameters in a non-volatile memory is much smaller than the parameters stored in an error-free storage device.
  • the LDPC code is selected to encode/decode data corresponding to the nonvolatile memory.
  • a matrix needs to be generated for encoding information, and the parameters required to decode the received signal for initializing the encoder associated with the generator matrix are predetermined for the hardware implementation.
  • the parameters required to initialize the decoder associated with the parity check matrix are also large.
  • the system In order to support multiple error correcting codes, the system must store different matrices for each LDPC error correcting code. According to the second and third embodiments, the matrix can now be loaded from non-volatile memory, thereby making the system design more flexible. Reduce the cost of the coding system.
  • the present invention provides a method of configurable encoding systems and methods for storing a plurality of error correcting codes for a device or device to provide error-free parameters efficiently and economically.

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  • Quality & Reliability (AREA)
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Abstract

L'invention concerne un procédé permettant d'utiliser diverses combinaisons de codes de correction d'erreurs dans un système de codage et de décodage, comprenant un ordinateur, une puce de commande maîtresse et une pluralité d'ensembles de stockage, l'ordinateur étant connecté à la puce de commande maîtresse au moyen d'un bus; la puce de commande maîtresse est connectée à la pluralité d'ensembles de stockage au moyen d'un bus; un codeur et un décodeur sont disposés dans la puce de commande maîtresse; et le codeur est en connexion bidirectionnelle avec le décodeur. L'invention concerne un système et un procédé de codage configurables pour un dispositif de stockage ou une pluralité de codes de correction d'erreurs du dispositif, de façon à fournir des paramètres sans erreur de manière efficace et économique.
PCT/CN2018/099755 2018-01-12 2018-08-09 Procédé permettant d'utiliser diverses combinaisons de codes de correction d'erreurs dans un système de codage et de décodage WO2019136976A1 (fr)

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CN108053860A (zh) * 2018-01-12 2018-05-18 江苏华存电子科技有限公司 一种编译码系统使用多种错误纠正码组合的方法
CN109144769A (zh) * 2018-07-20 2019-01-04 江苏华存电子科技有限公司 一种随机内存使用纠错码校验免去冗余储存单元的方法
CN109298967A (zh) * 2018-10-24 2019-02-01 江苏华存电子科技有限公司 一种闪存组件错误率调变核编译码速率节省耗电量的方法
CN113434328B (zh) * 2021-08-26 2021-11-30 西安热工研究院有限公司 一种分散控制系统逻辑组态编译纠错方法和系统

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US20100088575A1 (en) * 2008-10-07 2010-04-08 Eran Sharon Low density parity code (ldpc) decoding for memory with multiple log likelihood ratio (llr) decoders
CN101950586A (zh) * 2009-03-27 2011-01-19 联发科技股份有限公司 存储控制器及控制数据读取的方法
CN102929741A (zh) * 2012-09-29 2013-02-13 邹粤林 一种提高闪存芯片纠错码使用效率的方法、系统及控制器
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