WO2019136976A1 - Method for using various error correction code combinations in encoding and decoding system - Google Patents
Method for using various error correction code combinations in encoding and decoding system Download PDFInfo
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
Disclosed is a method for using various error correction code combinations in a encoding and decoding system, comprising a computer, a master control chip and a plurality of storage assemblies, wherein the computer is connected to the master control chip by means of a bus; the master control chip is connected to the plurality of storage assemblies by means of a bus; an encoder and a decoder are provided in the master control chip; and the encoder is in bidirectional connection with the decoder. Provided are a configurable encoding system and method for a storage device or a plurality of error correction codes of the device, so as to provide error-free parameters efficiently and economically.
Description
本发明涉及储存装置技术领域，具体为一种编译码系统使用多种错误纠正码组合的方法。The present invention relates to the technical field of storage devices, and in particular, to a method in which a coding and decoding system uses a plurality of combinations of error correction codes.
编码器/解码器或编解码器通常伴随着诸如闪存的非易失性存储器装置，在存储器访问过程中出现错误的问题。该闪存已经发展成许多不同类型的信息长度和奇偶长度在一些应用中，需要一种在同一芯片中支持不同类型的闪存的闪光控制器，从而可以保证数据的正确性，无论是否涉及何种类型的闪光。换句话说，该编解码器必须可配置用于多个纠错码。An encoder/decoder or codec is often accompanied by a non-volatile memory device such as a flash memory, which presents a problem of error during memory access. The flash memory has evolved into many different types of information lengths and parity lengths. In some applications, a flash controller that supports different types of flash memory in the same chip is required to ensure data correctness, regardless of the type involved. Flash. In other words, the codec must be configurable for multiple error correcting codes.
然而，多个纠错码导致用于初始化编解码器的多个参数，而一些参数可能相当大。这可以扩大编解码器或闪存控制器的电路面积。此外，在编解码器或控制器中存储参数可以使电路设计不灵活；由于传统编码器/解码器无法有效且经济地提供用于闪存的多个纠错码，需要提出一种新的编码系统和方法，用于缓解存储大量参数的负担的编解码器，而不会造成实质性的成本。However, multiple error correction codes result in multiple parameters for initializing the codec, and some parameters may be quite large. This can increase the circuit area of the codec or flash controller. Furthermore, storing parameters in a codec or controller can make circuit design inflexible; since conventional encoders/decoders cannot efficiently and economically provide multiple error correction codes for flash memory, a new coding system needs to be proposed. And methods for mitigating codecs that store a large amount of parameters without incurring substantial costs.
发明内容Summary of the invention
本发明的目的在于提供一种编译码系统使用多种错误纠正码组合的方法，以解决上述背景技术中提出的问题。It is an object of the present invention to provide a method of using a plurality of error correction code combinations in a codec system to solve the problems set forth in the background art above.
为实现上述目的，本发明提供如下技术方案：一种编译码系统使用多种错误纠正码组合的方法，包括计算机、主控芯片和多个储存组 件，所述计算机通过总线连接主控芯片，所述主控芯片通过总线连接多个储存组件，所述主控芯片内设有编码器和解码器，且所述编码器与解码器双向连接；多个储存组件包括第一储存组件、第二储存组件、第三储存组件、第N储存组件，N为大于3的整数。In order to achieve the above object, the present invention provides the following technical solution: a method for compiling a codec system using a plurality of error correction code combinations, including a computer, a main control chip, and a plurality of storage components, wherein the computer is connected to the main control chip through a bus. The main control chip is connected to a plurality of storage components through a bus, the main control chip is provided with an encoder and a decoder, and the encoder is bidirectionally connected with the decoder; the plurality of storage components include a first storage component and a second storage The component, the third storage component, and the Nth storage component, N is an integer greater than 3.
优选的，所述储存组件包括编译码核和多个非挥发性内存；所述编译码核内设有读个参数；所述编译码核连接多个非挥发性内存，多个非挥发性内存包括第一非挥发性内存、第二非挥发性内存、第三非挥发性内存和第M非挥发性内存，M为大于3的整数。Preferably, the storage component includes a codec core and a plurality of non-volatile memories; the compiled code core is provided with a read parameter; the codec core is connected to a plurality of non-volatile memories, and the plurality of non-volatile memories are The first non-volatile memory, the second non-volatile memory, the third non-volatile memory, and the M non-volatile memory, and M is an integer greater than 3.
优选的，所述编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；至少一个储存组件被配置为存储无差错参数，其中，将选定的无差错参数从所述储存组件加载到所述编码器、解码器以用于初始化编码器和解码器。Advantageously, said encoder, decoder is configured to selectively perform different error corrections having different parameters; at least one storage component is configured to store error-free parameters, wherein selected error-free parameters are stored from said Components are loaded into the encoder, decoder for initializing the encoder and decoder.
优选的，所述编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；外部储存组件被配置为存储不同的参数，辅助编码器、解码器被配置为从外部储存组件中选择和加载存储的参数之一，然后根据内建参数对加载参数进行修正，从而生成要提供给用于初始化编码器、解码器的无差错参数。Advantageously, said encoder, decoder is configured to selectively perform different error corrections having different parameters; the external storage component is configured to store different parameters, the auxiliary encoder, the decoder being configured to be stored from an external component Select and load one of the stored parameters, and then modify the load parameters according to the built-in parameters to generate an error-free parameter to be provided for initializing the encoder and decoder.
优选的，所述编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；一种无差错存储装置用于存储待加载到编码器、解码器的无差错固定参数以初始化编码器、解码器；外部储存组件被配置为存储不同的参数，所述编码器、解码器从储存组件中选择和加载所存储的参数中的一个，并根据所述固定参数对所述加载参数进 行修正，从而产生无差错参数。Preferably, the encoder and decoder are configured to selectively perform different error corrections with different parameters; an error-free storage device for storing error-free fixed parameters to be loaded to the encoder, the decoder to initialize the encoding And an external storage component configured to store different parameters, the encoder, the decoder selecting and loading one of the stored parameters from the storage component, and performing the loading parameter according to the fixed parameter Corrected to produce error-free parameters.
与现有技术相比，本发明的有益效果是：本发明提供一种可配置编码系统及方法用于存储设备或设备的多个纠错码的方法，以便有效和经济地提供无差错的参数。An advantageous effect of the present invention over the prior art is that the present invention provides a configurable encoding system and method for storing a plurality of error correcting codes of a device or device to provide error-free parameters efficiently and economically. .
图1为本发明使用多个纠错码的可配置编解码器的框图；1 is a block diagram of a configurable codec using multiple error correcting codes according to the present invention;
图2为根据图1的用于存储器装置的多个纠错码的可配置编解码器的框图；2 is a block diagram of a configurable codec for a plurality of error correcting codes for a memory device in accordance with FIG. 1;
图3为多个纠错码的可配置编码系统的框图；3 is a block diagram of a configurable encoding system of a plurality of error correcting codes;
图4为根据第一实施例的用于存储器件的多个纠错码的可配置编码方法的流程图；4 is a flowchart of a configurable encoding method for a plurality of error correcting codes of a memory device according to the first embodiment;
图5为根据图3的第一实施例的用于存储器装置的多个纠错码的可配置编码系统框图；Figure 5 is a block diagram of a configurable encoding system for a plurality of error correcting codes for a memory device in accordance with the first embodiment of Figure 3;
图6为根据图5的用于存储器装置的多个纠错码的可配置编码方法的流程图；6 is a flow chart of a configurable encoding method for a plurality of error correcting codes for a memory device in accordance with FIG. 5;
图7为多个纠错码的可配置编码系统的框图；Figure 7 is a block diagram of a configurable encoding system for a plurality of error correcting codes;
图8为根据第二实施例的用于存储器件的多个纠错码的可配置编码方法的流程图；8 is a flowchart of a configurable encoding method for a plurality of error correcting codes of a memory device according to a second embodiment;
图9为多个纠错码的可配置编码系统的框图；Figure 9 is a block diagram of a configurable encoding system for a plurality of error correcting codes;
图10为存储或更新参数流程图。Figure 10 is a flow chart for storing or updating parameters.
下面将结合本发明实施例中的附图，对本发明实施例中的技术方 案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
请参阅图1，本发明提供一种技术方案：一种编译码系统使用多种错误纠正码组合的方法，包括计算机1、主控芯片2和多个储存组件，所述计算机1通过总线连接主控芯片2，所述主控芯片2通过总线连接多个储存组件，所述主控芯片1内设有编码器3和解码器4，且所述编码器3与解码器4双向连接；多个储存组件包括第一储存组件5、第二储存组件6、第三储存组件7、第N储存组件，N为大于3的整数；储存组件包括编译码核8和多个非挥发性内存；所述编译码核8内设有读个参数；所述编译码核8连接多个非挥发性内存，多个非挥发性内存包括第一非挥发性内存9、第二非挥发性内存10、第三非挥发性内存11和第M非挥发性内存，M为大于3的整数。Referring to FIG. 1, the present invention provides a technical solution: a method for compiling a codec system using a plurality of error correction code combinations, including a computer 1, a master chip 2, and a plurality of storage components, the computer 1 being connected by a bus Control chip 2, the main control chip 2 is connected to a plurality of storage components through a bus, the main control chip 1 is provided with an encoder 3 and a decoder 4, and the encoder 3 and the decoder 4 are bidirectionally connected; The storage component includes a first storage component 5, a second storage component 6, a third storage component 7, and an Nth storage component, N is an integer greater than 3; the storage component includes a compiled code core 8 and a plurality of non-volatile memories; The compiled code core 8 is provided with a read parameter; the compiled code core 8 is connected to a plurality of non-volatile memories, and the plurality of non-volatile memories include a first non-volatile memory 9, a second non-volatile memory 10, and a third Non-volatile memory 11 and M-th non-volatile memory, M is an integer greater than 3.
实施例一：Embodiment 1:
本实施例中，编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；至少一个储存组件被配置为存储无差错参数，其中，将选定的无差错参数从所述储存组件加载到所述编码器、解码器以用于初始化编码器和解码器；在该实施例中，编解码器可配置用于使用多个纠错码中的一个来校正误差。例如，可将编解码器一次切换到第一存储设备的第一组纠错码，并且相同的编解码器可以在另一时间切换到第二存储设备的第二组纠错码,编解码器可以是主控 芯片控制器的一部分，或者可以与控制器分开，例如，控制器或编解码器可以被进一步控制，在所述实施例中，所述存储器装置，可为易失性存储器装置，例如依赖于纠错码的快闪存储器装置，以校正在正常装置操作期间失败的位。In this embodiment, the encoder and the decoder are configured to selectively perform different error corrections having different parameters; the at least one storage component is configured to store the error-free parameters, wherein the selected error-free parameters are from the storage A component is loaded to the encoder, decoder for initializing the encoder and decoder; in this embodiment, the codec is configurable to correct the error using one of the plurality of error correcting codes. For example, the codec can be switched to the first set of error correcting codes of the first storage device at a time, and the same codec can be switched to the second set of error correcting codes of the second storage device at another time, the codec It may be part of the master chip controller or may be separate from the controller, for example, the controller or codec may be further controlled, in the embodiment the memory device may be a volatile memory device, For example, a flash memory device that relies on an error correction code to correct bits that fail during normal device operation.
在实施例中，编解码器主要包括编码器和/或解码器，编解码器可以包括编码器和解码器，或可仅包括编码器，或可仅包括解码器。In an embodiment, the codec primarily comprises an encoder and/or a decoder, the codec may comprise an encoder and a decoder, or may comprise only an encoder, or may only comprise a decoder.
如图2所示，在该实施例中，存储器装置包括划分为多个块的非易失性存储器单元的阵列，所述多个页面中的每一个都包含多个页面。编解码器可被配置成使用不同的纠错码来分别校正相应页面(或块)的错误。As shown in FIG. 2, in this embodiment, a memory device includes an array of non-volatile memory cells divided into a plurality of blocks, each of the plurality of pages including a plurality of pages. The codec can be configured to use different error correction codes to separately correct errors for the corresponding page (or block).
如图3-4所示，在该实施例中，编码系统包括纠错码编解码器，该纠错码编解码器包括可配置成对不同的非易失性存储器执行不同的误差校正。编码系统还包括多个无差错参数存储设备，用于分别存储不同纠错码的参数，从而向纠错码编解码器在实施例中提供无差错参数，每个无差错参数存储设备，可以是静态随机存取存储器或只读存储器在每个无差错存储装置中，用于初始化在本说明书中纠错码编解码器或相对于相应的纠错配置纠错码编解码器的状态，无差错存储装置具有实质上小于纠错码编解码器的错误概率的错误概率。换句话说，在实际应用中，可忽略无差错参数存储装置中出现错误的概率。As shown in Figures 3-4, in this embodiment, the encoding system includes an error correction code codec that includes configurable to perform different error corrections on different non-volatile memories. The encoding system further includes a plurality of error-free parameter storage devices for respectively storing parameters of different error correcting codes, thereby providing an error-free parameter to the error correcting code codec in an embodiment, and each error-free parameter storage device may be Static random access memory or read only memory in each error-free storage device for initializing the error correction code codec in this specification or the error correction code codec relative to the corresponding error correction code, without error The storage device has an error probability that is substantially less than the error probability of the error correction code codec. In other words, in practical applications, the probability of an error in the error-free parameter storage device can be ignored.
如图5-6所示，在本实施例中，该编码系统与前述编码系统相似，利用一个无差错存储设备存储不同纠错码的参数。在步骤中，将多 个纠错码码的参数存储在存储设备中。例如，对应于不同纠错码的参数存储在存储设备中的不同地址处。随后，择可配置纠错码中的一个参数，通过寻址来从存储设备SD加载用于初始化纠错码编解码器中所选择的纠错码的需要。在完成初始化之后，准备纠错码编解码器以开始对相应非易失性存储器的数据进行编码和/或解码。或对应页面的数据的非易失性存储器；将参数存储在存储设备SD1-SDn中。例如，参数在编码系统20被运出工厂之前，可以存储在存储设备SD1-SDn中，如rom中。可替换地，参数可以存储在存储设1-N中，随后，由用户选择可配置的纠错码中的一个，在纠错码编解码器中初始化所选择的纠错码所需的参数从对应的存储装置加载。完成初始化后，准备纠错码编解码器以开始对相应非易失性存储器的数据进行编码和/或解码。或对应的非易失性存储器。如果选择了第二纠错码，则从第二存储设备2加载参数，然后准备纠错码编解码器以开始对第二非易失性存储器的数据进行编码和/或解码。另一个例子是选择纠错码之一组参数，然后从对应的存储装置中的一者加载，然后准备纠错码编解码器开始编码步骤和/或对所述至少一个页的非易失性存储器数据进行解码。As shown in FIG. 5-6, in the embodiment, the encoding system is similar to the foregoing encoding system, and uses an error-free storage device to store parameters of different error correcting codes. In the step, parameters of the plurality of error correction code codes are stored in the storage device. For example, parameters corresponding to different error correction codes are stored at different addresses in the storage device. Subsequently, a parameter in the error correcting code can be configured to load from the storage device SD by addressing the need to initialize the error correcting code selected in the error correcting code codec. After the initialization is completed, an error correction code codec is prepared to begin encoding and/or decoding the data of the corresponding non-volatile memory. Or a non-volatile memory corresponding to the data of the page; the parameters are stored in the storage devices SD1-SDn. For example, parameters may be stored in storage devices SD1-SDn, such as rom, before encoding system 20 is shipped out of the factory. Alternatively, the parameters may be stored in the memory set 1-N, and then the user selects one of the configurable error correcting codes, and the parameters required to initialize the selected error correcting code in the error correcting codec are The corresponding storage device is loaded. After initialization is complete, an error correction code codec is prepared to begin encoding and/or decoding data for the corresponding non-volatile memory. Or corresponding non-volatile memory. If the second error correction code is selected, the parameters are loaded from the second storage device 2, and then the error correction code codec is prepared to begin encoding and/or decoding the data of the second non-volatile memory. Another example is selecting a set of parameters of the error correcting code and then loading from one of the corresponding storage devices, then preparing the error correcting code codec to begin the encoding step and/or non-volatile to the at least one page The memory data is decoded.
实施例二：Embodiment 2:
如图7-8所示，编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；至少一个储存组件被配置为存储无差错参数，其中，将选定的无差错参数从所述储存组件加载到所述编码器、解码器以用于初始化编码器和解码器。As shown in Figures 7-8, the encoder, decoder are configured to selectively perform different error corrections with different parameters; at least one storage component is configured to store error-free parameters, wherein the selected error-free parameters are The storage component is loaded to the encoder, decoder for initializing the encoder and decoder.
在该实施例中，编码系统包括第一纠错码编解码器，该第一纠错码编解码器包括可配置成对不同的非易失性存储器执行不同的误差校正。编码系统还包括第二纠错码编解码器，其用于对初始化第一纠错码编解码器所需的参数进行加载的外部存储装置，存储参数的非易失性存储器可以是上述非易失性存储器中的一种，或者可以是另一单独的非易失性存储器；第二纠错码编解码器本身能够纠正加载参数的误差不需要初始化。例如，第二纠错码编解码器具有内置参数，因此能够进行纠错。随后，第二纠错码编解码器将校正的或无差错的参数输出到第一纠错码编解码器。In this embodiment, the encoding system includes a first error correction code codec that includes configurable to perform different error corrections on different non-volatile memories. The encoding system further includes a second error correction code codec for external storage for loading parameters required to initialize the first error correction code codec, the nonvolatile memory storing the parameters may be non-easy as described above One of the cryptographic memories, or may be another separate non-volatile memory; the second error correcting codec itself is capable of correcting errors in the loading parameters without initialization. For example, the second error correction code codec has built-in parameters and is therefore capable of error correction. Subsequently, the second error correction code codec outputs the corrected or error free parameters to the first error correction code codec.
将参数存储在一个或多个非易失性存储器。随后，加载所存储的参数的关联部分，从所述非易失性存储器到所述第二纠错码编解码器。接着，由第二纠错码编解码器对加载参数进行纠错。然后转发校正后的参数以便于相关联的初始化第一纠错码编解码器。在完成初始化后，准备第一纠错码编解码器以开始对编码和/或解码对应的非易失性存储器的数据。例如，如果加载参数与第二纠错码相关联，然后准备第一纠错码编解码器以开始对第二非易失性存储器的数据进行编码和/或解码Store parameters in one or more non-volatile memories. Subsequently, an associated portion of the stored parameters is loaded from the non-volatile memory to the second error correction code codec. Next, the load parameters are error corrected by the second error correction codec. The corrected parameters are then forwarded to facilitate initializing the first error correction code codec. After the initialization is completed, the first error correction code codec is prepared to start encoding and/or decoding the data of the corresponding non-volatile memory. For example, if the loading parameter is associated with the second error correcting code, then the first error correcting code codec is prepared to begin encoding and/or decoding the data of the second non-volatile memory.
该第二实施例保持了第一实施例的优点：纠错码编解码器不承担存储大量参数的负担。与第一实施例相比，由于各种纠错码的参数存储在非易失性存储器中，在所述第二实施例中，所述非易失性存储器的额外空间例如是非易失性存储器的额外空间，注意，在非易失性存储器中存储参数的成本远小于存储在无差错存储设备中的参数的成 本。此外，第二实施例具有两个纠错码编解码器。例如，第一纠错码编解码器可以是低密度奇偶校验编解码器，第二编解码器可以是BCH编解码器中。This second embodiment maintains the advantage of the first embodiment that the error correction code codec does not bear the burden of storing a large number of parameters. Compared with the first embodiment, since the parameters of the various error correcting codes are stored in the nonvolatile memory, in the second embodiment, the extra space of the nonvolatile memory is, for example, a nonvolatile memory. The extra space, note that the cost of storing parameters in non-volatile memory is much less than the cost of parameters stored in error-free storage devices. Furthermore, the second embodiment has two error correction codecs. For example, the first error correction code codec can be a low density parity check codec and the second codec can be a BCH codec.
实施例三：Embodiment 3:
如图9-10所示，编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；一种无差错存储装置用于存储待加载到编码器、解码器的无差错固定参数以初始化编码器、解码器；外部储存组件被配置为存储不同的参数，所述编码器、解码器从储存组件中选择和加载所存储的参数中的一个，并根据所述固定参数对所述加载参数进行修正，从而产生无差错参数。As shown in Figures 9-10, the encoder and decoder are configured to selectively perform different error corrections with different parameters; an error-free storage device for storing error-free fixed parameters to be loaded into the encoder, decoder Initializing an encoder, a decoder; the external storage component is configured to store different parameters, the encoder, the decoder selecting and loading one of the stored parameters from the storage component, and according to the fixed parameter Load parameters are corrected to produce error-free parameters.
在该实施例中，编码系统包括纠错码编解码器，该纠错码编解码器包括可配置成对不同的非易失性存储器执行不同的误差校正。编码系统还包括存储设备，例如SRAM或用于存储固定参数的ROM。基于该固定参数的ROM，纠错码编解码器可加载和校正参数，需要由外部存储装置对纠错码编解码器进行初始化；注意，纠错码编解码器能够校正具有固定参数的加载参数的误差，存储参数的非易失性存储器可以是上述非易失性存储器中的一种，或者可以是另一单独的非易失性存储器；随后，利用固定参数对纠错码编解码器进行初始化。接下来，加载所存储的参数的关联部分，从所述非易失性存储器到所述纠错码编解码器，通过基于固定参数的纠错码编解码器对加载参数进行纠错。通过校正参数初始化纠错码编解码器之后，准备纠错码编解码器以开始编码和/或解码步骤相对应的非易失性存储器的数据， 例如，如果加载参数与第二纠错码相关联，然后准备纠错码编解码器以开始对第二非易失性存储器的数据进行编码和/或解码。In this embodiment, the encoding system includes an error correction code codec that includes configurable to perform different error corrections on different non-volatile memories. The encoding system also includes a storage device such as an SRAM or a ROM for storing fixed parameters. Based on the fixed parameter ROM, the error correction code codec can load and correct parameters, and the error correction code codec needs to be initialized by the external storage device; note that the error correction code codec can correct the loading parameters with fixed parameters. The error, the non-volatile memory storing the parameters may be one of the above non-volatile memories, or may be another separate non-volatile memory; subsequently, the error-correcting codec is performed using fixed parameters. initialization. Next, the associated portion of the stored parameters is loaded, and from the non-volatile memory to the error correction code codec, the loading parameters are error corrected by the error parameter based codec based on the fixed parameters. After initializing the error correction code codec by the correction parameters, preparing an error correction code codec to start data of the nonvolatile memory corresponding to the encoding and/or decoding step, for example, if the loading parameter is related to the second error correction code The error code codec is then prepared to begin encoding and/or decoding the data of the second non-volatile memory.
第三实施例保持了第一实施例的优点：纠错码编解码器不承担存储大量参数的负担。此外，该第三实施例保持了第二实施例的优点：在非易失性存储器中存储参数的成本比存储在无差错存储设备中的参数小得多。The third embodiment maintains the advantage of the first embodiment that the error correction code codec does not bear the burden of storing a large number of parameters. Moreover, this third embodiment maintains the advantage of the second embodiment that the cost of storing parameters in a non-volatile memory is much smaller than the parameters stored in an error-free storage device.
上述实施例中，选择LDPC码对对应非易失性存储器的数据进行编码/解码。具体地，需要生成矩阵用于编码信息，并且需要奇偶校验矩阵来解码接收信号用于初始化与生成矩阵相关的编码器所需的参数对于硬件实现是预先确定的。类似地，初始化与奇偶校验矩阵相关的解码器所需的参数也很大。为了支持多个纠错码，系统必须为每个LDPC纠错码存储不同的矩阵根据第二和第三实施例，该矩阵现在可以从非易失性存储器中加载，从而使系统设计更加灵活，降低了编码系统的成本。In the above embodiment, the LDPC code is selected to encode/decode data corresponding to the nonvolatile memory. In particular, a matrix needs to be generated for encoding information, and the parameters required to decode the received signal for initializing the encoder associated with the generator matrix are predetermined for the hardware implementation. Similarly, the parameters required to initialize the decoder associated with the parity check matrix are also large. In order to support multiple error correcting codes, the system must store different matrices for each LDPC error correcting code. According to the second and third embodiments, the matrix can now be loaded from non-volatile memory, thereby making the system design more flexible. Reduce the cost of the coding system.
综上所述，本发明提供一种可配置编码系统及方法用于存储设备或设备的多个纠错码的方法，以便有效和经济地提供无差错的参数。In summary, the present invention provides a method of configurable encoding systems and methods for storing a plurality of error correcting codes for a device or device to provide error-free parameters efficiently and economically.
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the invention is defined by the appended claims and their equivalents.
Claims (5)
- 一种编译码系统使用多种错误纠正码组合的方法，其特征在于：包括计算机(1)、主控芯片(2)和多个储存组件，所述计算机(1)通过总线连接主控芯片(2)，所述主控芯片(2)通过总线连接多个储存组件，所述主控芯片(1)内设有编码器(3)和解码器(4)，且所述编码器(3)与解码器(4)双向连接；多个储存组件包括第一储存组件(5)、第二储存组件(6)、第三储存组件(7)、第N储存组件，N为大于3的整数。A method for compiling a codec system using a plurality of error correction code combinations, comprising: a computer (1), a main control chip (2) and a plurality of storage components, wherein the computer (1) is connected to the main control chip through a bus ( 2), the main control chip (2) is connected to a plurality of storage components through a bus, the main control chip (1) is provided with an encoder (3) and a decoder (4), and the encoder (3) Two-way connection with the decoder (4); the plurality of storage components include a first storage component (5), a second storage component (6), a third storage component (7), an Nth storage component, and N is an integer greater than 3.
- 根据权利要求1所述的一种编译码系统使用多种错误纠正码组合的方法，其特征在于：所述储存组件包括编译码核(8)和多个非挥发性内存；所述编译码核(8)内设有读个参数；所述编译码核(8)连接多个非挥发性内存，多个非挥发性内存包括第一非挥发性内存(9、)第二非挥发性内存(10)、第三非挥发性内存(11)和第M非挥发性内存，M为大于3的整数。A method for compiling a codec system using a plurality of error correction codes according to claim 1, wherein said storage component comprises a codec core (8) and a plurality of non-volatile memories; said codec core (8) having a read parameter; the compiled code core (8) is connected to a plurality of non-volatile memories, and the plurality of non-volatile memories includes a first non-volatile memory (9) and a second non-volatile memory ( 10), a third non-volatile memory (11) and an M-th non-volatile memory, and M is an integer greater than 3.
- 根据权利要求1所述的一种编译码系统使用多种错误纠正码组合的方法，其特征在于：所述编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；至少一个储存组件被配置为存储无差错参数，其中，将选定的无差错参数从所述储存组件加载到所述编码器、解码器以用于初始化编码器和解码器。A method of compiling a codec system using a plurality of error correction codes according to claim 1, wherein said encoder and decoder are configured to selectively perform different error corrections having different parameters; at least one The storage component is configured to store an error free parameter, wherein the selected error free parameter is loaded from the storage component to the encoder, decoder for initializing the encoder and the decoder.
- 根据权利要求1所述的一种编译码系统使用多种错误纠正码组合的方法，其特征在于：所述编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；外部储存组件被配置为存储不同的 参数，辅助编码器、解码器被配置为从外部储存组件中选择和加载存储的参数之一，然后根据内建参数对加载参数进行修正，从而生成要提供给用于初始化编码器、解码器的无差错参数。A method of compiling a codec system using a plurality of error correction codes according to claim 1, wherein said encoder and decoder are configured to selectively perform different error corrections having different parameters; external storage The component is configured to store different parameters, the auxiliary encoder, the decoder is configured to select and load one of the stored parameters from the external storage component, and then modify the loading parameters according to the built-in parameters to generate a supply to be used for Initialize the error-free parameters of the encoder and decoder.
- 根据权利要求1所述的一种编译码系统使用多种错误纠正码组合的方法，其特征在于：所述编码器、解码器被配置为选择性地执行具有不同参数的不同误差校正；一种无差错存储装置用于存储待加载到编码器、解码器的无差错固定参数以初始化编码器、解码器；外部储存组件被配置为存储不同的参数，所述编码器、解码器从储存组件中选择和加载所存储的参数中的一个，并根据所述固定参数对所述加载参数进行修正，从而产生无差错参数。A method for compiling a codec system using a plurality of error correction codes according to claim 1, wherein said encoder and decoder are configured to selectively perform different error corrections having different parameters; The error-free storage device is configured to store error-free fixed parameters to be loaded to the encoder and the decoder to initialize the encoder and the decoder; the external storage component is configured to store different parameters, the encoder and the decoder are from the storage component One of the stored parameters is selected and loaded, and the loading parameters are modified according to the fixed parameters to produce an error-free parameter.
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