WO2019135744A1 - Couche filtrante pour une pile antiferromagnétique synthétique supérieure perpendiculaire (saf) pour une mémoire à couple d'orbite de spin (sot) - Google Patents

Couche filtrante pour une pile antiferromagnétique synthétique supérieure perpendiculaire (saf) pour une mémoire à couple d'orbite de spin (sot) Download PDF

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Publication number
WO2019135744A1
WO2019135744A1 PCT/US2018/012242 US2018012242W WO2019135744A1 WO 2019135744 A1 WO2019135744 A1 WO 2019135744A1 US 2018012242 W US2018012242 W US 2018012242W WO 2019135744 A1 WO2019135744 A1 WO 2019135744A1
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Prior art keywords
fixed magnet
memory device
stack
magnet
diffusion barrier
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PCT/US2018/012242
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English (en)
Inventor
Kaan OGUZ
Kevin P. O'brien
Mark Doczy
Charles C. Kuo
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Intel Corporation
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Priority to PCT/US2018/012242 priority Critical patent/WO2019135744A1/fr
Publication of WO2019135744A1 publication Critical patent/WO2019135744A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials

Definitions

  • Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, a filter layer for a perpendicular top SAF stack for a SOT memory.
  • shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality.
  • the drive for ever-more functionality, however, is not without issue.
  • the necessity to optimize the performance of each device becomes increasingly significant.
  • Non-volatile embedded memory e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency.
  • leading embedded memory options such as spin torque transfer magnetoresistive random access memory (STT-MRAM) can suffer from high voltage and high current-density problems during the programming (writing) of the cell.
  • the density limitations of STT-MRAM may be due to large write switching current and select transistor requirements.
  • traditional STT-MRAM has a cell size limitation due to the drive transistor requirement to provide sufficient spin current.
  • such memory is associated with large write current (>100 mA) and voltage (>0.7 V) requirements of conventional magnetic tunnel junction (MTJ) based devices.
  • MTJ magnetic tunnel junction
  • FIG. 1 A illustrates a typical material stack for a SOT (spin orbit torque) based MTJ (Magnetic Tunnel Junction) MRAM having a top synthetic anti-Ferro-magnet (SAF) stack with perpendicular anisotropy, according to one embodiment.
  • SOT spin orbit torque
  • MTJ Magnetic Tunnel Junction
  • SAF synthetic anti-Ferro-magnet
  • FIG. 1B is a top view of the device of FIG. 1A.
  • FIG. 1C is a cross-section of the SOT layer that shows direction of spin currents and charge currents as decided by SOT in metals.
  • FIG. 2 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with perpendicular anisotropy and a multilayer barrier filter in accordance with a first embodiment.
  • FIG. 3 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with perpendicular anisotropy and a multilayer barrier filter in accordance with a second embodiment.
  • FIG. 4 is a flow diagram representing various operations in a method of fabricating a SOT MTJ memory device with a multilayer barrier filter in accordance with the embodiments disclosed herein.
  • FIGS. 5A and 5B illustrate a wafer composed of semiconductor material and that includes one or more dies having integrated circuit (IC) structures formed on a surface of the wafer.
  • IC integrated circuit
  • FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter.
  • IC integrated circuit
  • FIG. 7 illustrates a computing device in accordance with one implementation of the disclosure.
  • Embodiments for a filter layer for a perpendicular top SAF stack for a SOT memory are described.
  • numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well- known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure.
  • the various embodiments shown in the FIGS are illustrative representations and are not necessarily drawn to scale.
  • Embodiments described herein may be directed to front-end-of-line (FEOL)
  • FOL front-end-of-line
  • FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).
  • IC integrated circuit
  • Embodiments described herein may be directed to back end of line (BEOL)
  • BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers.
  • BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.
  • contacts pads
  • interconnect wires vias and dielectric structures are formed.
  • more than 10 metal layers may be added in the BEOL.
  • Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures.
  • an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing.
  • an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.
  • One or embodiments of the present invention is directed to one or more filter layers for a perpendicular top SAF MJT stack for a Spin Orbit Torque (SOT) MRAM.
  • SOT Spin Orbit Torque
  • General applications of such an array include, but are not limited to, embedded memory, magnetic tunnel junction architectures, MRAM, non-volatile memory, spin hall effects, spin torque memory, and embedded memory using magnetic memory devices.
  • MTJ based SOT MRAM utilizing the disclosed filter layers reduces diffusion of elements in the SAF stack.
  • a memory device comprises an interconnect having a spin orbit torque (SOT) material.
  • a magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a material stack is on the MTJ device, wherein the material stack comprises a barrier material, a first pinned fixed magnet, a spacer material, and a second pinned fixed magnet.
  • a multilayer filter is located within the material stack, wherein the multilayer filter is configured to separate the reference fixed magnet from the first pinned fixed magnet.
  • FIG. 1 A illustrates a typical material stack for a SOT (spin orbit torque) based MTJ (Magnetic Tunnel Junction) MRAM having a top synthetic anti- ferromagnet (SAF) stack with perpendicular anisotropy, according to one embodiment.
  • the MTJ device stack stores data as a resistance state value.
  • the MTJ device stack comprises two independent ferromagnetic layers referred to as a free layer nanomagnet (FM1) and a reference fixed magnet (FM2) that are separated by an insulating tunneling barrier material.
  • the barrier material should be sufficiently thin (e.g., ⁇ 1 nm) such that electrons can tunnel there through.
  • the magnetic field of the fee layer magnet FM1 (shown by the double arrows) is free to rotate based on a direction of a current, i.e., the spin of the electrons, flowing through the MTJ device stack.
  • the reference fixed magnet FM2 has a fixed magnetization, and is therefore referred to as a fixed or reference layer.
  • the“free” layer magnetic layer is a magnetic layer storing a computational variable.
  • A“fixed” magnetic layer is a magnetic layer with fixed magnetization (magnetically harder than the free magnetic layer).
  • a barrier material such as a tunneling dielectric or oxide layer (e.g., MgO), is one located between free and fixed magnetic layers.
  • the free layer and the fixed layer may be ferromagnetic layers.
  • the MTJ functions essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either“high” or“low,” depending on the direction or orientation of magnetization in the free layer magnet FM1 and in the fixed magnet FM2.
  • a high resistive state exists in the case that the directions of magnetization in the free layer magnet FM1 and the fixed magnet FM2 closest to it are substantially opposed or anti-parallel with one another.
  • a low resistive state exists in the case that the directions of magnetization in the coupled free magnetic layers and the fixed layer magnet FM1 closest to it are substantially aligned or parallel with one another. It is to be understood that the terms“low” and“high” with regard to the resistive state of the MTJ are relative to one another.
  • the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa.
  • the low and high resistive states can represent different bits of information (i.e. a“0” or a“1”).
  • a barrier material such as Ta or TaO, separates the MTJ stack from the top synthetic antiferromagnet (SAF) stack.
  • the SAF stack includes a first pinned fixed magnet (SAF1), a non- magnetic spacer material (Ru or Ir), and a second pinned fixed magnet (SAF2).
  • SAF1 first pinned fixed magnet
  • Ru or Ir non- magnetic spacer material
  • SAF2 second pinned fixed magnet
  • the SAF stack allows for cancelling the dipole fields around the free layer magnet FM1.
  • a top electrode completes the material stack.
  • the free layer magnet FM1 and the reference fixed magnet FM2 may comprise CoxFeyBz (Cobalt, Iron, Boron), where‘x,’‘y,’ and‘z’ are integers.
  • the barrier material typically comprises an oxide layer such as magnesium oxide (MgO).
  • the first and second pinned fixed magnets SAF1 and SAF2 may comprise cobalt (Co) and/or platinum (Pt), and may be referred to herein as Co/Pt SAF1 and Co/Pt SAF2, respectively.
  • the spacer material typically comprises Ru (Ruthenium) or Ir (Iridium). In alternative embodiments, other materials may be used to form the MTJ device and the SAF stack.
  • the free layer magnet FM1 of the material stack is in direct contact with an SOT interconnect having a write electrode.
  • Both the SOT interconnect and the write electrode may comprises a Giant Spin Hall Effect (GSHE) metal made of b-Tantalum (b-Ta), b-Tungsten (b- W), Pt, Copper (Cu) doped with elements such as iridium, bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table.
  • Other metals will include alloys of various high spin orbit coupling materials, in general one element will have a high Z (greater than or equal to Ta) and the other metal will have a lower Z.
  • the write electrode transitions into a normal high conductivity metal (e.g., Cu) to minimize write electrode resistance.
  • FIG. 1B is a top view of the device of FIG. 1A.
  • the magnet is oriented along the width of the write electrode for appropriate spin injection.
  • the magnetic cell is written by applying a charge current via the write electrode.
  • the direction of the magnetic writing is decided by the direction of the applied charge current.
  • Positive currents (along+y) produce a spin injection current with transport direction (along+z) and spins pointing to (+x) direction.
  • SOT can impact both perpendicular and in plane magnetic free layers, this disclosure applies to both.
  • an SOT- MRAM may also be referred to as a Giant Spin Hall Effect (GSPHE) MRAM.
  • GSPHE Giant Spin Hall Effect
  • FIG. 1C is a cross-section of the SOT layer that shows direction of spin currents and charge currents as decided by SOT in metals.
  • the injected spin current in-tum produces spin torque to align the magnet in the +x or -x direction.
  • the transverse spin current for a charge current in the write electrode is provided in equation (1):
  • Is Pshe(w,t,Zsf,0SHE)(oxIc) (1)
  • PSHE is the spin hall injection efficiency, which is the ratio of magnitude of transverse spin current to lateral charge current
  • w is the width of the magnet
  • t is the thickness of the GSHE metal electrode
  • k s r is the spin flip length in the GSHE metal
  • OGSHE is the spin hall angle for the GSHE-metal to FM1 interface.
  • the injected spin angular momentum responsible for spin torque can be determined by first solving equation 1.
  • the top SAF stack may suffer from a reduction in tunnel magnetoresistance (TMR) due a negative crystalliztion effect that the Co/Pt pinned fixed magnet SAF1 has on the reference fixed magnet FM2 when the stack is annealed above 300 C.
  • TMR tunnel magnetoresistance
  • the materials comprising the material stack are deposited and the material stack is then annealed to crystallize the materials.
  • the annealing process should result in the free layer magnet FM1, the MgO barrier material, and the reference fixed magnet FM2 having a body- centered cubic (bcc) structure, specifically, a bcc (001) surface state (e.g., 60 - 95%).
  • bcc body- centered cubic
  • the first and second pinned fixed magnets SAF1 and SAF2 comprise Co/Pt, which has a face-centered cubic (fee) (111) structure.
  • the fee structure of the first pinned fixed magnet SAF1 can influence the reference fixed magnet FM2 into crystallizing in the fee direction, resulting in low TMR.
  • the Ta/TaO barrier material which has a thickness of approximately .3 to .5 nm, is introduced in between the CofeB reference fixed magnet FM2 and the Co/Pt pinned fixed magnet SAF1 to prevent the CofeB reference fixed magnet FM2 from crystallizing in the fee direction. Ideally, this works at low temperatures, but at high temperatures, the Ta/TaO barrier material is too non-uniform at that thickness to prevent the CofeB reference fixed magnet FM2 from crystallizing in the fee direction. Providing a thicker Ta/TaO barrier material is not a viable solution as it would interfere with the magnetic coupling between the first and second pinned fixed magnets SAF1 and SAF2. As an additional problem, the first and second pinned fixed magnets SAF1 and SAF2 become magnetically weak at high annealing temperatures (e.g., 350 - 400 C).
  • an improved SOT MRAM memory is described below. More specifically, a multilayer filter layer is introduced in the SOT stack of the memory devices comprising the SOT MRAM that protects against a reduction in TMR when the stack is annealed above 300 C, while maintaining magnetic coupling between the first and second pinned fixed magnets SAF1 and SAF2, as shown in FIG. 2.
  • FIG. 2 illustrates a material stack for a SOT MTJ memory device 200 having a top SAF stack with perpendicular anisotropy and a multilayer barrier filter in accordance with a first embodiment.
  • the SOT MTJ memory device 200 comprises an interconnect 202 having a SOT material, and a MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.
  • a material stack 206 is on the MTJ device 204.
  • the material stack 202 comprises a top synthetic
  • the SAF stack includes a first pinned fixed magnet (SAF1), a non-magnetic spacer material (Ru or Ir), and a second pinned fixed magnet (SAF2), as described above.
  • the material stack 206 is further provided with a multilayer barrier filter 208 located within the material stack 206 configured to effectively separate the CofeB reference fixed magnet FM2 and the Co/Pt pinned fixed magnet SAF1 to minimize any loss in TMR during high temperatures.
  • the multilayer barrier filter 208 comprises three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy.
  • the multilayer barrier filter 208 is located between reference fixed magnet FM2 and the first pinned fixed magnet SAF1, as shown.
  • the diffusion barriers 1 and 2 comprise bcc-based tantalum (Ta) or tantalum oxide (TaO), and may have a thickness of approximately .1 to .5 nm.
  • the diffusion barrier 1 and the diffusion barrier 2 may comprise other types of bcc-based heavy metal such as tungsten, iridium, or molybdenum.
  • the ferromagnetic cobalt-based alloy may comprise Co, Co x Fey, or Co x FeyB z (cobalt, iron, boron), where‘x,’‘y,’ and‘z’ are integers.
  • the ferromagnetic cobalt-based alloy may comprise binary elements of cobalt with any other transition metal, such as cobalt/tungsten, cobalt/palladium,
  • the cobalt-based alloy may have a thickness of approximately .3 to 2 nm.
  • the cobalt-based alloy may also be bcc-based, e.g., a pure cobalt layer at a thickness of .5 nm can stabilize into a bcc phase.
  • the pinned fixed magnets SAF1 and SAF2 may each have a thickness of approximately .5 to 2 nm.
  • the advantage of the three-layer barrier filter 208 is that it decouples the negative crystallization effect of the Co/Pt pinned fixed magnet SAF1 from the reference fixed magnet FM2. Based on the thicknesses ranges of the three layers comprising the barrier filter 208, the three-layer barrier filter effectively separates the Co/Pt pinned fixed magnet SAF1 from the reference magnet FM2 by a separation distance of approximately .4 to 2 nm, while the single layer of tantalum oxide shown in FIG. 1 provides a separation distance of only .3 to .5 nm.
  • the diffusion barriers 1 and 2 of the multilayer barrier filter 208 are sufficiently thin so that the ferromagnetic cobalt-based alloy, the pinned fixed magnet SAF1 and the reference fixed magnet FM2 magnetically couple and have parallel magnetic moments (while the pinned fixed magnet SAF2 is antiparallel), creating a magnetically stronger reference fixed magnet FM2 for the MTJ device. Consequently, the multilayer barrier filter 208 of the present embodiments reduces the fee (111) texture formation of the CoFeB reference magnet FM2 during annealing, while maintaining strong magnetic coupling.
  • the multilayer barrier filter 208 of the present embodiments should enable the MTJ device 204 to handle temperatures up to 400 to 450 C without suffering from a reduction in TMR.
  • FIG. 3 illustrates a material stack for a SOT MTJ memory device 300 having a top SAF stack with perpendicular anisotropy and a multilayer barrier filter in accordance with a second embodiment, where like components from FIG. 1 have like reference numerals.
  • the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.
  • a material stack 302 is on the MTJ device 204.
  • the material stack 302 comprises the SAF stack and the top electrode.
  • the SAF stack comprises a first pinned fixed magnet SAF1, a spacer material, and a second pinned fixed magnet SAF2, and a, as described above.
  • the multilayer barrier filter 308 comprises three layers of material, a diffusion barrier (Ta), a ferromagnetic cobalt-based alloy on the diffusion barrier, and an fee metal on the cobalt-based alloy.
  • the fee metal comprises platinum (Pt), iridium (Ir) or alloys thereof, on the cobalt-based alloy.
  • the multilayer barrier filter 308 is located between the reference fixed magnet FM2 and the pinned fixed magnet SAF1. Although in this embodiment the multilayer barrier filter 308 effectively separates the reference magnet FM2 from the pinned fixed magnet SAF1, the top fee metal in the multilayer barrier filter 308 provides a seed layer for improved fee crystallization of the pinned fixed magnet SAF1.
  • the diffusion barrier comprises tantalum (Ta) or tantalum oxide (TaO).
  • the fee metal has a thickness of approximately .1 to .5 nm
  • the ferromagnetic cobalt-based alloy may have a thickness of approximately .3 to 2 nm
  • the diffusion barrier 1 may have a thickness of approximately .1 to .5 nm.
  • the fee metal comprises Ru
  • the fee metal may have a thickness of approximately .8 - .9 nm.
  • the pinned fixed magnets SAF1 and SAF2 may each have a thickness of approximately .5 to 2 nm.
  • the diffusion barrier 1 and the fee metal of the multilayer barrier filter 208 are sufficiently thin so that the ferromagnetic cobalt-based alloy, the pinned fixed magnet SAF1 and the reference magnet FM2 magnetically couple and have parallel magnetic moments.
  • FIG. 4 is a flow diagram representing various operations in a method of fabricating a SOT MTJ memory device having a top SAF stack with perpendicular anisotropy and a multilayer barrier filter in accordance with the embodiments disclosed herein.
  • the process may include forming an SOT interconnect with a write electrode in an opening in a dielectric layer (block 400).
  • the SOT interconnect is formed in an opening in the dielectric layer above a substrate.
  • the substrate may include a suitable semiconductor material such as but not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI).
  • SOI silicon on insulator
  • the substrate may include other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.
  • the SOT interconnect is formed in the dielectric layer by a damascene or a dual damascene process that is well known in the art.
  • both the SOT interconnect and the write electrode may comprises a Giant Spin Hall Effect (GSHE) metal made of b-Tantalum (b-Ta), b-Tungsten (b-W), Pt, Copper (Cu) doped with elements such as Iridum, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table.
  • the SOT interconnect is electrically connected to a circuit element such as an access transistor (not shown).
  • Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.
  • a MTJ material stack is formed on the SOT interconnect, and a material layer stack having a multilayer barrier filter is formed over the MTJ material stack (block 402).
  • the MTJ material stack and the material layer stack are blanket deposited.
  • the layers of the MTJ stack may be formed by sputter-deposition techniques with deposition rates in the Angstrom-per-second range. The techniques include physical vapor deposition (PVD), specifically planar magnetron sputtering, and ion-beam deposition.
  • the MTJ stack may be subjected to an annealing process performed at a temperature between 300-400 degrees Celsius.
  • layers of the material layer stack may be respectively blanket deposited by an evaporation process, an atomic layer deposition (ALD) process or by chemical vapor deposition (CVD) process.
  • the chemical vapor deposition process is enhanced by plasma techniques such as RF glow discharge (plasma enhanced CVD) to increase the density and uniformity of the film.
  • an uppermost layer of material layer stack may include the top electrode layer that ultimately acts as a hardmask.
  • the deposition process can be configured to control the magnetic properties of the magnetic layers.
  • the direction of the magnetic anisotropy of the ferromagnetic materials can be set during the deposition of the layer by applying a magnetic field across the wafer.
  • the resulting uniaxial anisotropy is observed as magnetic easy and hard directions in the magnetization of the layer. Since the anisotropy axis affects the switching behavior of the material, the deposition system must be capable of projecting a uniform magnetic field across the wafer, typically in the 20-100 Oe range, during deposition.
  • the deposition process can control other magnetic properties, such as coercivity and magnetorestriction, by the choice of magnetic alloy and deposition conditions. Because the switching field of a patterned bit depends directly on the thickness of the free layer magnet, the thickness uniformity and repeatability must meet strict requirements.
  • a lithography step is performed that forms a photoresist mask on an uppermost surface of the material layer stack (block 404).
  • the photoresist mask is formed at a minimum size required for the memory element MTJ material stack, which is self-aligned with the material layer stack, and defines a location where a memory cell will be subsequently formed.
  • example minimum sizes for the resist could be in the range of 10 nm - 100 nm.
  • the material layer stack and the MTJ material stack is then patterned in alignment with the photoresist mask to form an active memory device/cell (block 406).
  • a plasma etch process is utilized to pattern the material layer stack and the MTJ stack down to the SOT interconnect 202.
  • a second dielectric layer is deposited over the memory device and other interconnect lines (e.g. a bit line) are patterned over the second dielectric layer (block 408).
  • the memory cell may be completed by removing the photoresist mask and then forming the second dielectric layer on the bit line and on the active memory device (on the hardmask, on sidewalls of the memory device, resistive element and memory element).
  • the second dielectric letter is planarized to expose an uppermost surface of the top electrode.
  • the bit line is patterned on the uppermost surface of the top electrode and on the uppermost surface of the second dielectric layer to complete formation of the memory cell.
  • the bit line may comprise conductive material such as W, TiN, TaN or Ru.
  • the bit line is formed by using a dual damascene process (not shown) and includes a barrier layer such as Ru, Ta or Ti and a fill metal such as W or Cu.
  • an underlying semiconductor substrate e.g., as FEOL layer(s).
  • the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s).
  • an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits.
  • semiconductor substrate often includes a wafer or other piece of silicon or another
  • Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials.
  • SOI silicon on insulator
  • the semiconductor substrate depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like.
  • the substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
  • structures described herein may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.
  • BEOL back end of line
  • an embedded non-volatile memory structure is formed on a material composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy -nitride, silicon nitride, or carbon-doped silicon nitride.
  • a dielectric material such as, but not limited to, silicon dioxide, silicon oxy -nitride, silicon nitride, or carbon-doped silicon nitride.
  • an embedded non-volatile memory structure is formed on a low-k dielectric layer of an underlying BEOL layer.
  • a wafer 500 may be composed of semiconductor material and may include one or more dies 502 having integrated circuit (IC) structures formed on a surface of the wafer 500.
  • IC integrated circuit
  • Each of the dies 502 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, such as described above.
  • the wafer 500 may undergo a singulation process in which each of the dies 502 is separated from one another to provide discrete“chips” of the semiconductor product.
  • structures that include embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter as disclosed herein may take the form of the wafer 500 (e.g., not singulated) or the form of the die 502 (e.g., singulated).
  • the die 502 may include one or more embedded non volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter and/or supporting circuitry to route electrical signals, as well as any other IC components.
  • the wafer 500 or the die 502 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element.
  • SRAM static random access memory
  • logic device e.g., an AND, OR, NAND, or NOR gate
  • a memory array formed by multiple memory devices may be formed on a same die 502 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
  • FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with one or more of the embodiments disclosed herein.
  • IC integrated circuit
  • an IC device assembly 600 includes components having one or more integrated circuit structures described herein.
  • the IC device assembly 600 includes a number of components disposed on a circuit board 602 (which may be, e.g., a motherboard).
  • the IC device assembly 600 includes components disposed on a first face 640 of the circuit board 602 and an opposing second face 642 of the circuit board 602.
  • components may be disposed on one or both faces 640 and 642.
  • any suitable ones of the components of the IC device assembly 600 may include a number of embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, such as disclosed herein.
  • the circuit board 602 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 602.
  • the circuit board 602 may be a non-PCB substrate.
  • the IC device assembly 600 illustrated in FIG. 6 includes a package-on-interposer structure 636 coupled to the first face 640 of the circuit board 602 by coupling components 616.
  • the coupling components 616 may electrically and mechanically couple the package-on- interposer structure 636 to the circuit board 602, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 636 may include an IC package 620 coupled to an interposer 604 by coupling components 618.
  • the coupling components 618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 616. Although a single IC package 620 is shown in FIG. 8, multiple IC packages may be coupled to the interposer 604. It is to be appreciated that additional interposers may be coupled to the interposer 604.
  • the interposer 604 may provide an intervening substrate used to bridge the circuit board 602 and the IC package 620.
  • the IC package 620 may be or include, for example, a die (the die 702 of FIG. 7B), or any other suitable component.
  • the interposer 604 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 604 may couple the IC package 620 (e.g., a die) to a ball grid array (BGA) of the coupling components 616 for coupling to the circuit board 602.
  • BGA ball grid array
  • the IC package 620 and the circuit board 602 are attached to opposing sides of the interposer 604.
  • the IC package 620 and the circuit board 602 may be attached to a same side of the interposer 604.
  • three or more components may be interconnected by way of the interposer 604.
  • the interposer 604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer 604 may include metal interconnects 610 and vias 608, including but not limited to through-silicon vias (TSVs) 606.
  • TSVs through-silicon vias
  • the interposer 604 may further include embedded devices 614, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 604.
  • RF radio-frequency
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 636 may take the form of any of the package-on-interposer structures known in the art.
  • the IC device assembly 600 may include an IC package 624 coupled to the first face 640 of the circuit board 602 by coupling components 622.
  • the coupling components 622 may take the form of any of the embodiments discussed above with reference to the coupling components 616
  • the IC package 624 may take the form of any of the embodiments discussed above with reference to the IC package 620.
  • the IC device assembly 600 illustrated in FIG. 8 includes a package-on-package structure 634 coupled to the second face 642 of the circuit board 602 by coupling components 628.
  • the package-on-package structure 634 may include an IC package 626 and an IC package 632 coupled together by coupling components 630 such that the IC package 626 is disposed between the circuit board 602 and the IC package 632.
  • the coupling components 628 and 630 may take the form of any of the embodiments of the coupling components 616 discussed above, and the IC packages 626 and 632 may take the form of any of the embodiments of the IC package 620 discussed above.
  • the package-on-package structure 634 may be configured in accordance with any of the package-on-package structures known in the art.
  • FIG. 7 illustrates a computing device 700 in accordance with one implementation of the disclosure.
  • the computing device 700 houses a board 702.
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one
  • the processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700.
  • the term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706.
  • a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704.
  • the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.
  • the term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.
  • the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.
  • another component housed within the computing device 700 may contain an integrated circuit die that includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • embodiments described herein include embedded non-volatile memory structures having SOT MTJ memory device with a multilayer barrier filter elements.
  • a memory device comprises an interconnect having a spin orbit torque (SOT) material.
  • a magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a material stack is on the MTJ device, wherein the material stack comprises a first pinned fixed magnet, a spacer material, a second pinned fixed magnet, and a multilayer filter located within the material stack, the multilayer filter configured to separate the reference fixed magnet from the first pinned fixed magnet.
  • Example embodiment 2 the memory device of example embodiment 1 or 2, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet.
  • Example embodiment 3 the memory device of example embodiment 1 or 2, wherein the multilayer barrier filter comprises a first diffusion barrier, a ferromagnetic cobalt-based alloy on the diffusion barrier, and a second diffusion barrier on the cobalt-based alloy.
  • Example embodiment 4 the memory device of example embodiment 3, wherein the first diffusion barrier and the second diffusion barrier comprise a heavy metal.
  • Example embodiment 5 the memory device of example embodiment 3 or 4, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.
  • Example embodiment 6 the memory device of example embodiment 3 or 4, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to 2 nm.
  • Example embodiment 7 the memory device of example embodiment 3 or 4, wherein the ferromagnetic cobalt-based alloy comprises at least one of cobalt, iron, and boron.
  • Example embodiment 8 the memory device of example embodiment 4, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.
  • Example embodiment 9 the memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, or 8, wherein the material stack includes a synthetic antiferromagnet (SAF) stack comprising the first pinned fixed magnet, the spacer material, and the second pinned fixed magnet.
  • SAF synthetic antiferromagnet
  • Example embodiment 10 the memory device of example embodiment 1, 2, 3, 4, 5, 6, 7,
  • first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 2 nm.
  • Example embodiment 11 the memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 9 or 10, wherein the first pinned fixed magnet and the second pinned fixed magnet comprise at least one of cobalt and platinum.
  • Example embodiment 12 the memory device of example embodiment 14, or 11 wherein the multilayer barrier filter separates the first pinned fixed magnet from the reference magnet by a distance of approximately .4 to 2 nm.
  • Example embodiment 13 the memory device of example embodiment 14, or 11 wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to .4 nm.
  • Example embodiment 14 the memory device of example embodiment 1 wherein the multilayer barrier filter comprises a diffusion barrier, a ferromagnetic cobalt-based alloy on the diffusion barrier, and an fee metal on the cobalt-based alloy.
  • the multilayer barrier filter comprises a diffusion barrier, a ferromagnetic cobalt-based alloy on the diffusion barrier, and an fee metal on the cobalt-based alloy.
  • Example embodiment 15 the memory device of example embodiment 14, wherein the fee metal comprises at least one of platinum and iridium, and has a thickness of approximately .1 to .5 nm.
  • Example embodiment 16 the memory device of example embodiment 15, wherein the first pinned fixed magnet and the reference magnet are magnetically coupled and have parallel magnetic moments.
  • Example embodiment 17 the memory device of example embodiment 14, 15 or 16, wherein the fee metal provides a seed layer for fee crystallization of the first pinned fixed magnet.
  • Example embodiment 18 the memory device of example embodiment 14, 15, 16 or 17, wherein the diffusion barrier comprises tantalum or tantalum oxide and a thickness of approximately .1 to .5 nm.
  • Example embodiment 19 the memory device of example embodiment 14, 15, 16, 17 or 18, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to 2 nm.
  • a memory device comprises an interconnect having a spin orbit torque (SOT) material and a write electrode.
  • a magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a synthetic antiferromagnet (SAF) stack comprises a first pinned fixed magnet, a spacer material, and a second pinned magnet.
  • a three-layer filter is located between the reference fixed magnet and the first pinned fixed magnet, the three-layer filter. The three-layer filter comprises a first diffusion barrier on the on the reference fixed magnet; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.
  • Example embodiment 21 The memory device of claim 20, wherein the first diffusion barrier comprises one of tantalum and tantalum oxide and has a thickness of approximately .1 to .5 nm, and wherein the second diffusion barrier comprises one of tantalum, tantalum oxide, and an fee metal and has a thickness of approximately .1 to .5 nm.
  • Example embodiment 22 The memory device of claim 20 or 21, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to 2 nm.
  • Example embodiment 23 The memory device of claim 20, 21 or 22, wherein the ferromagnetic cobalt-based alloy comprises at least one of cobalt, iron, and boron.
  • Example embodiment 24 A method of fabricating an integrated circuit device comprises forming a SOT interconnect with a write electrode in an opening in a dielectric layer.
  • a MTJ material stack is formed on the SOT interconnect, and a material layer stack having a multilayer barrier filter is formed over the MTJ material stack.
  • a lithography step is performed that forms a photoresist mask on an uppermost surface of the material layer stack.
  • the material layer stack and the MTJ material stack are patterned in alignment with the photoresist mask to form a memory device.
  • a second dielectric layer is deposited over the memory device and patterning another interconnect line over the second dielectric layer.
  • Example embodiment 25 The method of claim 24, further comprises forming the multilayer barrier filter with: a first diffusion barrier; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

La présente invention concerne un dispositif de mémoire qui comprend une interconnexion ayant un matériau de couple d'orbite de spin (SOT). Un dispositif de jonction à effet tunnel magnétique (MTJ) comprend un aimant à couche libre couplé à l'interconnexion, un aimant fixe de référence, et un matériau barrière entre l'aimant à couche libre et l'aimant fixe de référence. Un empilement de matériaux se trouve sur le dispositif MTJ, l'empilement de matériaux comprenant un premier aimant fixe accroché, un matériau d'espacement, un second aimant fixe accroché, et un filtre multicouche situé à l'intérieur de l'empilement de matériaux, le filtre multicouche étant configuré pour séparer l'aimant fixe de référence du premier aimant fixe accroché.
PCT/US2018/012242 2018-01-03 2018-01-03 Couche filtrante pour une pile antiferromagnétique synthétique supérieure perpendiculaire (saf) pour une mémoire à couple d'orbite de spin (sot) WO2019135744A1 (fr)

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PCT/US2018/012242 WO2019135744A1 (fr) 2018-01-03 2018-01-03 Couche filtrante pour une pile antiferromagnétique synthétique supérieure perpendiculaire (saf) pour une mémoire à couple d'orbite de spin (sot)

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Cited By (1)

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WO2022122469A1 (fr) * 2020-12-07 2022-06-16 International Business Machines Corporation Structure de contact inférieure magnétique externe pour mram

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US20160111634A1 (en) * 2012-07-27 2016-04-21 Qualcomm Incorporated Amorphous alloy spacer for perpendicular mtjs
US20160276581A1 (en) * 2013-12-17 2016-09-22 Qualcomm Incorporated Hybrid synthetic antiferromagnetic layer for perpendicular magnetic tunnel junction (mtj)
WO2017052635A1 (fr) * 2015-09-25 2017-03-30 Intel Corporation Dispositif psttm comportant un matériau d'interface d'électrode inférieure
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WO2017222521A1 (fr) * 2016-06-22 2017-12-28 Intel Corporation Mémoire à effet hall de spin à base d'anisotropie magnétique perpendiculaire, utilisant l'effet spin-orbite

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WO2022122469A1 (fr) * 2020-12-07 2022-06-16 International Business Machines Corporation Structure de contact inférieure magnétique externe pour mram

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