WO2019182589A1 - Ingénierie d'interface d'un empilement de jonction tunnel magnétique perpendiculaire (pmtj) pour améliorer la perte de rétention à une température plus élevée - Google Patents

Ingénierie d'interface d'un empilement de jonction tunnel magnétique perpendiculaire (pmtj) pour améliorer la perte de rétention à une température plus élevée Download PDF

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Publication number
WO2019182589A1
WO2019182589A1 PCT/US2018/023632 US2018023632W WO2019182589A1 WO 2019182589 A1 WO2019182589 A1 WO 2019182589A1 US 2018023632 W US2018023632 W US 2018023632W WO 2019182589 A1 WO2019182589 A1 WO 2019182589A1
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Prior art keywords
magnet
stack
pmtj
pma
layer
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PCT/US2018/023632
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English (en)
Inventor
Tofizur RAHMAN
Christopher J. WIEGAND
Christopher Brockman
Daniel G. OUELLETTE
Juan G. ALZATE VINASCO
Angeline K. SMITH
Oleg Golonzka
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Intel Corporation
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Priority to PCT/US2018/023632 priority Critical patent/WO2019182589A1/fr
Publication of WO2019182589A1 publication Critical patent/WO2019182589A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Materials of the active region

Definitions

  • Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, interface engineering of a perpendicular magnetic tunnel junction (PMTJ) stack to improve retention loss of a PSSTM device at higher temperature.
  • PMTJ perpendicular magnetic tunnel junction
  • Magnetic tunnel junction (MTJ) devices and perpendicular MTJ devices (PMTJ) that typically have a fixed magnetic layer and a free magnetic layer separated by a tunneling barrier layer utilize a phenomenon known as tunneling magnetoresistance (TMR).
  • TMR tunneling magnetoresistance
  • the PMTJ can be switched between two states of electrical resistance, one state having a low- resistance and one state with a high resistance.
  • an MTJ device is in a spin-transferred torque (STT) memory where the MTJ is the basic storage unit used in STT random access memory (STT-RAM or STT-MRAM) devices.
  • STT spin-transferred torque
  • STT-RAM STT random access memory
  • STT-MRAM STT random access memory
  • current-induced magnetization switching may be used to set the bit states.
  • Polarization states of a first (free) ferromagnetic layer can be switched relative to a fixed polarization of the second (fixed) ferromagnetic layer via the spin transfer torque phenomenon, enabling states of the MTJ to be set by application of current.
  • Angular momentum (spin) of the electrons may be polarized through one or more structures and techniques (e.g., direct current, spin-hall effect, etc.).
  • spin-polarized electrons can transfer their spin angular momentum to the magnetization of the free layer and cause it to precess.
  • the magnetization of the free magnetic layer can be switched by a pulse of current that exceeds a certain critical value, while magnetization of the fixed magnetic layer remains unchanged as long as the current pulse is below some higher threshold associated with the fixed layer architecture.
  • shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality.
  • the drive for ever-more functionality, however, is not without issue.
  • the necessity to optimize the performance of each device becomes increasingly significant.
  • FIG. 1 illustrates a cross-sectional view of a state-of-the-art PMTJ.
  • FIG. 2 illustrates a cross-sectional view of a PMTJ memory device having PMA booster layer in accordance with a first embodiment.
  • FIG. 3 is a graph comparing retention bit errors between the PMTJ memory device shown in FIG. 1 and the PMTJ memory device having a PMA booster material shown in FIG. 2.
  • FIG. 4 illustrates a cross-sectional view of a logic region together with a PSTT-MRAM memory array integrated on a common substrate, in accordance with an embodiment of the present invention
  • FIGS. 5 A and 5B illustrate a wafer composed of semiconductor material and that includes one or more dies having integrated circuit (IC) structures formed on a surface of the wafer.
  • IC integrated circuit
  • FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer.
  • IC integrated circuit
  • FIG. 7 illustrates a computing device in accordance with one implementation of the disclosure.
  • Embodiments for interface engineering of a perpendicular magnetic tunnel junction (PMTJ) stack to improve retention loss of a PSTTM are described.
  • numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure.
  • the various embodiments shown in the FIGS are illustrative representations and are not necessarily drawn to scale.
  • One or embodiments of the present invention is directed to increasing perpendicular anisotropy through interface engineering of a PMTJ device having a perpendicular (out of a plane of a substrate) magnetic easy axis, and more particularly through an increased number of interfaces in the PMTJ device by adding a perpendicular magnetic anisotropy (PMA) booster material.
  • PMA perpendicular magnetic anisotropy
  • use of the PMA booster material in a PMTJ device increases PMA of the PMTJ device, which controls thermal stability. Therefore, the PMA booster material improves retention loss of a STTM device employing such PMTJs, where such a device is referred to herein as PSTTM.
  • PMTJ material stacks In accordance with an embodiment of the present invention, described herein are PMTJ material stacks, PSTTM devices employing such material stacks, and computing platforms employing such PSTTM devices.
  • Applications for embodiments described herein include embedded memory, embedded non-volatile memory (NVM), magnetic random access memory (MRAM), and non-embedded or stand-alone memories.
  • NVM embedded non-volatile memory
  • MRAM magnetic random access memory
  • one or more embodiments target the use or application of a perpendicular magnetic tunnel junction (PMTJ) device comprising a free layer magnet, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet.
  • a material stack is on the PMTJ device, wherein the material stack comprises a first cap material, a second free layer magnet, and a second cap material.
  • a PMA booster material comprising one or more layers is located within the material stack to increase perpendicular anisotropy based on an increased number of interfaces in the PMTJ.
  • the PMTJ further includes a synthetic anti-ferromagnet (SAF) stack disposed between the MTJ device and a bottom electrode.
  • SAF synthetic anti-ferromagnet
  • FIG. 1 illustrates a cross-sectional view of a state-of-the-art PMTJ.
  • the PMTJ device 100 formed over a substrate 102 comprises a botom electrode 104, a synthetic anti-ferromagnet (SAF) stack 106 over the bottom electrode 104, a PMTJ device stack 108 over the SAF stack 106, and a material stack 110 over the PMTJ device stack 108.
  • SAF synthetic anti-ferromagnet
  • the MTJ and PMTJ device stacks store data as a resistance state value.
  • the PMTJ device stack 108 comprises two independent ferromagnetic layers referred to as a reference layer magnet 112 and a free layer nanomagnet 116 that are separated by an insulating tunneling barrier material 114.
  • the barrier material 114 should be sufficiently thin (e.g., ⁇ 4 nm) such that electrons can tunnel there through.
  • the magnetic field of the free layer magnet 116 is free to rotate based on a direction of a current, i.e., the spin of the electrons, flowing through the PMTJ device stack 108.
  • the reference layer magnet 112 has a fixed magnetization, and is therefore referred to as a fixed or reference layer.
  • the PMTJ device 100 functions essentially as a resistor, where the resistance of an electrical path through the PMTJ device 100 may exist in two resistive states, either“high” or “low,” depending on the direction or orientation of magnetization in the free layer magnet 116 and in the reference layer magnet 112. In the case that the directions of magnetization in the free layer magnet 116 and the reference layer magnet 112 are substantially opposed or anti-parallel with one another, a high resistive state exists. In the case that the directions of magnetization in the coupled free layer magnet 116 and the reference layer magnet 112 are substantially aligned or parallel with one another, a low resistive state exists. It is to be understood that the terms “low” and“high” with regard to the resistive state of the PMTJ device 100 are relative to one another.
  • the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa.
  • the low and high resistive states can represent different bits of information (i.e. a“0” or a“1”) stored in the free layer magnet 116.
  • the SAF stack 106 below the PMTJ device stack 108 may allow for cancelling dipole fields around the free layer magnet 116.
  • the material stack 110 on the PMTJ device stack 108 comprises a first cap material 118, another protective layer 120 on the first cap material 118, a second cap material 122 on the protective layer 120, and a hard mask material 124 on the metal cap layer 122.
  • free layer magnets 116 and the reference fixed magnet 112 may comprise a single ferromagnetic metal and/or alloys of Fe, Co, Ni themselves or single ferromagnetic metals and alloys thereof with a nonmagnetic material (including but not limited to B, Pt, Pd), Co x FeyB z (Cobalt, Iron, Boron), where‘x,’‘y,’ and‘z’ are integers, FexPty, CoFe, CoFeNi and the like].
  • the barrier material 114 may comprise oxides of magnesium (Mg) and aluminum (Al), such as MgO, AlOx, and MgAlOx. In the embodiment where the barrier material 214 comprises MgO, the barrier material may have a thickness of approximately 3-40 A.
  • the protective layer 120 may a ferromagnetic metal including Fe, Co, B, and Ni, and alloys thereof. In one embodiment, the protective layer 120 may have a thickness of 2-20A in the case the protective layer 120 comprises CoFeB.
  • the first cap material 118 may comprise an oxide of multiple metals including but not limited to Mg, Al, Ta, W, Mo, Ru, and Hf.
  • the first cap material 218 comprises one of MgO, AlOx, MgAlOx, MgRuOx, MgHfOx, WO x , HfOx, TaOx, and MoOx.
  • the second cap materiall22 may include a metal, such as Tantalum (Ta).
  • the SAF stack 106 may include layers of cobalt (Co) and/or platinum (Pt), Nickel (Ni), Palladium (Pd), and alloys of magnetic and nonmagnetic materials. In alternative embodiments, other materials may be used to form the PMTJ device stack 108.
  • the bottom electrode 104 may include electrically conductive material such as titanium, aluminum, copper, tungsten, poly silicon, alloys, and the like.
  • the bottom electrode 104 is configured to conduct control currents Ic through the PMTJ device stack 108 to control a direction of magnetic polarization of the free layer magnet 116. Also, a read of the current state, e.g., a parallel state or antiparallel state, of the PMTJ device stack 108 may be determined through application of control currents Ic through the PMTJ device stack 108.
  • the PMTJ device stack 108 having a perpendicular axis has a potential for realizing higher density memory than in-plane variants.
  • perpendicular magnetic anisotropy can be achieved in the free layer magnet 116 through interfacial perpendicular anisotropy established by an adjacent layer, such as a magnesium oxide (MgO) tunnel barrier material 114, when the free layer magnet 116 is sufficiently thin.
  • MgO magnesium oxide
  • the PMA may also be aided by a free layer magnet
  • a PSTTM i.e., a STTM utlizing a PMTJ device
  • PMTJ device stability improve PMTJ device stability during heat exposure.
  • a memory device such as a PSTTM are described, in which interfacial PMA is enhanced through additional material layers or regions added to the PMTJ device stack that improve PMA of the PMTJ device and provide thermal stability, as shown in FIG. 2.
  • FIG. 2 illustrates a cross-sectional view of a PMTJ memory device 200 having PMA booster layer in accordance with a first embodiment.
  • the PMTJ device 200 formed over a substrate 202 comprises a bottom electrode 204, a synthetic anti- ferromagnet (SAF) stack 206 over the bottom electrode 204, a PMTJ device stack 208 over the SAF stack 206, and a material stack 210 over the PMTJ device stack 208.
  • SAF synthetic anti- ferromagnet
  • the PMTJ device stack 208 comprises two independent ferromagnetic layers referred to as a reference layer magnet 212 and a first free layer nanomagnet 216 that are separated by an insulating tunneling barrier material 214.
  • the material stack 210 on the PMTJ device stack 208 comprises a first cap material 218, a second free layer magnet 220 on the first cap material 218, a second cap material 222, and a hard mask material 224 on the metal cap layer 222.
  • the material stack 210 is provided with a PMA booster material 226 comprising one or more layers within the material stack 210 to increase the perpendicular magnetic anisotropy (PMA) of the PMTJ device stack 208 based on an increased number of interfaces in the PMTJ memory device 200.
  • the PMA booster material 226 is on the free layer magnet 220.
  • a protective layer 228 is added on the PMA booster material 226 to protect the PMA booster material 226.
  • the PMA booster material 226 can be same as or different than cap material 218 and may comprise a metal layer, such as Tungsten (W), Molybdenum (Mo) and/or an oxide layer, such as magnesium oxide (MgO) , aluminum oxide, or tungsten oxide (WOx) .
  • the barrier material 214 may comprise oxides of magnesium (Mg) and aluminum (Al), such as MgO, AlOx, and MgAlOx. In the embodiment where the barrier material 214 comprises MgO, the barrier material may have a thickness of approximately 3-40 A.
  • the protective layer 228 may comprise a ferromagnetic metal including Fe, Co, B, and Ni, and alloys thereof. In one embodiment, the protective layer 228 may comprise Co x FeyB z (Cobalt, Iron, Boron), where‘x,’ ‘y,’ and‘z’ are integers, and may have a thickness of 2-15 A.
  • the first cap material 218 may or may not be same as PMA booster layer 226 and may comprise an oxide of multiple metals including as Mg, Al and Hf.
  • the first cap material 218 comprises one of MgO, AlO x , MgAlOx, MgRuOx, MgHfOx, WOx, HfOx,
  • the reference fixed magnet 212 and the free layer magnets 216, 220 may also comprise Co x FeyB z .
  • the second cap material 222 may comprise a metal, such as Tantalum (Ta).
  • the SAF stack 106 may include layers of cobalt (Co) and/or platinum (Pt). In alternative embodiments, other materials may be used to form the PMTJ device stack 108.
  • the PMTJ memory device 200 includes the following barrier-magnet interfaces: a first barrier-magnet interface 230 between the barrier material 214 and first free layer magnet 216; a second barrier-magnet interface 232 between the first free layer magnet 216 and the first cap material 218; and a third barrier-magnet interface 234 between the first cap material 218 and the second free layer magnet.
  • PMA in the PMTJ device stack 208 typically originates from barrier- magnet interface 230 from oxygen from the MgO barrier material 214 and iron from the free layer magnet 216. By increasing the number of interfaces, the PMA interface contribution is multiplied.
  • Providing the PMA booster material 226 provides an additional fourth barrier-magnet interface 236 to the PMTJ memory device 200 between the second free layer magnet 220 and the PMA booster material 226.
  • the PMA booster material 226 and the barrier material 214 are the same thickness. In another embodiment, the thickness of the PMA booster material 226 may be less than the thickness of the barrier material 214.
  • the bottom electrode 204 may include electrically conductive material such as titanium, aluminum, copper, tungsten, polysilicon, alloys, and the like.
  • the bottom electrode 204 is configured to conduct control currents Ic through the PMTJ device stack 208 to control a direction of magnetic polarization of the free layer magnet 216. Also, a read of the current state, e.g., a parallel state or antiparallel state, of the PMTJ device stack 208 may be determined through application of control currents Ic through the PMTJ device stack 208.
  • FIG. 3 is a graph comparing retention bit errors between the PMTJ memory device 100 shown in FIG. 1 and the PMTJ memory device 200 having a PMA booster material shown in FIG. 2.
  • Three different sizes of both PMTJ memory device 100 and 200 were tested, where the sizes“1”,“2”,“3” represent increasing larger sizes (e.g., 45x45 nm).
  • the three sizes of PMTJ memory device 100 and 200 were heated at temperatures of 165C, 185C, 200C and 220C for 24 hours each, and then measured for retention loss, which is represented by % bit error.
  • the results show that all three sizes of the both PMTJ memory devices 100 and 200 have 0% bit error at 165C and 185C.
  • the PMTJ memory device 100 displays between .5 - 4% bit errors, while the PMTJ memory device 200 remains at 0% bit error.
  • the PMTJ device 100 displays between 60-64 % bit error.
  • the PMTJ device 200 clearly shows the advantage of the PMA booster material 226 by reducing the bit error to approximately 50% from 60-64 %. This improvement is attributed to the higher perpendicular anisotropy from the increased number of interfaces provided by the PMA boosting material 226.
  • a structure in which spin transfer torque random access memory (STT-MRAM) employ a multitude of perpendicular magnetic tunnel junctions (PMTJs), and is referred to as a PSTTM.
  • the array of PMTJs are embedded within a back-end interconnect layer of a high performance logic chip.
  • PMTJs perpendicular magnetic tunnel junctions
  • the combination of "thin vias" beneath the PMTJs, the presence of an MRAM pedestal material beneath the PMTJs, and an PMTJ-first type process flow where the PMTJs are fabricated prior to the interconnect in the neighboring logic area is disclosed.
  • FIG. 4 illustrates a cross-sectional view of a logic region together with a PSTT-MRAM memory array integrated on a common substrate, in accordance with an embodiment of the present invention.
  • a structure 400 includes a logic region 402 and a PSTT- MRAM array region 404 adjacent to the logic region.
  • metal 2 (M2) 408 and via 1 (VI) 410 pairing structures are formed above a substrate 406.
  • the M2 408 and VI 410 structures are formed in an inter-layer dielectric layer 412 disposed over an etch stop layer 414.
  • This geometric structure should not, however, be interpreted as limiting, as MTJ devices may be formed horizontally, radially, or otherwise, as well as vertically.
  • a plurality of conductive pedestals 416 and corresponding PMTJ memory devices 418 are formed in an inter-layer dielectric layer 420 disposed over an etch stop layer 422.
  • the PMTJ memory devices 418 comprise a PMTJ stack 208 and material stack 210 having a PMA booster material 226 and an optional protective layer 228.
  • Each of the PMTJ stacks may include a free layer MTJ film or films 428, a dielectric or tunneling layer 430, a fixed layer MTJ film or films 432, and a bottom electrode and top electrode 434.
  • the PMTJ stack may be reversed, in that layer 428 may be a fixed layer while layer 432 may be a free layer.
  • the plurality of conductive pedestals 416 may be coupled to corresponding ones of the M2 408 structures by a conductive layer 424.
  • a dielectric spacer layer 426 may be formed on sidewalls of the PMTJ memory devices 418 and on the upper surface of the plurality of conductive pedestals 416.
  • an etch stop layer 436 is disposed on the inter-layer dielectric layer 420.
  • Metal 4 (M4) 438 and via to junction (VTJ) 440 structures are formed in an inter-layer dielectric layer 442 disposed over the etch stop layer 436.
  • additional interconnect layer(s) may be formed on top of the M4/VTJ layers of the PSST-MRAM array region 404 of FIG. 4, e.g., using standard dual damascene process techniques that are well- known in the art.
  • M3 logic metal 3
  • the free layer MTJ film or films 428 (or, alternatively, 432) is composed of a material suitable for transitioning between a majority spin and a minority spin, depending on the application.
  • the free magnetic layer (or memory layer) may be referred to as a ferromagnetic memory layer.
  • the free magnetic layer is composed of a layer of cobalt iron (CoFe) or cobalt iron boron (CoFeB).
  • the dielectric or tunneling layer 430 is composed of a material suitable for allowing current of a majority spin to pass through the layer, while impeding at least to some extent current of a minority spin to pass through the layer.
  • the dielectric layer is composed of a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI203).
  • the dielectric layer has a thickness of
  • the fixed layer MTJ film or films 432 (or 428 in the case that 432 is a free layer) is composed of a material or stack of materials suitable for maintaining a fixed majority spin.
  • the fixed magnetic layer (or reference layer) may be referred to as a ferromagnetic layer.
  • the fixed magnetic layer is composed of a single layer of cobalt iron boron (CoFeB).
  • the fixed magnetic layer is composed of a cobalt iron boron (CoFeB) layer, ruthenium (Ru) layer, cobalt iron boron (CoFeB) layer stack.
  • a synthetic antiferromagnet (SAF) is disposed on or adjacent the fixed layer MTJ film or films 432.
  • the plurality of conductive pedestals 416 includes a thick metal layer, such as a relatively thick titanium nitride (TiN) layer.
  • the conductive metal layer 424 is a tantalum nitride (TaN) layer.
  • the conductive metal layer 424 is referred to as a "thin via" layer.
  • one or more interlayer dielectrics such as inter-layer dielectric material layers 412, 420 and 442, are used.
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S102), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the 1LD layers may include pores or air gaps to further reduce their dielectric constant.
  • the metal lines and vias are composed of one or more metal or other conductive structures.
  • a common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material.
  • the term metal includes alloys, stacks, and other combinations of multiple metals.
  • the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc.
  • the interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal, or simply interconnect.
  • etch stop materials are composed of dielectric materials different from the interlayer dielectric material.
  • an etch stop layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof.
  • Other suitable materials may include carbon-based materials, such as silicon carbide.
  • the dielectric spacer layer 426 is a silicon nitride layer.
  • substrate 406 (or substrate 102 or 102 described below in association with FIGS. 1 and 2, respectively) is a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon- on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.
  • germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built
  • an underlying semiconductor substrate 102, 202 or 406 represents a general workpiece object used to manufacture integrated circuits.
  • the semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials.
  • SOI silicon on insulator
  • the semiconductor substrate depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like.
  • the substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
  • the illustrated structures depicted in FIGS. 1, 2 and 4 are fabricated on underlying transistor or other semiconductor device layer(s) formed in or above the substrate 102, 202 or 406. In another embodiment, the illustrated structures depicted in FIGS. 1, 2 and 4 are fabricated on underlying lower level interconnect layers formed above the substrate 102, 202 or 406.
  • a "free" magnetic layer is a magnetic layer storing a computational variable.
  • a "fixed” magnetic layer is a magnetic layer with fixed magnetization (magnetically harder than the free magnetic layer).
  • a tunneling barrier such as a tunneling dielectric or tunneling oxide, is one located between free and fixed magnetic layers.
  • a fixed magnetic layer may be patterned to create inputs and outputs to an associated circuit. Magnetization may be written by spin hall effect. Magnetization may be read via the tunneling magneto-resistance effect while applying a voltage.
  • the role of the dielectric layer is to cause a large magneto-resistance ratio.
  • the magneto- resistance is the ratio of the difference between resistances when the two ferromagnetic layers have anti-parallel magnetizations and the resistance of the state with the parallel magnetizations.
  • the MTJ functions essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either "high” or "low,” depending on the direction or orientation of magnetization in the free magnetic layer and in the fixed magnetic layer.
  • the spin direction is of minority in the free magnetic layer
  • a high resistive state exists, wherein direction of magnetization in the free magnetic layer and the fixed magnetic layer are substantially opposed or anti-parallel with one another.
  • a low resistive state exists, wherein the direction of magnetization in the free magnetic layer and the fixed magnetic layer is substantially aligned or parallel with one another.
  • the terms “low” and “high” with regard to the resistive state of the MTJ are relative to one another.
  • the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa.
  • the low and high resistive states can represent different bits of information (i .e. a "0" or a "1").
  • the MTJ may store a single bit of information ("0" or "1") by its state of magnetization.
  • the information stored in the MTJ is sensed by driving a current through the MTJ.
  • the free magnetic layer does not require power to retain its magnetic orientations. As such, the state of the MTJ is preserved when power to the device is removed. Therefore, a memory bit cell such as depicted in FIG. 1 is, in an embodiment, non-volatile.
  • each bit of data is stored in a separate magnetic tunnel junction (MTJ).
  • the MTJ is a magnetic element that includes two magnetic layers separated by a thin insulating tunnel barrier layer.
  • One of the magnetic layers is referred to as the reference layer, the fixed layer, or the pinned magnetic layer, and it provides a stable reference magnetic orientation.
  • the bit is stored in the second magnetic layer which is called the free layer, and the orientation of the magnetic moment of the free layer can be either in one of two states— parallel to the reference layer or anti-parallel to the reference layer. Because of the tunneling magneto-resistance (TMR) effect, the electrical resistance of the anti-parallel state is significantly higher compared to the parallel state.
  • TMR tunneling magneto-resistance
  • the spin transfer torque effect is used to switch the free layer from the parallel to anti-parallel state and vice versa.
  • the passing of current through the MTJ produces spin polarized current, which results in a torque being applied to the magnetization of the free layer.
  • the sensing circuitry measures the resistance of the MTJ. Since the sensing circuitry needs to determine whether the MTJ is in the low resistance (e.g. parallel) state or in the high resistance state (e.g. anti-parallel) with acceptable signal-to-noise, the STT-MRAM cell needs to be designed such that the overall electrical resistance and resistance variation of the cell are minimized.
  • Embodiments described herein include a fabrication method for embedding STT-MRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.
  • a wafer 500 may be composed of semiconductor material and may include one or more dies 502 having integrated circuit (IC) structures formed on a surface of the wafer 500.
  • IC integrated circuit
  • Each of the dies 502 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer, such as described above.
  • the wafer 500 may undergo a singulation process in which each of the dies 502 is separated from one another to provide discrete“chips” of the semiconductor product.
  • structures that include embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer as disclosed herein may take the form of the wafer 500 (e.g., not singulated) or the form of the die 502 (e.g., singulated).
  • the die 502 may include one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer and/or supporting circuitry to route electrical signals, as well as any other IC components.
  • the wafer 500 or the die 502 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element.
  • SRAM static random access memory
  • logic device e.g., an AND, OR, NAND, or NOR gate
  • a memory array formed by multiple memory devices may be formed on a same die 502 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
  • FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer, in accordance with one or more of the embodiments disclosed herein.
  • IC integrated circuit
  • an IC device assembly 600 includes components having one or more integrated circuit structures described herein.
  • the IC device assembly 600 includes a number of components disposed on a circuit board 602 (which may be, e.g., a motherboard).
  • the IC device assembly 600 includes components disposed on a first face 640 of the circuit board 602 and an opposing second face 642 of the circuit board 602.
  • components may be disposed on one or both faces 640 and 642.
  • any suitable ones of the components of the IC device assembly 600 may include a number of embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer, such as disclosed herein.
  • the circuit board 602 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 602.
  • the circuit board 602 may be a non-PCB substrate.
  • the IC device assembly 600 illustrated in FIG. 6 includes a package-on-interposer structure 636 coupled to the first face 640 of the circuit board 602 by coupling components 616.
  • the coupling components 616 may electrically and mechanically couple the package-on- interposer structure 636 to the circuit board 602, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 636 may include an IC package 620 coupled to an interposer 604 by coupling components 618.
  • the coupling components 618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 616. Although a single IC package 620 is shown in FIG. 8, multiple IC packages may be coupled to the interposer 604. It is to be appreciated that additional interposers may be coupled to the interposer 604.
  • the interposer 604 may provide an intervening substrate used to bridge the circuit board 602 and the IC package 620.
  • the IC package 620 may be or include, for example, a die (the die 702 of FIG. 7B), or any other suitable component.
  • the interposer 604 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 604 may couple the IC package 620 (e.g., a die) to a ball grid array (BGA) of the coupling components 616 for coupling to the circuit board 602.
  • BGA ball grid array
  • the IC package 620 and the circuit board 602 are attached to opposing sides of the interposer 604.
  • the IC package 620 and the circuit board 602 may be attached to a same side of the interposer 604.
  • three or more components may be interconnected by way of the interposer 604.
  • the interposer 604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer 604 may include metal interconnects 610 and vias 608, including but not limited to through-silicon vias (TSVs) 606.
  • TSVs through-silicon vias
  • the interposer 604 may further include embedded devices 614, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 604.
  • RF radio-frequency
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 636 may take the form of any of the package-on-interposer structures known in the art.
  • the IC device assembly 600 may include an IC package 624 coupled to the first face 640 of the circuit board 602 by coupling components 622.
  • the coupling components 622 may take the form of any of the embodiments discussed above with reference to the coupling components 616
  • the IC package 624 may take the form of any of the embodiments discussed above with reference to the IC package 620.
  • the IC device assembly 600 illustrated in FIG. 6 includes a package-on-package structure 634 coupled to the second face 642 of the circuit board 602 by coupling components 628.
  • the package-on-package structure 634 may include an IC package 626 and an IC package 632 coupled together by coupling components 630 such that the IC package 626 is disposed between the circuit board 602 and the IC package 632.
  • the coupling components 628 and 630 may take the form of any of the embodiments of the coupling components 616 discussed above, and the IC packages 626 and 632 may take the form of any of the embodiments of the IC package 620 discussed above.
  • the package-on-package structure 634 may be configured in accordance with any of the package-on-package structures known in the art.
  • FIG. 7 illustrates a computing device 700 in accordance with one implementation of the disclosure.
  • the computing device 700 houses a board 702.
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one
  • the processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700.
  • the term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706.
  • a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704.
  • the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer, in accordance with implementations of embodiments of the disclosure.
  • the term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.
  • the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer, in accordance with implementations of embodiments of the disclosure.
  • another component housed within the computing device 700 may contain an integrated circuit die that includes one or more embedded non-volatile memory structures having a PMTJ memory device having PMA booster layer, in accordance with implementations of embodiments of the disclosure.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • embodiments described herein include embedded non-volatile memory structures having PMTJ memory device having PMA booster layer elements.
  • a memory device comprises a perpendicular magnetic tunnel junction (PMTJ) stack disposed above a substrate.
  • the PMTJ stack has a first free layer magnet, a reference fixed magnet, and a barrier material between the first free layer magnet and the reference fixed magnet.
  • a material stack is on the PMTJ device, where the material stack comprises a first cap material, a second free layer magnet, and a perpendicular magnetic anisotropy (PMA) booster material to increase PMA of the PMTJ stack.
  • PMTJ perpendicular magnetic tunnel junction
  • Example embodiment 2 the memory device of example embodiment 1, wherein the PMA booster material is on the second free layer magnet.
  • Example embodiment 3 the memory device of example embodiment 1 or 2, wherein the PMA booster material comprises an oxide.
  • Example embodiment 4 the memory device of example embodiment 3, wherein the PMA booster material comprises one of magnesium oxide and aluminum oxide.
  • Example embodiment 5 the memory device of example embodiment 1 or 2, wherein the PMA booster material provides an additional barrier-magnet interface to the memory device.
  • Example embodiment 6 the memory device of example embodiment 1, 2, 3, 4 or 5, wherein the memory device includes a first barrier-magnet interface between the barrier material and first free layer magnet; a second barrier-magnet interface between the first free layer magnet and the first cap material; a third barrier-magnet interface between the first cap material and the second free layer magnet; and a fourth barrier-magnet interface between the second free layer magnet and the PMA booster material.
  • Example embodiment 7 the memory device of example embodiment 1, further comprising a protective layer on the PMA booster material, wherein the protective layer comprises a ferromagnetic metal and alloys thereof.
  • Example embodiment 8 the memory device of example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the protective layer, the reference fixed magnet, the first free layer magnet, and the second free layer magnet each comprise at least cobalt and iron.
  • Example embodiment 9 the memory device of example embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the material stack further includes a second cap material and a hard mask on the second cap material.
  • Example embodiment 10 the memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the first cap material comprises one of MgO, AlOx, MgAlOx, MgRuOx, MgHfOx, WOx, HfOx.
  • Example embodiment 11 the memory device of example embodiment 9 or 10, wherein the second cap material is over the PMA booster material.
  • Example embodiment 12 the memory device of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the PMTJ stack material is over a synthetic anti-ferromagnet (SAF) stack.
  • SAF synthetic anti-ferromagnet
  • Example embodiment 13 the memory device of example embodiment 12, wherein the SAF stack is over a bottom electrode.
  • Example embodiment 14 the memory device of example embodiment 12 or 13, wherein the SAF stack comprises at least one of cobalt and platinum.
  • a memory device comprises a perpendicular magnetic tunnel junction (PMTJ) stack disposed above a substrate, the PMTJ stack having a first free layer magnet, a reference fixed magnet, and a barrier material between the first free layer magnet and the reference fixed magnet.
  • a material stack is on the PMTJ device. The material stack comprises a first cap material, a second free layer magnet on the first cap material, a
  • PMA perpendicular magnetic anisotropy
  • Example embodiment 16 the memory device of example embodiment 15, wherein the memory device includes a first barrier-magnet interface between the barrier material and first free layer magnet; a second barrier-magnet interface between the first free layer magnet and the first cap material; a third barrier-magnet interface between the first cap material and the second free layer magnet; and a fourth barrier-magnet interface between the second free layer magnet and the PMA booster material.
  • Example embodiment 17 the memory device of example embodiment 15 or 16, wherein the PMA booster material comprises one of magnesium oxide and aluminum oxide.
  • Example embodiment 18 the memory device of example embodiment 15, 16 or 17, wherein the protective layer comprises a ferromagnetic metal and alloys thereof.
  • Example embodiment 19 the memory device of example embodiment 15, 16, 17 or 18, wherein the first cap material comprises one of MgO, AlOx, MgAlOx, MgRuOx, MgHfOx, WOx, HfO.
  • Example embodiment 20 a method of fabricating memory structure comprises forming a plurality of first metal and first via pairing structures disposed in a first dielectric layer disposed above a substrate.
  • a plurality of conductive pedestals and corresponding PMTJ memory devices are formed in a first inter-layer dielectric layer disposed over an etch stop layer, wherein ones of the PMTJ memory devices comprise a PMTJ stack and a material stack having a perpendicular magnetic anisotropy (PMA) booster material.
  • a dielectric spacer layer is formed on sidewalls of the PMTJ memory devices and on an upper surface of the plurality of conductive pedestals.
  • an etch stop layer is disposed on the first inter-layer dielectric layer and second metal and via to junction (VTJ) structures are formed in a second inter-layer dielectric layer disposed over the etch stop layer.
  • VTJ via to junction
  • Example embodiment 21 the method of example embodiment 20, further comprises forming the PMTJ stack with a first free layer magnet, a reference fixed magnet, and a barrier material between the first free layer magnet and the reference fixed magnet.
  • Example embodiment 22 the method of example embodiment 20 or 21, further comprising forming the PMTJ material stack with: a first cap material, a second free layer magnet on the first cap material, the PMA booster material on the second free layer magnet to increase PMA of the PMTJ stack, a protective layer on the PMA booster material to protect the PMA booster material, a second cap material on the protective layer, and a hard mask on the second cap material.
  • Example embodiment 23 the method of example embodiment 20, 21, or 22, further comprising forming the ones of the PMTJ memory devices with: a first barrier-magnet interface between the barrier material and first free layer magnet; a second barrier-magnet interface between the first free layer magnet and the first cap material; a third barrier-magnet interface between the first cap material and the second free layer magnet; and a fourth barrier-magnet interface between the second free layer magnet and the PMA booster material.
  • Example embodiment 24 the method of example embodiment 20, 21, 22 or 23, further comprising fabricating the memory structure adjacent to a logic region.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

Un dispositif de mémoire comprend un empilement de jonction tunnel magnétique perpendiculaire (PMTJ) disposé au-dessus d'un substrat. L'empilement PMTJ comprend un premier aimant à couche libre, un aimant fixe de référence, et un matériau barrière entre le premier aimant à couche libre et l'aimant fixe de référence. Un empilement de matériaux est sur le dispositif PMTJ, l'empilement de matériaux comprenant un premier matériau de capot, un second aimant à couche libre, et un matériau de renforcement d'anisotropie magnétique perpendiculaire (PMA) pour augmenter la PMA de l'empilement PMTJ.
PCT/US2018/023632 2018-03-21 2018-03-21 Ingénierie d'interface d'un empilement de jonction tunnel magnétique perpendiculaire (pmtj) pour améliorer la perte de rétention à une température plus élevée WO2019182589A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951980A (zh) * 2019-12-11 2021-06-11 上海磁宇信息科技有限公司 一种磁性隧道结垂直各向异性场增强层及随机存储器
CN113013322A (zh) * 2019-12-19 2021-06-22 上海磁宇信息科技有限公司 一种具垂直各向异性场增强层的磁性隧道结单元结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120280336A1 (en) * 2011-05-04 2012-11-08 Magic Technologies, Inc. Multilayers having reduced perpendicular demagnetizing field using moment dilution for spintronic applications
US20140175582A1 (en) * 2012-12-20 2014-06-26 Dmytro Apalkov Method and system for providing magnetic junctions having engineered perpendicular magnetic anisotropy
US20150102441A1 (en) * 2010-12-10 2015-04-16 Avalanche Technology, Inc. Magnetic random access memory having perpendicular enhancement layer and thin reference layer
US20160155931A1 (en) * 2014-12-02 2016-06-02 Qualcomm Incorporated Magnetic etch stop layer for spin-transfer torque magnetoresistive random access memory magnetic tunnel junction device
WO2017155508A1 (fr) * 2016-03-07 2017-09-14 Intel Corporation Approches pour intégrer des matrices mémoire stt-mram dans un processeur logique, et structures ainsi obtenues

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150102441A1 (en) * 2010-12-10 2015-04-16 Avalanche Technology, Inc. Magnetic random access memory having perpendicular enhancement layer and thin reference layer
US20120280336A1 (en) * 2011-05-04 2012-11-08 Magic Technologies, Inc. Multilayers having reduced perpendicular demagnetizing field using moment dilution for spintronic applications
US20140175582A1 (en) * 2012-12-20 2014-06-26 Dmytro Apalkov Method and system for providing magnetic junctions having engineered perpendicular magnetic anisotropy
US20160155931A1 (en) * 2014-12-02 2016-06-02 Qualcomm Incorporated Magnetic etch stop layer for spin-transfer torque magnetoresistive random access memory magnetic tunnel junction device
WO2017155508A1 (fr) * 2016-03-07 2017-09-14 Intel Corporation Approches pour intégrer des matrices mémoire stt-mram dans un processeur logique, et structures ainsi obtenues

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951980A (zh) * 2019-12-11 2021-06-11 上海磁宇信息科技有限公司 一种磁性隧道结垂直各向异性场增强层及随机存储器
CN113013322A (zh) * 2019-12-19 2021-06-22 上海磁宇信息科技有限公司 一种具垂直各向异性场增强层的磁性隧道结单元结构
CN113013322B (zh) * 2019-12-19 2023-07-25 上海磁宇信息科技有限公司 一种具垂直各向异性场增强层的磁性隧道结单元结构

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