WO2019130633A1 - Procédé d'évaluation de tranche de silicium - Google Patents

Procédé d'évaluation de tranche de silicium Download PDF

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Publication number
WO2019130633A1
WO2019130633A1 PCT/JP2018/027425 JP2018027425W WO2019130633A1 WO 2019130633 A1 WO2019130633 A1 WO 2019130633A1 JP 2018027425 W JP2018027425 W JP 2018027425W WO 2019130633 A1 WO2019130633 A1 WO 2019130633A1
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Prior art keywords
silicon wafer
distortion
evaluation method
sections
determined
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PCT/JP2018/027425
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English (en)
Japanese (ja)
Inventor
治生 須藤
延恵 荒木
和樹 岡部
荒木　浩司
Original Assignee
グローバルウェーハズ・ジャパン株式会社
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Priority to CN201880083802.XA priority Critical patent/CN111512424B/zh
Priority to EP18894615.6A priority patent/EP3734648A4/fr
Priority to KR1020207021707A priority patent/KR102385259B1/ko
Priority to US16/957,612 priority patent/US11060983B2/en
Publication of WO2019130633A1 publication Critical patent/WO2019130633A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/16—Measuring arrangements characterised by the use of optical techniques for measuring the deformation in a solid, e.g. optical strain gauge
    • G01B11/168—Measuring arrangements characterised by the use of optical techniques for measuring the deformation in a solid, e.g. optical strain gauge by means of polarisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/24—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet
    • G01L1/241—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet by photoelastic stress analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L5/00—Apparatus for, or methods of, measuring force, work, mechanical power, or torque, specially adapted for specific purposes
    • G01L5/0047—Apparatus for, or methods of, measuring force, work, mechanical power, or torque, specially adapted for specific purposes measuring forces due to residual stresses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/17—Systems in which incident light is modified in accordance with the properties of the material investigated
    • G01N21/21—Polarisation-affecting properties
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/8806—Specially adapted optical and illumination features
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G01N21/9505—Wafer internal defects, e.g. microcracks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/17—Systems in which incident light is modified in accordance with the properties of the material investigated
    • G01N21/21—Polarisation-affecting properties
    • G01N2021/217—Measuring depolarisation or comparing polarised and depolarised parts of light
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/8806—Specially adapted optical and illumination features
    • G01N2021/8848—Polarisation of light

Definitions

  • the present invention relates to a method of evaluating a silicon wafer used as a substrate of a semiconductor device.
  • a silicon wafer used as a substrate of a semiconductor device is required to form a defect-free layer called a COP (Crystal Originated Particle) free of void defects on the surface and the surface to be an active region of the semiconductor device.
  • a technique for such a demand a technique of performing batch heat treatment on a silicon wafer at a temperature of 1100 ° C. or more using a vertical furnace and a technique of performing rapid thermal processing (RTO; Rapid Thermal Process) are known. .
  • a silicon wafer may be slipped and plastically deformed due to the application of thermal stress and bending stress during heat treatment.
  • the slip is a bundle of linear dislocation defects, and depending on the degree of occurrence, it is a factor that affects the electrical characteristics of the finished semiconductor device. Therefore, it is necessary to inspect the occurrence of slips before shipment to prevent the outflow of nonconforming products.
  • a surface inspection apparatus for example, Surfscan SP2 manufactured by KLA-Tencor
  • Surfscan SP2 manufactured by KLA-Tencor used in final visual inspection of silicon wafers to detect a step caused by the occurrence of slip and detect the occurrence of slip. Inspection methods are known. Further, there is also known a method of causing distortion that is latent in the surface layer of a silicon wafer to be revealed by heat treatment (see Patent Document 1).
  • the surface inspection apparatus used in the above-mentioned final appearance inspection can be applied to an inspection for a mirror-polished wafer, since the level of noise is high when the surface is relatively rough before the mirror polishing, the slip is It is difficult to detect the level difference caused by Further, by mirror-polishing the silicon wafer after the heat treatment to be inspected, the step caused by the slip is smoothed, and it is difficult to detect the slip.
  • the slip detection method using the surface inspection apparatus used in the final appearance inspection there is a technical problem that it depends on the surface condition and processing content of the silicon wafer.
  • a method of eliciting a strain underlying a surface layer of a silicon wafer by heat treatment is also a destructive inspection in that heat treatment is performed, and can not be applied under conditions where heat treatment is not permitted.
  • the present invention has been made focusing on the above-described points, and nondestructively and non-contact the slip which affects the electrical characteristics of the semiconductor device without being restricted by the surface condition and processing content of the silicon wafer as much as possible. It is an object of the present invention to provide a silicon wafer evaluation method that can be inspected by
  • a heat-treated single crystal silicon wafer is divided into equally spaced sections of 1 mm 2 or more and 25 mm 2 or less, Section analysis step of determining the presence or absence of distortion in each of the sections based on the conversion value, and evaluation of non-defective products in which the number of adjacent sections determined to have distortion in the section analysis step does not exceed a predetermined threshold And a screening step.
  • the number of adjacent sections determined to have the distortion is defined as the total number of sections determined to have distortion in the four directions around the section determined to have the distortion. Is preferred.
  • the predetermined threshold be determined by acquiring in advance a relationship between a slip length of a silicon wafer evaluated using X-ray topography and an adjacent number of sections determined to have distortion. .
  • the measured depolarization value is subjected to smoothing processing to extract a long period component, and the long period component is extracted from the measured depolarization value. It is preferable to carry out using the short period component obtained by removing.
  • surface roughness Ra of the said silicon wafer is 0.1 micrometer or less.
  • surface roughness Ra of the said silicon wafer is 0.001 micrometer or more.
  • the present invention it is possible to nondestructively and noncontactly inspect a slip that affects the electrical characteristics of a semiconductor device without being restricted as much as possible by the surface condition and processing content of the silicon wafer.
  • FIG. 1 is a view for explaining the principle of an apparatus used in the embodiment of the present invention.
  • FIG. 2 is a graph showing an example of the measured depolarization value.
  • FIG. 3 is a diagram illustrating an example of an in-plane map of measured depolarization values.
  • FIG. 4 is a graph in which long-period components are extracted by smoothing the depolarization values shown in FIG.
  • FIG. 5 is a diagram showing an in-plane map in which a long period component is extracted from the in-plane map of the depolarization value shown in FIG.
  • FIG. 6 is a graph in which a long period component is removed from the depolarization value shown in FIG. 2 to extract a short period component.
  • FIG. 1 is a view for explaining the principle of an apparatus used in the embodiment of the present invention.
  • FIG. 2 is a graph showing an example of the measured depolarization value.
  • FIG. 3 is a diagram illustrating an example of an in-plane map of measured depolarization values.
  • FIG. 7 is a view showing an in-plane map obtained by extracting a short period component from the in-plane map of the depolarization value shown in FIG.
  • FIG. 8 is a flowchart showing a method of evaluating a silicon wafer according to the embodiment of the present invention.
  • FIG. 9 is a diagram illustrating an example of determination using the number of neighbors.
  • FIG. 10 is a graph showing the relationship between the maximum value of the number of neighbors and the slip length.
  • FIG. 11 is a view showing an in-plane map of a typical measurement example.
  • the infrared photoelasticity measuring apparatus also called a SIRD (Scanning Infrared Depolarization) apparatus can be used.
  • SIRD Scnning Infrared Depolarization
  • the strain measuring device using infrared photoelasticity measures and measures the stress applied to the sample by utilizing birefringence (photoelasticity) when polarized light passes through the stressed sample. It is an apparatus.
  • infrared light having high transmittance to silicon is generally used.
  • FIG. 1 schematically illustrates the measurement principle of the infrared photoelasticity measurement apparatus 1.
  • infrared polarized light emitted from the infrared laser element 2 passes through the silicon wafer W, and infrared polarized light transmitted through the silicon wafer W is The strain generated in the silicon wafer W is measured by measuring with the analyzer 3.
  • a polarizer 4 is provided between the infrared laser device 2 and the silicon wafer W so that infrared polarized light emitted from the infrared laser device 2 is irradiated to the silicon wafer W after passing through the polarizer 4. It is arranged. The laser emitted from the infrared laser element 2 is polarized by itself, but the polarization plane is adjusted with high accuracy by transmitting the polarizer 4.
  • the analyzer 3 includes two light receiving elements 5 and 6 and a polarization beam splitter 7.
  • the polarization beam splitter 7 guides only the polarized light having the same polarization plane as the polarized light transmitting the polarizer 4 to the light receiving element 5 and guides only the polarized light having the polarization plane different from the polarized light transmitting the polarizer 4 to the light receiving element 6. Therefore, the ratio of the light intensity detected by the light receiving element 5 to the light intensity detected by the light receiving element 6 is an index (depolarization value) indicating the degree of depolarization generated by passing through the silicon wafer W. Since the silicon wafer W in the place where stress is applied generates photoelasticity, the depolarization value is an index indicating the distribution of stress applied to the silicon wafer W.
  • FIG. 2 is a graph showing an example of the measured depolarization value
  • FIG. 3 is a diagram showing an example of an in-plane map of the measured depolarization value.
  • the measured depolarization value itself contains a long period component and a short period component.
  • the long period component is mainly attributable to the crystal structure, and the short period component is related to slip occurrence. Therefore, in order to detect slip occurrence more accurately, short-period components are extracted from the measured depolarization value as follows.
  • FIG. 4 is a graph in which the long period component is extracted by smoothing the depolarization value shown in FIG. 2, and FIG. 5 shows the long period component from the in-plane map of the depolarization value shown in FIG. It is a figure which shows the extracted in-plane map.
  • FIG. 4 and FIG. 5 are obtained by smoothing the depolarization values shown in FIG. 2 and FIG.
  • the smoothing process can be, for example, a floating averaging process, and the floating averaging section is preferably, for example, 0.5 to 4 mm.
  • FIG. 6 is a graph in which a long period component is removed from the depolarization value shown in FIG. 2 to extract a short period component
  • FIG. 7 is a graph showing an in-plane map of the depolarization value shown in FIG. It is a figure which shows the in-plane map which extracted the periodic component.
  • FIGS. 6 and 7 are obtained by removing the long period components shown in FIGS. 4 and 5 from the depolarization values shown in FIGS.
  • the silicon wafer is divided into equally spaced sections of 1 mm 2 or more and 25 mm 2 or less, and if the amplitude of the short period component exceeds a predetermined threshold in the section, it is determined that the section is distorted .
  • a predetermined threshold for example, ⁇ 40 DU
  • FIG. 8 is a flowchart showing a method of evaluating a silicon wafer according to the embodiment of the present invention. Note that although the evaluation method of the recon wafer shown in FIG. 8 relates to one silicon wafer, when there are a plurality of silicon wafers to be evaluated, the evaluation method of the silicon wafer shown in FIG. You may repeat for the number of sheets.
  • the surface roughness Ra of the silicon wafer to be evaluated is preferably 0.1 ⁇ m or less, and more preferably 0.001 ⁇ m or more. With a silicon wafer having a surface roughness Ra of 0.1 ⁇ m or less, it is possible to obtain a sufficient amount of infrared polarization transmission. On the other hand, the surface roughness Ra of the silicon wafer before surface polishing is 0.001 ⁇ m or more. With such surface roughness Ra, slippage using a surface inspection device can not be appropriately performed, but in the silicon wafer evaluation method according to the embodiment of the present invention, the surface roughness Ra is 0.001 ⁇ m or more. Even if there is, it is possible to carry out.
  • the depolarization value of the silicon wafer is measured (step S1).
  • the measurement of the depolarization value is performed using the infrared photoelastic measurement device 1. That is, the stress applied to the silicon wafer is measured as a depolarization value using birefringence (photoelasticity) when polarized light passes through the inside of the stressed silicon wafer.
  • step S2 section analysis of the silicon wafer is performed (step S2).
  • This section analysis divides the heat-treated single crystal silicon wafer into equally spaced sections of 1 mm 2 or more and 25 mm 2 or less, and based on the depolarization values measured using the infrared photoelasticity measurement apparatus 1 Determine if there is distortion in the section.
  • the measured depolarization value is subjected to smoothing processing to extract a long-period component, and the long-period component is measured from the depolarization value measured. It is preferable to carry out using the short period component obtained by removing.
  • the depolarization value to be measured contains a long period component mainly caused by the crystal structure and a short period component related to the occurrence of slip.
  • a silicon wafer is screened based on the presence or absence of distortion for each section (step S3).
  • this screening those that do not exceed the predetermined threshold for the number of adjacent sections determined to have a strain in the section analysis are evaluated as non-defective products.
  • the number of adjacent sections determined to have distortion may be defined as the total number of sections determined to have distortion in the four directions around the section determined to have distortion. preferable.
  • FIG. 9 is a diagram illustrating an example of determination using the number of neighbors.
  • hatched sections mean sections determined to have distortion.
  • section (C) determined to have distortion is the center, the sections around the section become eight sections (1 to 8) in the front, rear, left, and right directions.
  • the number of neighbors in this case is defined as the number of segments determined to have distortion among the eight segments (1 to 8). That is, in the example shown in FIG. 9, since there are distortions in the three sections of section (3), section (4) and section (7), the number of adjacencies is three.
  • the threshold of the adjacent number used for screening it is preferable to determine the threshold of the adjacent number used for screening by obtaining in advance the relationship between the slip length of the silicon wafer evaluated using X-ray topography and the adjacent number of the sections determined to have distortion. .
  • the evaluation method of the silicon wafer has a good correlation with the slip length of the silicon wafer evaluated using X-ray topography. Therefore, if the threshold value of the adjacent number is determined based on the slip length of the silicon wafer previously evaluated using X-ray topography, evaluation of the silicon wafer with similar accuracy without using X-ray topography It can be performed.
  • step S4 It is judged whether the silicon wafer which has finished screening is to be paid out to the next process based on whether it is a good product or not (step S4).
  • a wafer whose number of adjacencies does not exceed a predetermined threshold (for example, 6) is judged as non-defective (Yes), and the silicon wafer judged as non-defective is paid out to the next process (step S5).
  • a silicon wafer judged to be a non-defective product is judged to be a non-defective product if the number of adjacent components is equal to or greater than a predetermined threshold (for example, 6) (step S6).
  • FIG. 10 is a graph showing the relationship between the maximum value of the adjacent number and the slip length
  • FIG. 11 is a diagram showing an in-plane map of a typical measurement example.
  • the sample used for the verification experiment is a silicon wafer having an oxygen concentration of 1.2 ⁇ 10 18 atoms / cm 3 , a nitrogen concentration of 3 ⁇ 10 14 atoms / cm 3 , and a diameter ⁇ of 300 mm.
  • the surface roughness Ra is 0.01 ⁇ m before mirror polishing and after mirror polishing It is 0.0001 ⁇ m.
  • RTO Rapid Thermal Oxidation
  • the data plotted in FIG. 10 are the evaluation method of a silicon wafer according to an embodiment of the present invention, the slip length (mm) using X-ray topography, and the final value for the sample before mirror polishing and the sample after mirror polishing It shows a comparison with a surface inspection apparatus (Surfscan SP2 manufactured by KLA-Tencor) used in visual inspection.
  • the abscissa represents the maximum value of the adjacent number according to the embodiment of the present invention
  • the slip length (mm) using the X-ray topography for comparison represents the sample difference and
  • the difference in judgment in the surface inspection apparatus is represented by the difference in the plotted symbols.
  • the data “o” plotted in FIG. 10 relates to the sample after mirror polishing, and the surface inspection apparatus judged it to be a non-defective item, and the plotted data ".DELTA.” Relates to the sample after mirror polishing In the surface inspection apparatus, the product was judged to be defective.
  • the data “ ⁇ ” plotted is for the sample before mirror polishing, and is a sample that can not be measured by the surface inspection apparatus because the surface is rough.
  • the silicon wafer evaluation method according to the embodiment of the present invention can appropriately screen the slip occurring in the silicon wafer with the same accuracy without directly performing the inspection using the X-ray topography. .
  • the evaluation method of a silicon wafer according to the embodiment of the present invention is applicable to a silicon wafer before mirror polishing, a surface inspection apparatus (for example, KLA-Tencor Co., Ltd.) used in the conventional final appearance inspection There is a wider range of silicon wafers that can be applied than Surfscan SP2).
  • a surface inspection apparatus for example, KLA-Tencor Co., Ltd.
  • the one having a long slip length measured using X-ray topography is also included. This indicates that in the conventional slip detection method using a surface inspection apparatus used in final visual inspection, the defective product to be removed may have been taken out to the next process. There is. In the slip detection method using the surface inspection apparatus used in the conventional final appearance inspection, it is considered that the step caused by the slip is smoothed at the time of mirror polishing, and the generated slip can not be detected.
  • the evaluation method of the silicon wafer according to the embodiment of the present invention has a good correlation with the slip length (mm) using the X-ray topography even for the sample after mirror polishing, so detection leakage There are also few. That is, the evaluation method of the silicon wafer according to the embodiment of the present invention is not only applicable to the silicon wafer before mirror polishing to which the surface inspection apparatus can not be applied, but is also mirror polish to which the surface inspection apparatus is applicable. More accurate screening can be performed on later silicon wafers.
  • FIG. 11A shows the result of applying the evaluation method of the silicon wafer according to the embodiment of the present invention to the silicon wafer before mirror polishing subjected to the RTO process
  • FIG. The silicon wafer evaluation method according to the embodiment of the present invention is applied to a silicon wafer after mirror polishing that has been subjected to RTO processing.
  • the evaluation method of the silicon wafer according to the embodiment of the present invention applies to both the silicon wafer before mirror polishing and the silicon wafer after mirror polishing. Appropriately applicable.
  • the place where the strain is generated is concentrated on the outer peripheral part of the silicon wafer when the holding part of the silicon wafer is in the RTO process. It is considered to be a source of distortion.
  • the slip affecting the electrical characteristics of the semiconductor device is not affected without being restricted by the surface condition and the processing content of the silicon wafer as much as possible. It can be inspected in a destructive and non-contact manner.
  • the silicon wafer evaluation method of the embodiment of the present invention it is possible to appropriately screen the slip occurring in the silicon wafer with the same accuracy without directly performing the inspection using the X-ray topography. it can.
  • the evaluation method of the silicon wafer according to the embodiment of the present invention is not only applicable to a silicon wafer before mirror polishing to which a surface inspection apparatus can not be applied, but is also mirror polish to which a surface inspection apparatus is applicable. More accurate screening can be performed on later silicon wafers.

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Abstract

L'invention concerne un procédé d'évaluation d'une tranche de silicium au moyen duquel il est possible d'effectuer une inspection non destructive et sans contact pour un glissement qui exerce une influence sur les propriétés électriques d'un dispositif à semi-conducteurs tout en provoquant aussi peu de restrictions que possible sur l'état de la surface de la tranche de silicium et les détails de son traitement. Ce procédé d'évaluation d'une tranche de silicium comprend : une étape d'analyse de section dans laquelle une tranche de silicium monocristallin traitée thermiquement est divisée en sections espacées de manière égale comprises entre 1 mm2 et 25 mm2 (inclus) et la présence ou l'absence de distorsion dans chacune des sections est déterminée sur la base d'une valeur de dépolarisation de la polarisation infrarouge ; et une étape de criblage dans laquelle des sections qui ont été déterminées dans l'étape d'analyse de section comme ayant une distorsion et qui n'ont pas de nombre de sections adjacentes dépassant un seuil prescrit sont évaluées comme étant de bonne qualité.
PCT/JP2018/027425 2017-12-25 2018-07-23 Procédé d'évaluation de tranche de silicium WO2019130633A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201880083802.XA CN111512424B (zh) 2017-12-25 2018-07-23 硅晶片的评价方法
EP18894615.6A EP3734648A4 (fr) 2017-12-25 2018-07-23 Procédé d'évaluation de tranche de silicium
KR1020207021707A KR102385259B1 (ko) 2017-12-25 2018-07-23 실리콘 웨이퍼의 평가 방법
US16/957,612 US11060983B2 (en) 2017-12-25 2018-07-23 Evaluation method of silicon wafer

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JP2017-247117 2017-12-25
JP2017247117A JP6978928B2 (ja) 2017-12-25 2017-12-25 シリコンウェーハの評価方法

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EP4160660A4 (fr) * 2020-06-01 2024-03-20 Shin-Etsu Handotai Co., Ltd. Procédé d'évaluation d'une déformation périphérique externe d'une tranche

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JP7143828B2 (ja) * 2019-09-20 2022-09-29 信越半導体株式会社 シリコン単結晶ウェーハのスリップ検出方法
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