WO2019128575A1 - 一种中断处理方法及中断处理装置 - Google Patents

一种中断处理方法及中断处理装置 Download PDF

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WO2019128575A1
WO2019128575A1 PCT/CN2018/117069 CN2018117069W WO2019128575A1 WO 2019128575 A1 WO2019128575 A1 WO 2019128575A1 CN 2018117069 W CN2018117069 W CN 2018117069W WO 2019128575 A1 WO2019128575 A1 WO 2019128575A1
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address
processing
interrupt
endian
pcie
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PCT/CN2018/117069
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English (en)
French (fr)
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徐阳
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the application relates to, but is not limited to, computer technology, such as an interrupt processing method and an interrupt processing device.
  • PCIE Peripheral Component Interconnect Express
  • CPU central processing unit
  • PCIE controller contained on the side of the CPU is the master controller, and the PCIE device outside the CPU is the slave device.
  • the PCIE standard defines three main types of transactions for data transfer: memory read and write transactions, input/output (I/O) read and write transactions, and configuration space read and write transactions. Among them, I/O read and write transactions are outdated, and mainstream PCIE devices are no longer used. Configuration space read and write transactions are primarily used during the device initialization phase. When the PCIE bus is running, most of the bus transactions transferred are memory read and write transactions. The memory read and write transactions of the PCIE bus can read and write to the target memory address (ie, the PCIE bus address).
  • the PCIE bus supports full-duplex, so the central processor (that is, the PCIE host controller) and the attached PCIE device (that is, the slave device) can actively initiate memory read and write transactions.
  • the PCIE device can actively read and write to the Double Rate Rate (DDR) memory that is connected to the CPU, or the PCIE device can actively read and write the registers of the CPU.
  • DDR Double Rate Rate
  • the system software can convert the DDR memory under the central processing unit, the registers of the central processing unit, and the registers on the PCIE device into a unique PCIE bus address.
  • the central processing unit or the PCIE device initiates a memory read/write transaction
  • the device corresponding to the read/write PCIE bus address automatically responds. For example, mapping a space on the DDR memory under the central processor to the PCIE bus, assuming that the address of the memory is PCIE bus address A, then direct memory access (DMA) on the PCIE device.
  • DMA direct memory access
  • the controller can actively initiate a memory read/write transaction, requesting read and write operations on the PCIE bus address A; and the central processor automatically responds to the external device's read and write operations on the PCIE bus address A without software participating in the DDR memory read and write. In this way, the external PCIE device can directly write data to the DDR address of the PCIE bus address A, or directly read data from the DDR address of the PCIE bus address A.
  • the register on the PCIE device is converted to the PCIE bus address.
  • the PICE standard it is implemented by configuring the six basic registers (BAR) of the configuration space on the PICE device.
  • BAR basic registers
  • the conversion of the DDR and CPU registers of the central processor to the PCIE bus address is implemented by the central processor manufacturers and is not universal.
  • the PowerPC series of CPUs from NXP (formerly Freescale Semiconductor) use the Fast Peripheral Component Interconnect Address Transfer and Mapping Unit (ATMU) Registers to centrally process
  • the internal registers of the device and the DDR memory under the central processor are mapped to the PCIE bus.
  • PCIE bus addresses for the entire board when making board support packages (BSPs) to ensure that the allocation of PCIE bus addresses does not conflict.
  • This configuration method is also fixed for a particular central processor.
  • the PowerPC processor is implemented by the Device Tree Source (DTS) file and the configuration of the Fast Peripheral Component Interconnect ATM Register (PCI Express Inbound ATMU Registers).
  • DTS Device Tree Source
  • PCI Express Inbound ATMU Registers PCI Express Inbound ATMU Registers
  • MSI Message Signaled Interrupt
  • MSI-X Message Signaled Interrupt Extended
  • the principle of interrupt reporting is that the external PCIE device initiates a memory write transaction and actively writes a register inside the central processing unit; by writing the internal processor register, the central processor can know that the PCIE device has reported the interrupt. Write different values representing different MSI interrupt numbers or MSI-X interrupt numbers. In this way, the central processor can trigger the interrupt processing flow.
  • MSI-X is an enhanced version of MSI. The principle of the two is the same.
  • MSI only configures a set of Message Address and Message Data registers, and reports an interrupt number; MSI-X Multiple sets of Message Address registers and Message Data registers can be configured to support multiple interrupt numbers.
  • MSI-X does not affect the application of the present application.
  • the Message Address register and the Message Data register are grouped together in a group.
  • the PCIE bus is led by Intel Corporation.
  • the mainstream PCIE devices first support the X86 architecture (The X86 architecture), and the X86 architecture uses the Little-Endian byte order. Therefore, the PCIE device support for the little endian CPU must be implemented.
  • Little-Endian means that the low byte is discharged at the low address end of the memory, and the high byte is discharged at the high address end of the memory; Big-Endian means that the high byte is discharged at the low address end of the memory, and the low byte is discharged in the memory. High address side.
  • big endian byte order CPU has a wider market application.
  • performance optimization with Enhanced RISC Performance Computing (PowerPC/PPC) is a reduced instruction set computer (RISC) architecture CPU, and based on advanced reduced instruction set machines ( Advanced RISC Machine, ARM) architecture QorIQ Layerscape processor.
  • RISC reduced instruction set computer
  • ARM Advanced RISC Machine
  • QorIQ Layerscape processor Such big endian byte order CPUs may encounter byte order incompatibility when paired with some vendors' PCIE devices, thus failing to support MSI/MSI-X messages.
  • the present application provides an interrupt processing method and an interrupt processing device, which can avoid the situation in which the interrupted message endian is incompatible.
  • the present application provides an interrupt processing method, including: the central processor performs endian adjustment on the value of the hardware corresponding to the write preprocessed address, so that the slave device is compatible with the endian of the central processor; the central processor will adjust The following byte-order adjusted value is written to the information signal interrupt MSI mechanism register to trigger the interrupt; wherein the pre-processing address is the fast peripheral component interconnect PCIE bus address; the hardware corresponding to the pre-processing address is set to check that it is modified , the software mode is called to adjust the byte order.
  • the PCIE bus address is determined as the pre-processing address; and the PCIE bus address is: a piece of memory applied on the system where the central processing unit is located. The mapped address on the PCIE bus; or the PCIE bus address that is not being used.
  • the MSI mechanism register is: an MSIIR register, or a register having the same function as the MSIIR register; the interrupt is an information signal interrupt or an extended information signal interrupt.
  • the present application also provides a computer readable storage medium storing computer executable instructions arranged to perform the interrupt processing method of any of the above.
  • the present application further provides a media transmission device comprising a processor, a memory, and a computer program stored on the memory and operable on the processor, the computer program being arranged to perform the step of: writing hardware corresponding to the pre-processed address The value is byte-ordered so that the slave device is compatible with the central processor byte order, and the byte-ordered value is written to the MSI mechanism register to trigger the interrupt; wherein the pre-processing address is the fast peripheral component interconnect PCIE Bus address; the hardware corresponding to the pre-processing address is set to check that it has been modified, and the software mode is called to adjust the byte order.
  • the application further provides an interrupt processing method, comprising: when the slave device is driven to register, the information address register on the slave device is configured to point to a pre-specified pre-processing address; when the slave device has an interrupt, the information address register is The hardware corresponding to the pre-processing address pointed to by the write operation; wherein the pre-processing address is a PCIE bus address; the hardware corresponding to the pre-processing address is set to check that the byte order is adjusted by calling the software mode when it is modified.
  • the pre-processing address is a PCIE bus address
  • the pre-processing address is a mapped address of a memory on the PCIE bus applied on the system where the central processing unit is located, and the memory is set to be Hardware breakpoint monitoring; or the pre-processing address is a PCIE bus address that is not being used.
  • the slave device is a PCIE device.
  • the present application further provides an interrupt processing apparatus, including: a preprocessing module and an interrupt processing module; wherein the preprocessing module is configured to perform endian adjustment on the value of the hardware corresponding to the write preprocessed address, so that the slave device and the slave device The central processor byte order is compatible; the interrupt processing module is configured to write the byte-order adjusted value to the MSI mechanism register to trigger the interrupt;
  • the pre-processing address is a PCIE bus address; the hardware corresponding to the pre-processing address is set to check that it is modified, and the software mode is used to adjust the byte order.
  • the present application also provides a computer readable storage medium storing computer executable instructions arranged to perform the interrupt processing method of any of the above.
  • the application further provides a media transmission device comprising a processor, a memory and a computer program stored on the memory and operable on the processor, the computer program being arranged to perform the following steps: when the slave device driver is interrupted during registration, The information address register on the slave device is configured to point to a pre-specified pre-processing address; when the slave device has an interrupt, the hardware corresponding to the pre-processing address pointed to by the information address register is written;
  • the pre-processing address is a PCIE bus address; the hardware corresponding to the pre-processing address is set to check that the byte order is adjusted by calling the software mode when the self-modification is checked.
  • FIG. 1 is a schematic diagram of interrupt reporting and processing in the related art
  • FIG. 2 is a schematic flowchart of an embodiment of an interrupt processing method according to the present application.
  • FIG. 3 is a schematic structural diagram of an embodiment of an interrupt processing apparatus of the present application.
  • FIG. 4 is a schematic diagram of processing of a first embodiment of an interrupt processing method according to the present application.
  • FIG. 5 is a schematic diagram of processing of a second embodiment of an interrupt processing method according to the present application.
  • FIG. 6 is a schematic diagram of processing of a third embodiment of an interrupt processing method according to the present application.
  • FIG. 1 is a schematic diagram of interrupt reporting and processing in the related art. Taking the Linux operating system as an example, as shown in FIG. 1, the support for the MSI/MSI-X interrupt may substantially include the following.
  • the pci_enable_msi interface or the pci_enable_msix interface is called to apply for the MSI/MSI-X interrupt number.
  • the driver configures the Message Address register and the Message Data register in the MSI/MSI-X Capability structure in the configuration space on the PCIE device.
  • the value written to the Message Address register is the address mapped to the PCIE bus by the Shared Message Signaled Interrupt Index Register (MSIIR) of the processor in the PowerPC processor; the value written to the Message Data register, It is the value calculated based on the MSI interrupt number applied by the current PCIE device driver.
  • MSIIR Shared Message Signaled Interrupt Index Register
  • the PCIE device when it needs to report the MSI/MSI-X interrupt, it sends an MSI/MSI-X interrupt message to the central processing unit, which is a memory write operation.
  • the result of the operation is: configured to the Message Address register.
  • the destination address written to the value in the Message Data register.
  • the central processor receives the MSI/MSI-X interrupt message, equivalent to writing to the specific register of the central processor, such as the MSIIR register for PowerPC, and writing the value in the Message Data register.
  • the write operation to the MSIIR register triggers the interrupt controller of the central processing unit to enter the interrupt processing flow, that is, executes the corresponding interrupt service program according to the value written by the MSIIR register. This completes an interrupt transaction report and processing.
  • MSI/MSI-X Capability structure For the definition of the MSI/MSI-X Capability structure, refer to the relevant protocol standards, and the details of the Message Data register are 16 bits (Bits).
  • the value in the Message Data register on the PCIE device is written to the MSIIR register of the central processor. Therefore, the initial configuration of the Message Data register must be combined with the definition of the MSIIR register of the central processor, and then calculated according to the interrupt number applied by the PCIE device.
  • the correct interrupt number can only be triggered by the central processor by writing the correct value to the MSIIR register of the central processor.
  • the PowerPC processor can handle 256 different MSI interrupts, and these interrupts are divided into 8 groups of 32, and in the MSIIR register, the Shared Interrupt Register Select (SRS) field indicates 0.
  • SRS Shared Interrupt Register Select
  • IBS Input Block Size
  • the standard PCIE MSI/MSI-X interrupt processing from the PCIE device to send interrupt messages to the central processor to generate interrupts, is automatically done by the hardware, the software can not participate without participation. Therefore, if the data itself to be written in the MSI/MSI-X message is incompatible, the data can only be written to the reserved portion of the MSIIR register of the central processor. In other words, the MSIIR register cannot be written with meaningful information at this time, and the central processor cannot generate the correct interrupt.
  • the processing in the related art is: since the software cannot participate in the identification of the MSI/MSI-X terminal message, the software cannot be used to avoid the incompatibility of the endian.
  • the chip scheme can only be modified to avoid, that is, either the central processor chip is replaced or the PCIE device chip is replaced for compatibility.
  • the replacement chip solution is not compatible with the code of the original product, and also increases the procurement cost and development cycle. If it is found in the development process that there is a byte incompatibility, and then want to replace the chip, it will cause more serious losses.
  • the inventor of the present application skillfully generates a pre-processing procedure for the current interrupt by replacing the target address configured in the information address register with a special address, and in the pre-processing process, the software processing can be simply implemented.
  • the interrupt message byte sequence incompatibility adjustment is adjusted, so that the correct information is written to the register pointed to by the target address of the information address register (such as the MSIIR register or the register having the same function as the MSIIR register), and finally the interrupt is correctly triggered, such as MSI/ MSI-X interrupted.
  • the interrupt processing method includes step 2001 and Step 2011.
  • step 2001 the slave device driver configures the information address register on the slave device to point to a pre-specified pre-processing address when the registration is interrupted.
  • the pre-processing address is a PCIE bus address, and the hardware corresponding to the pre-processing address is set to check that the byte order is adjusted by calling the software mode when it is modified.
  • the slave device may be a PCIE device.
  • the interrupt may be an interrupt such as an MSI, or an MSI-X interrupt.
  • step 2011 when the slave device has an interrupt generated, the hardware corresponding to the pre-processing address pointed to by the information address register is written.
  • the interrupt processing method provided by the present application points the Message Address register to the PCIE bus address, so that the reported interrupt message is not directly written into the MSIIR register of the central processing unit, but is written to the PCIE bus address, thereby triggering the central processor.
  • the pre-processing process rather than directly entering the MSIIR interrupt processing.
  • steps 2002 and 2012 are included.
  • step 2002 the central processor performs endian adjustment on the value of the hardware corresponding to the write preprocessed address, so that the slave device is compatible with the central processor endian.
  • the method before the step, further includes: applying the pre-processing address.
  • the PCIE bus address may be determined as a pre-processed address when the system in which the central processing unit is located is initialized.
  • the pre-processing address is a PCIE bus address, for example, applying a dedicated memory on the system where the central processing unit is located, calculating a mapped address of the memory on the PCIE bus as a pre-processing address, and the memory Set to be monitored by hardware breakpoints; for example: the preprocess address is the PCIE bus address that is not being used.
  • the preprocessed address belongs to the PCIE bus address.
  • PCIE bus address PA also known as the first PCIE bus address
  • the PCIE bus address Pan also referred to as the second PCIE bus address
  • each byte of the memory corresponding to the pre-processed address is filled with the initial value 0xff.
  • the system software developer in the related art makes an overall allocation of the PCIE bus address of the entire hardware board when the BSP is manufactured. Therefore, it is clear which hardware resources will be mapped to the PCIE bus and what the PCIE bus address range corresponds to these hardware resources. That is to say, it is easy for those skilled in the art to know which PCIE bus address ranges are not used.
  • step 2002 includes:
  • the pre-processing address is a mapped address on the PCIE bus on the system where the central processing unit is located, then when the pre-processing address is written, hardware breakpoint exception handling is triggered to enter the pre-processing; if the pre-processing address is For the PCIE bus address that is not used, then when the pre-processing address is written, the PCIE error interrupt processing is triggered to enter the pre-processing; if the pre-processing address is the PCIE bus address PAn, the central processor will pre- The 1024-byte memory corresponding to the address is processed, and the polling is performed in increments of 4 bytes (a total of 256 checks are required, 4 bytes of each check). When the value in the memory is detected, the value is not the initial value. 0xfffffffff, which means that the memory has been modified and entered the preprocessing process.
  • the byte value conversion processing is performed on the value of the hardware corresponding to the write preprocessed address, so that the little endian endian is adjusted to the big endian endian
  • the specific implementation of the endian conversion is not intended to limit the scope of protection of the present application.
  • exit hardware breakpoint exception handling PCIE error interrupt processing or polling processing.
  • step 2012 the central processor writes the byte-ordered value to the MSI mechanism register to trigger the interrupt.
  • the interrupt processing method provided by the present application subtly generates a pre-processing process for the current interrupt by replacing the target address configured in the information address register with a special address, and in the pre-processing process, the software processing method
  • the adjustment of the incompatibility of the interrupt message endian is simply implemented, ensuring that the slave device is compatible with the central processor byte order, thereby ensuring that the register having the same function as the register such as the MSIIR register or the MSIIR register is correctly written.
  • the information eventually triggers an interrupt such as an MSI/MSI-X interrupt.
  • the above MSIIR register of the present application exists in a PowerPC processor, an ARM architecture based QorIQ Layerscape processor, and the like.
  • the interrupt processing method provided by the present application is applicable to, but not limited to, a PowerPC processor, a QorIQ Layerscape processor, etc., and any register having the same function as the MSIIR register or the MSIIR register can be used, and this register is the default target of the Message Address register. The register pointed to by the address.
  • the embodiment of the present application further provides a computer readable storage medium storing computer executable instructions, the computer executable instructions being configured to perform the interrupt processing method according to any one of the above.
  • the embodiment of the present application further provides a media transmission apparatus, including a processor, a memory, and a computer program stored on the memory and operable on the processor, the computer program being configured to perform the following steps: corresponding to the write pre-processing address
  • the value of the hardware is adjusted in byte order so that the slave device is compatible with the central processor byte order, and the byte-ordered value is written to the MSI mechanism register to trigger the interrupt.
  • the application further provides an interrupt processing apparatus, comprising at least: a preprocessing module and an interrupt processing module; wherein the preprocessing module is configured to perform endian adjustment on the value of the hardware corresponding to the write preprocessed address, so that the slave device and the slave device
  • the central processor is byte-order compatible; the interrupt handling module is configured to write the byte-ordered value to the MSI mechanism register to trigger the interrupt.
  • the pre-processing module is configured to: the pre-processing address is a mapping address of a segment of the memory on the PCIE bus on the system where the interrupt processing device is located.
  • the memory is set to be monitored by a hardware breakpoint, and when the pre-processed address is written, hardware breakpoint exception handling is triggered to enter the pre-processing process.
  • the pre-processing address is a PCIE bus address that is not used; when the pre-processing address is written, PCIE error interrupt processing is triggered to enter the pre-processing.
  • the pre-processing address is the PCIE bus address PAn, and the 1024-byte memory corresponding to the pre-processed address is polled in increments of 4 bytes (a total of 256 checks are required, and 4 words are checked each time) Section), when it is detected that the value in the memory is not the initial value 0xfffffff, it means that the memory of the segment is modified and enters the preprocessing process; in the preprocessing process, the value of the hardware corresponding to the write preprocessed address is performed. Endian conversion processing, making little endian ordering into big endian order; exiting hardware breakpoint exception handling, PCIE error interrupt handling, or polling processing.
  • the interrupt is the MSI/MSI-X interrupt
  • the register corresponding to the destination address of the Message Address register is described as an MSIIR register.
  • the adjustment of the MSI/MSI-X interrupt message is implemented by using a hardware breakpoint.
  • a hardware breakpoint is a debugging mechanism provided by the central processor that can generate an exception when a particular memory address is modified.
  • the hardware breakpoint is used in the first embodiment to monitor the MSI/MSI-X interrupt message.
  • FIG. 4 is a schematic diagram of the processing of the first embodiment of the interrupt processing method of the present application. As shown in FIG. 4, the following content is included.
  • the hw_breakpoint_add interface provided by the linux system registers the write operation monitoring of the above-mentioned memory that is applied for.
  • the specific implementation only needs to register a hardware breakpoint.
  • a hardware breakpoint can only monitor 32-bit data, that is, monitor the first 4-byte memory corresponding to the PCIE bus address.
  • the MSI/MSI-X interrupt message reported by the PCIE device that is incompatible with the central processing unit triggers the exception handling interface of the hardware breakpoint, and in the exception handling interface of the hardware breakpoint,
  • the incompatible endian is corrected to match the byte order of the central processor, ensuring that the correct byte order value is filled into the MSIIR register, and finally the interrupt number is reported correctly.
  • the PCIE error detection interrupt of the central processor is utilized to quickly respond to the adjustment of the MSI/MSI-X interrupt message.
  • PCIE controller in the processor produced by NXP (formerly Freescale Semiconductor) as an example.
  • Both the PowerPC processor and the ARM-based QorIQ Layerscape processor provide PCIE error detection mechanism beyond the PCIE standard. That is, when an error occurs on the PCIE bus, an interrupt can be generated to notify the central processing unit and record the information of the message causing the error. For example, for a memory read/write transaction on the PCIE bus, if the target PCIE bus address of the access is not used, that is, no device responds to the read/write request, then a PCI interconnect unmapped (PCI Express) is generated. If the map is incorrect, the PCIE error interrupt is reported to the central processing unit. At the same time, the PCIE error capture register records the details of the error message. From the error information captured by these registers, the target PCIE bus address corresponding to the PCIE no map error can be analyzed.
  • PCIE error capture register records the details of the error message. From the error information captured by these registers, the target PCIE bus address
  • FIG. 5 is a schematic diagram of the processing of the second embodiment of the interrupt processing method of the present application. As shown in FIG. 5, the method includes:
  • the starting PCIE bus address can be 32 bits wide or 64 bits wide, which is consistent with the PCIE bus standard used by current PCIE devices.
  • the calculation rule of the PCIE bus address may be: the valid 2-byte data of the associated Message Data is obtained as a 16-bit wide unsigned number (ie, data type u16) plus the initial PCIE bus address. You also need to configure the PCIE bus controller, enable the PCI Express no map error detection interrupt, and register the PCIE error interrupt handler.
  • PCIE error interrupt handler first check if a PCI Express no map interrupt occurs. If a PCI Express no map interrupt occurs, further check the register R2 and register R3 in the PCI Express error capture register group to obtain the complete PCIE of the application.
  • the bus address the lowest 16 bits of the PCIE bus address, is the valid 2-byte data of Message Data.
  • the data in the lower 16 bits of the PCIE bus address is byte-order adjusted and written to the MSIIR register.
  • the PCIE error detection function clears the PCI Express no map (PNM) interrupt flag and the PCI Express error capture status register through the PCIE error interrupt handler. Error capture valid (ECV) bit.
  • the adjustment of the MSI/MSI-X interrupt message is implemented by using a polling manner.
  • FIG. 6 is a schematic diagram of the processing of the third embodiment of the interrupt processing method of the present application. As shown in FIG. 6, the following content is included.
  • each Message Address register on the PCIE device is reconfigured to point to the preprocessed address.
  • the pre-processing address that is, the PCIE bus address PAn is: multiply the requested MSI/MSI-X interrupt number by 4, and add the PCIE bus address PA corresponding to the applied 1024-byte memory to obtain the PCIE bus address Pan. Preprocess the address.
  • some hotspot functions of the Linux kernel including but not limited to: arch_cpu_idle function, irq_exit function, ret_fast_syscall function, retint_user function, etc., add a call to the processing function f set by the present application to implement polling processing.
  • the MSI/MSI-X interrupt message reported by the PCIE device that is incompatible with the central processing unit is written into the memory corresponding to the pre-processed address, and waits until the linux kernel executes these hotspot functions, and then checks The modification of the memory of these interrupt messages corrects the incompatible byte order to match the byte order of the central processing unit, ensuring that the correct byte order value is filled in the MSIIR register, and finally the correct implementation is achieved.
  • the interrupt number is reported.

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Abstract

一种中断处理方法及中断处理装置，包括：中央处理器对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容（2002）；中央处理器将进行字节序调整后的值写入MSI机制寄存器以触发中断（2012）。其中，预处理地址是PCIE总线地址；预处理地址对应的硬件，设置为检查到自身被修改时，调用软件方式对字节序进行调整。

Description

一种中断处理方法及中断处理装置
本申请要求在2017年12月28日提交中国专利局、申请号为201711462037.6的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于计算机技术，例如一种中断处理方法及中断处理装置。
背景技术
快速外围组件互连(Peripheral Component Interconnect Express，PCIE)总线是一种在计算机系统广泛采用的高速串行总线，设置为连接中央处理器(Central Processing Unit，CPU)和其他高性能芯片如网卡、显卡、以太网交换芯片等。中央处理器这一侧含有的PCIE控制器是主控制器，中央处理器外部的PCIE设备是从设备。
PCIE标准定义了用于数据传送的三大类事务，分别是：存储器读写事务、输入/输出(Input/Output，I/O)读写事务、以及配置空间读写事务。其中，I/O读写事务已经过时，主流PCIE设备不再使用。配置空间读写事务主要在设备初始化阶段使用。在PCIE总线运行时，传送的绝大部分总线事务都是存储器读写事务。PCIE总线的存储器读写事务能向目标存储器地址(也即PCIE总线地址)进行读写。
PCIE总线支持全双工，因此，中央处理器(即PCIE主控制器)和下挂的PCIE设备(即从设备)都可以主动发起存储器读写事务。PCIE设备可以主动向中央处理器下挂的双倍速率(Double Date Rate，DDR)内存进行读写，或者，PCIE设备可以主动读写中央处理器的寄存器。只要知道了目标DDR内存的PCIE总线地址，或者中央处理器内部寄存器的PCIE总线地址，就能发起PCIE存储器读写事务对目标进行读写操作。
系统软件可以将中央处理器下挂的DDR内存、中央处理器的寄存器，以及PCIE设备上的寄存器均转化成唯一的PCIE总线地址。当中央处理器或者PCIE设备发起存储器读写事务时，被读写的PCIE总线地址对应的设备会自动响应。比如：将中央处理器下挂的DDR内存上的一片空间映射到PCIE总线上，假设配置这片内存的地址为PCIE总线地址A，那么，PCIE设备上的直接内存访问 (Direct Memory Access，DMA)控制器就能主动发起存储器读写事务，请求对PCIE总线地址A进行读写操作；而中央处理器会自动响应外部设备对PCIE总线地址A的读写操作，无需软件参与DDR内存的读写，这样，外部PCIE设备就能直接把数据写入地址为PCIE总线地址A的DDR，或者直接从地址为PCIE总线地址A的DDR上读取数据。
将PCIE设备上的寄存器转换成PCIE总线地址，按照PICE标准，是通过配置PICE设备上配置空间的6个基本寄存器(Base Address Register，BAR)来实现。而将中央处理器下挂的DDR、中央处理器的寄存器转化成PCIE总线地址，则是中央处理器厂家各自实现的，并不通用。比如：NXP公司(原飞思卡尔半导体)生产的PowerPC系列中央处理器，使用快速外围组件互连快速接收(PCI Express Inbound)地址传输和映射单元(Address Translation and Mapping Unit，ATMU)Registers将中央处理器内部的寄存器和中央处理器下挂的DDR内存映射到PCIE总线上。系统软件开发人员会在制作板级支持包(Board Support Package，BSP)时，规划整个单板的PCIE总线地址的分配，以确保PCIE总线地址的分配不会冲突。这种配置方法对于特定的中央处理器也是固定的。比如：对于PowerPC处理器就是通过设备树源码(Device Tree Source，DTS)文件和快速外围组件互连快速接收地址传输和映射单元寄存器(PCI Express Inbound ATMU Registers)的配置来实现的。
在PCIE总线上，PCIE设备向中央处理器上报中断的主流方式是采用信息信号中断(Message Signaled Interrupt，MSI)或扩展信息信号中断(Message signaled interrupt extended，MSI-X)机制。这种中断上报原理就是：外部PCIE设备发起存储器写事务，主动去写中央处理器内部的一个寄存器；通过写这个中央处理器内部的寄存器，能让中央处理器知道PCIE设备上报了中断。写入不同的值，代表不同的MSI中断号或MSI-X中断号。这样，中央处理器就能触发中断处理流程。MSI-X是MSI的增强版，两者的原理是相同的，主要区别在于：MSI只配置一组信息地址(Message Address)寄存器和信息数据(Message Data)寄存器，上报一个中断号；MSI-X可以配置多组Message Address寄存器和Message Data寄存器，可以支持多个中断号。MSI-X和MSI的区别并不影响本申请的应用。Message Address寄存器和Message Data寄存器是一组一组关联的。一组Message Address寄存器和Message Data寄存器，对应一个MSI中断/MSI-X中断。
PCIE总线是因特尔公司主导发展的，主流的PCIE设备都首先支持X86架构(The X86 architecture)，X86架构采用小端(Little-Endian)字节序。所以PCIE设备对小端字节序CPU的支持都是必须实现的。但是，由于目前大端处理器总的市场占有率较低，部分制造PCIE设备的芯片厂商会疏于考虑对大端(Big-Endian)字节序CPU的支持。其中，Little-Endian就是低位字节排放在内存的低地址端，高位字节排放在内存的高地址端；Big-Endian就是高位字节排放在内存的低地址端，低位字节排放在内存的高地址端。
在数据通讯领域，大端字节序CPU有较广泛的市场应用。比如：性能优化增强精简指令集计算机性能计算(Performance Optimization With Enhanced RISC Performance Computing，PowerPC/PPC)是一种精简指令集(Reduced Instruction Set Computer，RISC)架构的CPU，以及基于高级精简指令集机器(Advanced RISC Machine，ARM)架构的QorIQ Layerscape处理器等。这类大端字节序CPU在搭配一些厂商的PCIE设备时，就可能遇到字节序不兼容的情况，从而无法支持MSI/MSI-X报文。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供一种中断处理方法及中断处理装置，能够避免中断报文字节序不兼容的情况。
本申请提供了一种中断处理方法，包括：中央处理器对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器的字节序兼容；中央处理器将调整后的字节序调整后的值写入信息信号中断MSI机制寄存器以触发中断；其中，预处理地址是快速外围组件互连PCIE总线地址；预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
在一实施例中，在所述中央处理器所在系统初始化时，确定所述PCIE总线地址作为所述预处理地址；所述PCIE总线地址为：在所述中央处理器所在系统上申请的一段内存在PCIE总线上的映射地址；或者为没有被使用的PCIE总线地址。
在一实施例中，所述MSI机制寄存器为：MSIIR寄存器，或者与MSIIR寄存器具有相同功能的寄存器；所述中断为信息信号中断或扩展信息信号中断。 本申请还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述任一项所述的中断处理方法。
本申请又提供了一种媒体传输装置，包括处理器、存储器以及存储在存储器上可在处理器上运行的计算机程序，所述计算机程序设置为执行以下步骤：对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容，将进行字节序调整后的值写入MSI机制寄存器以触发中断；其中，预处理地址是快速外围组件互连PCIE总线地址；预处理地址对应的硬件设置为检查到自身被修改，调用软件方式对字节序进行调整。
本申请再提供了一种中断处理方法，包括：从设备驱动在注册中断时，将从设备上的信息地址寄存器配置为指向预先指定的预处理地址；从设备有中断产生时，对信息地址寄存器指向的预处理地址对应的硬件进行写操作；其中，预处理地址是PCIE总线地址；预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
在一实施例中，所述预处理地址为PCIE总线地址，包括：所述预处理地址为在中央处理器所在系统上申请的一段内存在PCIE总线上的映射地址，并且所述内存设置为被硬件断点监控；或者所述预处理地址为没有被使用的PCIE总线地址。
在一实施例中，所述从设备为PCIE设备。
本申请还提供了一种中断处理装置，包括：预处理模块、中断处理模块；其中，预处理模块，设置为对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容；中断处理模块，设置为将进行字节序调整后的值写入MSI机制寄存器以触发中断；
其中，预处理地址是PCIE总线地址；预处理地址对应的硬件设置为检查到自身被修改，调用软件方式对字节序进行调整。
本申请还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述任一项所述的中断处理方法。
本申请又提供了一种媒体传输装置，包括处理器、存储器以及存储在存储器上可在处理器上运行的计算机程序，所述计算机程序设置为执行以下步骤：从设备驱动在注册中断时，将所述从设备上的信息地址寄存器配置为指向预先指定的预处理地址；所述从设备有中断产生时，对所述信息地址寄存器指向的所述预处理地址对应的硬件进行写操作；其中，所述预处理地址是PCIE总线地 址；所述预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为相关技术中中断上报和处理的示意图；
图2为本申请中断处理方法的实施例流程示意图；
图3为本申请中断处理装置的实施例的组成示意图；
图4为本申请中断处理方法第一实施例的处理示意图；
图5为本申请中断处理方法第二实施例的处理示意图；
图6为本申请中断处理方法第三实施例的处理示意图。
具体实施方式
下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
图1为相关技术中中断上报和处理的示意图，以Linux操作系统为例，如图1所示，对MSI/MSI-X中断的支持大致可以包括以下内容。
首先，PCIE设备驱动初始化时，调用pci_enable_msi接口或pci_enable_msix接口，申请MSI/MSI-X中断号。驱动程序会配置PCIE设备上的配置空间中MSI/MSI-X能力(Capability)结构中的Message Address寄存器和Message Data寄存器。其中，向Message Address寄存器写入的值，对于PowerPC处理器是处理器内部的MSI机制寄存器(Shared Message Signaled Interrupt Index Register，MSIIR)映射在PCIE总线上的地址；向Message Data寄存器写入的值，是根据当前PCIE设备驱动申请到的MSI中断号计算出来的值。
之后，在PCIE设备需要上报MSI/MSI-X中断时，会向中央处理器发送一个MSI/MSI-X中断报文，也就是一个存储器写操作，操作的结果是：向Message Address寄存器中配置的目标地址，写入Message Data寄存器中的值。
最后，中央处理器收到这个MSI/MSI-X中断报文，等效于向中央处理器的 特定寄存器如对于PowerPC是MSIIR寄存器，写入了Message Data寄存器中的值。而向MSIIR寄存器的写入操作，就会触发中央处理器的中断控制器进入中断处理流程，即根据MSIIR寄存器被写入的值，执行对应的中断服务程序。这样就完成了一次中断事务上报和处理。
关于MSI/MSI-X Capability结构的定义可以参见相关协议标准，这里不再赘述，其中的Message Data寄存器宽度都是16比特(Bits)的。
从图1所示的中断处理过程中可见，PCIE设备上的Message Data寄存器中的值会写入到中央处理器的MSIIR寄存器中。因此，对Message Data寄存器进行初始化配置，要结合中央处理器的MSIIR寄存器的定义，再根据PCIE设备申请到的中断号才能计算出来。只有向中央处理器的MSIIR寄存器写入正确的值，才能让中央处理器触发正确的中断号。比如：PowerPC处理器能处理256个不同的MSI中断，会将这些中断分成8组，每组32个，并在MSIIR寄存器中，采用共享中断寄存器选择(Shared Interrupt Register Select，SRS)字段指示是0-7组中的哪一组，采用输入块规格(Input Block Size，IBS)字段指示是组内0-31个中断中的哪一个中断。需要说明的是，MSIIR寄存器按照标准情况是提供给外部PCIE设备来写的，不过中央处理器上的软件也可以主动写这个寄存器。效果同外部PCIE设备使用MSI/MSI-X报文写这个寄存器是一样的。
标准的PCIE MSI/MSI-X中断处理，从PCIE设备发出中断报文，到中央处理器产生中断，都是硬件自动完成的，软件不用参与也不能参与。因此，如果MSI/MSI-X报文中要写的数据本身字节序不兼容，那么，只能向中央处理器的MSIIR寄存器的保留(Reserved)部分写入数据。换句话说，此时MSIIR寄存器是不能被写入有意义的信息的，而中央处理器也是不能产生正确的中断的。
面对这样的情况，相关技术中的处理是：既然软件不能参与MSI/MSI-X终端报文的识别，也就不能用软件的方法来避免字节序不兼容的情况。在硬件本身不能调整MSI/MSI-X中断报文中要写的数据的字节序时，只能修改芯片方案来规避，即要么更换中央处理器芯片，要么更换PCIE设备芯片，以求兼容。但是，更换芯片方案不能兼容原有产品的代码，也增加了采购成本和开发周期。要是在开发过程中才发现存在字节不兼容的情况，再想更换芯片的话，会造成更严重的损失。
本申请发明人通过将信息地址寄存器中配置的目标地址更换为特殊的地址，巧妙地产生一个针对当前中断的预处理过程，而在这个预处理过程中，能够通 过软件处理的方式简单地实现对中断报文字节序不兼容情况的调整，从而向信息地址寄存器的目标地址指向的寄存器(如MSIIR寄存器或者与MSIIR寄存器具有相同功能的寄存器)写入正确的信息，最终正确触发中断如MSI/MSI-X中断。
图2为本申请中断处理方法的实施例流程示意图，对于中央处理器与从设备存在字节序不兼容的情况，如图2所示，对于从设备侧，所述中断处理方法包括步骤2001和步骤2011。
在步骤2001中，从设备驱动在注册中断时，将从设备上的信息地址寄存器配置为指向预先指定的预处理地址。
其中，预处理地址是PCIE总线地址，预处理地址对应的硬件，设置为检查到自身被修改时，调用软件方式对字节序进行调整。
在一实施例中，从设备可以是PCIE设备。
在一实施例中，中断可以是如MSI中断，或MSI-X中断。
在步骤2011中，从设备有中断产生时，对信息地址寄存器指向的预处理地址对应的硬件进行写操作。
本申请提供的中断处理方法，将Message Address寄存器指向PCIE总线地址，使得上报的中断报文不再直接写入中央处理器的MSIIR寄存器，而是写到PCIE总线地址上，从而触发中央处理器的预处理过程，而不是直接进入MSIIR中断处理。
对于中央处理器侧，包括步骤2002和步骤2012。
在步骤2002中，中央处理器对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容。
在一实施例中，本步骤之前还包括：申请所述预处理地址。
在一实施例中，可以在中央处理器所在系统初始化时，确定出PCIE总线地址作为预处理地址。
在一实施例中，预处理地址是一个PCIE总线地址，比如：在中央处理器所在系统上申请一段专用的内存，计算出这些内存在PCIE总线上的映射地址作为预处理地址，并且这段内存设置为被硬件断点监控；再如：预处理地址为没有被使用的PCIE总线地址。预处理地址属于PCIE总线地址。又如：在中央处理器上申请1024字节内存并映射到PCIE总线得到PCIE总线地址PA(也称第一PCIE总线地址)，将申请到的中断号如MSI/MSI-X中断号乘以4，再加上得到 的PCIE总线地址PA得到的PCIE总线地址Pan(也称第二PCIE总线地址)作为预处理地址，而对应预处理地址的内存的每一个字节采用初始值0xff填充。
当预处理地址为一个没有被使用的PCIE总线地址时，由于相关技术中系统软件开发人员在制作BSP时，会对整个硬件单板的PCIE总线地址做一个整体的分配。因此，是很清楚哪些硬件资源会被映射到PCIE总线上，以及这些硬件资源对应的PCIE总线地址范围是多少。也就是说，对于本领域人员来讲，要想获知哪些PCIE总线地址范围是没有被使用的是容易实现的。
本申请实施例中，步骤2002包括：
首先，触发进入预处理过程：
如果预处理地址是中央处理器所在系统上一段内存在PCIE总线上的映射地址，那么，当该预处理地址被写入时，会触发硬件断点异常处理以进入预处理过程；如果预处理地址为没有被使用的PCIE总线地址，那么，当该预处理地址被写入时，会触发PCIE错误中断处理以进入预处理过程；如果预处理地址为PCIE总线地址PAn，中央处理器会对该预处理地址对应的1024字节内存，以4字节为单位，依次递增进行轮询(一共需要检查256次，每次检查的4个字节)，当检测出这段内存中的值不是初始值0xffffffff，则意味着该段内存被修改了，进入预处理过程。
然后，在硬件断点异常处理，PCIE错误中断处理或循环处理过程中，对写入预处理地址对应的硬件的值进行字节序转换处理，使得小端字节序调整为大端字节序；其中，字节序转换的具体如何实现并不用于限定本申请的保护范围。
最后，退出硬件断点异常处理，PCIE错误中断处理或轮询处理过程。
在步骤2012中，中央处理器将进行字节序调整后的值写入MSI机制寄存器以触发中断。
本申请提供的中断处理方法，通过将信息地址寄存器中配置的目标地址更换为特殊的地址，巧妙地产生了一个针对当前中断的预处理过程，而在这个预处理过程中，通过软件处理的方式简单地实现了对中断报文字节序不兼容的调整，保证了从设备与中央处理器字节序兼容，从而确保了向寄存器如MSIIR寄存器或者与MSIIR寄存器具有相同功能的寄存器写入正确的信息，最终正确触发了中断如MSI/MSI-X中断。
需要强调的是，本申请上述MSIIR寄存器存在于如PowerPC处理器、基于ARM架构的QorIQ Layerscape处理器等中。本申请提供的中断处理方法适用于 但不限于PowerPC处理器、QorIQ Layerscape处理器等，只要含有MSIIR寄存器或者与MSIIR寄存器具有相同功能的寄存器均可使用，而这个寄存器也就是Message Address寄存器的默认目标地址指向的寄存器。
本申请实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述任一项所述的中断处理方法。
本申请实施例还提供一种媒体传输装置，包括处理器、存储器以及存储在存储器上可在处理器上运行的计算机程序，所述计算机程序设置为执行以下步骤：对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容，将进行字节序调整后的值写入MSI机制寄存器以触发中断。
本申请还提供一种中断处理装置，至少包括：预处理模块以及中断处理模块；其中，预处理模块，设置为对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容；中断处理模块，设置为将进行字节序调整后的值写入MSI机制寄存器以触发中断。
在本申请实施例中，预处理模块设置为：预处理地址是所述中断处理装置所在系统上一段内存在PCIE总线上的映射地址。将所述内存设置为被硬件断点监控，当该预处理地址被写入时，触发硬件断点异常处理以进入预处理过程。或者，预处理地址为没有被使用的PCIE总线地址；当该预处理地址被写入时，触发PCIE错误中断处理以进入预处理过程。或者，预处理地址为PCIE总线地址PAn，会对该预处理地址对应的1024字节内存，以4字节为单位，依次递增进行轮询(一共需要检查256次，每次检查的4个字节)，当检测出这段内存中的值不是初始值0xffffffff时，意味着该段内存被修改了，进入预处理过程；在预处理过程中，对写入预处理地址对应的硬件的值进行字节序转换处理，使得小端字节序调整为大端字节序；退出硬件断点异常处理，PCIE错误中断处理，或轮询处理过程。
下面结合实施例对本申请方法进行详细描述。
以下实施例中以中断为MSI/MSI-X中断、Message Address寄存器的目的地址对应的寄存器为MSIIR寄存器为例进行描述。
第一实施例，利用硬件断点实现对MSI/MSI-X中断报文的调整。硬件断点是中央处理器提供的调试机制，可以在特定的内存地址发生修改时产生异常。第一实施例中使用硬件断点来监控MSI/MSI-X中断报文。
第一实施例中，在PCIE设备驱动初始化时，修改Message Address寄存器 的配置，使其指向被硬件断点监控的内存地址即预处理地址。这样，PCIE设备上报的MSI/MSI-X中断报文会触发硬件断点异常；而在硬件断点异常处理过程中，通过如预先设置的异常处理函数，则能够对写入预处理地址对应的内存的值调整字节序后再写入MSIIR寄存器。图4为本申请中断处理方法第一实施例的处理示意图，如图4所示，包括以下内容。
系统初始化时，假设申请一页内存并映射到PCIE总线上。以Linux操作系统为例，在Linux操作系统上有固定的一致性直接存储器访问(Direct Memory Access，DMA)和流式DMA接口，可以使用pci_alloc_consistent接口、pci_map_single接口来申请上述内存，而且，通过这些接口就能得到对应申请到的内存的PCIE总线地址。
通过linux系统提供的hw_breakpoint_add接口，注册对申请到的上述内存的写操作监控。具体实现只需要注册一个硬件断点即可。一个硬件断点只能监控32位的数据，也就是监控PCIE总线地址对应的最开始4字节内存。
当有与中央处理器不兼容的PCIE设备驱动在注册MSI/MSI-X中断时，将该PCIE设备的所有Message Address寄存器重新配置为指向申请到的PCIE总线地址。
通过linux的hw_breakpoint_exceptions_notify接口的开始位置判断出是被监控断点如图4中的断点A，检查被硬件断点监控的地址被写入的值V1，即触发硬件断点异常处理过程，将值V1重新调整为字节序正确的值V2，然后再写入MSIIR寄存器，并退出断点异常状态。
通过第一实施例的处理，与中央处理器不兼容的PCIE设备上报的MSI/MSI-X中断报文会触发硬件断点的异常处理接口，而在硬件断点的异常处理接口中，会对不兼容的字节序进行纠正以使其与中央处理器的字节序一致，保证了将正确字节序的值填入MSIIR寄存器，最终正确实现了中断号上报。
第二实施例，利用中央处理器的PCIE错误检测中断来快速响应对MSI/MSI-X中断报文的调整。
以NXP公司(原飞思卡尔半导体)生产的处理器中的PCIE控制器为例，无论是PowerPC处理器，还是基于ARM架构的QorIQ Layerscape处理器，都会提供PCIE标准之外的PCIE错误检测机制，即当PCIE总线上发生错误时，能产生中断通知中央处理器，并记录引起错误的报文的信息。比如：对于PCIE总线上的存储器读写事务，如果访问的目标PCIE总线地址是没有被使用的，即 没有任何设备响应这个读写请求的情况，那么，就会产生PCI互连无映射(PCI Express no map)错误，则向中央处理器上报PCIE错误中断；同时，PCIE错误抓取寄存器(PCI Express error capture register)会记录下错误报文的详细信息。从这些寄存器捕获的错误信息中能够分析出引起PCIE不存在映射(PCI Express no map)错误对应的目标PCIE总线地址。
第二实施例中，在PCIE设备驱动初始化时，修改Message Address寄存器的配置，使其指向没有被使用的PCIE总线地址即无效的PCIE总线地址，且地址的低16位是Message Data寄存器中的有效值。这样，由于目标地址是错误的，PCIE设备上报MSI/MSI-X中断报文时，中央处理器会捕获这个PCI Express no map错误，从而产生PCIE错误中断；而在PCIE错误中断处理过程中，如通过预先设置的PCIE错误中断处理函数，会分析导致错误的PCIE总线地址，对从地址的低16位得到的值进行字节序调整后得到正确的值后再写入MSIIR寄存器。图5为本申请中断处理方法第二实施例的处理示意图，如图5所示，包括：
选择没有被任何设备映射的，没有被使用的PCIE总线地址段。如果要求这个PCIE总线地址段的起始PCIE总线地址的最低16位全部是0，且从该起始PCIE总线地址开始，长度128KB的这一片PCIE总线空间都是没有被使用的。起始PCIE总线地址可以是32位宽，也可以是64位宽，与当前PCIE设备使用的PCIE总线标准相符即可。
当有与中央处理器不兼容的PCIE设备驱动在注册MSI/MSI-X中断时，将PCIE设备上的每一个Message Address寄存器(低32位的Message Address寄存器)重新配置为指向申请到的PCIE总线地址。
PCIE总线地址的计算规则可以是：将关联的Message Data的有效的2字节数据作为一个16位宽的无符号数(即数据类型u16)加上初始PCIE总线地址得到。还需要配置PCIE总线控制器，使能PCI Express no map错误检测中断，并注册PCIE错误中断处理函数。
通过PCIE错误中断处理函数，首先检查是不是发生PCI Express no map中断，如果发生PCI Express no map中断，则进一步检查PCI Express error capture register组中的寄存器R2和寄存器R3，从获取申请的完整的PCIE总线地址，PCIE总线地址的最低16位就是Message Data的有效的2字节数据。对PCIE总线地址的低16位中的数据进行字节序调整后写入MSIIR寄存器。最后，通过PCIE错误中断处理函数清除PCIE错误检测(PCI Express error detect)寄存器的 PCIE不存在映射(PCI Express no map，PNM)中断标志位和PCIE错误抓取状态(PCI Express error capture status)寄存器的错误抓取有效(Error capture valid，ECV)位。
第三实施例，利用轮询方式实现对MSI/MSI-X中断报文的调整。
实际应用中，有一些中央处理器，没有硬件断点或者linux操作系统不支持其上的硬件断点，则还可以采用轮询方式实现对MSI/MSI-X中断报文的调整。实现原理包括：修改Message Address寄存器的配置，使其指向被硬件断点监控的内存地址即预处理地址，让MSI/MSI-X报文将Message Data的值写到预处理地址对应的这段DDR内存中；而Linux操作系统在一些热点函数中，会检查这段内存，当发现有修改时，会对写入该端内存的信息字节序进行调整后再写入MSIIR寄存器。图6为本申请中断处理方法第三实施例的处理示意图，如图6所示，包括以下内容。
系统初始化时，假设申请1024字节内存并映射到PCIE总线上，以Linux操作系统为例，在Linux操作系统上有固定的一致性DMA和流式DMA接口，可以使用pci_alloc_consistent接口、pci_map_single接口来申请上述内存，而且，通过这些接口就能得到申请的1024字节内存对应的PCIE总线地址PA，并将这段内存的每一个字节都填充初始值0xff。
在与中央处理器存在字节许不兼容的PCIE设备驱动初始化后，会重新配置PCIE设备上的每一个Message Address寄存器以使其指向预处理地址。其中，预处理地址即PCIE总线地址PAn为：将申请到的MSI/MSI-X中断号乘以4，再加上申请的1024字节内存对应的PCIE总线地址PA后得到PCIE总线地址Pan，作为预处理地址。
设置一个处理函数f，设置为对该预处理地址对应的1024字节内存，以4字节为单位，依次递增进行轮询(一共需要检查256次，每次检查的4个字节)，当检测出这段内存中的值不是初始值0xffffffff，则意味着该段内存被修改了，进入预处理过程，将写入的信息进行字节序调整后再写入MSIIR寄存器。最后将预处理地址对应的1024字节内存的内存值恢复成0xffffffff。
其中，可以在linux内核的一些热点函数，包含但不限于：arch_cpu_idle函数、irq_exit函数、ret_fast_syscall函数、retint_user函数等中，加入对本申请设置的处理函数f的调用来实现轮询处理。
通过第三实施例的实现，与中央处理器不兼容的PCIE设备上报的 MSI/MSI-X中断报文被写入对应预处理地址的内存，等到linux内核执行到这些热点函数，就会检查到这些中断报文对内存的修改，会对不兼容的字节序进行纠正以使其与中央处理器的字节序一致，保证了将正确字节序的值填入MSIIR寄存器，最终正确实现了中断号上报。

Claims (14)

  1. 一种中断处理方法，包括：
    中央处理器对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与所述中央处理器的字节序兼容；
    所述中央处理器将进行字节序调整后的值写入信息信号中断MSI机制寄存器以触发中断；
    其中，所述预处理地址是快速外围组件互连PCIE总线地址；所述预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对所述字节序进行调整。
  2. 根据权利要求1所述的中断处理方法，其中，在所述中央处理器所在系统初始化时，确定所述PCIE总线地址作为所述预处理地址；
    所述PCIE总线地址为：在所述中央处理器所在系统上申请的一段内存在PCIE总线上的映射地址；或者为没有被使用的PCIE总线地址。
  3. 根据权利要求1或2所述的中断处理方法，其中，所述预处理地址为所述中央处理器所在系统上一段内存在PCIE总线上的映射地址；所述方法还包括：所述内存设置为被硬件断点监控；
    所述中央处理器对写入所述预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容，包括：
    当所述预处理地址被写入时，触发硬件断点异常处理；
    在所述硬件断点异常处理过程中，对写入所述预处理地址对应的硬件的值进行字节序转换处理，使得小端字节序调整为大端字节序；
    退出所述硬件断点异常处理过程。
  4. 根据权利要求1或2所述的中断处理方法，其中，所述预处理地址为没有被使用的PCIE总线地址；
    所述中央处理器对写入所述预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容，包括：
    当所述预处理地址被写入时，触发PCIE错误中断处理；
    在所述PCIE错误中断处理过程中，对写入所述预处理地址对应的硬件的值进行字节序转换处理，使得小端字节序调整为大端字节序；
    退出所述PCIE错误中断处理过程。
  5. 根据权利要求1或2所述的中断处理方法，其中，所述MSI机制寄存器为：MSIIR寄存器，或者与MSIIR寄存器具有相同功能的寄存器；
    所述中断为信息信号中断或扩展信息信号中断。
  6. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述权利要求1～5任一项所述的中断处理方法。
  7. 一种媒体传输装置，包括处理器、存储器以及存储在存储器上可在处理器上运行的计算机程序，所述计算机程序设置为执行以下步骤：
    对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容，将进行字节序调整后的值写入MSI机制寄存器以触发中断；其中，预处理地址是快速外围组件互连PCIE总线地址；预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
  8. 一种中断处理方法，包括：
    从设备驱动在注册中断时，将所述从设备上的信息地址寄存器配置为指向预先指定的预处理地址；
    所述从设备有中断产生时，对所述信息地址寄存器指向的所述预处理地址对应的硬件进行写操作；
    其中，所述预处理地址是PCIE总线地址；所述预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
  9. 根据权利要求8所述的中断处理方法，其中，所述预处理地址为PCIE总线地址，包括：
    所述预处理地址为在中央处理器所在系统上申请的一段内存在PCIE总线上的映射地址，并且所述内存设置为被硬件断点监控；或者所述预处理地址为没有被使用的PCIE总线地址。
  10. 根据权利要求8或9所述的中断处理方法，其中，所述从设备为PCIE设备。
  11. 一种中断处理装置，包括：预处理模块以及中断处理模块；其中，
    所述预处理模块，设置为对写入预处理地址对应的硬件的值进行字节序调整，使得从设备与中央处理器字节序兼容；
    所述中断处理模块，设置为将进行字节序调整后的值写入信息信号中断MSI机制寄存器以触发中断；
    其中，所述预处理地址是快速外围组件互连PCIE总线地址；所述预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
  12. 根据权利要求11所述的中断处理装置，其中，
    当所述预处理地址为所述中断处理装置所在系统上一段内存在PCIE总线上的映射地址时；
    所述预处理模块设置为：
    将所述内存设置为被硬件断点监控；当所述预处理地址被写入时，触发硬件断点异常处理；在所述硬件断点异常处理过程中，对写入所述预处理地址对应的硬件的值进行字节序转换处理，使得小端字节序调整为大端字节序；退出所述硬件断点异常处理过程；
    或者，当所述预处理地址为没有被使用的PCIE总线地址时；
    所述预处理模块设置为：
    当所述预处理地址被写入时，触发PCIE错误中断处理；在所述PCIE错误中断处理过程中，对写入所述预处理地址对应的硬件的值进行字节序转换处理，使得小端字节序调整为大端字节序；退出所述PCIE错误中断处理过程。
  13. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述权利要求8～10任一项所述的中断处理方法。
  14. 一种媒体传输装置，包括处理器、存储器以及存储在存储器上可在处理器上运行的计算机程序，所述计算机程序设置为执行以下步骤：
    从设备驱动在注册中断时，将所述从设备上的信息地址寄存器配置为指向预先指定的预处理地址；所述从设备有中断产生时，对所述信息地址寄存器指向的所述预处理地址对应的硬件进行写操作；其中，所述预处理地址是PCIE总线地址；所述预处理地址对应的硬件设置为检查到自身被修改时，调用软件方式对字节序进行调整。
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