WO2017101080A1 - 处理写请求的方法、处理器和计算机 - Google Patents

处理写请求的方法、处理器和计算机 Download PDF

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Publication number
WO2017101080A1
WO2017101080A1 PCT/CN2015/097742 CN2015097742W WO2017101080A1 WO 2017101080 A1 WO2017101080 A1 WO 2017101080A1 CN 2015097742 W CN2015097742 W CN 2015097742W WO 2017101080 A1 WO2017101080 A1 WO 2017101080A1
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Prior art keywords
processor
message
write
computer
target data
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PCT/CN2015/097742
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English (en)
French (fr)
Inventor
严春宝
张羽
郑伟
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华为技术有限公司
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Priority to PCT/CN2015/097742 priority Critical patent/WO2017101080A1/zh
Priority to JP2017525338A priority patent/JP2018503156A/ja
Priority to SG11201702806UA priority patent/SG11201702806UA/en
Priority to BR112017008674A priority patent/BR112017008674A2/pt
Priority to CA2963915A priority patent/CA2963915A1/en
Priority to RU2017118316A priority patent/RU2017118316A/ru
Priority to AU2015411096A priority patent/AU2015411096A1/en
Priority to CN201580012641.1A priority patent/CN107209725A/zh
Priority to KR1020177011796A priority patent/KR20170086484A/ko
Priority to EP15908487.0A priority patent/EP3211535A4/en
Priority to US15/487,779 priority patent/US20170220255A1/en
Publication of WO2017101080A1 publication Critical patent/WO2017101080A1/zh

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Definitions

  • Embodiments of the present invention relate to the field of computers and, more particularly, to a method, processor, and computer for processing a write request.
  • a cluster computer system generally consists of a plurality of computers, each of which runs its own operating system and can work independently.
  • the plurality of computers are represented by, for example, Ethernet, Peripheral Component Interface Express (PCIe), Infiniband and other input and output (IO) bus interconnections enable communication between computers and data exchange.
  • PCIe Peripheral Component Interface Express
  • IO input and output
  • Cluster computer systems have a wide range of applications in the high-end storage space.
  • a dual-control or multi-control storage area network (SAN) system is generally adopted, and each controller in such a dual-control and multi-control SAN system can be regarded as an independent device.
  • Computers, each controller running its own operating system, set its own memory, and the controllers are interconnected by IO bus to form a cluster computer system.
  • the high-end storage device adopts dual-control and multi-control SAN system to ensure the reliability of data storage.
  • the dual-control SAN system includes controller A and controller B.
  • Controller A and controller B each include their own CPU, DDR, and front-side bus, and controller A and controller B run their respective controllers.
  • Controller A and controller B are connected through a PCIe bus, and address translation and data exchange of two computer domains are implemented through a PCIe Non-Transparent Bridge (NTB).
  • NTB PCIe Non-Transparent Bridge
  • controller A When controller A receives an external write request for storing data (also referred to as write IO, or write IO request) through the front side bus, CPU0 of controller A first writes the data to DDR0; then CPU0 will The data is read from DDR0, the data is encapsulated into PCIe format data, and the encapsulated data is sent to controller B through the mirror channel formed by the PCIe bus between the two controllers, CPU1 of controller B This data is obtained by decapsulation and then written to DDR1.
  • data also referred to as write IO, or write IO request
  • controller A has a fatal error causing the downtime
  • controller B can still work normally, and the data in the memory of controller A is not controlled.
  • the downtime of the device A is lost, and the entire system can still operate and work normally, which improves the reliability of the storage device.
  • the entire mirror operation requires two direct memory access (DMA) operations (first read from DDR0, second write to DDR1); and PCIe ( Or Ethernet, Infiniband, etc.) IO access between devices interconnected by network protocols is bound to bring a large amount of software protocol overhead (such as data encapsulation, decapsulation), resulting in high mirror operation delay, system read and write operations per second ( Input/Output Operations Per Second (IOPS) performance is poor.
  • DMA direct memory access
  • PCIe Or Ethernet, Infiniband, etc.
  • Embodiments of the present invention provide a method and apparatus and a computer for processing a write request, which can reduce the delay of data mirroring operations in a cluster computer system and improve the IOPS of the system.
  • a method of processing a write request is provided, the method being applied to a first computer, the first computer and a second computer are connected, and the first computer and the second computer are respectively operated Operating system
  • the first computer includes a first processor
  • the second computer includes a second processor
  • the first processor and the second processor each include a system bus interface
  • the first processing The system bus interface of the device is coupled to the system bus interface of the second processor via a system bus
  • the method comprising: the first processor receiving a write request, the write request including target data to be written, and the a write address of the target data;
  • the first processor determines that the write address is located in the first memory address space;
  • the first processor writes target data in the write request to the first memory address Space, and transmitting target data in the write request to the second processor through the system bus.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, and the mirroring is reduced.
  • the delay of the operation improves the IOPS performance of the system.
  • the first processor sends the target data in the write request to the second processor by using the system bus, including: The first processor generates a mirrored message according to the write request, the mirrored message includes the target data and the write address, and the first processor sends the mirrored message to the first process a non-transparent bridge of the first processor; the non-transparent bridge of the first processor according to the first memory address space and the The mirroring relationship between the second memory address space, the write address in the mirrored message is converted into the mirrored address of the write address in the second memory address space, and the updated mirrored message is obtained; The non-transparent bridge of the first processor sends the updated mirrored message to the non-transparent bridge of the second processor through the system bus, so that the second processor is configured according to the second processor The updated mirror message received by the non-transparent bridge writes the target data to the mirror address.
  • the address translation in the mirrored message through the non-transparent bridge can simplify the internal implementation of the processor, further reduce the delay of the mirroring operation, and improve the IOPS performance of the system.
  • the method further includes: when the non-transparent bridge of the first processor is in a preset time After the second processor receives the mirroring complete message corresponding to the mirrored message, the non-transparent bridge of the first processor sends the mirroring complete message to the first processor, where the mirror completes the report.
  • the text is used to indicate that the target data has been written into the mirroring address; the first processor confirms that the mirroring operation of the target data is successful according to the mirroring completion message, and ends the mirroring transaction corresponding to the mirroring operation.
  • the method further includes: when the non-transparent bridge of the first processor is in the preset time The non-transparent bridge of the first processor sends a mirror timeout message to the first processor when the mirroring completion message is not received by the second processor; the first processor is configured according to the The mirrored timeout packet is sent to confirm that the mirroring operation fails, and the mirroring transaction ends.
  • the mirror transaction can be ended regardless of the success or failure of the mirror operation, avoiding the downtime caused by the error of the system bus operation, and enhancing the robustness of the system.
  • the first processor sends the target data in the write request to the system through the system bus
  • the second processor includes: the first processor generates a mirrored message according to the write request, where the mirrored message includes the target data and the write address; the first processor The mirrored message is sent to the non-transparent bridge of the first processor, and the non-transparent bridge of the first processor sends the mirrored message to the non-transparent bridge of the second processor by using the system bus.
  • the non-transparent bridge of the second processor is configured to convert the write address in the mirrored message into a mirrored address of the write address in the second memory address space, to obtain an updated mirrored message, and And causing the second processor to write the target data to the mirror address according to the updated mirror message.
  • the mirroring of the mirrored packets and the address translation in the mirrored packets can simplify the internal implementation of the processor, further reduce the delay of the mirroring operation, and improve the IOPS performance of the system.
  • the first processor writes target data in the write request to the first memory address space
  • the first processor generates a write message of the target data according to the write request, and the first processor writes the target data into the first memory according to the write message.
  • the write address of the address space is not limited to the first aspect, or any one of the foregoing implementation manners.
  • system bus is a QPI bus or an HT bus.
  • the second memory address space of the second computer is the first memory address space of the first computer Mirror the address space.
  • the first processor sends the target data in the write request to the system through the system bus
  • the second processor is configured to cause the second processor to write the target data to the second memory address space.
  • a method of processing a write request is provided, the method being applied to a second computer connected to a first computer, the first computer and the second computer respectively running respective operating systems
  • the first computer includes a first processor
  • the second computer includes a second processor
  • the first processor and the second processor each include a system bus interface
  • the system bus interface of the first processor passes
  • the system bus is connected to the system bus interface of the second processor
  • the second memory address space of the second computer is a mirror address space of the first memory address space of the first computer
  • the method comprising:
  • the second processor receives target data from the first processor through the system bus, where the target data is data to be written into a memory of the first processor, where a write address of the target data is located In the first memory address space; the second processor writes the target data into the second memory address space.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, and the mirroring is reduced.
  • the delay of the operation improves the IOPS performance of the system.
  • the second processor receives the target data from the first processor by using the system bus, including: the second processor a transparent bridge receives, by the system bus, a mirrored message from the first processor, the mirrored message including the target data and a mirrored address of the write address in the second memory address space; Writing, by the second processor, the target data to the second memory address space, comprising: the non-transparent bridge of the second processor converting the mirrored message into a write message of the target data; The non-transparent bridge of the second processor writes the write message into the mirror address of the second memory address space by a memory controller of the second computer.
  • the conversion of the message type or format through the non-transparent bridge can simplify the internal implementation of the processor, further reduce the delay of the mirror operation, and improve the IOPS performance of the system.
  • the method further includes: receiving, by the memory controller, the non-transparent bridge of the second processor Writing a completion message corresponding to the message, the write completion message including the mirror address; and the non-transparent bridge of the second processor according to the first memory address space and the second memory address space a mapping relationship, the mirroring address is converted into the write address; the non-transparent bridge of the second processor sends a mirroring complete message corresponding to the mirrored message to the first processor, where the mirror completes the report
  • the file includes the write address, and the mirror completion message is used to indicate that the target data has been written to the mirror address.
  • the second processor receives target data from the first processor by using the system bus, including The non-transparent bridge of the second processor receives, by the system bus, a mirrored message from the first processor, the mirrored message includes the target data and the write address;
  • the second process Writing the target data to the second memory address space includes: the non-transparent bridge of the second processor converts the mirrored message into a write message of the target data, and writes the Converting an address into a mirrored address of the write address in the second memory address space; the non-transparent bridge of the second processor writing the write message to the memory by a memory controller of the second computer The mirrored address of the second memory address space.
  • system bus is a QPI bus or an HT bus.
  • a processor is provided, where the processor is located in a first computer, the first computer and a second computer are connected, and the first computer and the second computer respectively run respective operating systems.
  • the second computer includes another processor, the processor and the other processor each include a system bus interface, and the system bus interface of the processor is coupled to the system bus Connected to a system bus interface of another processor, the processor further comprising a controller and an internal bus, the controller being coupled to the system bus interface of the processor via the internal bus, the controller for receiving a write request
  • the write request includes target data to be written, and a write address of the target data; determining that the write address is located in the first memory address space; and writing target data in the write request to the first a memory address space, and the target data in the write request is sent to the another processor through the system bus.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, and the mirroring is reduced.
  • the delay of the operation improves the IOPS performance of the system.
  • the processor further includes a non-transparent bridge, the non-transparent bridge is connected to the system bus interface, and the non-transparent bridge passes through the internal bus
  • the controller is connected to the controller, where the controller is configured to generate a mirrored message according to the write request, where the mirrored message includes the target data and the write address; and the mirrored message is sent to the a non-transparent bridge; the non-transparent bridge is configured to convert a write address in the mirror message into the write address according to a mirror relationship between the first memory address space and the second memory address space And the mirrored address in the second memory address space, the updated mirrored message is obtained; and the updated mirrored message is sent to the non-transparent bridge of the another processor by using the system bus, so that the Another processor writes the target data to the mirrored address according to the updated mirrored message received by the non-transparent bridge of the other processor.
  • the address translation in the mirrored message through the non-transparent bridge can simplify the internal implementation of the processor, further reduce the delay of the mirroring operation, and improve the IOPS performance of the system.
  • the non-transparent bridge is further configured to receive from the another processor within a preset time After the mirroring completion message corresponding to the mirrored message, the mirroring completion message is sent to the controller, where the mirroring completion message is used to indicate that the target data has been written into the mirroring address; It is further configured to: according to the mirroring completion message, confirm that the mirroring operation of the target data is successful, and end the mirroring transaction corresponding to the mirroring operation.
  • the non-transparent bridge is further configured to not use the another processor during the preset time And receiving, by the first processor, a mirror timeout message, and the controller is further configured to: according to the mirror timeout message, confirm that the mirroring operation fails, and end the mirroring transaction. .
  • the mirror transaction can be ended regardless of the success or failure of the mirror operation, avoiding the downtime caused by the error of the system bus operation, and enhancing the robustness of the system.
  • the controller is specifically configured to generate a mirrored message according to the write request, where the mirrored message includes Decoding the target data and the write address; transmitting the mirrored message to a non-transparent bridge of the processor, the non-transparent bridge of the processor passing through the system bus, to the non-transparent processor Transmitting, by the transparent bridge, the mirrored message, so that the non-transparent bridge of the another processor converts the write address in the mirrored message into a mirrored address of the write address in the second memory address space. Obtaining the updated mirror message, and causing the another processor to write the target data to the mirror address according to the updated mirror message.
  • the mirroring of the mirrored packets and the address translation in the mirrored packets can simplify the internal implementation of the processor, further reduce the delay of the mirroring operation, and improve the IOPS performance of the system.
  • the controller is specifically configured to generate, according to the write request, a write message of the target data; Writing a message, the target data being written into the write address of the first memory address space.
  • system bus is a QPI bus or an HT bus.
  • the second memory address space of the second computer is the first memory address space of the first computer Mirror the address space.
  • the processor sends the target data in the write request to the another by using the system bus a processor for the other processor to write the target data to the second memory address space.
  • a processor is provided, where the processor is located in a second computer connected to the first computer, where the first computer and the second computer respectively run respective operating systems, the first The computer includes another processor, the other processor and the processor each including a system bus interface, the system bus interface of the other processor being coupled to the system bus interface of the processor via a system bus,
  • the second memory address space of the second computer is the first calculation a mirrored address space of a first memory address space of the machine
  • the processor including a controller, a non-transparent bridge, and an internal bus, the non-transparent bridge being coupled to a system bus interface of the processor, the controller and the A non-transparent bridge is connected through the internal bus, the non-transparent bridge is configured to receive target data from the another processor through the system bus, the target data being a memory to be written to the another processor Data in which the write address of the target data is located in the first memory address space; the target data is written into the second memory address space.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, and the mirroring is reduced.
  • the delay of the operation improves the IOPS performance of the system.
  • the non-transparent bridge is configured to receive, by using the system bus, a mirrored message from the another processor, where the mirrored message includes the Target data and a mirrored address of the write address in the second memory address space; converting the mirrored message into a write message of the target data; the memory controller of the second computer The write message is written into the mirror address of the second memory address space.
  • the conversion of the message type or format through the non-transparent bridge can simplify the internal implementation of the processor, further reduce the delay of the mirror operation, and improve the IOPS performance of the system.
  • the non-transparent bridge is further configured to receive, from the memory controller, a write completion corresponding to the write message a message, the write completion message includes the mirror address; converting the mirror address to the write address according to a mapping relationship between the first memory address space and the second memory address space;
  • the other processor sends a mirroring completion message corresponding to the mirrored message, where the mirroring completion message includes the write address, and the mirroring completion message is used to indicate that the target data has been written into the mirrored address.
  • the non-transparent bridge is specifically configured to receive a mirror image from the another processor by using the system bus And the mirrored message includes the target data and the write address; converting the mirrored message into a write message of the target data, and converting the write address into the write address in the a mirrored address in the second memory address space; the write message is written into the mirrored address of the second memory address space by a memory controller of the second computer.
  • system bus is a QPI bus or an HT bus.
  • a computer is provided, the computer being connected to another computer, the computer and the other computer respectively running respective operating systems, the computer comprising a first processor, the other computer
  • a second processor is included, each of the first processor and the second processor includes a system bus interface, and a system bus interface of the first processor is connected to a system bus interface of the second processor through a system bus
  • the computer includes: a receiving module, configured to receive a write request, the write request includes target data to be written, and a write address of the target data; and a determining module, configured to determine that the write address is located in the first a mirroring module, configured to write target data in the write request to the first memory address space, and send target data in the write request to the first Two processors.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, and the mirroring is reduced.
  • the delay of the operation improves the IOPS performance of the system.
  • the mirroring module is configured to generate a mirroring message according to the write request, where the mirrored message includes the target data and the write address; And sending the mirrored packet to the non-transparent bridge of the first processor; and writing the mirrored packet according to a mirroring relationship between the first memory address space and the second memory address space Converting an address into a mirrored address of the write address in the second memory address space to obtain an updated mirror message; sending the update to the non-transparent bridge of the second processor by using the system bus The mirrored message, so that the second processor writes the target data to the mirrored address according to the updated mirrored message received by the non-transparent bridge of the second processor.
  • the address translation in the mirrored message through the non-transparent bridge can simplify the internal implementation of the processor, further reduce the delay of the mirroring operation, and improve the IOPS performance of the system.
  • the mirroring module is further configured to: when the non-transparent bridge of the first processor is within a preset time After receiving the mirroring complete message corresponding to the mirrored message, the second processor sends the mirroring complete message to the first processor, where the mirrored complete message is used to indicate that the target data has been The mirroring address is written, and the mirroring operation of the target data is successful according to the mirroring completion message, and the mirroring transaction corresponding to the mirroring operation is ended.
  • the mirroring module is further configured to: when the non-transparent bridge of the first processor is in the preset time Sending a mirror to the first processor when the mirror completion message is not received from the second processor Such as a timeout message; according to the mirror timeout message, it is confirmed that the mirroring operation fails, and the mirroring transaction is ended.
  • the mirror transaction can be ended regardless of the success or failure of the mirror operation, avoiding the downtime caused by the error of the system bus operation, and enhancing the robustness of the system.
  • the mirroring module is further configured to generate a mirrored message according to the write request, where the mirrored message includes Transmitting the mirrored message to a non-transparent bridge of the first processor, the non-transparent bridge of the first processor passes the system bus, to the second The non-transparent bridge of the processor sends the mirrored message, so that the non-transparent bridge of the second processor converts the write address in the mirrored message into the write address in the second memory address space.
  • the mirrored address, the updated mirrored message is obtained, and the second processor is caused to write the target data to the mirrored address according to the updated mirrored message.
  • the mirroring of the mirrored packets and the address translation in the mirrored packets can simplify the internal implementation of the processor, further reduce the delay of the mirroring operation, and improve the IOPS performance of the system.
  • the mirroring module is configured to generate a write message of the target data according to the write request; Writing a message, the target data being written into the write address of the first memory address space.
  • system bus is a QPI bus or an HT bus.
  • the second memory address space of the another computer is a mirror address of the first memory address space of the computer space.
  • the mirroring module sends the target data in the write request to the first a second processor, such that the second processor writes the target data to the second memory address space.
  • a computer is provided, the computer being connected to another computer, the other computer and the computer respectively running respective operating systems, the another computer comprising a first processor, the computer Including a second processor, the first processor and the second processor Each includes a system bus interface, the system bus interface of the first processor is connected to the system bus interface of the second processor through a system bus, and the second memory address space of the computer is the first of the another computer a mirrored address space of the memory address space, the computer comprising: a mirroring module, configured to receive target data from the first processor through the system bus, where the target data is to be written to the first processor The data in the memory, the write address of the target data is located in the first memory address space; and the write operation module is configured to write the target data into the second memory address space.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, and the mirroring is reduced.
  • the delay of the operation improves the IOPS performance of the system.
  • the mirroring module is configured to receive, by using the system bus, a mirrored message from the first processor, where the mirrored message includes the target Data and a mirrored address of the write address in the second memory address space; the write operation module is specifically configured to convert the mirrored message into a write message of the target data; and pass the memory of the computer The controller writes the write message into the mirror address of the second memory address space.
  • the conversion of the message type or format through the non-transparent bridge can simplify the internal implementation of the processor, further reduce the delay of the mirror operation, and improve the IOPS performance of the system.
  • the mirroring module is further configured to receive, from the memory controller, a write completion report corresponding to the write message And the write completion message includes the mirror address; converting the mirror address to the write address according to a mapping relationship between the first memory address space and the second memory address space; A processor sends a mirroring completion message corresponding to the mirrored message, the mirroring completion message includes the write address, and the mirroring completion message is used to indicate that the target data has been written into the mirrored address.
  • the mirroring module is specifically configured to receive a mirrored message from the first processor by using the system bus
  • the mirroring message includes the target data and the write address
  • the write operation module is specifically configured to convert the mirrored message into a write message of the target data, and convert the write address into The mirror address of the write address in the second memory address space
  • the write message is written into the mirror address of the second memory address space by a memory controller of the computer.
  • system bus is a QPI bus or an HT bus.
  • the system bus is generally used to realize the connection of various functional components in the computer, which belongs to a type of computer internal bus, and has the characteristics of high bandwidth and low delay.
  • two are The processors of different computers are connected together, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and complicated protocol conversion is not required, thereby reducing the delay of the mirroring operation.
  • FIG. 1 is a schematic diagram of a connection of a conventional cluster computer system.
  • FIG. 2 is a schematic diagram of the connection of a computer system according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for processing a write request according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a CPU based on QPI technology.
  • FIG. 5 is a schematic flowchart of a data mirroring operation according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a data mirroring operation according to an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart of a method for processing a write request according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • Figure 10 is a schematic block diagram of a computer in accordance with an embodiment of the present invention.
  • Figure 11 is a schematic block diagram of a computer in accordance with an embodiment of the present invention.
  • a computer cluster system generally includes a plurality of computers, and a plurality of computers are in a certain form. Connected to each other, each computer runs its own operating system independently, and each computer can communicate and exchange data with each other.
  • a computer in the computer cluster system (hereinafter referred to as the first computer) mirrors the data to be written into the memory (hereinafter referred to as target data) to another through mirroring operation.
  • the memory of the computer (hereinafter referred to as the second computer) is equivalent to backing up the data in the memory of the first computer in the second computer. When the first computer is down for some reason, the data in the memory is in the second.
  • the computer still has backups, which will not cause loss of memory data and improve the reliability of data storage.
  • the first computer and/or the second computer described above may be a device or a node including a processor and a memory and independently operating an operating system, which is named as the first computer and/or the first embodiment of the present invention.
  • the two computers are merely for convenience of description and mutual distinction, and should not be construed as limiting the embodiments of the present invention.
  • the first computer and/or the second computer may correspond to different devices or nodes.
  • the computer in the field of common cluster computer systems, such as communication or server, the computer may be a host.
  • storage devices such as dual-control or multi-control SAN, computers can be controllers.
  • the computer in the cluster system is taken as an example for example.
  • the method for processing the write request provided by the embodiment of the present invention can be applied as long as the processors in the two independent computers are connected through the system bus.
  • the computers of the computer cluster system are connected through an IO bus, such as PCIe, Ethernet, and Infiniband.
  • IO bus such as PCIe, Ethernet, and Infiniband.
  • the mirroring of data between computers via the IO bus involves not only multiple DMA operations, but also complex software protocol overhead.
  • the first computer needs to extract the target data from the memory, and package the target data into a protocol conforming to PCIe, Ethernet, Infiniband, etc., to the second computer, and the second computer needs to decapsulate the packet, and then The target data is written into the memory of the second computer, so the mirroring operation is less efficient.
  • the embodiment of the present invention directly connects the processors of two or more computers in the cluster computer system by using the system bus, and can design a suitable system based on the system.
  • the data mirroring operation flow completed on the bus is described in detail below with reference to FIG. 2 and FIG. 3.
  • FIG. 2 is a schematic diagram of the connection of a computer system according to an embodiment of the present invention.
  • the first computer and the second computer may be two computers in a cluster computer system, each of which independently operates its own operating system.
  • the processors of the two computers both include a system bus interface, and a similar "loosely coupled" side is used between the processors. , connected by a system bus.
  • at least part of the memory address space (hereinafter referred to as the second memory address space) of the second computer is a mirror address space of at least part of the memory address space (hereinafter referred to as the first memory address space) of the first computer.
  • FIG. 3 is a schematic flowchart of a method for processing a write request according to an embodiment of the present invention.
  • the method of FIG. 3 can be performed by the first processor of FIG. 2, and the method of FIG. 3 includes:
  • the first processor receives a write request, where the write request includes target data to be written, and a write address of the target data.
  • the first processor determines that the write address is located in the first memory address space.
  • the first processor writes the target data in the write request into the first memory address space according to the write request, and sends the target data in the write request to the second processor through the system bus, so as to indicate (or indicate)
  • the second processor writes the target data to the second memory address space.
  • the first processor may directly write the target data to the first memory address space; in another embodiment, the first processor may write the target data to the first memory address space through the memory controller.
  • the embodiment of the present invention does not specifically limit the operation sequence in which the first processor writes the target data into the first memory address space and the first processor sends the target data to the second processor through the system bus, and may be executed in parallel. Can be executed sequentially.
  • the system bus is generally used to realize the connection of various functional components in the computer, which belongs to a type of computer internal bus, and has the characteristics of high bandwidth and low delay.
  • the computer is connected through the system bus.
  • the processors belonging to two different computers in the cluster system are connected together, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, thereby reducing
  • the delay of the mirroring operation improves the IOPS performance of the system.
  • the prior art sends a mirrored message between two computers through an IO device, so the mirror data (corresponding to the target data in the above) needs to be taken out from the memory first, and then the target data is sent to the IO.
  • the device using the network card as an example
  • the network card encapsulates the mirrored data into a packet by the software driver of the network card, and sends the packet to the receiving end.
  • the receiving end decapsulates the packet, and then reports the packet.
  • the text is written into the memory of the receiving end.
  • the whole process requires multiple memory read and write operations, and involves encapsulation and decapsulation of complex protocols.
  • the embodiment of the present invention is directly sent by the first processor to the second processor through the system bus, eliminating the need to read from the memory.
  • the process of data in addition, although the system bus can also be encapsulated in the message (image message as described below), but the system bus belongs to the internal bus, and the package form of the message can also be designed. It is relatively simple. For example, it is possible to distinguish between the write message of the data and the mirrored message of the data by changing some of the fields in the write message, without involving complex protocols and encapsulation forms like IO devices (such as network cards).
  • the processor may include one or more system bus interfaces.
  • the system bus may be a bus that supports Cache Coherent (CC).
  • CC Cache Coherent
  • the system bus may be referred to as a CC bus.
  • the system bus can be one of a Hyper Transport (HT) bus and a Quick Path Interconnect (QPI) bus.
  • HT Hyper Transport
  • QPI Quick Path Interconnect
  • the method illustrated in FIG. 3 may be applied to the field of storage devices.
  • the cluster computer system may be a dual-control or multi-control system, and any of the first computer and the second computer is equivalent to a controller in the field of storage devices.
  • the first memory address space may be a partial memory address space of the first computer, and the second memory address space may be a partial memory address space of the second computer.
  • the first memory address space may also be a mirror address space of the second memory address space, or the first memory address space and the second memory address space may be mutually mirrored address spaces.
  • the first memory address space and the second memory address space may be spaces with consecutive addresses (referred to as consecutive address spaces); or spaces with discontinuous addresses (referred to as non-contiguous address spaces).
  • the first memory address space and the second memory address space are consecutive address spaces, and setting the first memory address space and the second memory address space to a continuous address space may simplify hardware implementation of the system.
  • the spatial size of the first memory address space and the second memory address space may be equal.
  • the first memory address space and the second memory address space may be in-memory cacheable spaces, so that the first memory address space and the second memory address space can be mirrored. Operation can also solve the cache consistency problem between multiple processors.
  • the second memory address space is a mirror address space of the first memory address space, and the data written in the first memory address space needs to be written into the second memory address space, or The write operation to the first memory address space needs to be mirrored into the second memory address space. That is, the same data is in the first memory address space and the second memory address space. All are stored, which ensures that the data of the cluster computer system is safe and reliable.
  • the mirror relationship between the first memory address space and the second memory address space may be pre-configured. After pre-configuration, the mirror relationship can be set to remain static or set to dynamic adjustment.
  • the firmware of the processor can be responsible for the initialization of the mirror address space, and then the processors of the two computers mutually send notification messages through the system bus to notify each other of the location and size of the respective mirror address space.
  • it may be configured by the out-of-band management system at system initialization, and the configuration results are notified to each computer.
  • the mirror relationship of the first memory address space and the second memory address space may be configured or updated (in real time) according to the needs of the cluster computer system.
  • the success of the mirrored address space configuration can affect whether a mirror operation can be performed between computers, but does not affect the normal startup and operation of the computer.
  • step 330 may include: the first processor generates a write message of the target data according to the write request; and the first processor writes the target data into the first memory address space according to the write message.
  • Write address The message here can also be called a message.
  • the concept of PCIe's non-transparent bridge In order to realize the system bus-based mirroring function between two computer systems, you can refer to the concept of PCIe's non-transparent bridge, and set a non-transparent bridge between the two systems to separate the address fields of the two systems.
  • the transparent bridge can complete the conversion of the memory address (converting the memory address of one system into the mirror address corresponding to the memory address in another system), and other mirror-related operations.
  • the following is a specific example of the non-transparent bridge. The form is described in detail.
  • Non-transparent bridges can be implemented in hardware or in software.
  • a non-transparent bridge can be implemented by a circuit, and in this case, the non-transparent bridge can be referred to as a non-transparent bridge circuit.
  • the non-transparent bridge is implemented in hardware to further improve the efficiency of the mirroring operation and the overall IOPS of the system.
  • the prior art sends mirrored messages through IO devices (such as network cards). These IO devices process mirrored packets through their respective software drivers. Compared with the pure hardware, the software processes the mirrored packets. Significantly lower, the delay is larger. You can set the non-transparent bridge to the hardware that handles the mirroring operation.
  • the non-transparent bridge translates the address and/or packet type of the mirrored packets.
  • the hardware implementation can further improve the efficiency of the mirroring operation.
  • a non-transparent bridge can be implemented by code.
  • the non-transparent bridge can be referred to as a non-transparent bridge logic module. Setting the non-transparent bridge to hardware that handles mirroring operations can reduce the burden on the processor.
  • the following uses a non-transparent bridge as the hardware. The location of the non-transparent bridge and the connection between the non-transparent bridge and other components inside the processor. The relationship is illustrated.
  • the processor generally includes a controller and an arithmetic unit, and the controller is generally responsible for logic control inside the processor. System and overall scheduling, the operator performs data-related integer or floating-point operations. To better support mirror-related operations, a non-transparent bridge can be placed at the system bus interface of the processor, which can be connected to the controller inside the processor through the internal bus of the processor. It should be understood that the names and types of controllers and internal buses in different types of processors may be different. Referring to FIG. 4, taking a processor based on QPI technology as an example, the internal controller may refer to its internal cache proxy (Cache). Agent, CA), Home Agent (HA), etc., the devices inside the processor are connected by a ring bus (Ring Bus).
  • Cache cache proxy
  • Agent, CA Agent
  • HA Home Agent
  • the CA is a transaction processing engine located inside the CPU on the cache side.
  • the HA is a transaction processing engine located inside the CPU on the memory controller side, and is connected to the DDR.
  • the internal transaction processing engines of the CPU are connected by a ring bus, and the message is Message) can be passed between the engines through the ring bus according to certain rules, and complete a certain transaction, such as read transaction, write transaction, etc., under the cooperation of each engine.
  • the CA may be responsible for sending a data writeback message (WbData) for requesting to write data to the memory to the HA, requesting that the data in the write request be written into the memory, and receiving the HA return.
  • WbData data writeback message
  • the response message indicates that the data write operation is complete.
  • a non-transparent bridge (NTB in Figure 4) can be placed at the system bus interface, one end connected to the system bus interface and the other end connected to the internal bus of the CPU, such that the controller inside the processor, such as The CA can exchange messages or data through the internal bus and the non-transparent bridge.
  • the non-transparent bridge in order to cooperate with the mirroring operation of the target data, you can import mirrored transactions and configure mirror-related transactions. Further, the memory address conversion, the packet format conversion, the normal end of the mirror transaction, the abnormal end judgment, the interrupt report, and the like can be implemented by using the NTB. The details are described below separately.
  • the message related to the mirror transaction can be divided into a message with a data payload (or a payload, corresponding to the target data above) and a message without a data payload.
  • the packet with the data payload can be referred to as a mirrored message
  • the mirrored message can be used to mirror the data payload of the memory address space to be written into the first computer to the memory address space of the second computer.
  • the mirrored transaction may carry the transaction number of the mirror transaction, the write address of the data payload (the address will be converted by a non-transparent bridge, as described below), and the data payload.
  • the mirror operation transaction number in the mirrored message may be represented by an 8-bit binary number, and the address in the mirrored message may be determined according to a specific implementation of the processor, for example, a 46-bit to 48-bit binary number in the X86.
  • the mirror operation transaction number can be 0X01, indicating a mirrored transaction numbered 01.
  • the mirror address can be 0X001234.
  • a packet without a data payload may include a mirroring completion packet and a mirroring timeout packet.
  • the packet may be used to complete the mirroring operation.
  • the mirroring completion packet may be used to indicate that the mirroring operation is completed, and the mirroring timeout is performed.
  • the message can be used to indicate that the mirror operation failed due to a timeout. You can also carry the address related to the mirror operation and the mirror transaction number in such packets.
  • the memory address space ⁇ 0X04_0000, 0X04_FFFF ⁇ of the first processor is mirrored with the memory address space ⁇ 0X0A_0000, 0A_FFFF ⁇ of the second processor (the mirror relationship can be pre-configured), and the mirror transaction related flow example is as follows.
  • Step 1 A CA in the first processor needs to write some data into a memory address (such as 0X04_1234).
  • the CA can find that the memory address belongs to an address in the mirror address space ⁇ 0X04_0000, 0X04_FFFF ⁇ that has been paired with other systems, so the CA not only sends a write message for the first processor, but also issues a mirror image.
  • a mirrored packet in space can be written in the normal write operation.
  • the mirrored packet can be sent to the non-transparent bridge and processed by the non-transparent bridge of the first processor.
  • the CA may perform the foregoing operations in parallel, or may perform the foregoing operations in sequence.
  • Step 2 After receiving the mirrored message, the non-transparent bridge of the first processor can modify the address of 0X04_1234 to 0X0A_1234 according to the mirroring relationship of the memory address space, update the mirrored message, and then update the mirrored message.
  • Send to the system bus interface here can be the QPI port.
  • Step 3 The system bus interface of the first processor sends the updated mirror message to the system bus interface of the second processor;
  • Step 4 The system bus interface of the second processor sends the mirrored message to the non-transparent bridge of the second processor;
  • Step 5 The non-transparent bridge of the second processor converts the mirrored message into a write message, and sends the write message to the memory controller through the internal bus of the second processor to complete the corresponding memory write operation;
  • Step 6 After completing the memory write operation, the memory controller of the second processor returns a mirror write completion message to the non-transparent bridge of the second processor;
  • Step 7 The non-transparent bridge of the second processor will mirror according to the mirror relationship of the memory address space.
  • the address field 0X0A_1234 in the write completion message is modified to 0X04_1234, and is sent to the system bus interface of the second processor;
  • Step 8 The system bus interface of the second processor sends the mirroring completion message to the system bus interface of the first processor
  • Step 9 The system bus interface of the first processor sends the mirroring completion message to the non-transparent bridge of the first processor;
  • Step 10 The non-transparent bridge of the first processor sends the mirroring completion message to the initiator of the mirrored message through the internal bus of the first processor, that is, the CA in step one;
  • Step 11 The CA receives the mirroring completion packet, determines that a mirroring operation is successfully completed, ends the transaction, and releases the corresponding resource.
  • the non-transparent bridge of the first processor may be configured with a timer.
  • the mirroring timeout packet may be sent to the CA to indicate that the mirroring operation fails.
  • the functions of the NTB may include the conversion of a memory address, the conversion of a message or a message format, the judgment of an abnormal end of a mirror transaction, and the interruption of an advertisement.
  • the foregoing step 340 may include: the first processor generates a mirrored message according to the write request, where the mirrored message includes the target data and the write The address, the mirror message is used to write the target data to the mirror address of the write address in the second memory address space; the first processor sends the mirrored message to the non-transparent bridge of the first processor; The transparent bridge converts the write address in the mirrored message into a mirrored address according to the mirroring relationship between the first memory address space and the second memory address space, and obtains the updated mirrored message; the non-transparent bridge of the first processor passes The system bus sends the updated mirror message to the second processor, so that the second processor writes the target data to the mirror address according to the updated mirror message.
  • the target data can be written into the first memory address space by using the write message, and the target data can be written into the second memory address space by using the mirrored message, and the message format of the write message and the mirrored message can be Differently, the first processor can perform corresponding transaction operations according to their formats. For example, the first processor performs a write operation on the write message of the target data, and writes the target data into the memory; the first processor performs a mirror operation on the mirrored message, and mirrors the message through the system bus and the second processor. The target data in the image is mirrored into the second memory address space.
  • the format and name of the write message generated by different types of processors may be different.
  • an Intel processor supporting QPI technology is used as an example, and the generated write message may be referred to as a data write-back message, that is, WbData message.
  • WbData message When the system bus is a QPI bus, the above-mentioned write message may be a WbData message.
  • the mirrored message may be referred to as a WbMir message, and the two may use different message formats.
  • the method of FIG. 3 may further include: after the non-transparent bridge of the first processor receives the mirroring completion message corresponding to the mirrored message from the second processor within a preset time, A non-transparent bridge of the processor sends a mirroring completion message to the first processor, and the mirroring completion message is used to indicate that the target data has been written into the mirroring address; the first processor confirms that the mirroring operation of the target data is successful according to the mirroring completion message. , ends the mirror transaction corresponding to the mirror operation.
  • the method of FIG. 3 may further include: when the non-transparent bridge of the first processor does not receive the mirroring completion message from the second processor within a preset time, the first processor The non-transparent bridge sends a mirrored timeout packet to the first processor.
  • the first processor confirms that the mirroring operation fails and ends the mirroring transaction according to the mirroring timeout packet.
  • the timeout There may be multiple ways to determine the timeout. For example, when sending the updated mirror message to the second processor, the non-transparent bridge of the first processor may set a timer, if the timer expires, When the mirroring completion packet is received, it is determined that the mirroring operation has timed out.
  • the embodiment of the present invention adds complete logic for performing a mirroring operation on the system bus in the first processor, which causes the mirroring operation to be ended regardless of the success or failure of the mirroring operation, thereby preventing the mirroring operation on the system bus from failing.
  • the resulting system downtime On this basis, it is possible to further support the violent hot plugging of the system bus interface of the processor inside the computer, such as the hot plug or surge removal of the system bus interface.
  • each processor can access local memory, or access non-local memory through the system bus, that is, the memory of multiple processors can be shared.
  • system bus such as non-uniform Memory Access Architecture , NUMA
  • each processor can access local memory, or access non-local memory through the system bus, that is, the memory of multiple processors can be shared.
  • the operation of a single operating system in the memory of such a multiprocessor system is essentially a stand-alone system, not a clustered computer system.
  • the operation of the system bus between multiple processors is still essentially regarded as a stand-alone system. Operation.
  • the system bus operation of a stand-alone system is done by hardware.
  • a system bus operation error occurs in a processor (such as the violent hot swap of the system bus interface), it will be a hardware error, and a hardware error will cause a single system. machine.
  • complete logic is added to the first processor to perform mirror operations on the system bus, which ends the process regardless of the success or failure of the mirror operation. At the mirroring operation, the system will not be down because the system bus operation is not completed or an error occurs.
  • the processor is a processor supporting QPI technology
  • the system bus is a QPI bus as an example (see FIG. 4 for specific structure), and details are described between the computers connected by the system bus in the cluster computer system.
  • Data mirroring operation process It should be understood that the embodiment of the present invention does not limit the timing of the steps of FIG. 5 and FIG. 6.
  • the steps in FIG. 5 and FIG. 6 may be performed in a different order from that presented in FIG. 5 and FIG. 6, and may not be All the operations in FIGS. 5 and 6 are to be performed.
  • the triggering condition of the process of the mirroring operation described in FIG. 5 and FIG. 6 may be that the CA of the first computer finds that the write address of the write request it receives is located in the mirror address space of the memory of the first computer (corresponding to the first in the above) Memory address space), where the mirrored address space can be pre-configured.
  • the CA of the first CPU generates a data writeback message (WbData), and sends the write message to the HA of the first CPU.
  • the write message includes the target data to be written to the memory.
  • the CA of the first CPU generates a mirrored message (WbMir), and sends the mirrored message to the non-transparent bridge of the first CPU.
  • the mirrored message includes the target data to be written to the memory.
  • the format of the data write-back message and the mirrored message may be different, so that the processor determines, according to the message format, the operation type corresponding to the message of the next different format. For example, a write operation is performed on a data writeback message, and a mirror operation is performed on the mirrored message. Step S502 and step S504 may be performed simultaneously, or any one of them may be executed first.
  • the HA of the first CPU After receiving the data writeback message, the HA of the first CPU writes the target data into the memory DDR of the first computer, and returns a data write completion message to the CA.
  • the non-transparent bridge can be located at the system bus interface of the CPU, and the transfer between the non-transparent bridges can be done through the QPI interface between the CPUs and the QPI bus.
  • the non-transparent bridge of the second CPU After receiving the mirrored message, the non-transparent bridge of the second CPU converts the mirrored message into a data write-back message and sends the message to the HA in the second CPU.
  • the data writeback message includes target data.
  • the HA of the second CPU After receiving the data writeback message, the HA of the second CPU writes the target data into the memory DDR of the second computer, and returns a data write completion message to the non-transparent bridge of the second CPU.
  • the memory address space of the write target data and the first memory address space of the first computer are mutually mirrored address spaces.
  • the non-transparent bridge of the second CPU sends the data back after the received data is written back. Write the completion message to the non-transparent bridge of the first CPU.
  • the data return completion message can be delivered through the QPI bus between the non-transparent bridge modules.
  • S516 The non-transparent bridge of the first CPU converts the received data write completion message into a mirror completion message (MirCMP), and sends the message to the CA of the first CPU.
  • MirCMP mirror completion message
  • the CA of the first CPU can notify the upper application that the mirror transaction is completed, or notify the upper application that the mirror operation is successful.
  • the embodiment of the invention connects the processor of the computer through the QPI bus, and designs a set of mirror operation flow based on the QPI bus. Since the QPI bus belongs to the system bus, it has a low delay and a high bandwidth, which can improve the efficiency of the data mirroring operation.
  • the mirroring operation does not always end successfully. It may cause a mirroring operation due to a system bus interface failure or a hot swap (hot add or hot removal) of the bus cable between the CPU or the two hosts. failure.
  • a hot swap hot add or hot removal
  • the embodiment of the present invention provides a processing manner in which the mirroring operation ends abnormally. For details, refer to FIG. 6.
  • S602, S604, S608, S610, and S612 in FIG. 6 are similar to S502, S504, S508, S510, and S512 in FIG. 5, respectively, and are not described herein again.
  • the non-transparent bridge of the first CPU may set a timer when executing S608, and the timing duration may be set according to experiments or experience.
  • the CA of the first CPU After receiving the mirror timeout packet, the CA of the first CPU confirms that the mirror operation fails (TranFial) and ends the mirroring operation.
  • the CA can report the result of the failure of the mirroring operation to the operating system, and the operating system records the log related to the failure of the mirroring operation.
  • FIG. 7 is a schematic flowchart of a method for processing a write request according to an embodiment of the present invention.
  • the method of Figure 7 can be performed by the second processor of Figure 2, the method of Figure 7 comprising:
  • the second processor receives the target data from the first processor by using the system bus, where the target data is data to be written into the memory of the first computer, and the write address of the target data is located in the first memory address space.
  • the second processor writes the target data into the second memory address space.
  • the second processor can directly write the target data to the first memory address space; in another embodiment, the second processor can write the target data to the first memory address space through the memory controller.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated Protocol conversion reduces the latency of mirroring operations and improves system IOPS performance.
  • step 710 may include: the non-transparent bridge of the second processor receives the mirrored message from the first processor by using the system bus, the mirrored message includes the target data, and the write address is in the second a mirror address in the memory address space; the second processor writes the target data into the second memory address space, including: the non-transparent bridge of the second processor converts the mirrored message into a write message of the target data; the second processor The non-transparent bridge writes the write message to the mirror address of the second memory address space through the memory controller of the second computer.
  • the method of FIG. 7 may further include: the non-transparent bridge of the second processor receives, from the memory controller, a write completion message corresponding to the write message, where the write completion message includes a mirror address;
  • the non-transparent bridge of the processor converts the mirrored address into a write address according to the mapping relationship between the first memory address space and the second memory address space;
  • the non-transparent bridge of the second processor sends the mirror image corresponding to the mirrored message to the first processor
  • the mirror completion message includes the write address, and the mirror completion message is used to indicate that the target data has been written to the mirror address.
  • the system bus is a QPI bus or an HT bus.
  • the non-transparent bridge of the first processor is responsible for converting the write address in the mirrored message to a mirrored address (the mirrored address is the write address and the second memory address is empty)
  • the non-transparent bridge of the second processor is responsible for converting the mirrored message into a write message that can be recognized by the second processor, but the embodiment of the present invention is not limited thereto.
  • the second The processor's non-transparent bridge is responsible for both the address translation and the packet conversion.
  • the non-transparent bridge of the second processor is responsible for converting the mirrored address in the write completion message into a write address
  • the non-transparent bridge of the first processor is responsible for writing the completed message.
  • the image is converted into a mirroring completion message, but the embodiment of the present invention is not limited thereto.
  • the non-transparent bridge of the first processor can be responsible for both the address translation work and the packet conversion work.
  • the non-transparent bridge in the processor can be responsible for mirroring related operations, such as packet conversion, address translation in the message, and other operations or functions (such as generating write and mirror messages, data, and data).
  • the write operation, the operation of sending the mirrored message to the non-transparent bridge, etc. can all be performed by the processor body, such as a controller or control logic in the processor, to support the CPU of the QPI technology as an example.
  • the body of the device can be a processing engine such as CA, HA, etc. in the CPU.
  • a method for processing a write request in a cluster computer system according to an embodiment of the present invention is described in detail above with reference to FIGS. 2 through 7, and a processor and a computer according to an embodiment of the present invention will be described in detail below with reference to FIGS. 8 through 11. .
  • FIG. 8 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • the processor 800 of FIG. 8 is capable of implementing the various steps performed by the first processor in FIGS. 1 through 7. To avoid repetition, details are not described herein.
  • the processor 800 is located in a first computer, the first computer and the second computer are connected, the first computer and the second computer respectively run respective operating systems, and the second computer includes another processor
  • the processor 800 includes a system bus interface 810, and the system bus interface of the processor 800 is connected to the system bus interface of the other processor through a system bus, and the second memory address space of the second computer is The mirror address space of the first memory address space of the first computer, the processor 800 further includes a controller 820 and an internal bus 830, the controller 820 and the system bus of the processor 800 through the internal bus 830
  • the interface 810 is connected,
  • the controller 820 is configured to receive a write request, where the write request includes target data to be written, and a write address of the target data; determining that the write address is located in the first memory address space; The target data in the request is written into the first memory address space, and the target data in the write request is sent to the another processor through the system bus, so that the another processor will The target data is written to the second memory address space.
  • the processors of two different computers are connected through a system bus.
  • the system bus is used to implement the mirroring operation of the data to be written, without performing multiple DMA operations as in the prior art, and no complicated protocol conversion is required, which reduces the delay of the mirroring operation and improves the IOPS performance of the system.
  • the processor 800 may further include a non-transparent bridge 840 connected to the system bus interface 810 through which the non-transparent bridge 840 is
  • the controller 820 is connected to the controller 820, and the controller 820 is specifically configured to generate a mirrored message according to the write request, where the mirrored message includes the target data and the write address, and the mirrored message is used to Writing, by the target data, a mirrored address of the write address in the second memory address space; sending the mirrored message to the non-transparent bridge; the non-transparent bridge 840 is configured to be according to the first a mirroring relationship between the memory address space and the second memory address space, converting the write address in the mirrored message into the mirrored address, to obtain an updated mirrored message; The non-transparent bridge of another processor sends the updated mirror message, so that the another processor receives the updated mirror message according to the non-transparent bridge of the other processor.
  • the target data is written into the mirror Address.
  • the non-transparent bridge 840 is further configured to: after receiving the mirroring complete message corresponding to the mirrored message from the another processor within a preset time, to the control
  • the 820 is configured to send the mirroring completion message, where the mirroring completion message is used to indicate that the target data has been written into the mirroring address, and the controller 820 is further configured to confirm the message according to the mirroring completion message.
  • the mirroring operation of the target data is successful, and the mirroring transaction corresponding to the mirroring operation is ended.
  • the non-transparent bridge 840 is further configured to: when the mirror completion message is not received from the another processor within the preset time, to the controller 820 The mirroring timeout message is sent; the controller 820 is further configured to: according to the mirror timeout message, confirm that the mirroring operation fails, and end the mirroring transaction.
  • the controller 820 is specifically configured to generate a mirrored message according to the write request, where the mirrored message includes the target data and the write address; and the mirrored message is Sending to the non-transparent bridge of the processor, the non-transparent bridge of the processor transmitting the mirrored message to the non-transparent bridge of the other processor through the system bus, so that the another processing
  • the non-transparent bridge converts the write address in the mirrored message into a mirrored address of the write address in the second memory address space, obtains an updated mirrored message, and causes the other processor to And writing the target data to the mirror address according to the updated mirror message.
  • the controller is specifically configured to generate according to the write request. Writing a message of the target data; writing the target data into the write address of the first memory address space according to the write message.
  • the system bus is a QPI bus or an HT bus.
  • FIG. 9 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • the processor 900 of FIG. 9 can implement the various steps performed by the second processor in FIGS. 1 through 7. To avoid repetition, details are not described herein.
  • the processor 900 is located in a second computer connected to the first computer, the first computer and the second computer respectively running respective operating systems, the first computer comprising another processor, the processor 900 includes a system bus interface 910, the system bus interface of the other processor is connected to the system bus interface of the processor through a system bus, and the second memory address space of the second computer is the first computer A mirrored address space of a memory address space, the processor 900 includes a controller 920, an internal bus 930, and a non-transparent bridge 940, the non-transparent bridge 930 being coupled to the system bus interface 910 of the processor 900, the control The 920 and the non-transparent bridge 940 are connected by the internal bus 930.
  • the non-transparent bridge 940 is configured to receive target data from the another processor through the system bus, where the target data is data to be written into a memory of the another processor, where the target data
  • the write address is located in the first memory address space; the target data is written into the second memory address space.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated Protocol conversion reduces the latency of mirroring operations and improves system IOPS performance.
  • the non-transparent bridge 940 is specifically configured to receive, by using the system bus, a mirrored message from the another processor, where the mirrored message includes the target data and the write a mirrored address of the address in the second memory address space; converting the mirrored message into a write message of the target data; writing the write message to the memory controller of the second computer In the mirror address of the second memory address space.
  • the non-transparent bridge 940 is further configured to receive, from the memory controller, a write completion message corresponding to the write message, where the write completion message includes the mirror address; a mapping relationship between the first memory address space and the second memory address space, converting the mirrored address to the write address, and sending the mirrored complete message corresponding to the mirrored message to the another processor
  • the mirroring completion message includes the write address, and the mirror completion message is used to indicate the location The target data has been written to the mirror address.
  • the system bus is a QPI bus or an HT bus.
  • FIG. 10 is a schematic block diagram of a computer in accordance with an embodiment of the present invention.
  • the computer 1000 of FIG. 10 corresponds to the first computer of FIGS. 1 through 7, and is capable of executing the various steps performed by the first processor. To avoid repetition, details are not described herein.
  • the computer 1000 is connected to another computer, and the computer 1000 and the other computer respectively run respective operating systems, the computer 1000 includes a first processor, and the other computer includes a second processor.
  • the first processor and the second processor each include a system bus interface, and a system bus interface of the first processor is connected to a system bus interface of the second processor through a system bus, the another computer
  • the second memory address space is a mirrored address space of the first memory address space of the computer,
  • the computer 1000 includes:
  • the receiving module 1010 is configured to receive a write request, where the write request includes target data to be written, and a write address of the target data;
  • a determining module 1020 configured to determine that the write address is located in the first memory address space
  • the mirroring module 1030 is configured to write the target data in the write request into the first memory address space, and send the target data in the write request to the second processor by using the system bus.
  • the second processor writes the target data to the second memory address space.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated Protocol conversion reduces the latency of mirroring operations and improves system IOPS performance.
  • the mirroring module 1030 is specifically configured to generate a mirrored message according to the write request, where the mirrored message includes the target data and the write address, and the mirrored message is used by the mirrored message.
  • the non-transparent bridge of the second processor sends the updated mirrored message, so that the second processor sends the updated mirrored message according to the non-transparent bridge of the second processor
  • the target data is written to the mirror address.
  • the mirroring module 1030 is further configured to: when the first processing After receiving the mirroring complete message corresponding to the mirrored message from the second processor, the non-transparent bridge sends the mirroring complete message to the first processor, where the mirror is complete.
  • the completion message is used to indicate that the target data has been written into the mirroring address. According to the mirroring completion message, it is confirmed that the mirroring operation of the target data is successful, and the mirroring transaction corresponding to the mirroring operation is ended.
  • the mirroring module 1030 is further configured to: when the non-transparent bridge of the first processor does not receive the mirror completion report from the second processor within the preset time And sending, by the first processor, a mirror timeout message; according to the mirror timeout message, confirming that the mirroring operation fails, and ending the mirroring transaction.
  • the mirroring module 1030 is further configured to generate, according to the write request, a mirrored message, where the mirrored message includes the target data and the write address; Sending to the non-transparent bridge of the first processor, the non-transparent bridge of the first processor sends the mirrored message to the non-transparent bridge of the second processor through the system bus, so that The non-transparent bridge of the second processor converts the write address in the mirror message into a mirror address of the write address in the second memory address space, obtains an updated mirror message, and causes the The second processor writes the target data to the mirror address according to the updated mirror message.
  • the mirroring module 1030 is specifically configured to generate a write message of the target data according to the write request, and write the target data into the first file according to the write message.
  • the write address of a memory address space is specifically configured to generate a write message of the target data according to the write request, and write the target data into the first file according to the write message.
  • the system bus is a QPI bus or an HT bus.
  • FIG. 11 is a schematic block diagram of a computer in accordance with an embodiment of the present invention.
  • the computer 1100 of FIG. 11 corresponds to the second computer of FIG. 1 to FIG. 7, and can implement various steps performed by the second processor in the second computer. To avoid repetition, details are not described herein.
  • the computer 1100 is connected to another computer, and the other computer and the computer 1100 respectively run respective operating systems, the other computer includes a first processor, and the computer 1100 includes a second processor.
  • the first processor and the second processor each include a system bus interface, and a system bus interface of the first processor is connected to a system bus interface of the second processor through a system bus, where the computer 1100
  • the second memory address space is a mirrored address space of the first memory address space of the other computer,
  • the computer 1100 includes:
  • a mirroring module 1110 configured to receive target data from the first processor by using the system bus, where the target data is data to be written into a memory of the first processor, the target data The write address is located in the first memory address space;
  • the write operation module 1120 is configured to write the target data into the second memory address space.
  • the processors of two different computers are connected together through the system bus, and the mirroring operation of the data to be written is realized by using the system bus, without performing multiple DMA operations as in the prior art, and no complicated Protocol conversion reduces the latency of mirroring operations and improves system IOPS performance.
  • the mirroring module 1110 is specifically configured to receive, by using the system bus, a mirrored message from the first processor, where the mirrored message includes the target data and the write address. a mirroring address in the second memory address space; the write operation module is specifically configured to convert the mirrored message into a write message of the target data; and the write is performed by a memory controller of the computer The message is written into the mirror address of the second memory address space.
  • the mirroring module 1110 is further configured to receive, from the memory controller, a write completion message corresponding to the write message, where the write completion message includes the mirror address; a mapping relationship between the first memory address space and the second memory address space, the image address is converted into the write address, and the mirrored message corresponding to the mirrored message is sent to the first processor,
  • the mirroring completion message includes the write address, and the mirroring completion message is used to indicate that the target data has been written to the mirror address.
  • the system bus is a QPI bus or an HT bus.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • Another point that is shown or discussed between each other The coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

本发明实施例提供一种处理写请求的方法、处理器和计算机，第一计算机和第二计算机连接，第一计算机与第二计算机上分别运行着各自的操作系统，第一计算机包括第一处理器，第一处理器通过系统总线与第二计算机的第二处理器相连，第一计算机包括第一内存地址空间，第二计算机的第二内存地址空间为第一内存地址空间的镜像地址空间，第一处理器通过系统总线将写入第一内存地址空间的数据镜像至第二内存地址空间，能够降低了镜像操作的延时，提高了系统的IOPS性能。

Description

处理写请求的方法、处理器和计算机 技术领域
本发明实施例涉及计算机领域，并且更具体地，涉及一种处理写请求的方法、处理器和计算机。
背景技术
集群计算机系统一般由多个计算机组成，多个计算机上分别运行着各自的操作系统，能够独立地工作，多个计算机之间通过例如以太网、外围元件接口表达(Peripheral Component Interface Express，PCIe)、Infiniband等输入输出(Input Output，IO)总线互联，能够实现计算机之间的通信以及数据交换。
集群计算机系统在高端存储领域有着广泛的应用。例如，对于高端的存储设备，一般均采用双控或多控存储区域网络(Storage Area Network，SAN)系统，而这样的双控、多控SAN系统中的每个控制器就可以看成一个独立的计算机，每个控制器上运行着各自的操作系统、设置有各自的内存，控制器之间通过IO总线互连，形成集群计算机系统。高端存储设备采用双控、多控SAN系统能够保证数据存储的可靠性，下面结合图1，以基于PCIe互连的双控SAN系统为例进行详细描述。
如图1所示，双控SAN系统包括控制器A和控制器B，控制器A和控制器B均包括各自的CPU、DDR和前端总线，而且控制器A和控制器B上分别运行着各自的操作系统。控制器A和控制器B之间通过PCIe总线相连，通过PCIe非透明桥(Non-Transparent Bridge，NTB)实现两个计算机域的地址转换和数据交换。
当控制器A通过前端总线接收到外部的用于存储数据的写请求(也可称为写IO，或写IO请求)时，控制器A的CPU0会先将该数据写入DDR0；然后CPU0会从DDR0中读取该数据，将该数据封装成符合PCIe格式数据，并通过两控制器之间的由PCIe总线形成的镜像通道，将封装后的数据发送至控制器B，控制器B的CPU1通过解封装得到该数据，然后将该数据写入DDR1。
以上就是双控SAN系统中的一次完整的镜像操作过程，通过这种镜像 操作，相当于在控制器B上备份了控制器A的数据，当控制器A出现致命错误导致宕机时，控制器B仍能正常工作，而且控制器A的内存中的数据不会因为控制器A的宕机而丢失，整个系统仍能正常运行和工作，提高了存储设备的可靠性。但是，从上面描述的镜像过程可以看出，整个镜像操作需要两次直接内存访问(Directional Memory Access，DMA)操作(第一次从DDR0中读，第二次向DDR1中写)；而且PCIe(或者以太网、Infiniband等)网络协议互连的设备之间的IO访问势必带来大量的软件协议开销(如数据的封装、解封装)，导致镜像操作延迟高、系统的每秒读写操作(Input/Output Operations Per Second，IOPS)性能较差。
发明内容
本发明实施例提供一种处理写请求的方法和装置和计算机，可以降低集群计算机系统中的数据镜像操作的延迟，提高系统的IOPS。
第一方面，提供一种处理写请求的方法，所述方法应用于第一计算机中，所述第一计算机和第二计算机连接，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括第一处理器，所述第二计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述方法包括：所述第一处理器接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；所述第一处理器确定所述写地址位于所述第一内存地址空间中；所述第一处理器将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器。
通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
结合第一方面，在第一方面的一种实现方式中，所述第一处理器将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，包括：所述第一处理器根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；所述第一处理器将所述镜像报文发送至所述第一处理器的非透明桥；所述第一处理器的非透明桥根据所述第一内存地址空间和所述 第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文；所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述更新后的镜像报文，以便所述第二处理器根据所述第二处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
通过非透明桥进行镜像报文中的地址转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述方法还包括：当所述第一处理器的非透明桥在预设时间内从所述第二处理器接收到所述镜像报文对应的镜像完成报文后，所述第一处理器的非透明桥向所述第一处理器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；所述第一处理器根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述方法还包括：当所述第一处理器的非透明桥在所述预设时间内未从所述第二处理器接收到所述镜像完成报文时，所述第一处理器的非透明桥向所述第一处理器发送镜像超时报文；所述第一处理器根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
通过设计完整的镜像事务或镜像相关报文处理流程，无论镜像操作成功或失败均可以结束镜像事务，避免系统总线操作出错引起的宕机问题，增强了系统的鲁棒性。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述第一处理器将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，包括：所述第一处理器根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；所述第一处理器将所述镜像报文发送至所述第一处理器的非透明桥，所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述镜像报文，以使所述第二处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述第二处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
通过非透明桥进行镜像报文以及镜像报文中的地址转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述第一处理器将所述写请求中的目标数据写入所述第一内存地址空间，包括：所述第一处理器根据所述写请求，生成所述目标数据的写报文；所述第一处理器根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述系统总线为QPI总线或HT总线。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间。
结合第一方面或其上述实现方式的任一种，在第一方面的另一种实现方式中，所述第一处理器将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，以便所述第二处理器将所述目标数据写入所述第二内存地址空间。
第二方面，提供一种处理写请求的方法，所述方法应用于与第一计算机连接的第二计算机，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括第一处理器，所述第二计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，所述方法包括：所述第二处理器通过所述系统总线，从所述第一处理器接收目标数据，所述目标数据为待写入所述第一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；所述第二处理器将所述目标数据写入所述第二内存地址空间。
通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
结合第二方面，在第二方面的一种实现方式中，所述第二处理器通过所述系统总线，从所述第一处理器接收目标数据，包括：所述第二处理器的非 透明桥通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；所述第二处理器将所述目标数据写入所述第二内存地址空间，包括：所述第二处理器的非透明桥将所述镜像报文转换成所述目标数据的写报文；所述第二处理器的非透明桥通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
通过非透明桥完成报文类型或格式的转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第二方面或其上述实现方式的任一种，在第二方面的另一种实现方式中，所述方法还包括：所述第二处理器的非透明桥从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；所述第二处理器的非透明桥根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；所述第二处理器的非透明桥向所述第一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
结合第二方面或其上述实现方式的任一种，在第二方面的另一种实现方式中，所述第二处理器通过所述系统总线，从所述第一处理器接收目标数据，包括：所述第二处理器的非透明桥通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址；所述第二处理器将所述目标数据写入所述第二内存地址空间，包括：所述第二处理器的非透明桥将所述镜像报文转换成所述目标数据的写报文，并将所述写地址转换成所述写地址在所述第二内存地址空间中的镜像地址；所述第二处理器的非透明桥通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
结合第二方面或其上述实现方式的任一种，在第二方面的另一种实现方式中，所述系统总线为QPI总线或HT总线。
第三方面，提供一种处理器，所述处理器位于第一计算机，所述第一计算机和第二计算机连接，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第二计算机包括另一处理器，所述处理器和所述另一处理器均包括系统总线接口，所述处理器的系统总线接口通过系统总线与所述 另一处理器的系统总线接口相连，所述处理器还包括控制器和内部总线，所述控制器通过所述内部总线与所述处理器的系统总线接口相连，所述控制器用于接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；确定所述写地址位于所述第一内存地址空间中；将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述另一处理器。
通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
结合第三方面，在第三方面的一种实现方式中，所述处理器还包括非透明桥，所述非透明桥与所述系统总线接口相连，所述非透明桥通过所述内部总线与所述控制器相连，所述控制器具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述非透明桥；所述非透明桥用于根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文；通过所述系统总线，向所述另一处理器的非透明桥发送所述更新后的镜像报文，以便所述另一处理器根据所述另一处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
通过非透明桥进行镜像报文中的地址转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述非透明桥还用于当在预设时间内从所述另一处理器接收到所述镜像报文对应的镜像完成报文后，向所述控制器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；所述控制器还用于根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述非透明桥还用于当在所述预设时间内未从所述另一处理器接收到所述镜像完成报文时，向所述第一处理器发送镜像超时报文；所述控制器还用于根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
通过设计完整的镜像事务或镜像相关报文处理流程，无论镜像操作成功或失败均可以结束镜像事务，避免系统总线操作出错引起的宕机问题，增强了系统的鲁棒性。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述控制器具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述处理器的非透明桥，所述处理器的非透明桥通过所述系统总线，向所述另一处理器的非透明桥发送所述镜像报文，以使所述另一处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述另一处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
通过非透明桥进行镜像报文以及镜像报文中的地址转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述控制器具体用于根据所述写请求，生成所述目标数据的写报文；根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述系统总线为QPI总线或HT总线。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间。
结合第三方面或其上述实现方式的任一种，在第三方面的另一种实现方式中，所述处理器将所述写请求中的目标数据通过所述系统总线，发送至所述另一处理器，以便所述另一处理器将所述目标数据写入所述第二内存地址空间。
第四方面，提供一种处理器，所述处理器位于与第一计算机连接的第二计算机中，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括另一处理器，所述另一处理器和所述处理器均包括系统总线接口，所述另一处理器的系统总线接口通过系统总线与所述处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算 机的第一内存地址空间的镜像地址空间，所述处理器包括控制器、非透明桥和内部总线，所述非透明桥与所述处理器的系统总线接口相连，所述控制器和所述非透明桥通过所述内部总线相连，所述非透明桥用于通过所述系统总线，从所述另一处理器接收目标数据，所述目标数据为待写入所述另一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；将所述目标数据写入所述第二内存地址空间。
通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
结合第四方面，在第四方面的一种实现方式中，所述非透明桥具体用于通过所述系统总线，从所述另一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；将所述镜像报文转换成所述目标数据的写报文；通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
通过非透明桥完成报文类型或格式的转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第四方面或其上述实现方式的任一种，在第四方面的另一种实现方式中，所述非透明桥还用于从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；向所述另一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
结合第四方面或其上述实现方式的任一种，在第四方面的另一种实现方式中，所述非透明桥具体用于通过所述系统总线，从所述另一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址；将所述镜像报文转换成所述目标数据的写报文，并将所述写地址转换成所述写地址在所述第二内存地址空间中的镜像地址；通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
结合第四方面或其上述实现方式的任一种，在第四方面的另一种实现方式中，所述系统总线为QPI总线或HT总线。
第五方面，提供一种计算机，所述计算机和另一计算机连接，所述计算机与所述另一计算机上分别运行着各自的操作系统，所述计算机包括第一处理器，所述另一计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述计算机包括：接收模块，用于接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；确定模块，用于确定所述写地址位于所述第一内存地址空间中；镜像模块，用于将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器。
通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
结合第五方面，在第五方面的一种实现方式中，所述镜像模块具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述第一处理器的非透明桥；根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文；通过所述系统总线，向所述第二处理器的非透明桥发送所述更新后的镜像报文，以便所述第二处理器根据所述第二处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
通过非透明桥进行镜像报文中的地址转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述镜像模块还用于当所述第一处理器的非透明桥在预设时间内从所述第二处理器接收到所述镜像报文对应的镜像完成报文后，向所述第一处理器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述镜像模块还用于当所述第一处理器的非透明桥在所述预设时间内未从所述第二处理器接收到所述镜像完成报文时，向所述第一处理器发送镜 像超时报文；根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
通过设计完整的镜像事务或镜像相关报文处理流程，无论镜像操作成功或失败均可以结束镜像事务，避免系统总线操作出错引起的宕机问题，增强了系统的鲁棒性。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述镜像模块还用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述第一处理器的非透明桥，所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述镜像报文，以使所述第二处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述第二处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
通过非透明桥进行镜像报文以及镜像报文中的地址转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述镜像模块具体用于根据所述写请求，生成所述目标数据的写报文；根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述系统总线为QPI总线或HT总线。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述另一计算机的第二内存地址空间为所述计算机的第一内存地址空间的镜像地址空间。
结合第五方面或其上述实现方式的任一种，在第五方面的另一种实现方式中，所述镜像模块将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，以便所述第二处理器将所述目标数据写入所述第二内存地址空间。
第六方面，提供一种计算机，所述计算机和另一计算机连接，所述另一计算机与所述计算机上分别运行着各自的操作系统，所述另一计算机包括第一处理器，所述计算机包括第二处理器，所述第一处理器和所述第二处理器 均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述计算机的第二内存地址空间为所述另一计算机的第一内存地址空间的镜像地址空间，所述计算机包括：镜像模块，用于通过所述系统总线，从所述第一处理器接收目标数据，所述目标数据为待写入所述第一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；写操作模块，用于将所述目标数据写入所述第二内存地址空间。
通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
结合第六方面，在第六方面的一种实现方式中，所述镜像模块具体用于通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；所述写操作模块具体用于将所述镜像报文转换成所述目标数据的写报文；通过所述计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
通过非透明桥完成报文类型或格式的转换，能够简化处理器内部的实现，进一步降低了镜像操作的延时，提高了系统的IOPS性能。
结合第六方面或其上述实现方式的任一种，在第六方面的另一种实现方式中，所述镜像模块还用于从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；向所述第一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
结合第六方面或其上述实现方式的任一种，在第六方面的另一种实现方式中，所述镜像模块具体用于通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址；所述写操作模块具体用于将所述镜像报文转换成所述目标数据的写报文，并将所述写地址转换成所述写地址在所述第二内存地址空间中的镜像地址；通过所述计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
结合第六方面或其上述实现方式的任一种，在第六方面的另一种实现方式中，所述系统总线为QPI总线或HT总线。
在现有技术中，系统总线一般用来实现计算机内部各功能部件的连接，其属于计算机内部总线的一种，具有带宽高、延时低的特点，本发明实施例中，通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有集群计算机系统的连接示意图。
图2是本发明实施例的计算机系统的连接示意图。
图3是本发明实施例的处理写请求的方法的示意性流程图。
图4是基于QPI技术的CPU的结构示意图。
图5是本发明实施例的数据镜像操作的示意性流程图。
图6是本发明实施例的数据镜像操作的示意性流程图。
图7是本发明实施例的处理写请求的方法的示意性流程图。
图8是本发明实施例的处理器的示意性结构图。
图9是本发明实施例的处理器的示意性结构图。
图10是本发明实施例的计算机的示意性结构图。
图11是本发明实施例的计算机的示意性结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
计算机集群系统一般包括多个计算机，多个计算机之间按照一定的形式 相互连接在一起，各个计算机上独立地运行各自的操作系统，且各计算机之间可以彼此通信和数据交换。为了保证计算机集群系统中的数据存储的可靠性，计算机集群系统中的某个计算机(以下称为第一计算机)会将待写入内存的数据(下称目标数据)通过镜像操作镜像至另一个计算机(下称第二计算机)的内存中，相当于在第二计算机中备份了第一计算机的内存中的数据，当第一计算机由于某种原因宕机时，其内存中的数据在第二计算机仍有备份，不会造成内存数据的丢失，提高了数据存储的可靠性。
应理解，上文描述的第一计算机和/或第二计算机可以是包括处理器和内存，并独立运行着操作系统的设备或节点，本发明实施例将其命名为第一计算机和/或第二计算机仅仅是为了描述方便和相互区分，不应理解为对本发明实施例的限制。具体地，在不同的应用场景中，第一计算机和/或第二计算机可以对应不同的设备或节点，例如，在普通的集群计算机系统领域，比如通信或服务器领域，计算机可以是主机(host)；在存储设备领域，如双控或多控SAN领域，计算机可以是控制器。
还应理解，本文以集群系统中的计算机为例进行举例说明，实际中，只要是两个独立的计算机内部的处理器通过系统总线相连即可应用本发明实施例提供的处理写请求的方法。
现有技术中，计算机集群系统的计算机之间是通过IO总线相连，如PCIe，以太网、Infiniband。如前文所述，计算机之间通过IO总线执行数据的镜像操作不但涉及多次DMA操作，而且涉及复杂的软件协议开销。例如，第一计算机需要从内存中提取目标数据，并将目标数据封装成符合PCIe，以太网、Infiniband等协议的报文发送至第二计算机，第二计算机需要对报文进行解封装，再将目标数据写入第二计算机的内存中，因此镜像操作的效率比较低。为了提高集群计算机系统之间的数据镜像操作的效率，本发明实施例利用系统总线将集群计算机系统中的两个或多个计算机的处理器直接相连，并可以在此基础上设计一套适合系统总线上完成的数据镜像操作流程，下面结合图2和图3进行详细描述。
图2是本发明实施例的计算机系统的连接示意图。在图2中，第一计算机和第二计算机可以为集群计算机系统中的两个计算机，这两个计算机分别独立地运行着各自的操作系统。两个计算机的处理器(图2中的第一处理器和第二处理器)均包括系统总线接口，处理器之间采用类似“松耦合”的方 式，通过系统总线连接在一起。此外，所述第二计算机的至少部分内存地址空间(下称第二内存地址空间)为所述第一计算机的至少部分内存地址空间(下称第一内存地址空间)的镜像地址空间。在图2所示的连接关系和配置的基础上，下面结合图3，详细描述根据本发明实施例的集群计算机系统中的处理写请求的方法。
图3是本发明实施例的处理写请求的方法的示意性流程图。图3的方法可以由图2中的第一处理器执行，图3的方法包括：
310、第一处理器接收写请求，写请求包含待写的目标数据，以及目标数据的写地址。
320、第一处理器确定写地址位于第一内存地址空间中。
330、第一处理器根据写请求，将写请求中的目标数据写入第一内存地址空间，并将写请求中的目标数据通过系统总线，发送至第二处理器，以便(或指示)第二处理器将目标数据写入第二内存地址空间。
在一个实施例，第一处理器可以直接将目标数据写入第一内存地址空间；在另一个实施例中，第一处理器可以通过内存控制器将目标数据写入第一内存地址空间。
应理解，本发明实施例对第一处理器将目标数据写入第一内存地址空间与第一处理器通过系统总线向第二处理器发送目标数据的操作顺序不作具体限定，可以并行执行，也可以先后执行。
在现有技术中，系统总线一般用来实现计算机内部各功能部件的连接，其属于计算机内部总线的一种，具有带宽高、延时低的特点，本发明实施例中，通过系统总线将计算机集群系统中的分属于两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。具体而言，现有技术是通过IO设备在两个计算机之间发送镜像报文，因此需要先将镜像数据(对应于上文中的目标数据)从内存中取出，然后将该目标数据发给IO设备(以网卡为例)，接着由网卡通过网卡的软件驱动将该镜像数据封装成报文，发送至接收端，接收端收到报文之后，会对报文进行解封装，然后再将报文写入接收端的内存中，整个过程需要多次内存读写操作，而且涉及复杂协议的封装和解封装。本发明实施例是由第一处理器直接通过系统总线发送至第二处理器，省去了从内存中读 数据的过程，此外，系统总线虽然也可以将目标数据封装在报文(如下文中描述的镜像报文)中发送，但系统总线属于内部总线的一种，其报文的封装形式也可以设计的比较简单，例如，可以通过改变写报文中的部分字段来区分数据的写报文和数据的镜像报文，无需像IO设备(如网卡)涉及复杂的协议和封装形式。
可选地，在一个实施例中，处理器可以包括一个或多个系统总线接口。
可选地，在一个实施例中，系统总线可以是支持缓存一致性(Cache Coherent，CC)的总线，例如，系统总线可以称为CC总线。在一个实施例中，系统总线可以是超级传输(Hyper Transport，HT)总线和快速通道互连(Quick Path Interconnect，QPI)总线中的一种。
可选地，在一个实施例中，图3所示的方法可以应用于存储设备领域。在存储设备领域，集群计算机系统可以为双控或多控系统，上述第一计算机和第二计算机中的任意计算机相当于存储设备领域的一个控制器。
上述第一内存地址空间可以是第一计算机的部分内存地址空间，上述第二内存地址空间可以是第二计算机的部分内存地址空间。在一个实施例中，第一内存地址空间也可以是第二内存地址空间的镜像地址空间，或者第一内存地址空间与第二内存地址空间可以互为镜像地址空间。
上述第一内存地址空间和第二内存地址空间可以是地址连续的空间(简称为连续的地址空间)；也可以是地址不连续的空间(简称非连续的地址空间)。在一个实施例中，第一内存地址空间和第二内存地址空间均为连续的地址空间，将第一内存地址空间和第二内存地址空间设置为连续的地址空间可以简化系统的硬件实现。在一个实施例中，第一内存地址空间和第二内存地址空间的空间大小可以相等。
可选地，在一个实施例中，第一内存地址空间和第二内存地址空间可以是内存中的可缓存(cacheable)空间，这样，第一内存地址空间和第二内存地址空间除了可以完成镜像操作，还可以解决多处理器之间的缓存一致性问题。
可选地，在一个实施例中，第二内存地址空间为所述第一内存地址空间的镜像地址空间可以表示：写入第一内存地址空间中的数据需要写入第二内存地址空间，或者，对第一内存地址空间的写操作均需要镜像至第二内存地址空间中。也就是说，同样的数据在第一内存地址空间和第二内存地址空间 都进行存储，这样能够保证集群计算机系统数据安全可靠。
可选地，在一个实施例中，第一内存地址空间和第二内存地址空间之间的镜像关系可以是预先配置。预先配置后，镜像关系可以设置为保持静态，或者设置为动态调整。例如，可以由处理器的固件负责镜像地址空间的初始化，然后由两个计算机的处理器通过系统总线互发通知报文，通知对方各自的镜像地址空间的位置和大小。或者，也可以由带外管理系统在系统初始化时配置，并将配置结果通知各计算机。在一个实施例中，第一内存地址空间和第二内存地址空间的镜像关系可以根据集群计算机系统的需要而(实时)配置或更新。在一个实施例中，镜像地址空间配置的成功与否会影响计算机之间能否执行镜像操作，但不影响计算机的正常启动和运行。
可选地，作为一个实施例，步骤330可包括：第一处理器根据写请求，生成目标数据的写报文；第一处理器根据写报文，将目标数据写入第一内存地址空间的写地址中。此处的报文也可称为消息(message)。
为了实现两个计算机系统之间的基于系统总线的镜像功能，可以参考PCIe的非透明桥的理念，在两个系统之间设置非透明桥，将两个系统的地址域隔开，通过该非透明桥可以完成内存地址的转换(将一个系统的内存地址转换成另一个系统中的与该内存地址对应的镜像地址)，以及其他镜像相关操作，下面结合具体的实施例对非透明桥的具体形式进行详细描述。
非透明桥可以通过硬件实现，也可以通过软件实现。例如，非透明桥可以通过电路实现，此时，可以将该非透明桥称为非透明桥电路。非透明桥采用硬件实现能够进一步提高镜像操作的效率以及系统整体的IOPS。具体来说，现有技术是通过IO设备(例如网卡)发送镜像报文，这些IO设备通过各自的软件驱动来处理镜像报文，与纯硬件的方式相比，软件对镜像报文的处理效率明显较低，延时较大。可以将非透明桥设置为专门处理镜像操作的硬件，例如，非透明桥专门对镜像报文进行地址和/或报文类型的转换，纯硬件的实现方式可以进一步提升镜像操作的效率。
又如，非透明桥可以通过代码实现，此时，可以将该非透明桥称为非透明桥逻辑模块。将非透明桥设置成专门处理镜像操作的硬件，可以降低处理器的负担，下面以非透明桥为硬件为例，对非透明桥的位置以及非透明桥与处理器内部其他部件之间的连接关系进行举例说明。
处理器一般包括控制器和运算器，控制器一般负责处理器内部的逻辑控 制和整体调度，运算器进行数据相关的整数或浮点运算。为了更好地支持镜像相关操作，可以在处理器的系统总线接口处设置非透明桥，该非透明桥可以通过处理器的内部总线与处理器内部的控制器相连。应理解，不同类型的处理器中的控制器和内部总线的名称或类型可以不同，参见图4，以基于QPI技术的处理器为例，其内部的控制器可以指其内部的缓存代理(Cache Agent，CA)、家乡引擎(Home Agent，HA)等，该处理器内部的器件通过环形总线(Ring Bus)相连。具体而言，CA是CPU内部的位于缓存端的事务处理引擎，HA是CPU内部的位于内存控制器端的事务处理引擎，与DDR相连，CPU内部的事务处理引擎之间通过环形总线相连，报文(message)可以按照一定规则，通过环形总线在各个引擎之间传递，在各个引擎的相互配合下完成某个事务，如读事务、写事务等。例如，在CPU接收到写请求之后，CA可以负责向HA发送用于请求向内存写入数据的数据回写报文(WbData)，请求将写请求中的数据写入内存中，并接收HA返回的响应报文(WbCMP)，指示数据的写操作完成。继续参见图4，非透明桥(图4中的NTB)可以设置在系统总线接口处，一端与系统总线接口相连，另一端连接在CPU的内部总线上，这样，处理器内部的控制器，如CA，可以通过内部总线与非透明桥进行消息或数据的交互。
在引入非透明桥的基础上，为了配合目标数据的镜像操作，可以引入镜像事务，并配置镜像事务相关的报文。进一步地，可以通过NTB实现内存地址的转换，报文格式转换，镜像事务正常结束和非正常结束的判断，中断上报等。下面分别进行详细说明。
镜像事务相关的报文可以分为带数据payload(或称净荷，对应于上文中的目标数据)的报文和不带数据payload的报文。例如，带数据payload的报文可以称为镜像报文，该镜像报文可用于将待写入第一计算机的内存地址空间的数据payload镜像至第二计算机的内存地址空间。进一步地，可以在镜像报文中携带镜像事务的事务号、数据payload的写地址(该地址后续会通过非透明桥进行转换，详见下文)、以及数据payload。
具体地，镜像报文中的镜像操作事务号可以用8位二进制数表示，镜像报文中的地址可以根据处理器具体实现来确定，例如：X86中为46位～48位二进制数。例如，镜像操作事务号可以为0X01，表示编号为01的镜像事务。镜像地址可以为0X001234。
不带数据payload的报文，例如可以包括镜像完成报文、镜像超时报文等，此类报文可用于完善镜像操作的逻辑，例如，镜像完成报文可用于指示镜像操作已完成，镜像超时报文可用于指示镜像操作由于超时而失败。也可以在此类报文中携带镜像操作相关的地址以及镜像事务号等。
接下来以基于QPI技术的处理器为例，详细介绍非透明桥的地址转换功能和报文转换功能。
首先，假设第一处理器的内存地址空间{0X04_0000,0X04_FFFF}与第二处理器的内存地址空间{0X0A_0000,0A_FFFF}互为镜像(镜像关系可以预先配置)，镜像事务相关流程示例如下。
步骤1：第一处理器中某个CA需要将某数据写入某个内存地址(如0X04_1234)中。该CA可以根据系统配置，发现该内存地址属于已与其他系统配对的镜像地址空间{0X04_0000,0X04_FFFF}中的地址，于是，该CA不但发出针对第一处理器的写报文，而且发出针对镜像空间的镜像报文，写报文可以按照正常的写操作执行，镜像报文可以发送给非透明桥，由第一处理器的非透明桥处理。应理解，本发明实施例对CA发出写报文的操作和发出镜像报文的操作的时序不作具体限定，例如，CA可以并行执行上述操作，也可以先后执行上述操作。
步骤2：第一处理器的非透明桥收到镜像报文之后，根据上述内存地址空间的镜像关系，可以将0X04_1234地址修改为0X0A_1234，对镜像报文进行更新，然后将更新后的镜像报文发送给系统总线接口(此处可以是QPI端口)。
步骤3：第一处理器的系统总线接口将更新后的镜像报文发送到第二处理器的系统总线接口；
步骤4：第二处理器的系统总线接口将该镜像报文发给第二处理器的非透明桥；
步骤5：第二处理器的非透明桥将该镜像报文转换成写报文，通过第二处理器的内部总线将该写报文发送至内存控制器，完成相应的内存写入操作；
步骤6：第二处理器的内存控制器在完成内存写入操作后，返回镜像写完成报文给第二处理器的非透明桥；
步骤7：第二处理器的非透明桥根据内存地址空间的镜像关系，将镜像 写完成报文中地址字段0X0A_1234修改为0X04_1234，发送给第二处理器的系统总线接口；
步骤8：第二处理器的系统总线接口将镜像完成报文发送到第一处理器的系统总线接口；
步骤9：第一处理器的系统总线接口将镜像完成报文发给第一处理器的非透明桥；
步骤10：第一处理器的非透明桥通过第一处理器的内部总线将镜像完成报文发送给镜像报文的发起者，即步骤一中的CA；
步骤11：该CA收到镜像完成报文，判断一个镜像操作成功完成，结束该事务，释放相应资源。
此外，第一处理器的非透明桥可以设置一个定时器，当在定时器超时前仍未收到上述镜像完成报文，可以向CA发送镜像超时报文，指示镜像操作失败。
从上述流程可以看出，NTB的功能可以包括内存地址的转换，报文或报文格式的转换、镜像事务非正常结束的判断、中断上报等。
在引入上述镜像报文、非透明桥的基础上，可选地，作为一个实施例，上述步骤340可包括：第一处理器根据写请求，生成镜像报文，镜像报文包含目标数据和写地址，镜像报文用于将目标数据写入写地址在第二内存地址空间中的镜像地址；第一处理器将镜像报文发送至第一处理器的非透明桥；第一处理器的非透明桥根据第一内存地址空间和第二内存地址空间之间的镜像关系，将镜像报文中的写地址转换成镜像地址，得到更新后的镜像报文；第一处理器的非透明桥通过系统总线，向第二处理器发送更新后的镜像报文，以便第二处理器根据更新后的镜像报文将目标数据写入镜像地址。
在一个实施例中，目标数据可以通过写报文写入第一内存地址空间中，目标数据可以通过镜像报文写入第二内存地址空间中，写报文和镜像报文的报文格式可以不同，第一处理器可以根据它们的格式，执行对应的事务操作。例如，第一处理器对目标数据的写报文执行写操作，将目标数据写入内存中；第一处理器对镜像报文执行镜像操作，通过系统总线和第二处理器，将镜像报文中的目标数据镜像至第二内存地址空间中。
应理解，不同类型的处理器生成的写报文的格式、名称可以不同，以支持QPI技术的英特尔处理器为例，其生成的写报文可称为数据回写报文，即 WbData报文。当系统总线为QPI总线时，上述写报文可以是WbData报文，为了与第一写报文进行区分，镜像报文可称为WbMir报文，二者可以采用不同的报文格式。
可选地，作为一个实施例，图3的方法还可包括：当第一处理器的非透明桥在预设时间内从第二处理器接收到镜像报文对应的镜像完成报文后，第一处理器的非透明桥向第一处理器发送镜像完成报文，镜像完成报文用于指示目标数据已写入镜像地址；第一处理器根据镜像完成报文，确认目标数据的镜像操作成功，结束镜像操作对应的镜像事务。
可选地，作为一个实施例，图3的方法还可包括：当第一处理器的非透明桥在预设时间内未从第二处理器接收到镜像完成报文时，第一处理器的非透明桥向第一处理器发送镜像超时报文；第一处理器根据镜像超时报文，确认镜像操作失败，结束镜像事务。超时判断的方式可以有多种，例如，在向第二处理器发送更新后的镜像报文时，第一处理器的非透明桥可以设置一个定时器，如果在该定时器超时后，仍未收到镜像完成报文，则判断镜像操作超时。
本发明实施例在第一处理器中添加了关于系统总线上执行镜像操作的完整逻辑，该逻辑使得无论镜像操作成功与失败，均会结束此处镜像操作，能够避免系统总线上的镜像操作失败而导致的系统宕机。在此基础上，能够进一步支持计算机内部的处理器的系统总线接口的暴力热插拔，如系统总线接口的热添加或热移除(surprise plug/surprise removal)。具体而言，在现有技术中，单机系统内的多个处理器之间也会通过某种系统总线相连，如现有技术中的支持缓存一致性的非均匀内存访问(Non Uniform Memory Access Architecture，NUMA)系统，每个处理器可以访问本地的内存，也可以通过系统总线访问非本地的内存，也就是说，多个处理器的内存是可以共享的。但这样的多处理器系统的内存中共同运行单一的操作系统，本质上仍是由单机系统，并非集群计算机系统，多个处理器之间通过系统总线的操作本质上仍看成是单机系统内部的操作。单机系统的系统总线操作均是由硬件完成的，一旦某个处理器的系统总线操作出现错误(如出现系统总线接口的暴力热插拔)，就会是硬件错误，硬件错误会导致单机系统宕机。为了避免系统总线上的操作出错导致系统宕机，在第一处理器中添加了关于系统总线上执行镜像操作的完整逻辑，该逻辑使得无论镜像操作成功与失败，均会结束此 处镜像操作，不会因为系统总线操作未完成或出现错误而导致系统宕机。
下面结合图5和图6，以处理器为支持QPI技术的处理器，系统总线为QPI总线为例(具体结构参见图4)，详细描述集群计算机系统中的通过系统总线相连的计算机之间的数据镜像操作过程。应理解，本发明实施例对图5和图6的步骤执行的时序不作限定，图5和图6中的各个步骤可以按照与图5和图6呈现的不同的顺序来执行，并且有可能并非要执行图5和图6中的全部操作。图5和图6中描述的镜像操作的过程的触发条件可以是第一计算机的CA发现其接收到的写请求的写地址位于第一计算机的内存的镜像地址空间(对应于上文中的第一内存地址空间)，其中，镜像地址空间可以是预先配置的。
S502、第一CPU的CA生成数据回写报文(WbData)，并将该写报文发送至第一CPU的HA。写报文包括待写入内存的目标数据。
S504、第一CPU的CA生成镜像报文(WbMir)，并将该镜像报文发送至第一CPU的非透明桥。镜像报文包括待写入内存的目标数据。
具体地，数据回写报文和镜像报文的格式可以不同，以便处理器根据报文格式确定接下来不同格式的报文对应的操作类型。例如，对数据回写报文执行写操作，对镜像报文执行镜像操作。步骤S502和步骤S504可以同时执行，或者任意一个先执行。
S506、第一CPU的HA收到数据回写报文之后，将目标数据写入第一计算机的内存DDR中，并向CA返回数据回写完成报文。
S508、第一CPU的非透明桥收到镜像报文之后，将此镜像报文发送至第二CPU的非透明桥。
非透明桥可以位于CPU的系统总线接口处，非透明桥之间的传输可以是通过CPU之间的QPI接口以及QPI总线完成的。
S510、第二CPU的非透明桥收到镜像报文之后，将该镜像报文转换成数据回写报文，发送至第二CPU内部的HA。该数据回写报文包括目标数据。
S512、第二CPU的HA收到数据回写报文之后，将目标数据写入第二计算机的内存DDR中，并向第二CPU的非透明桥返回数据回写完成报文。
应理解，第二计算机中，写入目标数据的内存地址空间与第一计算机的第一内存地址空间互为镜像地址空间。
S514、第二CPU的非透明桥在将收到的数据回写完成后，发送数据回 写完成报文至第一CPU的非透明桥。
具体地，可以通过非透明桥模块之间QPI总线完成上述数据回写完成报文的传递。
S516、第一CPU的非透明桥将收到的数据回写完成报文转换成镜像完成报文(MirCMP)，发送至第一CPU的CA。
S518、第一CPU的CA收到S506中的数据回写完成报文以及S516中的镜像完成报文之后，确认目标数据已经分别写入第一计算机和第二计算机的互为镜像的内存地址空间，结束镜像事务。
第一CPU的CA可以通知上层应用镜像事务完成，或通知上层应用镜像操作成功。
本发明实施例将计算机的处理器通过QPI总线相连，基于QPI总线设计了一套镜像操作流程，由于QPI总线属于系统总线，具有延迟低、带宽高的有点，能够提高数据镜像操作的效率。
实际中，镜像操作并不一定总是能成功结束，可能会由于系统总线接口出现故障，或者暴力热插拔(热添加或热移除)CPU或者两个主机间的总线线缆，引起镜像操作失败。为了保证镜像操作相关事务的成功与否不影响整个系统的其他事务的处理，本发明实施例提出一种镜像操作非正常结束的处理方式，具体参见图6。
图6中的S602、S604、S608、S610、S612分别与图5中的S502、S504、S508、S510、S512类似，此处不再赘述。
S616、如果在定时器超时后，第一CPU的非透明桥未收到第二CPU的非透明桥发送的数据回写完成报文，则向第一CPU的CA发送镜像超时报文。
具体地，第一CPU的非透明桥可以在执行S608时设置定时器，定时时长可以根据实验或经验设定。
S618、第一CPU的CA收到镜像超时报文之后，确认镜像操作失败(TranFial)，结束此次镜像操作。
该CA可以将上述镜像操作失败的结果上报给操作系统，由操作系统记录镜像操作失败相关的日志。
上文中结合图2-图6，从第一处理器的角度详细描述了根据本发明实施例的集群计算机系统中的处理写请求的方法，下面将结合图7，从第二处理 器的角度描述根据本发明实施例的集群计算机系统中的处理写请求的方法。应理解，第二处理器描述的第一处理器与第二处理器的交互及相关特性、功能等与第一处理器侧的描述相应，为了简洁，适当省略重复的描述。
图7是本发明实施例的处理写请求的方法的示意性流程图。图7的方法可以由图2中的第二处理器执行，图7的方法包括：
710、第二处理器通过系统总线，从第一处理器接收目标数据，目标数据为待写入第一计算机的内存中的数据，目标数据的写地址位于第一内存地址空间中。
720、第二处理器将目标数据写入第二内存地址空间。
在一个实施例，第二处理器可以直接将目标数据写入第一内存地址空间；在另一个实施例中，第二处理器可以通过内存控制器将目标数据写入第一内存地址空间。
本发明实施例中，通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
可选地，作为一个实施例，步骤710可包括：第二处理器的非透明桥通过系统总线，从第一处理器接收镜像报文，镜像报文包含目标数据以及所述写地址在第二内存地址空间中的镜像地址；第二处理器将目标数据写入第二内存地址空间，包括：第二处理器的非透明桥将镜像报文转换成目标数据的写报文；第二处理器的非透明桥通过第二计算机的内存控制器将写报文写入第二内存地址空间的镜像地址中。
可选地，作为一个实施例，图7的方法还可包括：第二处理器的非透明桥从内存控制器接收写报文对应的写完成报文，写完成报文包括镜像地址；第二处理器的非透明桥根据第一内存地址空间和第二内存地址空间的映射关系，将镜像地址转换为写地址；第二处理器的非透明桥向第一处理器发送镜像报文对应的镜像完成报文，镜像完成报文包括写地址，镜像完成报文用于指示目标数据已写入镜像地址。
可选地，作为一个实施例，系统总线为QPI总线或HT总线。
应理解，在上文中的某些实施例中，第一处理器的非透明桥负责将镜像报文中的写地址转换成镜像地址(该镜像地址为该写地址在第二内存地址空 间中的对应地址)，第二处理器的非透明桥负责将镜像报文转换成第二处理器能够识别的写报文，但本发明实施例并不限于此，实际中，可以由第二处理器的非透明桥既负责地址的转换工作，也负责报文的转换工作。同理，在上文的某些实施例中，第二处理器的非透明桥负责将写完成报文中的镜像地址转换成写地址，第一处理器的非透明桥负责将写完成报文转换成镜像完成报文，但本发明实施例也不限于此，实际中，可以由第一处理器的非透明桥既负责地址转换工作，也负责报文的转换工作。
还应理解，处理器中的非透明桥可以负责镜像相关的操作，如报文的转换、报文中的地址的转换，其余操作或功能(如生成写报文和镜像报文的操作、数据的写操作、将镜像报文发送至非透明桥的操作等)均可由处理器本体执行，例如处理器中的控制器或控制逻辑执行，以支持QPI技术的CPU为例，这里所说的处理器的本体可以CPU中的CA、HA等处理引擎。
上文中结合图2至图7，详细描述了根据本发明实施例的集群计算机系统中的处理写请求的方法，下面将结合图8至图11，详细描述根据本发明实施例的处理器和计算机。
图8是本发明实施例的处理器的示意性结构图。图8的处理器800能够实现图1至图7中的由第一处理器执行的各个步骤，为避免重复，此处不再详述。处理器800位于第一计算机中，所述第一计算机和第二计算机连接，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第二计算机包括另一处理器，所述处理器800包括系统总线接口810，所述处理器800的系统总线接口通过系统总线与所述另一处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，所述处理器800还包括控制器820和内部总线830，所述控制器820通过所述内部总线830与所述处理器800的系统总线接口810相连，
所述控制器820用于接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；确定所述写地址位于所述第一内存地址空间中；将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述另一处理器，以便所述另一处理器将所述目标数据写入所述第二内存地址空间。
本发明实施例中，通过系统总线将两个不同计算机的处理器连接在一 起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
可选地，作为一个实施例，所述处理器800还可包括非透明桥840，所述非透明桥840与所述系统总线接口810相连，所述非透明桥840通过所述内部总线830与所述控制器820相连，所述控制器820具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址，所述镜像报文用于将所述目标数据写入所述写地址在所述第二内存地址空间中的镜像地址；将所述镜像报文发送至所述非透明桥；所述非透明桥840用于根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述镜像地址，得到更新后的镜像报文；通过所述系统总线，向所述另一处理器的非透明桥发送所述更新后的镜像报文，以便所述另一处理器根据所述另一处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
可选地，作为一个实施例，所述非透明桥840还用于当在预设时间内从所述另一处理器接收到所述镜像报文对应的镜像完成报文后，向所述控制器820发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；所述控制器820还用于根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
可选地，作为一个实施例，所述非透明桥840还用于当在所述预设时间内未从所述另一处理器接收到所述镜像完成报文时，向所述控制器820发送镜像超时报文；所述控制器820还用于根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
可选地，作为一个实施例，所述控制器820具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述处理器的非透明桥，所述处理器的非透明桥通过所述系统总线，向所述另一处理器的非透明桥发送所述镜像报文，以使所述另一处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述另一处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
可选地，作为一个实施例，所述控制器具体用于根据所述写请求，生成 所述目标数据的写报文；根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
可选地，作为一个实施例，所述系统总线为QPI总线或HT总线。
图9是本发明实施例的处理器的示意性结构图。图9的处理器900能够实现图1至图7中由第二处理器执行的各个步骤，为避免重复，此处不再详述。处理器900位于与第一计算机连接的第二计算机中，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括另一处理器，所述处理器900包括系统总线接口910，所述另一处理器的系统总线接口通过系统总线与所述处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，所述处理器900包括控制器920、内部总线930和非透明桥940，所述非透明桥930与所述处理器900的系统总线接口910相连，所述控制器920和所述非透明桥940通过所述内部总线930相连，
所述非透明桥940用于通过所述系统总线，从所述另一处理器接收目标数据，所述目标数据为待写入所述另一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；将所述目标数据写入所述第二内存地址空间。
本发明实施例中，通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
可选地，作为一个实施例，所述非透明桥940具体用于通过所述系统总线，从所述另一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；将所述镜像报文转换成所述目标数据的写报文；通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
可选地，作为一个实施例，所述非透明桥940还用于从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；向所述另一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所 述目标数据已写入所述镜像地址。
可选地，作为一个实施例，所述系统总线为QPI总线或HT总线。
图10是本发明实施例的计算机的示意性结构图。图10的计算机1000与图1至图7中的第一计算机对应，能够执行由第一处理器执行的各个步骤，为避免重复，此处不再详述。所述计算机1000和另一计算机连接，所述计算机1000与所述另一计算机上分别运行着各自的操作系统，所述计算机1000包括第一处理器，所述另一计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述另一计算机的第二内存地址空间为所述计算机的第一内存地址空间的镜像地址空间，
所述计算机1000包括：
接收模块1010，用于接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；
确定模块1020，用于确定所述写地址位于所述第一内存地址空间中；
镜像模块1030，用于将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，以便所述第二处理器将所述目标数据写入所述第二内存地址空间。
本发明实施例中，通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
可选地，作为一个实施例，所述镜像模块1030具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址，所述镜像报文用于将所述目标数据写入所述写地址在所述第二内存地址空间中的镜像地址；将所述镜像报文发送至所述第一处理器的非透明桥；根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述镜像地址，得到更新后的镜像报文；通过所述系统总线，向所述第二处理器的非透明桥发送所述更新后的镜像报文，以便所述第二处理器根据所述第二处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
可选地，作为一个实施例，所述镜像模块1030还用于当所述第一处理 器的非透明桥在预设时间内从所述第二处理器接收到所述镜像报文对应的镜像完成报文后，向所述第一处理器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
可选地，作为一个实施例，所述镜像模块1030还用于当所述第一处理器的非透明桥在所述预设时间内未从所述第二处理器接收到所述镜像完成报文时，向所述第一处理器发送镜像超时报文；根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
可选地，作为一个实施例，所述镜像模块1030还用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述第一处理器的非透明桥，所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述镜像报文，以使所述第二处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述第二处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
可选地，作为一个实施例，所述镜像模块1030具体用于根据所述写请求，生成所述目标数据的写报文；根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
可选地，作为一个实施例，所述系统总线为QPI总线或HT总线。
图11是本发明实施例的计算机的示意性框图。图11的计算机1100对应于图1至图7中的第二计算机，能够实现第二计算机中的第二处理器执行的各个步骤，为避免重复，此处不再详述。所述计算机1100和另一计算机连接，所述另一计算机与所述计算机1100上分别运行着各自的操作系统，所述另一计算机包括第一处理器，所述计算机1100包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述计算机1100的第二内存地址空间为所述另一计算机的第一内存地址空间的镜像地址空间，
所述计算机1100包括：
镜像模块1110，用于通过所述系统总线，从所述第一处理器接收目标数据，所述目标数据为待写入所述第一处理器的内存中的数据，所述目标数据 的写地址位于所述第一内存地址空间中；
写操作模块1120，用于将所述目标数据写入所述第二内存地址空间。
本发明实施例中，通过系统总线将两个不同计算机的处理器连接在一起，利用系统总线实现待写入的数据的镜像操作，无需像现有技术那样执行多次DMA操作，也无需复杂的协议转换，降低了镜像操作的延时，提高了系统的IOPS性能。
可选地，作为一个实施例，所述镜像模块1110具体用于通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；所述写操作模块具体用于将所述镜像报文转换成所述目标数据的写报文；通过所述计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
可选地，作为一个实施例，所述镜像模块1110还用于从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；向所述第一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
可选地，作为一个实施例，所述系统总线为QPI总线或HT总线。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间 的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (36)

  1. 一种处理写请求的方法，应用于第一计算机中，其特征在于，所述第一计算机和第二计算机连接，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括第一处理器，所述第二计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，
    所述方法包括：
    所述第一处理器接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；
    所述第一处理器确定所述写地址位于所述第一内存地址空间中；
    所述第一处理器将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，以便所述第二处理器将所述目标数据写入所述第二内存地址空间。
  2. 如权利要求1所述的方法，其特征在于，所述第一处理器将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，包括：
    所述第一处理器根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；
    所述第一处理器将所述镜像报文发送至所述第一处理器的非透明桥；
    所述第一处理器的非透明桥根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文；
    所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述更新后的镜像报文，以便所述第二处理器根据所述第二处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
  3. 如权利要求2所述的方法，其特征在于，所述方法还包括：
    当所述第一处理器的非透明桥在预设时间内从所述第二处理器接收到所述镜像报文对应的镜像完成报文后，所述第一处理器的非透明桥向所述第一处理器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据 已写入所述镜像地址；
    所述第一处理器根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
  4. 如权利要求3所述的方法，其特征在于，所述方法还包括：
    当所述第一处理器的非透明桥在所述预设时间内未从所述第二处理器接收到所述镜像完成报文时，所述第一处理器的非透明桥向所述第一处理器发送镜像超时报文；
    所述第一处理器根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
  5. 如权利要求1所述的方法，其特征在于，所述第一处理器将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，包括：
    所述第一处理器根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；
    所述第一处理器将所述镜像报文发送至所述第一处理器的非透明桥，所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述镜像报文，以使所述第二处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述第二处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
  6. 如权利要求1-5中任一项所述的方法，其特征在于，所述第一处理器将所述写请求中的目标数据写入所述第一内存地址空间，包括：
    所述第一处理器根据所述写请求，生成所述目标数据的写报文；
    所述第一处理器根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
  7. 如权利要求1-6中任一项所述的方法，其特征在于，所述系统总线为快速通道互连QPI总线或超级传输HT总线。
  8. 一种处理写请求的方法，所述方法应用于与第一计算机连接的第二计算机，其特征在于，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括第一处理器，所述第二计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连， 所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，
    所述方法包括：
    所述第二处理器通过所述系统总线，从所述第一处理器接收目标数据，所述目标数据为待写入所述第一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；
    所述第二处理器将所述目标数据写入所述第二内存地址空间。
  9. 如权利要求8所述的方法，其特征在于，所述第二处理器通过所述系统总线，从所述第一处理器接收目标数据，包括：
    所述第二处理器的非透明桥通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；
    所述第二处理器将所述目标数据写入所述第二内存地址空间，包括：
    所述第二处理器的非透明桥将所述镜像报文转换成所述目标数据的写报文；
    所述第二处理器的非透明桥通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
  10. 如权利要求9所述的方法，其特征在于，所述方法还包括：
    所述第二处理器的非透明桥从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；
    所述第二处理器的非透明桥根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；
    所述第二处理器的非透明桥向所述第一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
  11. 如权利要求8所述的方法，其特征在于，所述第二处理器通过所述系统总线，从所述第一处理器接收目标数据，包括：
    所述第二处理器的非透明桥通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址；
    所述第二处理器将所述目标数据写入所述第二内存地址空间，包括：
    所述第二处理器的非透明桥将所述镜像报文转换成所述目标数据的写 报文，并将所述写地址转换成所述写地址在所述第二内存地址空间中的镜像地址；
    所述第二处理器的非透明桥通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
  12. 如权利要求8-11中任一项所述的方法，其特征在于，所述系统总线为快速通道互连QPI总线或超级传输HT总线。
  13. 一种处理器，其特征在于，所述处理器位于第一计算机，所述第一计算机与第二计算机连接，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第二计算机包括另一处理器，所述处理器和所述另一处理器均包括系统总线接口，所述处理器的系统总线接口通过系统总线与所述另一处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，所述处理器还包括控制器和内部总线，所述控制器通过所述内部总线与所述处理器的系统总线接口相连，
    所述控制器用于接收写请求，所述写请求包含待写的目标数据，以及所述目标数据的写地址；确定所述写地址位于所述第一内存地址空间中；将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述另一处理器，以便所述另一处理器将所述目标数据写入所述第二内存地址空间。
  14. 如权利要求13所述的处理器，其特征在于，所述处理器还包括非透明桥，所述非透明桥与所述系统总线接口相连，所述非透明桥通过所述内部总线与所述控制器相连，
    所述控制器具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；
    所述非透明桥用于根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文；通过所述系统总线，向所述另一处理器的非透明桥发送所述更新后的镜像报文，以便所述另一处理器根据所述另一处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
  15. 如权利要求14所述的处理器，其特征在于，所述非透明桥还用于 当在预设时间内从所述另一处理器接收到所述镜像报文对应的镜像完成报文后，向所述控制器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；
    所述控制器还用于根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
  16. 如权利要求15所述的处理器，其特征在于，所述非透明桥还用于当在所述预设时间内未从所述另一处理器接收到所述镜像完成报文时，向所述控制器发送镜像超时报文；
    所述控制器还用于根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
  17. 如权利要求13所述的处理器，其特征在于，所述控制器具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述处理器的非透明桥，所述处理器的非透明桥通过所述系统总线，向所述另一处理器的非透明桥发送所述镜像报文，以使所述另一处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述另一处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
  18. 如权利要求13-17中任一项所述的处理器，其特征在于，所述控制器具体用于根据所述写请求，生成所述目标数据的写报文；根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
  19. 如权利要求13-18中任一项所述的处理器，其特征在于，所述系统总线为快速通道互连QPI总线或超级传输HT总线。
  20. 一种处理器，其特征在于，所述处理器位于与第一计算机连接的第二计算机中，所述第一计算机与所述第二计算机上分别运行着各自的操作系统，所述第一计算机包括另一处理器，所述另一处理器和所述处理器均包括系统总线接口，所述另一处理器的系统总线接口通过系统总线与所述处理器的系统总线接口相连，所述第二计算机的第二内存地址空间为所述第一计算机的第一内存地址空间的镜像地址空间，所述处理器包括控制器、非透明桥和内部总线，所述非透明桥与所述处理器的系统总线接口相连，所述控制器和所述非透明桥通过所述内部总线相连，
    所述非透明桥用于通过所述系统总线，从所述另一处理器接收目标数据，所述目标数据为待写入所述另一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；将所述目标数据写入所述第二内存地址空间。
  21. 如权利要求20所述的处理器，其特征在于，所述非透明桥具体用于通过所述系统总线，从所述另一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；将所述镜像报文转换成所述目标数据的写报文；通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
  22. 如权利要求21所述的处理器，其特征在于，所述非透明桥还用于从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；向所述另一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
  23. 如权利要求20所述的处理器，其特征在于，所述非透明桥具体用于通过所述系统总线，从所述另一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址；将所述镜像报文转换成所述目标数据的写报文，并将所述写地址转换成所述写地址在所述第二内存地址空间中的镜像地址；通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
  24. 如权利要求20-23中任一项所述的处理器，其特征在于，所述系统总线为快速通道互连QPI总线或超级传输HT总线。
  25. 一种计算机，其特征在于，所述计算机与另一计算机连接，所述计算机与所述另一计算机上分别运行着各自的操作系统，所述计算机包括第一处理器，所述另一计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述另一计算机的第二内存地址空间为所述计算机的第一内存地址空间的镜像地址空间，
    所述计算机包括：
    接收模块，用于接收写请求，所述写请求包含待写的目标数据，以及所 述目标数据的写地址；
    确定模块，用于确定所述写地址位于所述第一内存地址空间中；
    镜像模块，用于将所述写请求中的目标数据写入所述第一内存地址空间，并将所述写请求中的目标数据通过所述系统总线，发送至所述第二处理器，以便所述第二处理器将所述目标数据写入所述第二内存地址空间。
  26. 如权利要求25所述的计算机，其特征在于，所述镜像模块具体用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述第一处理器的非透明桥；根据所述第一内存地址空间和所述第二内存地址空间之间的镜像关系，将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文；通过所述系统总线，向所述第二处理器的非透明桥发送所述更新后的镜像报文，以便所述第二处理器根据所述第二处理器的非透明桥收到的所述更新后的镜像报文将所述目标数据写入所述镜像地址。
  27. 如权利要求26所述的计算机，其特征在于，所述镜像模块还用于当所述第一处理器的非透明桥在预设时间内从所述第二处理器接收到所述镜像报文对应的镜像完成报文后，向所述第一处理器发送所述镜像完成报文，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址；根据所述镜像完成报文，确认所述目标数据的镜像操作成功，结束所述镜像操作对应的镜像事务。
  28. 如权利要求27所述的计算机，其特征在于，所述镜像模块还用于当所述第一处理器的非透明桥在所述预设时间内未从所述第二处理器接收到所述镜像完成报文时，向所述第一处理器发送镜像超时报文；根据所述镜像超时报文，确认所述镜像操作失败，结束所述镜像事务。
  29. 如权利要求25所述的计算机，其特征在于，所述镜像模块还用于根据所述写请求，生成镜像报文，所述镜像报文包含所述目标数据和所述写地址；将所述镜像报文发送至所述第一处理器的非透明桥，所述第一处理器的非透明桥通过所述系统总线，向所述第二处理器的非透明桥发送所述镜像报文，以使所述第二处理器的非透明桥将所述镜像报文中的写地址转换成所述写地址在所述第二内存地址空间中的镜像地址，得到更新后的镜像报文，以及使得所述第二处理器根据所述更新后的镜像报文将所述目标数据写入所述镜像地址。
  30. 如权利要求25-29中任一项所述的计算机，其特征在于，所述镜像模块具体用于根据所述写请求，生成所述目标数据的写报文；根据所述写报文，将所述目标数据写入所述第一内存地址空间的所述写地址中。
  31. 如权利要求25-30中任一项所述的计算机，其特征在于，所述系统总线为快速通道互连QPI总线或超级传输HT总线。
  32. 一种计算机，其特征在于，所述计算机和另一计算机连接，所述另一计算机与所述计算机上分别运行着各自的操作系统，所述另一计算机包括第一处理器，所述计算机包括第二处理器，所述第一处理器和所述第二处理器均包括系统总线接口，所述第一处理器的系统总线接口通过系统总线与所述第二处理器的系统总线接口相连，所述计算机的第二内存地址空间为所述另一计算机的第一内存地址空间的镜像地址空间，
    所述计算机包括：
    镜像模块，用于通过所述系统总线，从所述第一处理器接收目标数据，所述目标数据为待写入所述第一处理器的内存中的数据，所述目标数据的写地址位于所述第一内存地址空间中；
    写操作模块，用于将所述目标数据写入所述第二内存地址空间。
  33. 如权利要求32所述的计算机，其特征在于，所述镜像模块具体用于通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址在所述第二内存地址空间中的镜像地址；所述写操作模块具体用于将所述镜像报文转换成所述目标数据的写报文；通过所述计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
  34. 如权利要求33所述的计算机，其特征在于，所述镜像模块还用于从所述内存控制器接收所述写报文对应的写完成报文，所述写完成报文包括所述镜像地址；根据所述第一内存地址空间和所述第二内存地址空间的映射关系，将所述镜像地址转换为所述写地址；向所述第一处理器发送所述镜像报文对应的镜像完成报文，所述镜像完成报文包括所述写地址，所述镜像完成报文用于指示所述目标数据已写入所述镜像地址。
  35. 如权利要求32所述的计算机，其特征在于，所述镜像模块具体用于通过所述系统总线，从所述第一处理器接收镜像报文，所述镜像报文包含所述目标数据以及所述写地址；所述写操作模块具体用于将所述镜像报文转 换成所述目标数据的写报文，并将所述写地址转换成所述写地址在所述第二内存地址空间中的镜像地址；通过所述第二计算机的内存控制器将所述写报文写入所述第二内存地址空间的所述镜像地址中。
  36. 如权利要求32-35中任一项所述的计算机，其特征在于，所述系统总线为快速通道互连QPI总线或超级传输HT总线。
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