WO2019095655A1 - 一种数据交互方法和计算设备 - Google Patents

一种数据交互方法和计算设备 Download PDF

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Publication number
WO2019095655A1
WO2019095655A1 PCT/CN2018/087408 CN2018087408W WO2019095655A1 WO 2019095655 A1 WO2019095655 A1 WO 2019095655A1 CN 2018087408 W CN2018087408 W CN 2018087408W WO 2019095655 A1 WO2019095655 A1 WO 2019095655A1
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Prior art keywords
data packet
bios
bmc
interaction area
application
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PCT/CN2018/087408
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English (en)
French (fr)
Inventor
陈焱
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华为技术有限公司
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Publication of WO2019095655A1 publication Critical patent/WO2019095655A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the field of information technology (IT), and in particular, to a data interaction method and a computing device.
  • IT information technology
  • BIOS basic input output system
  • Baseboard Management Controller Baseboard Management Controller
  • BIOS Basic input output system
  • Baseboard Management Controller Baseboard Management Controller
  • the BIOS is a set of programs that are solidified onto a Read-Only Memory (ROM) chip in the server, which stores the most important basic input and output programs of the computer, the self-test program after booting, and the system self-starting program. Wait.
  • the BMC is typically included in the main board of the template or monitored device. The BMC can use sensors to monitor the status of computers, network servers, or other hardware-driven devices, and communicate with system administrators through separate connection lines.
  • the BIOS can exchange data with the BMC through an Intelligent Platform Management Interface (IPMI) based on the hardware Low Speed Count (LPC) and Block Transfer (BT) protocols.
  • IPMI Intelligent Platform Management Interface
  • LPC Low Speed Count
  • BT Block Transfer
  • the maximum transmission value of LPC is only 16 megabits per second (MB/s), which is generally applied to some low-speed peripherals such as mouse and keyboard.
  • BIOS and BMC such as system management BIOS (System Management) BIOS, SMBIOS) data, the data packet needs to be unpacked and transmitted.
  • the SMBIOS data of a server with a power port of 8 or more pins can usually reach 110 kilobytes (Kb).
  • Kb kilobytes
  • the data packet needs to be split into more than 400 IPMI messages to be transmitted, and the transmission time is long. low efficiency.
  • IPMI is a server/client (CS/S) architecture
  • the BMC acts as a server and the BIOS acts as a client.
  • the BMC does not support sending messages to the BIOS.
  • the BMC actively informs the BIOS that the general purpose input/output (GPIO) trigger is adopted. Due to the limitation of the number of GPIO pins, the flexibility of the BMC active notification is reduced.
  • the BMC cannot receive events reported by the BIOS during the restart process, which may result in data loss.
  • BT only supports synchronous transmission, and does not support asynchronous transmission.
  • the embodiment of the present application provides a data interaction method and a computing device, which can improve data interaction efficiency between a BIOS and a BMC.
  • the embodiment of the present application provides a data interaction method, which is applied to a data transmission scenario including a BIOS and a BMC.
  • the BMC includes a virtual external device interconnect (PCI) device, and a virtual device.
  • the PCIE device includes an input/output (I/O) memory space, and the I/O memory space includes a first shared interaction area;
  • the data interaction method includes: the BIOS uses the first packet of the first application through the PCIE channel. Copying to the first shared interaction area; the BMC obtains the first data packet from the first shared interaction area through the memory channel; the BMC determines, according to the mapping relationship between the first application and the second application, that the second application acquires the first data packet.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the first data packet of the first application to the second application. Since the size of the first shared interaction area in the virtual PCIE device is configurable, for example, it can be 32M, 64M, 128M, etc., and can transmit more and larger data packets in a short time, thereby improving the BIOS and the BMC. Data interaction efficiency.
  • the acquiring, by the BMC, the first data packet from the first shared interaction area by using the memory channel includes: acquiring, by the BMC, the first data packet from the first shared interaction area within a preset time.
  • the BMC can obtain the first data packet from the first shared interaction area within a preset time, and can solve the problem that the BMC cannot receive the data packet sent by the BIOS when the BIOS copies the data packet to the first shared interaction area during the BMC restart. The problem of packet loss.
  • the BMC acquires the first data packet from the first shared interaction area according to the interrupt notification.
  • this application is not limited to this.
  • the method further includes: the BIOS is connected between the central processing unit (CPU) and the virtual PCIE device.
  • the PCIE channel accesses the configuration space of the virtual PCIE device; the BIOS determines the physical address of the first shared interaction area by accessing the configuration space of the virtual PCIE device; the BIOS determines the first shared interaction area by using the physical address of the first shared interaction area.
  • the CPU can establish a serial link with at least one PCIE device. For each PCIE device, the serial link between the PCIE device and the CPU is considered to be a PCIE channel.
  • the PCIE management module on the CPU can control the PCIE channel.
  • the PCIE management module can control the PCIE channel of the CPU and the virtual PCIE device. Therefore, the BIOS can access the configuration space of the virtual PCIE device through the PCIE management module on the CPU, that is, the BIOS can access the configuration space of the virtual PCIE device through the PCIE channel.
  • the method before the BIOS copies the first data packet of the first application to the first shared interaction area through the PCIE channel, the method further includes: the BIOS determining whether the first shared interaction area exceeds a maximum capacity limit; It is determined that the first shared interaction area does not exceed the maximum capacity limit, and the BIOS copies the first data packet to the first shared interaction area. If the BIOS determines that the first shared interaction area exceeds the maximum capacity limit, the BIOS may wait for the first shared interaction area to be idle, and then copy the first data packet to the first shared interaction area.
  • the method before the BIOS copies the first data packet of the first application to the first shared interaction area through the PCIE channel, the method further includes: the BIOS acquiring the sending address, the receiving address, and the second data packet of the second data packet.
  • the length of the data packet, the sending address of the second data packet is used to indicate the memory unit of the BIOS
  • the receiving address of the second data packet is used to indicate the memory unit of the BMC
  • the virtual PCIE device is sent from the BIOS according to the sending address of the second data packet.
  • the memory unit acquires the second data packet, and sends the second data packet to the memory unit of the BMC according to the receiving address of the second data packet.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through a virtual PCIE device, for example, transmitting a second data packet of the first application to the second application, where the second data packet can be a direct memory access (Direct Memory Access, DMA) packet. Since the virtual PCIE device can perform DMA transmission, it can transmit DMA data packets with a large amount of data in a short time, thereby improving the data interaction efficiency between the BIOS and the BMC.
  • a virtual PCIE device can perform DMA transmission, it can transmit DMA data packets with a large amount of data in a short time, thereby improving the data interaction efficiency between the BIOS and the BMC.
  • the first data packet includes a transmission address of the second data packet, a reception address, and a length of the second data packet. Therefore, when the BMC parses the first data packet and determines information such as the sending address, the receiving address, and the length of the second data packet, the BMC can determine that the second data packet has been transmitted, so that the BMC can The memory unit on the BMC side acquires the second data packet.
  • the first data packet may not carry the sending address and the receiving address of the second data packet.
  • the I/O memory space further includes a second shared interaction area
  • the method further includes: the BMC copies the third data packet of the second application to the second shared interaction area through the memory channel; and the BIOS passes the PCIE.
  • the channel obtains the third data packet from the second shared interaction area; the BIOS determines, according to the mapping relationship between the second application and the first application, that the first application acquires the third data packet. Therefore, compared with the prior art, the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the third data packet of the second application to the first application.
  • the size of the second shared interaction area in the virtual PCIE device is configurable, for example, it can be 32M, 64M, 128M, etc., so that more and larger data packets can be transmitted in a short time, thereby improving BIOS and BMC data interaction efficiency.
  • the method before the BMC copies the third data packet to the second shared interaction area through the memory channel, the method further includes: determining, by the BMC, whether the second shared interaction area exceeds a maximum capacity limit; if the BMC determines the second share The interaction area does not exceed the maximum capacity limit, and the BMC copies the third data packet to the second shared interaction area. If the BMC determines that the second shared interaction area exceeds the maximum capacity limit, the BMC may wait for the second shared interaction area to be idle, and then copy the third data packet to the second shared interaction area.
  • the method further includes: the BMC acquires a sending address, a receiving address, and a length of the fourth data packet of the fourth data packet, where the sending address of the fourth data packet is used to indicate the memory unit of the BMC, and fourth The receiving address of the data packet is used to indicate the memory unit of the BIOS; the virtual PCIE device acquires the fourth data packet from the memory unit of the BMC according to the sending address of the fourth data packet, and sets the fourth data packet according to the receiving address of the fourth data packet. A memory unit that is sent to the BIOS.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through a virtual PCIE device, for example, transmitting a fourth data packet of the second application to the first application, where the fourth data packet can be a DMA data packet. Since the virtual PCIE device can perform DMA transmission, it can transmit DMA data packets with a large amount of data in a short time, thereby improving the data interaction efficiency between the BIOS and the BMC.
  • the third data packet includes a transmission address of the fourth data packet, a reception address, and a length of the fourth data packet.
  • the BIOS may obtain the sending address, the receiving address, and the length of the fourth data packet of the fourth data packet, and write the sending address, the receiving address, and the length of the fourth data packet of the fourth data packet. Enter the registers in the configuration space of the virtual PCIE device and start the DMA transfer.
  • the method further includes: the BIOS communicating with the BMC by using a synchronous communication manner or an asynchronous communication manner; wherein the synchronous communication manner is used to instruct the BIOS to receive the response packet of the first data packet sent by the BMC and the BMC receiving
  • the reply packet of the third data packet sent by the BIOS is used to indicate that the BIOS does not receive the reply packet of the first data packet sent by the BMC, and the BMC does not receive the reply packet of the third data packet sent by the BIOS. Therefore, when the BIOS communicates with the BMC through the asynchronous communication mode, the BMC does not need to wait for the reply packet of the data packet, and the BMC restarts the data that can be asynchronously transmitted after the BMC restarts. package.
  • a second aspect provides a computing device, including a BIOS and a BMC.
  • the BMC includes a virtual PCIE device.
  • the virtual PCIE device includes an input/output I/O memory space, and the I/O memory space includes a first shared interaction area.
  • the BIOS is configured to: copy the first data packet of the first application to the first shared interaction area through the PCIE channel;
  • the BMC is configured to: obtain the first data packet from the first shared interaction area through the memory channel;
  • the BMC is further configured to: The mapping relationship between the first application and the second application determines that the second application acquires the first data packet.
  • the BMC is configured to: acquire the first data packet from the first shared interaction area within a preset time; or acquire the first data packet from the first shared interaction area according to the interruption notification.
  • the BIOS is further configured to: access a configuration space of the virtual PCIE device through a PCIE channel between the central processing unit CPU and the virtual PCIE device; determine the first share by accessing a configuration space of the virtual PCIE device. The physical address of the interaction area; determining the first shared interaction area by the physical address of the first shared interaction area.
  • the BIOS is further configured to: determine whether the first shared interaction area exceeds a maximum capacity limit; if it is determined that the first shared interaction area does not exceed the maximum capacity limit, copy the first data packet to the first shared interaction area. .
  • the BIOS is further configured to: obtain a sending address, a receiving address, and a length of the second data packet of the second data packet, where the sending address of the second data packet is used to indicate a memory unit of the BIOS, and the second data
  • the receiving address of the packet is used to indicate the memory unit of the BMC
  • the virtual PCIE device is configured to: obtain the second data packet from the memory unit of the BIOS according to the sending address of the second data packet, and use the second data packet according to the receiving address of the second data packet. The packet is sent to the memory unit of the BMC.
  • the first data packet includes a transmission address of the second data packet, a reception address, and a length of the second data packet.
  • the I/O memory space further includes a second shared interaction area
  • the BMC is further configured to: copy the third data packet of the second application to the second shared interaction area through the memory channel; the BIOS is also used to Obtaining, by the PCIE channel, the third data packet from the second shared interaction area; determining, according to the mapping relationship between the second application and the first application, that the first application acquires the third data packet.
  • the BMC is further configured to: determine whether the second shared interaction area exceeds a maximum capacity limit; if it is determined that the second shared interaction area does not exceed the maximum capacity limit, copy the third data packet to the second shared interaction area. .
  • the BMC is further configured to: obtain a sending address, a receiving address, and a length of the fourth data packet of the fourth data packet, where the sending address of the fourth data packet is used to indicate the memory unit of the BMC, and the fourth data The receiving address of the packet is used to indicate the memory unit of the BIOS;
  • the virtual PCIE device is further configured to: obtain the fourth data packet from the memory unit of the BMC according to the sending address of the fourth data packet, and according to the receiving address of the fourth data packet, Four data packets are sent to the memory unit of the BIOS.
  • the third data packet includes a transmission address of the fourth data packet, a reception address, and a length of the fourth data packet.
  • the BIOS communicates with the BMC by using a synchronous communication mode or an asynchronous communication mode.
  • the synchronous communication mode is used to instruct the BIOS to receive the response packet of the first data packet sent by the BMC and the third message sent by the BMC receiving BIOS.
  • the reply packet of the data packet is used to indicate that the BIOS does not receive the reply packet of the first data packet sent by the BMC, and the BMC does not receive the reply packet of the third data packet sent by the BIOS.
  • an embodiment of the present invention provides a computing device, where the computing device exists in a product form of a chip, where the computing device includes a processor and a memory, where the memory is used to couple with the processor to save the computing device.
  • the necessary program instructions and data are used by the processor to execute program instructions stored in the memory such that the computing device performs the functions of the computing device in the method described above.
  • the embodiment of the present invention provides a computing device, which can implement the functions performed by the computing device in the foregoing method, and the functions can be implemented by using hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the computing device includes a processor and a communication interface configured to support the computing device to perform the corresponding functions of the methods described above.
  • the communication interface is used to support communication between the computing device and other network elements.
  • the computing device can also include a memory for coupling with the processor that holds the program instructions and data necessary for the computing device.
  • an embodiment of the present invention provides a computing device readable storage medium, including instructions, when executed on a computing device, causing the computing device to perform any of the methods provided by the first aspect.
  • an embodiment of the present invention provides a program product including instructions, when executed on a computing device, causing the computing device to perform any of the methods provided by the first aspect.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the first data packet of the first application to the second application, or transmitting the third data packet of the second application to the first application.
  • the size of the first shared interaction area and the second shared interaction area in the virtual PCIE device is configurable, for example, it may be 32M, 64M, 128M, etc., and can transmit more and larger data packets in a short time. Thereby, the data interaction efficiency between the BIOS and the BMC can be improved.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the second data packet of the first application to the second application, or transmitting the fourth data packet of the second application to the second application.
  • the second data packet or the fourth data packet may be a DMA data packet. Since the virtual PCIE device can perform DMA transmission, it can transmit DMA data packets with a large amount of data in a short time, thereby improving the data interaction efficiency between the BIOS and the BMC.
  • FIG. 1 is a schematic structural diagram of an embodiment of the present application
  • FIG. 2 is a schematic diagram of signal interaction of a data interaction method according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a data packet processing mechanism of a BMC according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of signal interaction of a data interaction method according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of signal interaction of a data interaction method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of signal interaction of a data interaction method according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a computing device according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a computing device according to an embodiment of the present application.
  • the embodiment of the present application can be applied to the scenario of data interaction between the BIOS and the BMC, including a small data transmission scenario and a big data transmission scenario.
  • the BIOS receives the system startup item information sent by the BMC or the information of the cabinet-level hard partition server interaction.
  • the BIOS sends the system SMBIOS data to the BMC.
  • the embodiment of the present application can also be applied to other data interaction scenarios, such as an operating system (OS) and a BMC data interaction scenario, which is not limited in this application.
  • OS operating system
  • BMC data interaction scenario which is not limited in this application.
  • the architecture of the present application may include a BIOS and a BMC.
  • the BIOS includes a first application and an Enhanced Direct Memory Access (EDMA) control module.
  • the BMC includes a second application, an EDMA management module, and a virtual PCIE device.
  • the BIOS and BMC can exchange data through virtual PCIE devices.
  • Virtual PCIE devices include I/O memory space, configuration space, and DMA controllers.
  • the I/O memory space includes a first shared interaction area and a second shared interaction area. The size of the first shared interaction area and the second shared interaction area may be set at the time of initialization, for example, may be 32M, 64M, 128M, or the like.
  • the I/O memory space may also include a DMA indicator area (not shown in Figure 1).
  • the configuration space is used to store the physical addresses of the first shared interaction area, the second shared interaction area, and the DMA indication area, and may also include a register for triggering DMA transmission.
  • the DMA controller is used for DMA transfer according to the value of the register that triggers the DMA transfer. More or less functional modules may be included in the BIOS and the BMC, which are not limited in this embodiment.
  • BIOS may include multiple types of applications, and the BMC may also include multiple types of applications, and the applications in the BIOS are in one-to-one correspondence with the applications in the BMC.
  • the BIOS includes a first application
  • the BMC includes a second application as an example. The first application corresponds to the second application.
  • the EDMA control module in the BIOS is configured to copy the first data packet sent by the first application in the BIOS to the first shared interaction area of the virtual PCIE device, or obtain the second data from the second shared interaction area of the virtual PCIE device.
  • the EDMA management module in the BMC is configured to: copy the third data packet sent by the second application in the BMC to the second shared interaction area of the virtual PCIE device, or obtain the first information sent by the first application from the first shared interaction area. data pack.
  • the EDMA control module can also preset the physical address of the memory unit in the BIOS for storing DMA packets.
  • the physical address of the DMA packet is the transmission address of the second packet of the first application, or the receiving address of the fourth packet of the second application.
  • the EDMA management module can also preset the physical address of the memory unit in the BMC for storing DMA packets.
  • the physical address of the DMA packet is the transmission address of the fourth packet of the second application, or the reception address of the second packet of the first application.
  • the first data packet sent by the first application is smaller than the second data packet sent by the first application, and the third data packet sent by the second application is smaller than the fourth data packet sent by the second application.
  • the first data packet sent by the first application may include information such as a component health event.
  • the second data packet sent by the first application may be a DMA data packet, and the DMA data packet may include SMBIOS data and the like.
  • the third data packet sent by the second application may include system startup item information or information of a cabinet-level hard partition server interaction.
  • the fourth data packet sent by the second application may be a DMA data packet, and the DMA data packet may include setting information of the BIOS and the like.
  • An embodiment of the present application provides a data interaction method, where the first application sends the first data packet to the second application as an example. As shown in FIG. 2, the method includes:
  • the first application registers a type identifier on the BIOS, and the second application registers a type identifier on the BMC.
  • the first application may register the type identifier of the first application on the EDMA control module
  • the second application may register the type identifier of the second application on the EDMA management module.
  • the type identifier of the first application and the type identifier of the second application may be the same to indicate that the first application and the second application have a mapping relationship.
  • the application is not limited thereto.
  • the BIOS accesses a configuration space of the virtual PCIE device.
  • the BIOS can access the configuration space of the virtual PCIE device through the PCIE management module on the CPU, and obtain the physical address of the first shared interaction area, the physical address of the second shared interaction area, and the like.
  • the CPU can establish a serial link with at least one PCIE device.
  • the serial link between the PCIE device and the CPU is considered to be a PCIE channel.
  • the PCIE management module on the CPU can control the PCIE channel.
  • the PCIE management module can control the PCIE channel of the CPU and the virtual PCIE device. Therefore, the BIOS can access the configuration space of the virtual PCIE device through the PCIE management module on the CPU, that is, the BIOS can access the configuration space of the virtual PCIE device through the PCIE channel.
  • the BIOS may access the first shared interaction area and the second shared interaction area according to the physical address of the first shared interaction area and the physical address of the second shared interaction area. Access includes reading data from the corresponding area and writing data to the corresponding area.
  • the BIOS copies the first data packet of the first application to the first shared interaction area by using a PCIE channel.
  • the first data packet includes a type identifier of the first application.
  • the EDMA control module may add the type identifier of the first application to the first data packet sent by the first application, and copy the data packet to the first through the PCIE channel. Share the interactive area.
  • the first data packet is a data packet encapsulated by at least one layer of a service protocol
  • the service protocol may include: a Transmission Control Protocol (TCP)/Internet Protocol (IP), and an Internet Data Packet Interaction Protocol. (Internet work Packet Exchange, IPX)/Sequenced Packet Exchange protocol (SPX), NetBios Enhanced User Interface (NetBEUI) or custom protocol.
  • TCP Transmission Control Protocol
  • IP Internet Protocol
  • SPX Sequenced Packet Exchange protocol
  • NetBEUI NetBios Enhanced User Interface
  • the service protocol may also include other types of communication protocols, which are not limited in this application.
  • the EDMA control module may determine whether the first shared interaction area exceeds a maximum capacity limit; if the first shared interaction area does not exceed the maximum capacity limit, The EDMA control module may copy the first data packet to the first shared interaction area; if the first shared interaction area exceeds the maximum capacity limit, the EDMA control module may notify the EDMA management module to the first shared interaction area by triggering a corresponding interrupt. The data is processed.
  • the EDMA control module may determine, according to a preset time interval, whether the first shared interaction area exceeds a maximum capacity.
  • the BIOS can receive a reply packet of the first data packet sent by the BMC. If the BIOS communicates with the BMC in asynchronous communication mode, the BIOS may not receive the reply packet of the first data packet sent by the BMC.
  • the OS may determine whether the pre-transmission buffer of the OS is idle before copying the first data packet to the first shared interaction area, and if the OS is determined to be sent. The buffer area is idle, and the OS can import the first data packet into the pre-transmission buffer area of the OS to copy the data packets in the pre-send buffer area to the first shared interaction area.
  • the BMC obtains the first data packet from the first shared interaction area by using a memory channel.
  • the BMC can include system memory, system memory bus, and control chip.
  • the system memory accesses the control chip through the system memory bus to form a memory channel.
  • the system memory of the BMC includes a first shared interaction area.
  • an interrupt notification may be sent to notify the BMC to acquire the first data packet.
  • the BMC can obtain the first data packet from the first shared interaction area through the memory channel.
  • the BMC may acquire the first data packet from the first shared interaction area within a preset time. For example, the BMC may detect whether the first shared interaction area has a BIOS copy of the data packet after a preset time interval; or the BMC may detect whether the first shared interaction area has a BIOS copy data packet at a preset time. If the BMC detects a packet with a BIOS copy in the first shared interaction area within a preset time, for example, the first data packet, the BMC can read the first data packet.
  • the BMC can obtain the first data packet from the first shared interaction area within a preset time, and can solve the problem that the BMC cannot receive the data packet sent by the BIOS when the BIOS copies the data packet to the first shared interaction area during the BMC restart.
  • the problem of packet loss is the reason for packet loss.
  • the BMC determines, according to the mapping relationship between the first application and the second application, that the second application obtains the first data packet.
  • the BIOS and the BMC negotiate the meaning of the type identifier of the application registration in the design phase. Therefore, the BMC can identify the type according to the type of the first application. Determining that the first data packet corresponds to the second application, and determining that the second application obtains the first data packet according to the mapping relationship between the first application and the second application.
  • the EDMA management module determines that the first data packet corresponds to the second application according to the type identifier of the first application
  • the first data packet may be copied to the memory area corresponding to the second application, and the second application is used.
  • the detecting module (poll) can detect whether there is a data packet in the memory area corresponding to the second application within a preset time, and if the poll detects the first data packet, the data packet can be sent to the processing cache of the second application, and The processing module notifying the second application processes the first data packet.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the data packet of the first application to the second application. Since the size of the first shared interaction area and the second shared interaction area in the virtual PCIE device is configurable, for example, it may be 32M, 64M, 128M, etc., and can transmit more and larger data packets in a short time. Thereby, the data interaction efficiency between the BIOS and the BMC can be improved.
  • An embodiment of the present application provides a data interaction method, where the first application sends a second data packet and a first data packet to the second application as an example. As shown in FIG. 4, the method includes:
  • the first application registers a type identifier on the BIOS, and the second application registers a type identifier on the BMC.
  • step 201 For the specific process, refer to step 201.
  • the BIOS accesses a configuration space of the virtual PCIE device.
  • step 202 For the specific process, reference may be made to step 202.
  • BIOS can also determine the physical address of the DMA marked area by accessing the configuration space of the virtual PCIE device, and can access the DMA marked area according to the physical address of the DMA marked area.
  • the BIOS acquires a sending address, a receiving address, and a length of the second data packet of the second data packet.
  • the BIOS can obtain the sending address, the receiving address, and the length of the second data packet of the second data packet by accessing the DMA marking area.
  • the second data packet may be a DMA data packet to be sent by the first application, the sending address of the second data packet is used to indicate a memory unit of the BIOS, and the receiving address of the second data packet is used to indicate a memory unit of the BMC. That is, the transmission address of the second data packet is the physical address of the memory unit for storing the DMA data packet on the BIOS side, and the reception address of the second data packet is the physical address of the memory unit for storing the DMA data packet on the BMC side.
  • the BIOS writes the sending address, the receiving address, and the length of the second data packet of the second data packet into a register in a configuration space of the virtual PCIE device.
  • the configuration space of the virtual PCIE device may include a register for triggering DMA transfer, and the register may include a send address register of the DMA data packet, a receive address register of the DMA data packet, a data packet length register of the DMA data packet, and Whether to start the DMA transfer register.
  • the BIOS may write the sending address of the second data packet to the sending address register of the DMA data packet; write the receiving address of the second data packet to the receiving address register of the DMA data packet; and write the length of the second data packet The packet length register of the DMA packet; and sets the value of whether to enable the DMA transfer register to initiate a DMA transfer.
  • the virtual PCIE device acquires the second data packet from the memory unit indicated by the sending address of the second data packet, and sends the second data packet to the memory unit indicated by the receiving address of the second data packet.
  • the second data packet may be obtained from the memory unit indicated by the sending address of the second data packet, and the second data packet is sent.
  • the memory unit indicated by the receiving address of the second data packet That is, the DMA controller acquires the second data packet from the memory unit for storing the DMA data packet on the BIOS side, and sends the second data packet to the memory unit of the BMC side for storing the DMA data packet.
  • the BIOS can notify the BIOS of the end of the DMA transmission by using the interrupt notification or the preset identifier. Then, the BIOS may generate a first data packet according to the second data packet, where the first data packet is used to notify the BMC that the second data packet has been transmitted to the physical address of the DMA data packet on the BMC side and the related parameters of the second data packet.
  • the first data packet may include a type identifier of the first application and a length of the second data packet (ie, a size of the second data packet).
  • the BIOS copies the first data packet to the first shared interaction area.
  • step 203 For the specific process, reference may be made to step 203.
  • the BMC acquires the first data packet from the first shared interaction area.
  • step 204 For the specific process, reference may be made to step 204.
  • the BMC determines the second data packet according to the first data packet, and acquires the second data packet from the memory unit on the BMC side.
  • the BMC may determine that the second data packet has been transmitted, so that the EDMA management module can
  • the memory unit on the BMC side acquires the second data packet.
  • the first data packet may not carry the sending address and the receiving address of the second data packet.
  • the second data packet can be split into multiple data packets for transmission.
  • the transmission mode of each data packet can refer to the transmission mode of the first data packet in the embodiment shown in FIG. 2 .
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the DMA data packet of the first application to the second application. Since the virtual PCIE device can perform DMA transmission, it can transmit DMA data packets with a large amount of data in a short time, thereby improving the data interaction efficiency between the BIOS and the BMC.
  • An embodiment of the present application provides a data interaction method. As shown in FIG. 5, the second application sends a third data packet to the first application as an example, including:
  • the first application registers a type identifier on the BIOS, and the second application registers a type identifier on the BMC.
  • step 201 For the specific process, refer to step 201.
  • the BIOS accesses a configuration space of the virtual PCIE device.
  • step 202 For the specific process, reference may be made to step 202.
  • the BMC copies the third data packet to the second shared interaction area.
  • the third data packet includes a type identifier of the second application.
  • the EDMA management module may add the type identifier of the second application to the third data packet sent by the second application, and copy the data packet to the second shared interaction area. .
  • the third data packet is a data packet encapsulated by at least one layer of service protocol
  • the service protocol may include the following protocols: TCP/IP, IPX/SPX protocol, NetBEUI protocol, and custom protocol.
  • the service protocol may also include other types of communication protocols, which are not limited in this application.
  • the BMC if the BMC communicates with the BIOS by means of synchronous communication, the BMC receives a reply packet of the third data packet sent by the BIOS. If the BMC communicates with the BIOS in asynchronous communication mode, the BMC does not receive the reply packet of the third data packet sent by the BIOS.
  • the BIOS acquires a third data packet from the second shared interaction area by using a PCIE channel.
  • the BIOS may acquire a third data packet from the second shared interaction area every time an operational phase is elapsed. For example, the BIOS may detect whether the second shared interaction area has a BMC copy data packet when each operation phase is completed; or the BIOS may detect whether the second shared interaction area has a BMC copy data packet at the beginning of each operation phase. If the BIOS detects that the second shared interaction area has a BMC copied data packet, such as a third data packet, the BIOS can read the third data packet. In this way, the BMC can send the data required in each stage of the BIOS to the second shared interaction area through the third data packet before the BIOS is started, and the BIOS can obtain the required number from the second shared interaction area in each operation phase.
  • the BIOS may acquire a third data packet from the second shared interaction area every time an operational phase is elapsed. For example, the BIOS may detect whether the second shared interaction area has a BMC copy data packet when each operation phase is completed; or the BIOS may detect whether the second shared interaction area has a B
  • the BMC can only notify the BIOS through a limited GPIO, and the limitation of the number of GPIO pins reduces the flexibility of the BMC active notification, which may cause the BIOS to fail to obtain the required data packets in time.
  • the embodiment of the present application can solve the problem that the BIOS cannot obtain the required data packet in time.
  • the BIOS determines, according to the mapping relationship between the second application and the first application, that the first application obtains the third data packet.
  • the EDMA control module determines that the type identifier carried in the third data packet is the same as the type identifier of the first application, so that the third data packet can be sent according to the mapping relationship between the second application and the first application.
  • the first application so that the first application processes the third data packet.
  • this application is not limited to this.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the third data packet of the second application to the first application. Since the size of the first shared interaction area and the second shared interaction area in the virtual PCIE device is configurable, for example, it may be 32M, 64M, 128M, etc., so that more and larger data packets can be transmitted in a short time. Therefore, the data interaction efficiency between the BIOS and the BMC can be improved.
  • An embodiment of the present application provides a data interaction method. As shown in FIG. 6 , the second application sends a fourth data packet and a third data packet to the first application as an example, including:
  • the first application registers a type identifier on the BIOS, and the second application registers a type identifier on the BMC.
  • step 201 For the specific process, refer to step 201.
  • the BIOS accesses a configuration space of the virtual PCIE device.
  • step 202 For the specific process, reference may be made to step 202.
  • the BMC obtains a sending address, a receiving address, and a length of the fourth data packet of the fourth data packet.
  • the fourth data packet may be a DMA data packet to be sent by the second application, and the sending address of the fourth data packet is the physical address of the memory unit used for storing the DMA data packet on the BMC side, and the receiving address of the fourth data packet is the BIOS.
  • the BMC generates a third data packet according to the fourth data packet, and copies the third data packet to the second shared interaction area.
  • the BMC can generate a third data packet according to the fourth data packet, and notify the BIOS to initiate the DMA transmission through the third data packet.
  • the third data packet includes a type identifier of the second application, a sending address of the fourth data packet, a receiving address, and a length of the fourth data packet.
  • the BIOS acquires a third data packet from the second shared interaction area by using a PCIE channel.
  • the BMC can copy the third data packet to the second shared interaction area, and the BIOS can acquire the third data packet from the second shared interaction area.
  • the BIOS may obtain the sending address, the receiving address, and the length of the fourth data packet of the fourth data packet, and write the sending address, the receiving address, and the length of the fourth data packet of the fourth data packet.
  • the BIOS may write the sending address of the fourth data packet to the sending address register of the DMA data packet; write the receiving address of the fourth data packet to the receiving address register of the DMA data packet; and write the length of the fourth data packet The packet length register of the DMA packet; and sets the value of whether to enable the DMA transfer register to initiate a DMA transfer.
  • the virtual PCIE device acquires a fourth data packet from a memory unit indicated by a sending address of the fourth data packet, and sends the fourth data packet to a memory unit indicated by the receiving address of the fourth data packet.
  • the fourth data packet can be obtained from the memory unit indicated by the sending address of the fourth data packet, and the fourth data packet is sent.
  • the memory unit indicated by the receiving address of the fourth data packet That is, the DMA controller acquires the fourth data packet from the memory unit on the BMC side, and sends the fourth data packet to the memory unit on the BIOS side.
  • the BIOS acquires a fourth data packet.
  • the BIOS can be notified by a preset identifier to obtain the fourth data packet from the memory unit on the BIOS side.
  • the fourth data packet can be split into multiple data packets for transmission.
  • the transmission mode of each data packet can refer to the transmission mode of the third data packet in the embodiment shown in FIG. 5.
  • the BIOS performs data interaction based on the LPC and the BMC, and the maximum transmission value of the LPC is only 16 MB/s, resulting in low efficiency of data packet transmission.
  • the BIOS and the BMC can perform data interaction through the virtual PCIE device, for example, transmitting the DMA data packet of the second application to the first application. Since the virtual PCIE device can perform DMA transmission, it can transmit DMA data packets with a large amount of data in a short time, thereby improving the data interaction efficiency between the BIOS and the BMC.
  • the solution provided by the embodiment of the present application is mainly introduced from the perspective of a computing device.
  • the computing device includes corresponding hardware structures and/or software modules for performing the respective functions in order to implement the above functions.
  • the present application can be implemented in hardware or a combination of hardware and software in combination with the algorithm steps described in the embodiments disclosed herein. Whether a function is implemented in hardware or software-driven hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.
  • the embodiment of the present application may perform the division of the function module on the computing device according to the foregoing method example.
  • each function module may be divided according to each function, or two or more functions may be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present application is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • FIG. 7 shows a possible structural diagram of the computing device 7 involved in the foregoing embodiment, where the computing device includes: a BIOS 701, a BMC 702, and a virtual PCIE device. 703.
  • the BIOS 701 is configured to support the computing device to perform the processes 201-203 of FIG. 2, the processes 401, 402, 403, 404, and 406 of FIG. 4, the processes 501, 502, 504, and 505 of FIG. 5, the process of FIG. 601, 602, 605, and 607.
  • the BMC 702 is used to support the computing device to perform the processes 201, 204, and 205 of FIG. 2, processes 401, 407, and 408 of FIG. 4, processes 501 and 503 of FIG. 5, and processes 601, 603, and 604 of FIG.
  • the virtual PCIE device 703 is used to support the computing device to perform the process 405 of FIG. 4, process 606 of FIG. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional descriptions of the corresponding functional modules, and details are not described herein again.
  • the computing device can be implemented by the computing device (or system) of FIG.
  • FIG. 8 is a schematic diagram of a computing device provided by an embodiment of the present application.
  • Computing device 800 includes at least one processor 801, a communication bus 802, a memory 803, and at least one communication interface 804.
  • the processor 801 can be a general purpose CPU, a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application.
  • ASIC application-specific integrated circuit
  • Communication bus 802 can include a path for communicating information between the components described above.
  • the communication interface 804 is used to communicate with other computing devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), and the like.
  • networks such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), and the like.
  • the memory 803 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type that can store information and instructions.
  • the dynamic storage device can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, and a disc storage device. (including compact discs, laser discs, compact discs, digital versatile discs, Blu-ray discs, etc.), disk storage media or other magnetic storage devices, or can be used to carry or store desired program code in the form of instructions or data structures and can be calculated Any other media accessed by the device, but is not limited to this.
  • the memory can exist independently and be connected to the processor via a bus. The memory can also be integrated with the processor.
  • the memory 803 is used to store application code, such as a BIOS, that executes the solution of the present application, and is controlled by the processor 801 for execution.
  • the processor 801 is configured to execute application code stored in the memory 803 to implement the functions in the method of the present patent.
  • the processor 801 may include one or more CPUs, such as CPU0 and CPU1 in FIG.
  • computing device 800 can include multiple processors, such as processor 801 and processor 807 in FIG. Each of these processors can be a single-CPU processor or a multi-core processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computing device program instructions).
  • computing device 800 can also include an output device 805 and an input device 806.
  • Output device 805 is in communication with processor 801 and can display information in a variety of ways.
  • the output device 805 can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. Wait.
  • Input device 806 is in communication with processor 801 and can accept user input in a variety of ways.
  • input device 806 can be a mouse, keyboard, touch screen device, sensing device, or monitored device, and the like.
  • the monitored device can include a BMC.
  • the computing device 800 described above can be a general purpose computing device or a dedicated computing device.
  • the computing device 800 can be a desktop computer, a portable computer, a network server, a personal digital assistant (PDA), a mobile phone, a tablet, a wireless terminal device, a communication device, an embedded device, or have FIG. A device of similar structure.
  • PDA personal digital assistant
  • the embodiment of the present application does not limit the type of computing device 800.
  • the steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware or may be implemented by a processor executing software instructions.
  • the software instructions may be comprised of corresponding software modules that may be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable hard disk, read-only optical disk, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in a core network interface device.
  • the processor and the storage medium may also exist as discrete components in the core network interface device.
  • the functions described herein can be implemented in hardware, software, firmware, or any combination thereof.
  • the functions may be stored in a computing device readable medium or transmitted as one or more instructions or code on a computing device readable medium.
  • Computing device readable media includes computing device storage media and communication media including any medium that facilitates transfer of a computing device program from one location to another.
  • a storage medium may be any available media that can be accessed by a general purpose or special purpose computing device.

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Abstract

本申请实施例提供一种数据交互方法和计算设备，涉及IT领域，能够提高BIOS与BMC的数据交互效率。其方法为：BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域；BMC通过内存通道从第一共享交互区域获取第一数据包；BMC根据第一应用与第二应用的映射关系确定指示第二应用获取第一数据包。其中，BMC中包括虚拟的PCIE设备，虚拟的PCIE设备中包括I/O内存空间，I/O内存空间包括第一共享交互区域。本申请实施例应用于包含BIOS和BMC的数据传输场景。

Description

一种数据交互方法和计算设备 技术领域
本申请涉及信息技术(Information Technology，IT)领域，尤其涉及一种数据交互方法和计算设备。
背景技术
随着IT技术的加速发展，对服务器处理数据的效率和可靠性的要求越来越高，从而对服务器中的基本输入输出系统(Basic Input Output System，BIOS)和基板管理控制器(Baseboard Management Controller，BMC)间的数据交互的效率和可靠性要求也越来越高。其中，BIOS是一组固化到服务器中的只读存储器(Read-Only Memory，ROM)芯片上的程序，其保存着计算机最重要的基本输入输出的程序、开机后自检程序和系统自启动程序等。BMC通常被包含在模板或者被监控的设备的主电路板里。BMC可以利用传感器监控计算机、网络服务器、或其他硬件驱动设备的状态，并且通过独立的连接线路和系统管理员进行通信。BIOS在启动过程中可以通过基于硬件低速总线(Low Pin Count，LPC)和块传输(Block Transfer，BT)协议的智能平台管理接口(Intelligent Platform Management Interface，IPMI)与BMC进行数据交互。但是，LPC最大传输值仅有16兆比特每秒(MB/s)，一般应用于鼠标，键盘等一些低速外设，对于BIOS和BMC之间进行的大数据传输，例如系统管理BIOS(System Management BIOS，SMBIOS)数据，需对数据包进行拆包传输。
举例来说，电源接口为8针以上的服务器的SMBIOS数据通常可以达到110千字节(Kb)左右，此时需要将数据包拆成400多个IPMI消息才能传完，传输时间长，数据传输效率低。而且，由于IPMI是服务器/客户端(Client/Server，CS)架构，BMC作为服务端，BIOS作为客户端，不支持BMC主动发送消息给BIOS。当前BMC主动通知BIOS机制主要是采用通用输入/输出(General Purpose Input Output，GPIO)触发，由于GPIO管脚个数的限制，降低了BMC主动通知的灵活性。另外，BMC重启过程中无法接收BIOS上报的事件，会导致数据丢失。且BT只支持同步传输，不支持异步传输。
发明内容
本申请实施例提供一种数据交互方法和计算设备，能够提高BIOS与BMC的数据交互效率。
第一方面，本申请实施例提供一种数据交互方法，应用于包含BIOS和BMC的数据传输场景，BMC中包括虚拟的外部设备互连总线(PCI(Peripheral Component Interconnect)Express，PCIE)设备，虚拟的PCIE设备中包括输入/输出(input/output，I/O)内存空间，I/O内存空间包括第一共享交互区域；数据交互方法包括：BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域；BMC通过内存通道从第一共享交互区域获取第一数据包；BMC根据第一应用与第二应用的映射关系确定指示第二应用获取第一数据包。由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请 实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第一应用的第一数据包传输给第二应用。由于虚拟的PCIE设备中的第一共享交互区域的大小是可设置的，例如可以为32M、64M、128M等，能够在短时间内传输更多、更大的数据包，从而能够提高BIOS与BMC的数据交互效率。
在一种可能的设计中，BMC通过内存通道从第一共享交互区域获取第一数据包包括：BMC在预设时间内从第一共享交互区域获取第一数据包。这样一来，BMC可以在预设时间内从第一共享交互区域获取第一数据包，能够解决BMC重启期间，BIOS拷贝数据包到第一共享交互区域时，BMC无法接收BIOS发送的数据包导致数据包丢失的问题。
在一种可能的设计中，BMC根据中断通知从第一共享交互区域获取第一数据包。当然，本申请不限于此。
在一种可能的设计中，BIOS通过PCIE通道将第一数据包拷贝到第一共享交互区域之前，该方法还包括：BIOS通过中央处理器(Central Processing Unit，CPU)与虚拟的PCIE设备之间的PCIE通道访问虚拟的PCIE设备的配置空间；BIOS通过访问虚拟的PCIE设备的配置空间确定第一共享交互区域的物理地址；BIOS通过第一共享交互区域的物理地址确定第一共享交互区域。可以理解的是，CPU可以与至少一个PCIE设备分别建立串行链路，对于每个PCIE设备来说，该PCIE设备与CPU之间的串行链路认为是一个PCIE通道。CPU上的PCIE管理模块可以控制PCIE通道，例如PCIE管理模块可以控制CPU与虚拟的PCIE设备的PCIE通道。由此BIOS可以通过CPU上的PCIE管理模块来访问虚拟的PCIE设备的配置空间，即BIOS可以通过PCIE通道访问虚拟的PCIE设备的配置空间。
在一种可能的设计中，BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域之前，该方法还包括：BIOS确定第一共享交互区域是否超出最大容量限制；若BIOS确定第一共享交互区域未超出最大容量限制，BIOS将第一数据包拷贝到第一共享交互区域。若BIOS确定第一共享交互区域超出最大容量限制，BIOS可以等待第一共享交互区域空闲时，再将第一数据包拷贝到第一共享交互区域。
在一种可能的设计中，BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域之前，该方法还包括：BIOS获取第二数据包的发送地址、接收地址以及第二数据包的长度，第二数据包的发送地址用于指示BIOS的内存单元，第二数据包的接收地址用于指示BMC的内存单元；虚拟的PCIE设备根据第二数据包的发送地址从BIOS的内存单元获取第二数据包，并根据第二数据包的接收地址将第二数据包发送至BMC的内存单元。由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第一应用的第二数据包传输给第二应用，第二数据包可以是直接内存存取(Direct Memory Access，DMA)数据包。由于虚拟的PCIE设备可以进行DMA传输，能够在短时间内传输数据量很大的DMA数据包，从而能够提高BIOS与BMC的数据交互效率。
在一种可能的设计中，第一数据包包括第二数据包的发送地址、接收地址以及第二数据包的长度。由此，当BMC解析第一数据包后，确定其中携带第二数据包的发送地址、 接收地址以及第二数据包的长度等信息时，BMC可以确定第二数据包已传输完毕，从而可以从BMC侧的内存单元获取第二数据包。可选的，第一数据包可以不携带第二数据包的发送地址和接收地址。
在一种可能的设计中，I/O内存空间还包括第二共享交互区域，该方法还包括：BMC通过内存通道将第二应用的第三数据包拷贝到第二共享交互区域；BIOS通过PCIE通道从第二共享交互区域获取第三数据包；BIOS根据第二应用与第一应用的映射关系确定指示第一应用获取第三数据包。由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第二应用的第三数据包传输给第一应用。由于虚拟的PCIE设备中的第二共享交互区域的大小是可设置的，例如可以为32M、64M、128M等，从而能够在短时间内传输更多、更大的数据包，从而能够提高BIOS与BMC的数据交互效率。
在一种可能的设计中，BMC通过内存通道将第三数据包拷贝到第二共享交互区域之前，该方法还包括：BMC确定第二共享交互区域是否超出最大容量限制；若BMC确定第二共享交互区域未超出最大容量限制，BMC将第三数据包拷贝到第二共享交互区域。若BMC确定第二共享交互区域超出最大容量限制，BMC可以等待第二共享交互区域空闲时，再将第三数据包拷贝到第二共享交互区域。
在一种可能的设计中，该方法还包括：BMC获取第四数据包的发送地址、接收地址以及第四数据包的长度，第四数据包的发送地址用于指示BMC的内存单元，第四数据包的接收地址用于指示BIOS的内存单元；虚拟的PCIE设备根据第四数据包的发送地址从BMC的内存单元获取第四数据包，并根据第四数据包的接收地址将第四数据包发送至BIOS的内存单元。由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第二应用的第四数据包传输给第一应用，第四数据包可以为DMA数据包。由于虚拟的PCIE设备可以进行DMA传输，能够在短时间内传输数据量很大的DMA数据包，从而能够提高BIOS与BMC的数据交互效率。
在一种可能的设计中，第三数据包包括第四数据包的发送地址、接收地址以及第四数据包的长度。BIOS对第三数据包进行解析后，可以获取第四数据包的发送地址、接收地址以及第四数据包的长度，并将第四数据包的发送地址、接收地址以及第四数据包的长度写入虚拟的PCIE设备的配置空间中的寄存器，并可以启动DMA传输。
在一种可能的设计中，该方法还包括：BIOS采用同步通信方式或异步通信方式与BMC通信；其中，同步通信方式用于指示BIOS接收BMC发送的第一数据包的回复报文以及BMC接收BIOS发送的第三数据包的回复报文，异步通信方式用于指示BIOS不接收BMC发送的第一数据包的回复报文以及BMC不接收BIOS发送的第三数据包的回复报文。由此，BIOS通过异步通信方式与BMC通信时，无需等待数据包的回复报文，在进行大量数据报文交互时，可以不受BMC重启的影响，且BMC重启后可以处理BIOS异步发送的数据包。
第二方面，提供一种计算设备，包括BIOS和BMC，BMC中包括虚拟的PCIE设备，虚拟的PCIE设备中包括输入/输出I/O内存空间，I/O内存空间包括第一共享交互区域；， BIOS用于：通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域；BMC用于：通过内存通道从第一共享交互区域获取第一数据包；BMC还用于：根据第一应用与第二应用的映射关系确定指示第二应用获取第一数据包。
在一种可能的设计中，BMC用于：在预设时间内从第一共享交互区域获取第一数据包；或根据中断通知从第一共享交互区域获取第一数据包。
在一种可能的设计中，BIOS还用于：通过中央处理器CPU与虚拟的PCIE设备之间的PCIE通道访问虚拟的PCIE设备的配置空间；通过访问虚拟的PCIE设备的配置空间确定第一共享交互区域的物理地址；通过第一共享交互区域的物理地址确定第一共享交互区域。
在一种可能的设计中，BIOS还用于：确定第一共享交互区域是否超出最大容量限制；若确定第一共享交互区域未超出最大容量限制，将第一数据包拷贝到第一共享交互区域。
在一种可能的设计中，BIOS还用于：获取第二数据包的发送地址、接收地址以及第二数据包的长度，第二数据包的发送地址用于指示BIOS的内存单元，第二数据包的接收地址用于指示BMC的内存单元；虚拟的PCIE设备用于：根据第二数据包的发送地址从BIOS的内存单元获取第二数据包，并根据第二数据包的接收地址将第二数据包发送至BMC的内存单元。
在一种可能的设计中，第一数据包包括第二数据包的发送地址、接收地址以及第二数据包的长度。
在一种可能的设计中，I/O内存空间还包括第二共享交互区域，BMC还用于：通过内存通道将第二应用的第三数据包拷贝到第二共享交互区域；BIOS还用于：通过PCIE通道从第二共享交互区域获取第三数据包；根据第二应用与第一应用的映射关系确定指示第一应用获取第三数据包。
在一种可能的设计中，BMC还用于：确定第二共享交互区域是否超出最大容量限制；若确定第二共享交互区域未超出最大容量限制，将第三数据包拷贝到第二共享交互区域。
在一种可能的设计中，BMC还用于：获取第四数据包的发送地址、接收地址以及第四数据包的长度，第四数据包的发送地址用于指示BMC的内存单元，第四数据包的接收地址用于指示BIOS的内存单元；虚拟的PCIE设备还用于：根据第四数据包的发送地址从BMC的内存单元获取第四数据包，并根据第四数据包的接收地址将第四数据包发送至BIOS的内存单元。
在一种可能的设计中，第三数据包包括第四数据包的发送地址、接收地址以及第四数据包的长度。
在一种可能的设计中，BIOS采用同步通信方式或异步通信方式与BMC通信；其中，同步通信方式用于指示BIOS接收BMC发送的第一数据包的回复报文以及BMC接收BIOS发送的第三数据包的回复报文，异步通信方式用于指示BIOS不接收BMC发送的第一数据包的回复报文以及BMC不接收BIOS发送的第三数据包的回复报文。
第二方面及其各种可能的实现方式的技术效果可以参见第一方面及其各种可能的实现方式的技术效果，此处不再赘述。
第三方面，本发明实施例提供了一种计算设备，该计算设备以芯片的产品形态存在， 该计算设备的结构中包括处理器和存储器，该存储器用于与处理器耦合，保存该计算设备必要的程序指令和数据，该处理器用于执行存储器中存储的程序指令，使得该计算设备执行上述方法中计算设备的功能。
第四方面，本发明实施例提供了一种计算设备，该计算设备可以实现上述方法中计算设备所执行的功能，所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个上述功能相应的模块。
在一种可能的设计中，该计算设备的结构中包括处理器和通信接口，该处理器被配置为支持该计算设备执行上述方法中相应的功能。该通信接口用于支持该计算设备与其他网元之间的通信。该计算设备还可以包括存储器，该存储器用于与处理器耦合，其保存该计算设备必要的程序指令和数据。
第五方面，本发明实施例提供一种计算设备可读存储介质，包括指令，当其在计算设备上运行时，使得计算设备执行第一方面提供的任意一种方法。
第六方面，本发明实施例提供了一种包含指令的程序产品，当其在计算设备上运行时，使得计算设备执行第一方面提供的任意一种方法。
由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第一应用的第一数据包传输给第二应用，或将第二应用的第三数据包传输给第一应用。由于虚拟的PCIE设备中的第一共享交互区域和第二共享交互区域的大小是可设置的，例如可以为32M、64M、128M等，能够在短时间内传输更多、更大的数据包，从而能够提高BIOS与BMC的数据交互效率。而且，本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第一应用的第二数据包传输给第二应用，或将第二应用的第四数据包传输给第一应用。其中，第二数据包或第四数据包可以为DMA数据包。由于虚拟的PCIE设备可以进行DMA传输，从而能够在短时间内传输数据量很大的DMA数据包，从而能够提高BIOS与BMC的数据交互效率。
附图说明
图1为本申请实施例提供的一种架构示意图；
图2为本申请实施例提供的一种数据交互方法的信号交互示意图；
图3为本申请实施例提供的一种BMC的数据包处理机制示意图；
图4为本申请实施例提供的一种数据交互方法的信号交互示意图；
图5为本申请实施例提供的一种数据交互方法的信号交互示意图；
图6为本申请实施例提供的一种数据交互方法的信号交互示意图；
图7为本申请实施例提供的一种计算设备的结构示意图；
图8为本申请实施例提供的一种计算设备的结构示意图。
具体实施方式
本申请实施例可以应用于BIOS和BMC的数据交互的场景中，包括小数据传输场景和大数据传输场景。小数据传输场景例如，BIOS接收BMC发送的系统启动项信息或柜 级硬分区服务器交互的信息等；大数据传输场景例如，BIOS向BMC发送系统SMBIOS数据等。本申请实施例还可以应用于其他数据交互的场景中，例如操作系统(Operating System，OS)和BMC的数据交互场景，本申请不做限定。
如图1所示，本申请的架构可以包括BIOS和BMC。BIOS中包括第一应用和增强型直接内存存取(Enhanced Direct Memory Access，EDMA)控制模块。BMC中包括第二应用、EDMA管理模块以及虚拟的PCIE设备。BIOS和BMC可以通过虚拟的PCIE设备进行数据交互。虚拟的PCIE设备中包括I/O内存空间、配置空间以及DMA控制器。I/O内存空间包括第一共享交互区域和第二共享交互区域，第一共享交互区域和第二共享交互区域的大小可在初始化时进行设置，例如可以为32M、64M、128M等。I/O内存空间还可以包括DMA标示区域(图1中未示出)。配置空间用于存储第一共享交互区域、第二共享交互区域和DMA标示区域的物理地址，还可以包括用于触发DMA传输的寄存器。DMA控制器用于根据触发DMA传输的寄存器的取值进行DMA传输。BIOS和BMC中还可以包括更多或更少的功能模块，本申请实施例不做限定。
需要说明的是，BIOS中可以包括多种类型的应用，BMC中也可以包括多种类型的应用，且BIOS中的应用与BMC中的应用是一一对应的。本申请实施例以BIOS包括第一应用，BMC包括第二应用为例进行说明，第一应用与第二应用对应。
BIOS中的EDMA控制模块用于，将BIOS中的第一应用发送的第一数据包复制到虚拟的PCIE设备的第一共享交互区域，或从虚拟的PCIE设备的第二共享交互区域获取第二应用发送的第三数据包。BMC中的EDMA管理模块用于，将BMC中的第二应用发送的第三数据包复制到虚拟的PCIE设备的第二共享交互区域，或从第一共享交互区域获取第一应用发送的第一数据包。EDMA控制模块还可以预设BIOS中，用于存储DMA数据包的内存单元的物理地址。在BIOS侧，DMA数据包的物理地址即第一应用的第二数据包的发送地址，或第二应用的第四数据包的接收地址。EDMA管理模块还可以预设BMC中，用于存储DMA数据包的内存单元的物理地址。在BMC侧，DMA数据包的物理地址即第二应用的第四数据包的发送地址，或第一应用的第二数据包的接收地址。其中，第一应用发送的第一数据包小于第一应用发送的第二数据包，第二应用发送的第三数据包小于第二应用发送的第四数据包。举例来说，第一应用发送的第一数据包可以包括部件健康事件等信息。第一应用发送的第二数据包可以为DMA数据包，该DMA数据包可以包括SMBIOS数据等。第二应用发送的第三数据包可以包括系统启动项信息或柜级硬分区服务器交互的信息等。第二应用发送的第四数据包可以为DMA数据包，该DMA数据包可以包括BIOS的设置信息等。
本申请实施例提供一种数据交互方法，以第一应用向第二应用发送第一数据包为例进行说明，如图2所示，包括：
201、第一应用在BIOS上注册类型标识，第二应用在BMC上注册类型标识。
如图1所示，第一应用可以在EDMA控制模块上注册第一应用的类型标识，第二应用可以在EDMA管理模块上注册第二应用的类型标识。第一应用的类型标识和第二应用的类型标识可以相同，以指示第一应用和第二应用具有映射关系，当然，本申请不限于此。
202、BIOS访问虚拟的PCIE设备的配置空间。
BIOS可以通过CPU上的PCIE管理模块访问虚拟的PCIE设备的配置空间，获取第一共享交互区域的物理地址、第二共享交互区域的物理地址等。
需要说明的是，CPU可以与至少一个PCIE设备分别建立串行链路，对于每个PCIE设备来说，该PCIE设备与CPU之间的串行链路认为是一个PCIE通道。CPU上的PCIE管理模块可以控制PCIE通道，例如PCIE管理模块可以控制CPU与虚拟的PCIE设备的PCIE通道。由此BIOS可以通过CPU上的PCIE管理模块来访问虚拟的PCIE设备的配置空间，即BIOS可以通过PCIE通道访问虚拟的PCIE设备的配置空间。
BIOS可以根据第一共享交互区域的物理地址以及第二共享交互区域的物理地址访问第一共享交互区域以及第二共享交互区域。访问包括读取相应区域的数据以及向相应区域写入数据。
203、BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域。
第一数据包包括第一应用的类型标识。
具体的，第一应用注册第一应用的类型标识后，EDMA控制模块可以将第一应用的类型标识添加到第一应用发送的第一数据包，并通过PCIE通道将该数据包拷贝到第一共享交互区域。
需要说明的是，第一数据包为至少一层业务协议封装的数据包，业务协议可以包括：传输控制协议(Transmission Control Protocol，TCP)/网际协议(Internet Protocol，IP)、互联网数据包交互协议(Internet work Packet Exchange，IPX)/序列分组交换协议(Sequenced Packet Exchange protocol，SPX)、网络基本输入输出系统用户扩展接口(NetBios Enhanced User Interface，NetBEUI)或自定义协议。业务协议还可以包括其他类型的通信协议，本申请不做限定。
在一种可能的设计中，EDMA控制模块将第一数据包拷贝到第一共享交互区域之前，可以确定第一共享交互区域是否超出最大容量限制；若第一共享交互区域未超出最大容量限制，EDMA控制模块可以将第一数据包拷贝到第一共享交互区域；若第一共享交互区域超出最大容量限制，EDMA控制模块可以通过触发相应的中断来通知EDMA管理模块对第一共享交互区域中的数据进行处理。可选的，EDMA控制模块可以每隔预设时间间隔确定第一共享交互区域是否超出最大容量。
在一种可能的设计中，若BIOS采用同步通信方式与BMC通信，BIOS可以接收BMC发送的第一数据包的回复报文。若BIOS采用异步通信方式与BMC通信，BIOS可以不接收BMC发送的第一数据包的回复报文。
另外，若本申请实施例应用在OS和BMC的数据交互场景中，则OS将第一数据包复制到第一共享交互区域之前，可以确定OS的预发送缓存区是否空闲，若确定OS的发送缓存区空闲，OS可以将第一数据包导入OS的预发送缓存区，以便将预发送缓存区中的数据包一并拷贝到第一共享交互区域。
204、BMC通过内存通道从第一共享交互区域获取第一数据包。
BMC可以包括系统内存、系统内存总线和控制芯片。系统内存通过系统内存总线接入控制芯片，形成内存通道。BMC的系统内存包括第一共享交互区域。
当BIOS在第一共享交互区域拷贝第一数据包完成时，可以发送中断通知，以便通知BMC获取第一数据包。BMC接收到中断通知后，可以通过内存通道从第一共享交互区 域获取第一数据包。
在一种可能的设计中，BMC可以在预设时间内从第一共享交互区域获取第一数据包。例如，BMC可以每经过一个预设时间间隔就检测第一共享交互区域是否有BIOS拷贝的数据包；或BMC可以在预设时刻检测第一共享交互区域是否有BIOS拷贝的数据包。若BMC在预设时间内检测到第一共享交互区域有BIOS拷贝的数据包，例如第一数据包，BMC可以读取第一数据包。这样一来，BMC可以在预设时间内从第一共享交互区域获取第一数据包，能够解决BMC重启期间，BIOS拷贝数据包到第一共享交互区域时，BMC无法接收BIOS发送的数据包导致数据包丢失的问题。
205、BMC根据第一应用与第二应用的映射关系确定指示第二应用获取第一数据包。
需要说明的是，第一应用的类型标识虽然是第一应用向BIOS注册的，但是BIOS和BMC在设计阶段会协商应用注册的类型标识所代表的含义，因此BMC可以根据第一应用的类型标识确定第一数据包对应第二应用，进而可以根据第一应用与第二应用的映射关系确定指示第二应用获取第一数据包。
示例性的，如图3所示，EDMA管理模块根据第一应用的类型标识确定第一数据包对应第二应用时，可以将第一数据包拷贝到第二应用对应的内存区域，第二应用的检测模块(poll)可以在预设时间内检测第二应用对应的内存区域是否有数据包，若poll检测到第一数据包，可以将该数据包发送到第二应用的处理缓存中，并通知第二应用的处理模块对第一数据包进行处理。
由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第一应用的数据包传输给第二应用。由于虚拟的PCIE设备中的第一共享交互区域和第二共享交互区域的大小是可设置的，例如可以为32M、64M、128M等，能够在短时间内传输更多、更大的数据包，从而能够提高BIOS与BMC的数据交互效率。
本申请实施例提供一种数据交互方法，以第一应用向第二应用发送第二数据包和第一数据包为例进行说明，如图4所示，包括：
401、第一应用在BIOS上注册类型标识，第二应用在BMC上注册类型标识。
具体过程可以参考步骤201。
402、BIOS访问虚拟的PCIE设备的配置空间。
具体过程可以参考步骤202。
需要说明的是，BIOS还可以通过访问虚拟的PCIE设备的配置空间确定DMA标示区域的物理地址，并可以根据DMA标示区域的物理地址访问DMA标示区域。
403、BIOS获取第二数据包的发送地址、接收地址以及第二数据包的长度。
BIOS可以通过访问DMA标示区域，从而获取第二数据包的发送地址、接收地址以及第二数据包的长度。
其中，第二数据包可以为第一应用待发送的DMA数据包，第二数据包的发送地址用于指示BIOS的内存单元，第二数据包的接收地址用于指示BMC的内存单元。即第二数据包的发送地址为BIOS侧用于存储DMA数据包的内存单元的物理地址，第二数据包的接收地址为BMC侧用于存储DMA数据包的内存单元的物理地址。
404、BIOS将第二数据包的发送地址、接收地址以及第二数据包的长度写入虚拟的PCIE设备的配置空间中的寄存器。
可以理解的是，虚拟的PCIE设备的配置空间可以包括用于触发DMA传输的寄存器，寄存器可以包括DMA数据包的发送地址寄存器、DMA数据包的接收地址寄存器、DMA数据包的数据包长度寄存器以及是否启动DMA传输寄存器。
具体的，BIOS可以将第二数据包的发送地址写入DMA数据包的发送地址寄存器；将第二数据包的接收地址写入DMA数据包的接收地址寄存器；将第二数据包的长度写入DMA数据包的数据包长度寄存器；并将是否启动DMA传输寄存器的值置1，以启动DMA传输。
405、虚拟的PCIE设备从第二数据包的发送地址指示的内存单元获取第二数据包，并将第二数据包发送至第二数据包的接收地址指示的内存单元。
具体的，虚拟的PCIE设备中的DMA控制器确定是否启动DMA传输寄存器的值置1时，可以从第二数据包的发送地址指示的内存单元获取第二数据包，并将第二数据包发送至第二数据包的接收地址指示的内存单元。即DMA控制器从BIOS侧用于存储DMA数据包的内存单元获取第二数据包，并将第二数据包发送至BMC侧用于存储DMA数据包的内存单元。
虚拟的PCIE设备将第二数据包发送至BMC侧的内存单元完成时，可以通过中断通知或预设的标识向BIOS通知DMA传输结束。而后，BIOS可以根据第二数据包生成第一数据包，第一数据包用于通知BMC，第二数据包已经传输至BMC侧的DMA数据包的物理地址以及该第二数据包的相关参数。具体的，第一数据包可以包括第一应用的类型标识和第二数据包的长度(即第二数据包的大小)。
406、BIOS将第一数据包拷贝到第一共享交互区域。
具体过程可以参考步骤203。
407、BMC从第一共享交互区域获取第一数据包。
具体过程可以参考步骤204。
408、BMC根据第一数据包确定第二数据包，并从BMC侧的内存单元获取第二数据包。
当BMC解析第一数据包后，确定其中携带第二数据包的发送地址、接收地址以及第二数据包的长度等信息时，BMC可以确定第二数据包已传输完毕，从而EDMA管理模块可以从BMC侧的内存单元获取第二数据包。可选的，第一数据包可以不携带第二数据包的发送地址和接收地址。
在一种可能的设计中，可以将第二数据包拆分为多个数据包来传输，每个数据包的传输方式可以参考图2所示实施例中的第一数据包的传输方式。
由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第一应用的DMA数据包传输给第二应用。由于虚拟的PCIE设备可以进行DMA传输，从而能够在短时间内传输数据量很大的DMA数据包，从而能够提高BIOS与BMC的数据交互效率。
本申请实施例提供一种数据交互方法，如图5所示，以第二应用向第一应用发送第 三数据包为例进行说明，包括：
501、第一应用在BIOS上注册类型标识，第二应用在BMC上注册类型标识。
具体过程可以参考步骤201。
502、BIOS访问虚拟的PCIE设备的配置空间。
具体过程可以参考步骤202。
503、BMC将第三数据包拷贝到第二共享交互区域。
第三数据包包括第二应用的类型标识。
具体的，第二应用注册第二应用的类型标识后，EDMA管理模块可以将第二应用的类型标识添加到第二应用发送的第三数据包，并将该数据包拷贝到第二共享交互区域。
需要说明的是，第三数据包为至少一层业务协议封装的数据包，业务协议可以包括以下协议：TCP/IP、IPX/SPX协议、NetBEUI协议以及自定义协议。业务协议还可以包括其他类型的通信协议，本申请不做限定。
在一种可能的设计中，若BMC采用同步通信方式与BIOS通信，BMC接收BIOS发送的第三数据包的回复报文。若BMC采用异步通信方式与BIOS通信，BMC不接收BIOS发送的第三数据包的回复报文。
504、BIOS通过PCIE通道从第二共享交互区域获取第三数据包。
在一种可能的设计中，BIOS可以每经过一个运行阶段就从第二共享交互区域获取第三数据包。例如，BIOS可以在每个运行阶段完成时检测第二共享交互区域是否有BMC拷贝的数据包；或BIOS可以在每个运行阶段开始时检测第二共享交互区域是否有BMC拷贝的数据包。若BIOS检测到第二共享交互区域有BMC拷贝的数据包，例如第三数据包，BIOS可以读取第三数据包。这样一来，BMC在BIOS启动前就可以将BIOS各个阶段需要的数据通过第三数据包发送到第二共享交互区域内，BIOS可以在每个运行阶段从第二共享交互区域获取所需的第三数据包，相比现有技术，BMC只能通过有限的GPIO通知BIOS，而GPIO管脚个数的限制，降低了BMC主动通知的灵活性，可能导致BIOS不能及时获取所需的数据包。本申请实施例能够解决BIOS不能及时获取所需的数据包的问题。
505、BIOS根据第二应用与第一应用的映射关系确定指示第一应用获取第三数据包。
在一种可能的设计中，EDMA控制模块确定第三数据包中携带的类型标识和第一应用的类型标识相同，从而可以根据第二应用与第一应用的映射关系将第三数据包发送给第一应用，以便第一应用对第三数据包进行处理。当然，本申请不限于此。
由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第二应用的第三数据包传输给第一应用。由于虚拟的PCIE设备中的第一共享交互区域和第二共享交互区域的大小是可设置的，例如可以为32M、64M、128M等，从而能够在短时间内传输更多、更大的数据包，从而能够提高BIOS与BMC的数据交互效率。
本申请实施例提供一种数据交互方法，如图6所示，以第二应用向第一应用发送第四数据包和第三数据包为例进行说明，包括：
601、第一应用在BIOS上注册类型标识，第二应用在BMC上注册类型标识。
具体过程可以参考步骤201。
602、BIOS访问虚拟的PCIE设备的配置空间。
具体过程可以参考步骤202。
603、BMC获取第四数据包的发送地址、接收地址以及第四数据包的长度。
其中，第四数据包可以为第二应用待发送的DMA数据包，第四数据包的发送地址即BMC侧用于存储DMA数据包的内存单元的物理地址，第四数据包的接收地址即BIOS侧用于存储DMA数据包的内存单元的物理地址。
604、BMC根据第四数据包生成第三数据包，并将第三数据包拷贝到第二共享交互区域。
需要说明的是，在发送第四数据包时，即启动DMA传输时，需要将第四数据包的相关内容写入虚拟的PCIE设备中的寄存器。由于BMC无法对虚拟的PCIE设备中的寄存器进行读写操作，因此，BMC可以根据第四数据包生成第三数据包，通过第三数据包通知BIOS启动DMA传输。其中，第三数据包包括第二应用的类型标识、第四数据包的发送地址、接收地址以及第四数据包的长度等内容。
605、BIOS通过PCIE通道从第二共享交互区域获取第三数据包。
可以理解的是，BMC可以将第三数据包复制到第二共享交互区域，BIOS可以从第二共享交互区域获取第三数据包。
BIOS对第三数据包进行解析后，可以获取第四数据包的发送地址、接收地址以及第四数据包的长度，并将第四数据包的发送地址、接收地址以及第四数据包的长度写入虚拟的PCIE设备的配置空间中的寄存器。
具体的，BIOS可以将第四数据包的发送地址写入DMA数据包的发送地址寄存器；将第四数据包的接收地址写入DMA数据包的接收地址寄存器；将第四数据包的长度写入DMA数据包的数据包长度寄存器；并将是否启动DMA传输寄存器的值置1，以启动DMA传输。
606、虚拟的PCIE设备从第四数据包的发送地址指示的内存单元获取第四数据包，并将第四数据包发送至第四数据包的接收地址指示的内存单元。
具体的，虚拟的PCIE设备中的DMA控制器确定是否启动DMA传输寄存器的值置1时，可以从第四数据包的发送地址指示的内存单元获取第四数据包，并将第四数据包发送至第四数据包的接收地址指示的内存单元。即DMA控制器从BMC侧的内存单元获取第四数据包，并将第四数据包发送至BIOS侧的内存单元。
607、BIOS获取第四数据包。
DMA传输完成时，可以通过预设的标识通知BIOS，以便从BIOS侧的内存单元获取第四数据包。
在一种可能的设计中，可以将第四数据包拆分为多个数据包来传输，每个数据包的传输方式可以参考图5所示实施例中的第三数据包的传输方式。
由此，相比现有技术，BIOS基于LPC与BMC进行数据交互，而LPC最大传输值仅有16MB/s，导致数据包传输效率低。本申请实施例中，BIOS和BMC可以通过虚拟的PCIE设备进行数据交互，例如将第二应用的DMA数据包传输给第一应用。由于虚拟的PCIE设备可以进行DMA传输，从而能够在短时间内传输数据量很大的DMA数据包， 从而能够提高BIOS与BMC的数据交互效率。
上述主要从计算设备的角度对本申请实施例提供的方案进行了介绍。可以理解的是，计算设备为了实现上述功能，其包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的算法步骤，本申请能够以硬件或硬件和软件的结合形式来实现。某个功能究竟以硬件还是软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对计算设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图7示出了上述实施例中所涉及的计算设备7的一种可能的结构示意图，计算设备包括：BIOS 701、BMC 702和虚拟的PCIE设备703。BIOS 701用于支持计算设备执行图2中的过程201-203，图4中的过程401、402、403、404和406，图5中的过程501、502、504和505，图6中的过程601、602、605和607。BMC 702用于支持计算设备执行图2中的过程201、204和205，图4中的过程401、407和408，图5中的过程501和503，图6中的过程601、603和604。虚拟的PCIE设备703用于支持计算设备执行图4中的过程405，图6中的过程606。其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在一种可能的设计中，计算设备可以通过图8中的计算设备(或系统)来实现。
图8所示为本申请实施例提供的计算设备示意图。计算设备800包括至少一个处理器801，通信总线802，存储器803以及至少一个通信接口804。
处理器801可以是一个通用CPU，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路。
通信总线802可包括一通路，在上述组件之间传送信息。
通信接口804，计算设备用于与其他计算设备或通信网络通信，如以太网，无线接入网(radio access network，RAN)，无线局域网(wireless local area networks，WLAN)等。
存储器803可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算设备存取的任何其他介质，但不限于此。存储器可以是独立存在，通过总线与处理器相连接。存储器也可以和处理器集成在一起。
其中，存储器803用于存储执行本申请方案的应用程序代码，例如BIOS，并由处理器801来控制执行。处理器801用于执行存储器803中存储的应用程序代码，从而实现本专利方法中的功能。
在具体实现中，作为一种实施例，处理器801可以包括一个或多个CPU，例如图8中的CPU0和CPU1。
在具体实现中，作为一种实施例，计算设备800可以包括多个处理器，例如图8中的处理器801和处理器807。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算设备程序指令)的处理核。
在具体实现中，作为一种实施例，计算设备800还可以包括输出设备805和输入设备806。输出设备805和处理器801通信，可以以多种方式来显示信息。例如，输出设备805可以是液晶显示器(liquid crystal display，LCD),发光二级管(light emitting diode，LED)显示设备，阴极射线管(cathode ray tube，CRT)显示设备，或投影仪(projector)等。输入设备806和处理器801通信，可以以多种方式接受用户的输入。例如，输入设备806可以是鼠标、键盘、触摸屏设备、传感设备或被监控的设备等。其中，被监控的设备里可以包括BMC。
上述的计算设备800可以是一个通用计算设备或者是一个专用计算设备。在具体实现中，计算设备800可以是台式机、便携式电脑、网络服务器、掌上电脑(personal digital assistant，PDA)、移动手机、平板电脑、无线终端设备、通信设备、嵌入式设备或有图8中类似结构的设备。本申请实施例不限定计算设备800的类型。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于RAM、闪存、ROM、EPROM、EEPROM、寄存器、硬盘、移动硬盘、只读光盘或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算设备可读介质中或者作为计算设备可读介质上的一个或多个指令或代码进行传输。计算设备可读介质包括计算设备存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算设备程序的任何介质。存储介质可以是通用或专用计算设备能够存取的任何可用介质。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (17)

  1. 一种数据交互方法，应用于包含基本输入输出系统BIOS和基板管理控制器BMC的数据传输场景，所述BMC中包括虚拟的外部设备互连总线PCIE设备，所述虚拟的PCIE设备中包括输入/输出I/O内存空间，所述I/O内存空间包括第一共享交互区域；其特征在于，所述数据交互方法包括：
    所述BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域；
    所述BMC通过内存通道从所述第一共享交互区域获取所述第一数据包；
    所述BMC根据所述第一应用与第二应用的映射关系确定指示所述第二应用获取所述第一数据包。
  2. 根据权利要求1所述的方法，其特征在于，所述BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域之前，所述方法还包括：
    所述BIOS通过中央处理器CPU与所述虚拟的PCIE设备之间的PCIE通道访问所述虚拟的PCIE设备的配置空间；
    所述BIOS通过访问所述虚拟的PCIE设备的配置空间确定所述第一共享交互区域的物理地址；
    所述BIOS通过所述第一共享交互区域的物理地址确定所述第一共享交互区域。
  3. 根据权利要求1或2所述的方法，其特征在于，所述BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域之前，所述方法还包括：
    所述BIOS确定所述第一共享交互区域是否超出最大容量限制；
    若所述BIOS确定所述第一共享交互区域未超出最大容量限制，所述BIOS将所述第一数据包拷贝到第一共享交互区域。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述BIOS通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域之前，所述方法还包括：
    所述BIOS获取第二数据包的发送地址、接收地址以及所述第二数据包的长度，所述第二数据包的发送地址用于指示所述BIOS的内存单元，所述第二数据包的接收地址用于指示所述BMC的内存单元；
    所述虚拟的PCIE设备根据所述第二数据包的发送地址从所述BIOS的内存单元获取所述第二数据包，并根据所述第二数据包的接收地址将所述第二数据包发送至所述BMC的内存单元。
  5. 根据权利要求1-4任一项所述的方法，所述I/O内存空间还包括第二共享交互区域，其特征在于，所述方法还包括：
    所述BMC通过所述内存通道将所述第二应用的第三数据包拷贝到所述第二共享交互区域；
    所述BIOS通过所述PCIE通道从所述第二共享交互区域获取所述第三数据包；
    所述BIOS根据所述第二应用与所述第一应用的映射关系确定指示所述第一应用获取所述第三数据包。
  6. 根据权利要求5所述的方法，其特征在于，所述BMC通过所述内存通道将所述第二应用的第三数据包拷贝到所述第二共享交互区域之前，所述方法还包括：
    所述BMC确定所述第二共享交互区域是否超出最大容量限制；
    若所述BMC确定所述第二共享交互区域未超出最大容量限制，所述BMC将所述第三数据包拷贝到第二共享交互区域。
  7. 根据权利要求5或6所述的方法，其特征在于，所述方法还包括：
    所述BMC获取第四数据包的发送地址、接收地址以及所述第四数据包的长度，所述第四数据包的发送地址用于指示所述BMC的内存单元，所述第四数据包的接收地址用于指示所述BIOS的内存单元；
    所述虚拟的PCIE设备根据所述第四数据包的发送地址从所述BMC的内存单元获取所述第四数据包，并根据所述第四数据包的接收地址将所述第四数据包发送至所述BIOS的内存单元。
  8. 根据权利要求5-7任一项所述的方法，其特征在于，所述方法还包括：
    所述BIOS采用同步通信方式或异步通信方式与所述BMC通信；
    其中，所述同步通信方式用于指示所述BIOS接收所述BMC发送的所述第一数据包的回复报文以及所述BMC接收所述BIOS发送的所述第三数据包的回复报文，所述异步通信方式用于指示所述BIOS不接收所述BMC发送的所述第一数据包的回复报文以及所述BMC不接收所述BIOS发送的所述第三数据包的回复报文。
  9. 一种计算设备，包括基本输入输出系统BIOS和基板管理控制器BMC，所述BMC中包括虚拟的外部设备互连总线PCIE设备，所述虚拟的PCIE设备中包括输入/输出I/O内存空间，所述I/O内存空间包括第一共享交互区域；其特征在于，所述BIOS用于：
    通过PCIE通道将第一应用的第一数据包拷贝到第一共享交互区域；
    所述BMC用于：通过内存通道从所述第一共享交互区域获取所述第一数据包；
    所述BMC还用于：根据所述第一应用与第二应用的映射关系确定指示所述第二应用获取所述第一数据包。
  10. 根据权利要求9所述的计算设备，其特征在于，所述BIOS还用于：
    通过中央处理器CPU与所述虚拟的PCIE设备之间的PCIE通道访问所述虚拟的PCIE设备的配置空间；
    通过访问所述虚拟的PCIE设备的配置空间确定所述第一共享交互区域的物理地址；
    通过所述第一共享交互区域的物理地址确定所述第一共享交互区域。
  11. 根据权利要求9或10所述的计算设备，其特征在于，所述BIOS还用于：
    确定所述第一共享交互区域是否超出最大容量限制；
    若确定所述第一共享交互区域未超出最大容量限制，将所述第一数据包拷贝到第一共享交互区域。
  12. 根据权利要求9-11任一项所述的计算设备，其特征在于，所述BIOS还用于：
    获取第二数据包的发送地址、接收地址以及所述第二数据包的长度，所述第二数据包的发送地址用于指示所述BIOS的内存单元，所述第二数据包的接收地址用于指示所述BMC的内存单元；
    所述虚拟的PCIE设备用于：根据所述第二数据包的发送地址从所述BIOS的内存单元获取所述第二数据包，并根据所述第二数据包的接收地址将所述第二数据包发送至所述BMC的内存单元。
  13. 根据权利要求9-12任一项所述的计算设备，所述I/O内存空间还包括第二共享交互区域，其特征在于，所述BMC还用于：
    通过所述内存通道将所述第二应用的第三数据包拷贝到所述第二共享交互区域；
    所述BIOS还用于：通过所述PCIE通道从所述第二共享交互区域获取所述第三数据包；
    根据所述第二应用与所述第一应用的映射关系确定指示所述第一应用获取所述第三数据包。
  14. 根据权利要求13所述的计算设备，其特征在于，所述BMC还用于：
    确定所述第二共享交互区域是否超出最大容量限制；
    若确定所述第二共享交互区域未超出最大容量限制，将所述第三数据包拷贝到第二共享交互区域。
  15. 根据权利要求13或14所述的计算设备，其特征在于，所述BMC还用于：
    获取第四数据包的发送地址、接收地址以及所述第四数据包的长度，所述第四数据包的发送地址用于指示所述BMC的内存单元，所述第四数据包的接收地址用于指示所述BIOS的内存单元；
    所述虚拟的PCIE设备还用于：根据所述第四数据包的发送地址从所述BMC的内存单元获取所述第四数据包，并根据所述第四数据包的接收地址将所述第四数据包发送至所述BIOS的内存单元。
  16. 根据权利要求13-15任一项所述的计算设备，其特征在于，
    所述BIOS采用同步通信方式或异步通信方式与所述BMC通信；
    其中，所述同步通信方式用于指示所述BIOS接收所述BMC发送的所述第一数据包的回复报文以及所述BMC接收所述BIOS发送的所述第三数据包的回复报文，所述异步通信方式用于指示所述BIOS不接收所述BMC发送的所述第一数据包的回复报文以及所述BMC不接收所述BIOS发送的所述第三数据包的回复报文。
  17. 一种程序产品，所述程序产品包括指令；当所述指令被计算设备运行时，计算设备执行权利要求1至8任一项所述的数据交互方法。
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