WO2019128445A1 - 一种温度传感器及芯片 - Google Patents

一种温度传感器及芯片 Download PDF

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Publication number
WO2019128445A1
WO2019128445A1 PCT/CN2018/112370 CN2018112370W WO2019128445A1 WO 2019128445 A1 WO2019128445 A1 WO 2019128445A1 CN 2018112370 W CN2018112370 W CN 2018112370W WO 2019128445 A1 WO2019128445 A1 WO 2019128445A1
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level
temperature
pmos transistor
gate
circuit
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PCT/CN2018/112370
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English (en)
French (fr)
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魏威
周宙
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华为技术有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K13/00—Thermometers specially adapted for specific purposes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/01—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using semiconducting elements having PN junctions

Definitions

  • the present application relates to the field of electronic circuit design, and in particular, to a temperature sensor and a chip.
  • SoC system on chip
  • CPU central processing unit
  • GPU graphics processing unit
  • the SoC chip may fail and cause it to malfunction.
  • a temperature sensor is disposed on the SoC chip to measure the temperature inside the chip, so as to adjust the operating frequency of the subsystem in the SoC chip to ensure the performance of the SoC chip.
  • the temperature sensor provided inside the SoC chip is generally designed using an electronic device such as a bipolar junction transistor (BJT), an operational amplifier, and an analog-to-digital converter (ADC).
  • BJT bipolar junction transistor
  • ADC analog-to-digital converter
  • an analog level signal that changes with temperature and an analog level signal that does not change with temperature are generated inside the temperature sensor, and the two analog level signals are input to the ADC, and the ADC converts the level signal into temperature information.
  • the analog level signal used by the above temperature sensor needs to be powered by analog power supply.
  • the larger size electronic components such as BJT, operational amplifier and ADC used in the above temperature sensor cause the volume of the above temperature sensor. Larger.
  • the above temperature sensor can only be set to a small number of analog power supply chip positions, through the above temperature.
  • the temperature value measured by the sensor can only reflect the temperature of the circuit of the analog power supply part, but can not accurately reflect the overall temperature of the entire SoC chip, causing the temperature value measured by the temperature sensor to be inaccurate, affecting the regulation of the SoC chip, and reducing the The performance of the SoC chip.
  • the application provides a temperature sensor and a chip for improving the measurement accuracy of the temperature sensor and accurately measuring the chip temperature of the SoC chip.
  • a first aspect of the present application provides a temperature sensor comprising:
  • the first circuit When the temperature sensor is in the working state, the first circuit outputs the first level, and within the preset temperature value range, the first level does not change with the temperature change, that is, the change of the first level is not affected by the temperature.
  • the second circuit outputs a second level, and the level change of the second level has a correlation relationship with the temperature, that is, the level change of the second level is affected by the temperature, and the correlation relationship may be a positive correlation relationship, Can be a negative correlation;
  • the XOR gate circuit is used to input the first level and the second level, and the output level difference is used to determine the temperature value of the temperature sensor.
  • the present application has the following advantages:
  • the above temperature sensor includes an inverter and an exclusive OR gate. It can be known that the temperature sensor is a digital circuit, and the digital logic circuit has a small area and low power consumption, and is placed in a large number of SoC chips such as a CPU and a GPU, so that the overall SoC chip can be accurately measured. temperature.
  • the first circuit and the second circuit form a ring structure by the same number of inverters, and are connected to the XOR gate output level difference, which is equivalent to differential processing of the first level signal and the second level signal.
  • the differential processing ensures that the voltage at the same time of the measured temperature and the influence of the process are mostly offset, so that most of the difference reflects the temperature influence.
  • the first inverter includes:
  • a source of the first PMOS transistor and a drain of the second PMOS transistor are connected to a positive pole of the power source, and a gate of the first PMOS transistor and a gate of the second PMOS transistor are connected to the first node.
  • a drain of the first PMOS transistor and a source of the first NMOS transistor are connected to the second node, and the first node is connected to the second node;
  • a gate of the first NMOS transistor and a gate of the second NMOS transistor are connected to a third node, and a drain of the first NMOS transistor and a source of the second NMOS transistor are connected to a negative pole of a power source;
  • a drain of the second NMOS transistor is connected to a source of the third NMOS transistor, a source of the second PMOS transistor is connected to a drain of the third PMOS transistor, and a gate of the third PMOS transistor
  • the gate of the third NMOS transistor is connected to the fourth node, and the source of the third PMOS transistor and the drain of the third NMOS transistor are connected to the fifth node.
  • the small area of the MOS transistor and the low power consumption make the first circuit have a small overall area and low power consumption.
  • the first inverter further includes a voltage dividing circuit, and the voltage dividing circuit is configured to adjust the first
  • the bias voltage of the NMOS transistor is such that the level change of the first level is independent of temperature, and the bias voltage is the voltage difference between the gate and the source of the first NMOS transistor, and the bias voltage satisfies the following formula:
  • V GS V th (T0)+ ⁇ *(T-T0)+2*( ⁇ *T/km), where V th (T0) is the threshold voltage V th , ⁇ of the MOS tube corresponding to the temperature value T0 It is the temperature coefficient of the threshold voltage V th , T is the temperature variable, and km is the coefficient related to the MOS transistor process.
  • the bias voltage is positively correlated with the temperature.
  • the temperature positive correlation effect of the bias voltage and the temperature negative correlation effect of the mobility of the MOS tube cancel each other out, so that the first The current output from the NMOS transistor is not affected by temperature.
  • first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected to form a current mirror, and the current mirror maps the current of the first NMOS transistor to the fifth node output of the first inverter. .
  • the voltage dividing circuit includes:
  • a gate of the fourth PMOS transistor is connected to the third node, a drain of the fourth PMOS transistor is connected to the anode of the power source, a source of the fourth PMOS transistor is connected to a drain of the fifth PMOS transistor, and a gate of the fifth PMOS transistor is The source of the fifth PMOS transistor is connected to the negative pole of the power source.
  • the voltage dividing circuit can adjust the parameters of the PMOS transistor such that the bias voltage satisfies the above formula so that the current output from the MOS transistor is not affected by the temperature.
  • the temperature value of the temperature sensor For T T satisfies the following linear simulation model:
  • T f(X, V, P), where X is the level difference, V is the supply voltage value of the temperature sensor, and P is a process parameter of the MOS transistor; the linear simulation model is described by The level difference, the supply voltage value of the temperature sensor, and the process parameters of the MOS transistor are trained and modeled by big data fitting.
  • the second inverter includes:
  • the drain of the sixth PMOS transistor is connected to the positive pole of the power source, the source of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor, and the fourth NMOS transistor is connected.
  • the source is connected to the negative pole of the power supply.
  • the second aspect provides a system-level SoC chip, the first aspect of the first aspect, the first implementation of the first aspect, and the at least one temperature of any one of the fifth implementation manners of the first aspect sensor.
  • FIG. 1 is a schematic diagram of an embodiment of a temperature sensor according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a first inverter in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a second inverter in the embodiment of the present application.
  • FIG. 4 is a schematic diagram showing a level signal change of a temperature sensor according to an embodiment of the present application.
  • the application provides a temperature sensor and a chip for improving the measurement accuracy of the temperature sensor and accurately measuring the chip temperature of the SoC chip.
  • a temperature sensor is a sensing device that measures temperature. Commonly used in some temperature monitoring scenarios, such as some constant temperature control systems, intelligent temperature control systems. It is also common in the field of electronic circuits and chip design. It is well known that the normal operation of electronic devices needs to be within a certain temperature range. If the temperature is too high, it is easy to burn out the electronic devices. If the temperature is too low, the electronic devices may not work properly. The accuracy of the measured temperature is especially important.
  • the embodiment of the present application provides a temperature sensor with high accuracy, which is mainly applied to the inside of the chip, especially a SoC chip, such as a GPU and a CPU.
  • the temperature sensor includes:
  • first circuit 10 includes N first inverters 11 and an AND gate 40
  • second circuit 20 includes M second inverters 21 and The door 50, wherein, in FIG. 1, N and M are both 32 as an example, the numbers of the inverters are shown in FIG. 1;
  • the first inverters 11 of the first circuit 10 are connected in series with the AND gate 40 in a ring structure, and one of the input terminals of the AND gate 40 is connected to the input end of the thirty-second first inverter, and the gate 40 is The output terminal is connected to the output of the first first inverter, and the second circuit 20 is connected in the same manner as the first circuit 10, so that the other input terminal of the AND gate 40 and the other of the AND gate 50 The inputs are all connected to the enable signal.
  • the first circuit 10 and the second circuit 20 simultaneously enter an active state when the enable signal is enabled, since the first circuit 10 is a ring structure formed by the first inverter 11.
  • the function of the inverter is to invert the phase of the input level signal by 180 degrees to obtain an output level signal. Therefore, after the first circuit 10 enters the working state, a high-low level periodic flipping side is generated inside the first circuit 10.
  • the wave is the first level signal.
  • the second circuit 20 is a ring structure composed of the second inverter 21. Similar to the first circuit 10, a high-low level periodic flipping is generated inside the circuit.
  • the wave is the second level signal.
  • the first inverter 11 is designed through a special circuit structure, and within a preset temperature value range, the level width of the input level of the first inverter 11 can remain unchanged when the temperature changes, so that the first inversion
  • the level width of the output level of the device 11 is the same as the level width of the input level. It can be understood that the period size in the first level signal is determined by the level width of the high level and the low level in the square wave, since each The output level of one first inverter 11 is equal to the level width of the input level. Therefore, the period of the first level signal is the duration of the level width corresponding to the high level and the low level, which is a duration. A substantially constant period value.
  • the second inverter 21 is a normal inverter, and the level width of the input level thereof varies with temperature, so that the level width of the output level of the second inverter 21 is equal to the input level.
  • the flat widths are not equal, and therefore, the period of the second level signal changes with temperature, for example, when the temperature rises, the level width of the output level of the second inverter 21 is greater than the input level.
  • the level width when the temperature is lowered, the level width of the output level of the second inverter 21 is smaller than the level width of the input level.
  • the period of the second level signal changes with the level width of the high and low levels, is a period value that changes with temperature, the temperature rises, the period of the second level signal becomes larger, and the temperature decreases.
  • the period of the second level signal becomes small, and therefore, the period of the first level signal generated by the first circuit 10 and the level signal generated by the second circuit 20 are different.
  • the two inputs of the XOR gate 30 are coupled to the first circuit 10 and the second circuit 20, respectively, such that the XOR gate 30 collects the first level signal and the second level signal.
  • the XOR gate 30 works as follows: at the same time, if the first level signal and the second level signal are both high level or low level, the output of the XOR gate 30 is low level, at the same time, If one of the first level signal and the second level signal is low level and the other signal is high level, the output of the exclusive OR gate 30 is high. It can be understood that, according to the foregoing description of the period of the first level signal and the second level signal, it can be known that, within a preset temperature value range, the first level signal does not remain unchanged with temperature changes.
  • the second level signal changes with the temperature, resulting in the generation of the above two level signals having different periods under the enable of the same enable signal.
  • the XOR gate 30 can be The output level difference can represent the same time, the first level signal is used as the reference level, and the level change of the second level signal with the temperature is obtained. Therefore, the level difference is the first circuit signal and the second power. A level signal obtained by XOR logic between flat signals, not a difference.
  • the acquisition of the first level signal and the second level signal may be performed from the output of any one of the two inverter loops, as shown in FIG. 1 from the fifth inverter numbered 4.
  • the output is collected to ensure that the number of inverters from the enable terminal to the signal acquisition terminal is equal to prevent the first level signal and the second level signal from being affected by the number of inverters, causing unnecessary errors, further Improve the accuracy of temperature measurements.
  • the ordinary second inverter 21 has a temperature-sensitive characteristic, and the level signal of the output thereof varies with temperature. Since the first inverter 11 has a special circuit design, the first inverter 11 is provided. Insensitive to temperature, the level signal output by the first inverter 11 does not change with temperature during the preset temperature range. Therefore, the first level signal is not sensitive to temperature and does not change with temperature. The change of the second level signal is sensitive to temperature, and the specific change is as described above for the second inverter 21, and details are not described herein again.
  • the structure and the connection relationship of the second inverter 21 affect whether the relationship between the level signal and the temperature is a positive correlation or a negative correlation.
  • the first circuit 10 and the second circuit 20 adopt a symmetrical chain structure. Therefore, the influence of the voltage V and the manufacturing process P of the electronic device on the first circuit 10 and the second circuit 20 can be regarded as equivalent. Therefore, the only variable that changes the level difference output from the XOR gate 30 is temperature.
  • the temperature value can be calculated by the above difference value.
  • the temperature value corresponding to the level difference is calculated according to a linear model between the level difference and the temperature, wherein the linear model satisfies the following formula:
  • T f(X,V,P), where X is the level difference, V is the supply voltage value of the temperature sensor, P is the process parameter of the MOS transistor; the linear simulation model is composed of the level difference and the temperature sensor The power supply voltage value and the process parameters of the MOS transistor are trained and modeled by big data fitting.
  • the level difference value outputted from the XOR gate 30 is brought into the above linear model to calculate the temperature value of the temperature sensor.
  • the power supply voltage is opposite.
  • the influence of the level signal 20 of a circuit 10 and the second circuit is equivalent.
  • the same circuit process MOS tube is used in the first circuit 10 and the second circuit 20, and the process parameters of the MOS transistor are applied to the first circuit 10 and the
  • the influence of the level signal of the two circuits is also equivalent, and the influence factor of the level difference output from the XOR gate 30 is the temperature, and therefore, the temperature information can be obtained based on the above level difference.
  • the supply voltage and process parameters may still have some influence.
  • the linear model can be used to further calibrate the influence of different supply voltages and process parameters, and increase the temperature of the temperature sensor. measurement accuracy.
  • the linear model described above can be modeled using a high-dimensional fitting algorithm in an electronics design automation (EDA) phase using a simulation tool, and the data is modeled using a large amount of data. training.
  • EDA electronics design automation
  • the gate is represented as G in FIG. 2
  • the source is represented as S
  • the drain is represented as D
  • the above-mentioned representation method is used in the above, and the first inverter 11 in the embodiment of the present application includes:
  • a first P-channel MOSFET denoted P1
  • a second PMOS transistor denoted P2
  • a third PMOS transistor denoted P3, a first N-channel MOSFET, Recorded as N1, the second NMOS transistor, denoted as N2, the third NMOS transistor, denoted as N3;
  • the source of the first PMOS transistor and the drain of the second PMOS transistor are connected to the positive pole of the power source, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected to the first node, and the drain of the first PMOS transistor is The source of an NMOS transistor is connected to the second node, and the first node is connected to the second node;
  • a gate of the first NMOS transistor and a gate of the second NMOS transistor are connected to the third node, and a drain of the first NMOS transistor and a source of the second NMOS transistor are connected to a negative pole of the power source;
  • the drain of the second NMOS transistor is connected to the source of the third NMOS transistor.
  • the source of the second PMOS transistor is connected to the drain of the third PMOS transistor.
  • the gate of the third PMOS transistor is coupled to the gate of the third NMOS transistor to form a signal input terminal of the first inverter 11.
  • the source of the third PMOS transistor is connected to the drain of the third NMOS transistor to form a signal output terminal of the first inverter 11.
  • the first inverter further includes: a voltage dividing circuit, wherein the voltage dividing circuit is configured to adjust a voltage value of the third node to cause the first NMOS transistor to output a temperature independent of the temperature;
  • the voltage dividing circuit comprises: a fourth PMOS transistor and a fifth PMOS transistor, respectively denoted as P4 and P5;
  • a gate of the fourth PMOS transistor is connected to the third node, a drain of the fourth PMOS transistor is connected to the anode of the power source, a source of the fourth PMOS transistor is connected to a drain of the fifth PMOS transistor, and a gate of the fifth PMOS transistor is The source of the fifth PMOS transistor is connected to the negative pole of the power source.
  • the gate bias voltage V GS of the first NMOS transistor satisfies the following formula 1 by adjusting the relevant parameters of the fourth PMOS transistor and the fifth PMOS transistor in the voltage dividing circuit:
  • V GS V th (T0)+ ⁇ *(T-T0)+2*( ⁇ *T/km), where V th (T0) is the threshold voltage V th , ⁇ of the MOS tube corresponding to the temperature value T0 It is the temperature coefficient of the threshold voltage V th , T is the temperature variable, and km is the coefficient related to the MOS transistor manufacturing process; as can be seen from the formula 1, the gate bias voltage V GS has a positive correlation with the temperature.
  • I DS is the drain current
  • ⁇ is the electron mobility of the MOS transistor
  • W is the width of the MOS transistor conductive channel
  • L is the length of the MOS transistor conductive channel
  • C ox is the gate oxide capacitance per unit area.
  • V GS is the gate bias voltage of the MOS transistor
  • V th is the threshold voltage of the MOS transistor.
  • the electron mobility of the MOS tube has a negative correlation with the temperature. From the saturation current formula, if the V GS is constant, the electron mobility of the MOS tube increases with the increase of the temperature. The ⁇ becomes smaller as the temperature rises, eventually resulting in a smaller drain current I DS .
  • the MOS transistors P1, P2, N1 and N2 constitute a common-gate current mirror, in which the MOS transistor P1 and N1 form one mirror arm, and MOS tubes P2 and N2 constitute another mirror arm.
  • the function of the common-gate current mirror is to make the currents on the two mirror arms the same or proportional, thus causing the first NMOS transistor to generate
  • the temperature-independent drain current I DS is mapped to the MOS transistors P2 and N2 to form the mirror arm, and the MOS transistors P2 and N2 form the mirror arm.
  • the second inverter 21 includes:
  • the drain of the sixth PMOS transistor is connected to the positive pole of the power source, the source of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor, and the fourth NMOS transistor is connected.
  • the source is connected to the negative pole of the power supply.
  • the sixth PMOS transistor and the fourth NMOS transistor constitute a common inverter, and since the electron mobility in the MOS transistor changes with temperature, the MOS transistors P6 and N4 are generated.
  • the drain current changes with temperature, so that the output level of the signal output terminal of the second inverter 21 is affected by the temperature, so that the level width of the output level is different from the level width of the input level, and finally The second level signal generated by the second circuit 20 is varied as a function of temperature.
  • the level signal of the temperature sensor in the embodiment of the present application is illustrated.
  • the temperature sensor of the AND gate input terminal is enabled, and after being enabled, the level signal phase in the two inverter loops is enabled.
  • the flipping occurs, and two sets of square waves of different periods, that is, the first level signal and the second level signal are generated due to different temperatures, wherein a level change process of the first level signal and the second level signal is as follows
  • Figure 4 shows:
  • the trigger level signal is input at the enable signal end of the temperature sensor.
  • the temperature sensor enters an active state, triggering the first circuit 10 and the second circuit 20 to generate a high and low level of 180 degrees without interruption.
  • the signal as in the first level signal in FIG. 4: wherein the level widths of the high level and the low level are equal, it can be understood that since the current signal generated in the first circuit 10 does not change with temperature, it flows through
  • the level signal is only phase inverted by 180 degrees and the level width is not changed; similarly, the second level signal as shown in FIG.
  • the XOR gate 30 when flowing through the second inverter, not only the phase inversion At 180 degrees, the level width also changes, so that the level widths between the high and low levels in the second level signal are no longer equal. Finally, the XOR gate 30 outputs the level difference as shown in FIG. .
  • the embodiment of the present application further provides an SoC chip, and the temperature sensor described in at least one of the foregoing embodiments is placed inside the SoC chip.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • a computer readable storage medium A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program code. .

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Abstract

一种温度传感器，包括：第一电路（10）、第二电路（20）以及异或门电路（30），所述第一电路（10）包括N个第一反相器（11），所述N个第一反相器（11）串联成环状结构，所述第二电路（20）包括M个第二反相器（21），所述M个第二反相器（21）串联成环状结构，M＝N，所述M，N为不小于2的正整数；当所述温度传感器处于工作状态时，所述第一电路（10）输出第一电平，所述第一电平的电平变化与温度无关，所述第二电路（20）输出第二电平，所述第二电平的电平变化与温度之间具有关联关系；所述异或门电路（30）用于输入所述第一电平和所述第二电平，输出电平差值，所述电平差值用于确定所述温度传感器的温度值。用于提高温度传感器的测量精度，准确地测量SoC芯片的芯片温度。还公开了一种芯片。

Description

一种温度传感器及芯片
本申请要求于2017年12月28日提交中国专利局、申请号为201711459892.1、发明名称为“一种温度传感器及芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路设计领域，尤其涉及一种温度传感器及芯片。
背景技术
系统级芯片(system on a chip，SoC)是一种集成电路芯片，包括中央处理器(central processing unit，CPU)和图像处理器(graphics processing unit，GPU)等芯片。SoC芯片上的温度越高，SoC芯片的处理性能越差，温度超出一定门限值时，SoC芯片可能会失效导致无法正常工作。在SoC芯片上设置有温度传感器对其芯片内部的温度进行测量，以便调整SoC芯片内子系统的工作频率，保证SoC芯片的性能。
在SoC芯片内部设置的温度传感器一般使用双极结型晶体管(bipolar junction transistor，BJT)、运算放大器和模数转换器(analog-to-digital converter，ADC)等电子器件设计而成。其中，在温度传感器内部生成一个随温度变化的模拟电平信号和一个不随温度变化的模拟电平信号，上述两个模拟电平信号输入至ADC，ADC将电平信号转化为温度信息。一方面，上述温度传感器使用的模拟电平信号，需模拟电源供电才能工作，另一方面，上述温度传感器中使用的BJT、运算放大器和ADC等体积较大的电子器件，导致上述温度传感器的体积较大。CPU和GPU等SoC芯片上使用模拟电源供电的电路较少，面积占比小，并且上述温度传感器的体积较大，因此，上述温度传感器只能设置于少数模拟电源供电的芯片位置，通过上述温度传感器测量得到的温度值只能反映模拟电源供电部分的电路的温度，而不能准确的反映整个SoC芯片的整体温度，造成温度传感器测量得到的温度值不准确，影响对SoC芯片的调控，降低了SoC芯片的性能。
发明内容
本申请提供了一种温度传感器及芯片，用于提高温度传感器的测量精度，准确地测量SoC芯片的芯片温度。
本申请第一方面提供了一种温度传感器，包括：
第一电路、第二电路以及异或门电路，第一电路包括N个第一反相器，N个第一反相器串联连接形成环状结构，第二电路包括M个第二反相器，M个第二反相器串联连接形成环状结构，M＝N，M，N为不小于2的正整数；
当温度传感器处于工作状态时，第一电路输出第一电平，在预设温度值范围内，第一电平不会随温度变化而变化，即第一电平的变化不会受到温度的影响，第二电路输出第二电平，第二电平的电平变化与温度之间具有关联关系，即第二电平的电平变化会受到温度 的影响，其关联关系可以是正相关关系，也可以是负相关关系；
异或门电路用于输入第一电平和第二电平，输出电平差值，电平差值用于确定温度传感器的温度值。
从以上技术方案可以看出，本申请具有以下优点：
上述温度传感器包括反相器和异或门，可知上述温度传感器是数字电路，数字逻辑电路具有面积小，功耗低特点，CPU和GPU等SoC芯片中大量放置，可以准确地测量SoC芯片的整体温度。第一电路和第二电路由相同数量的反相器构成环状结构，并接入异或门输出电平差值，相当于对第一电平信号和第二电平信号进行差分处理，此差分处理，保证了将测量温度同时存在的电压、工艺影响绝大部分的抵消，使差值绝大部分体现温度影响。
结合本申请的第一方面，在第一方面的第一种可能的实现方式中，所述第一反相器包括：
第一P沟道金属氧化物半导体场效应PMOS晶体管、第二PMOS晶体管、第三PMOS晶体管、第一N沟道金属氧化物半导体场效应NMOS晶体管、第二NMOS晶体管、第三NMOS晶体管；
所述第一PMOS晶体管的源极与所述第二PMOS晶体管的漏极连接于电源正极，所述第一PMOS晶体管的栅极与所述第二PMOS晶体管的栅极连接于第一节点，所述第一PMOS晶体管的漏极与所述第一NMOS晶体管的源极连接于第二节点，所述第一节点与所述第二节点相连接；
所述第一NMOS晶体管的栅极与所述第二NMOS晶体管的栅极连接于第三节点，所述第一NMOS晶体管的漏极与所述第二NMOS晶体管的源极连接于电源负极；
所述第二NMOS晶体管的漏极与所述第三NMOS晶体管的源极连接，所述第二PMOS晶体管的源极与所述第三PMOS晶体管的漏极连接，所述第三PMOS晶体管的栅极与所述第三NMOS晶体管的栅极连接于第四节点，所述第三PMOS晶体管的源极与所述第三NMOS晶体管的漏极相连于第五节点。
MOS晶体管面积较小以及功耗较低，使得第一电路的整体面积小，功耗也较低。
结合第一方面或第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，第一反相器还包括分压电路，分压电路用于调节第一NMOS管的偏置电压，以使得第一电平的电平变化与温度无关，偏置电压为第一NMOS管的栅极和源极之间的电压差值，偏置电压满足以下公式：
V GS＝V th(T0)+α*(T-T0)+2*(α*T/km)，其中，V th(T0)为温度值为T0对应的MOS管的阈值电压V th，α为阈值电压V th的温度系数，T为温度变量，km为与MOS晶体管制程工艺相关的系数。
从上述公式可以看出，偏置电压与温度正相关，当偏置电压满足上述公式时，偏置电压的温度正相关效应，与MOS管的迁移率的温度负相关效应相互抵消，使得第一NMOS管输出的电流不受温度的影响。
另外，上述第一PMOS晶体管、第二PMOS晶体管、第一NMOS晶体管和第二NMOS晶体管连接形成一个电流镜，该电流镜将第一NMOS管的电流映射到第一反相器的第五节点输 出。
结合第一方面的第二种可能的实现方式，在第一方面的第三种可能的实现方式中，分压电路包括：
第四PMOS晶体管和第五PMOS晶体管；
第四PMOS晶体管的栅极连接与第三节点，第四PMOS晶体管的漏极连接于电源正极，第四PMOS晶体管的源极与第五PMOS晶体管的漏极连接，第五PMOS晶体管的栅极和第五PMOS晶体管的源极连接于电源负极。
上述分压电路可以通过调节PMOS晶体管的相关参数使得上述偏置电压满足上述公式，以使得MOS管输出的电流不受温度的影响。
结合第一方面、第一方面的第一种可能的实现方式至第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述温度传感器的温度值为T，T满足以下线性仿真模型：
T＝f(X,V,P)，其中，X为所述电平差值，V为所述温度传感器的的供电电压值，P为MOS晶体管的制程参数；所述线性仿真模型由所述电平差值、所述温度传感器的供电电压值和MOS晶体管的制程参数进行大数据拟合训练及建模得到。
结合第一方面，在第一方面的第五种可能的实现方式中，第二反相器包括：
第六PMOS晶体管和第四NMOS晶体管；
第六PMOS晶体管的漏极连接于电源正极，第六PMOS晶体管的源极与第四NMOS晶体管的漏极连接，第六PMOS晶体管的栅极和第四NMOS晶体管的栅极连接，第四NMOS晶体管的源极连接于电源负极。
第二方面提供了一种系统级SoC芯片，SoC芯片内放置有第一方面、第一方面的第一种实现方式至第一方面的第五种实现方式中任意一项所述的至少一个温度传感器。
附图说明
图1为本申请实施例中温度传感器的一个实施例示意图；
图2为本申请实施例中第一反相器的一个结构示意图；
图3为本申请实施例中第二反相器的一个结构示意图；
图4为本申请实施例中温度传感器的一个电平信号变化示意图。
具体实施方式
本申请提供了一种温度传感器及芯片，用于提高温度传感器的测量精度，准确地测量SoC芯片的芯片温度。
下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这 里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
温度传感器是一种测量温度的传感设备。通常常见于一些温度监控的场景中，比如一些恒温控制系统，智能温度控制系统等。在电子电路以及芯片设计领域也较为常见，众所周知，电子器件正常工作需要在一定的温度范围内，温度过高容易烧坏电子器件，温度过低电子器件可能无法正常工作，由此可见，温度传感器测量得到的温度的准确性尤为重要。
本申请实施例提供了一种准确度高的温度传感器，主要应用于芯片内部，尤其是SoC芯片，例如GPU和CPU。
为了便于理解本申请实施例中的温度传感器，下面结合以下实施例对其进行详细说明，具体如下：
如图1所示，本申请实施例中温度传感器的一个实施例，温度传感器包括：
第一电路10、第二电路20和异或门30，其中，第一电路10包括N个第一反相器11和与门40，第二电路20包括M个第二反相器21和与门50，其中，图1中以N和M均为32为例进行说明，各反相器的编号图1中已示出；
第一电路10中32个第一反相器11与与门40串联成环形结构，与门40的其中一个输入端与第三十二个第一反相器的输入端连接，与门40的输出端与第一个第一反相器的输端连接，第二电路20的连接方式与第一电路10的连接方式相同，因此，与门40的另一个输入端与与门50的另一个输入端均连接到使能信号端。
当使能信号端产生使能信号，在使能信号的使能下，第一电路10和第二电路20同时进入工作状态，由于第一电路10是第一反相器11构成的环状结构，反向器的作用是将输入电平信号的相位翻转180度得到输出电平信号，因此，第一电路10进入工作状态后在第一电路10内部会产生一个高低电平周期性翻转的方波即第一电平信号，同理，第二电路20是第二反相器21构成的环状结构，与第一电路10类似，在其电路内部会产生一个高低电平周期性翻转的方波即第二电平信号。
第一反相器11经过特殊电路结构设计，在预设的温度值范围内，第一反相器11的输入电平的电平宽度在温度发生改变时可以保持不变，使得第一反相器11的输出电平的电平宽度与其输入电平的电平宽度相同，可以理解，第一电平信号中的周期大小决定于方波中高电平和低电平的电平宽度，由于，每一个第一反相器11的输出电平与输入电平的电平宽度均相等，因此，第一电平信号的周期即为高电平和低电平的电平宽度对应的持续时长，是一个基本恒定的周期值。
第二反相器21为普通反相器，其输入电平的电平宽度会随着温度的变化而变化，使得第二反相器21的输出电平的电平宽度与输入电平的电平宽度不相等，因此，第二电平信号的周期会随着温度的变化而改变，例如，当温度升高时，第二反相器21的输出电平的电平宽度大于输入电平的电平宽度，当温度降低时，第二反相器21的输出电平的电平宽度小于 输入电平的电平宽度。可以理解，第二电平信号的周期会随着高低电平的电平宽度的变化而变化，是一个随温度变化的周期值，温度升高，第二电平信号的周期变大，温度降低，第二电平信号的周期变小，因此，第一电路10产生的第一电平信号和第二电路20产生的电平信号的周期不同。
异或门30的两个输入端分别与第一电路10和第二电路20连接，以使得异或门30将第一电平信号和第二电平信号采集出来。异或门30工作原理为：在同一时刻，若第一电平信号和第二电平信号同为高电平或低电平，则异或门30的输出为低电平，在同一时刻，若第一电平信号和第二电平信号两个信号中，其中一个信号为低电平，另外一个信号为高电平，则异或门30的输出为高电平。可以理解，根据上述对第一电平信号和第二电平信号的周期的相关描述，可以知道，在预设的温度值范围内，第一电平信号会不随着温度变化而保持不变，第二电平信号会随着温度的变化而变化，导致在相同使能信号的使能下产生周期不同的上述两个电平信号，如上述异或门30工作原理可知，异或门30可以输出的电平差值可以表征出同一时刻，第一电平信号作为参考电平，得到第二电平信号随温度的电平变化，因此，电平差值是第一电路信号与第二电平信号之间通过异或逻辑得到的电平信号，而不是一个差值。
上述第一电平信号与第二电平信号的采集可以从两反相器环中任一个反相器的输出端进行采集，如图1所示均从编号为4的第五个反相器的输出端进行采集，保证从使能端至信号采集端的反相器数量相等，以避免第一电平信号和第二电平信号受到反相器数量的影响，带来不必要的误差，进一步提高温度测量值的准确度。
普通的第二反相器21具有对温度敏感的特性，其输出的电平信号会随温度的变化而变化，由于第一反相器11具有特殊的电路结构设计，使得第一反相器11对温度不敏感，在预设温度范围内，第一反相器11输出的电平信号不会随温度的变化而变化，因此，第一电平信号对温度不敏感不会随着温度的变化而变化，而第二电平信号对温度敏感会随着温度的变化而变化，其具体变化如上述对第二反相器21的相关描述，此处不再赘述。
可选的，第二反相器21的结构以及连接关系等均会影响电平信号与温度之间的关系是正相关关系或是负相关关系。由图1可知，第一电路10和第二电路20采用对称的链式结构，因此，电压V以及电子器件的制程工艺P对第一电路10和第二电路20的影响可以看做是等效的，因此，异或门30输出的电平差值变化的唯一变量是温度。
通过上述电平差值可以计算得到温度值，可选的，根据电平差值与温度之间的线性模型计算得到电平差值对应的温度值，其中，上述线性模型满足以下公式：
T＝f(X,V,P)，其中，X为电平差值，V为温度传感器的的供电电压值，P为MOS晶体管的制程参数；线性仿真模型由电平差值、温度传感器的供电电压值和MOS晶体管的制程参数进行大数据拟合训练及建模得到。
将上述异或门30中输出的电平差值带入上述线性模型中进行计算得到温度传感器的温度值，对于同一个温度传感器而言，在某一固定的供电电压工作时，供电电压对第一电路10以及第二电路的电平信号20的影响是等效的，同样，第一电路10和第二电路20中使用一样制程工艺MOS管，MOS管的制程参数对第一电路10以及第二电路的电平信号的影 响也是等效的，异或门30输出的电平差值的影响因素是温度，因此，根据上述电平差值可以得到温度信息。但是不同的供电电压和制程参数不一样的温度传感器而言，供电电压和制程参数还是会存在一定影响的，使用上述线性模型可以进一步校准不同的供电电压和制程参数的影响，提高温度传感器的温度测量精度。
可选的，上述线性模型可以使用高维拟合算法，在电子设计自动化阶段(electronics design automation，EDA)阶段，使用仿真工具进行建模得到，并使用大量数据对建模得到的线性模型进行数据训练。
下面对本申请实施例中第一反相器11的结构进行详细说明，如图2所示，图2中栅极表示为G，源极表示为S，漏极表示为D，图3和图4中均采用上述表示方法，本申请实施例中第一反相器11包括：
第一P沟道金属氧化物半导体场效应PMOS晶体管，记为P1，第二PMOS晶体管，记为P2，第三PMOS晶体管，记为P3，第一N沟道金属氧化物半导体场效应NMOS晶体管，记为N1，第二NMOS晶体管，记为N2，第三NMOS晶体管，记为N3；
第一PMOS晶体管的源极与第二PMOS晶体管的漏极连接于电源正极，第一PMOS晶体管的栅极与第二PMOS晶体管的栅极连接于第一节点，第一PMOS晶体管的漏极与第一NMOS晶体管的源极连接于第二节点，第一节点与第二节点相连接；
第一NMOS晶体管的栅极与第二NMOS晶体管的栅极连接于第三节点，第一NMOS晶体管的漏极与第二NMOS晶体管的源极连接于电源负极；
第二NMOS晶体管的漏极与第三NMOS晶体管的源极连接。第二PMOS晶体管的源极与第三PMOS晶体管的漏极连接。第三PMOS晶体管的栅极与第三NMOS晶体管的栅极连接，构成第一反相器11的信号输入端。第三PMOS晶体管的源极与第三NMOS晶体管的漏极相连，构成第一反相器11的信号输出端。
第一反相器还包括：分压电路，上述分压电路用于调节上述第三节点的电压值，以使得第一NMOS管输出与温度无关的电流；
分压电路包括：第四PMOS晶体管和第五PMOS晶体管，分别记为P4和P5；
第四PMOS晶体管的栅极连接于第三节点，第四PMOS晶体管的漏极连接于电源正极，第四PMOS晶体管的源极与第五PMOS晶体管的漏极连接，第五PMOS晶体管的栅极和第五PMOS晶体管的源极连接于电源负极。
下面结合上述图2对应的电路结构对第一反相器11的工作原理进行说明：
通过调节分压电路中第四PMOS晶体管和第五PMOS晶体管的相关参数使得，第一NMOS晶体管的栅极偏置电压V GS满足以下公式一：
V GS＝V th(T0)+α*(T-T0)+2*(α*T/km)，其中，V th(T0)为温度值为T0对应的MOS管的阈值电压V th，α为阈值电压V th的温度系数，T为温度变量，km为与MOS晶体管制程工艺相关的系数；从公式一中可以看出，栅极偏置电压V GS与温度具有正相关关系。
结合如下饱和电流公式：
Figure PCTCN2018112370-appb-000001
其中，I DS为漏极电流，μ为MOS管的电子迁移率，W为MOS管导电沟道的宽度，L为MOS管导电沟道的长度，C ox为单位面积的栅极氧化层电容，V GS为MOS管的栅极偏置电压，V th为MOS管的阈值电压。
由于MOS管的自身特性使得MOS管的电子迁移率与温度之间具有负相关关系，从饱和电流公式可以看出，若V GS不变，则随着温度的升高，MOS管的电子迁移率μ会随着温度的升高而变小，最终导致漏极电流I DS变小。因此，当V GS满足如上公式一使得栅极偏置电压与温度具有正相关关系，此时，MOS管的栅极偏置电压V GS的温度正效应和MOS管的电子迁移率μ的负效应相互抵消，以使得漏极电流I DS随着温度的变化而保持不变，因此，第一NMOS晶体管产生与温度无关的漏极电流I DS。
另外，MOS管P1和P2的栅极连接在一起，MOS管N1和N2的栅极也连接在一起，因此，图中MOS管P1、P2、N1和N2构成一个共栅电流镜，其中MOS管P1和N1构成一个镜臂，MOS管P2和N2构成另一个镜臂，共栅电流镜的作用在于可以使得上述两个镜臂上的电流相同或成正比，因此，使得第一NMOS晶体管产生与温度无关的漏极电流I DS被映射到MOS管P2和N2构成镜臂上，而在MOS管P2和N2构成镜臂存在一个由MOS管P3和N4构成的反相器，因此第一NMOS晶体管产生的漏极电流I DS不会随着温度的变化而变化，最终被映射到MOS管P3和N4构成的反相器上，使得MOS管P3和P4的漏极电流不会随着温度的变化而变化。最终，在第一反相器的工作电压恒定的情况下，信号输出端的高电平或低电平不会随着温度的变化而变化，从而使得第一电路10产生的第一电平信号与不会随着温度的变化而变化。如图3所示，第二反相器21包括：
第六PMOS晶体管和第四NMOS晶体管，分别记为P6和N4；
第六PMOS晶体管的漏极连接于电源正极，第六PMOS晶体管的源极与第四NMOS晶体管的漏极连接，第六PMOS晶体管的栅极和第四NMOS晶体管的栅极连接，第四NMOS晶体管的源极连接于电源负极。
与上述MOS管P3和P4的组成类似，第六PMOS晶体管和第四NMOS晶体管构成一个普通反相器，由于MOS管中的电子迁移率会随着温度变化而变化，使得MOS管P6和N4产生的漏极电流随温度变化而变化，从而导致第二反相器21的信号输出端的输出电平由于受到温度的影响，使得输出电平的电平宽度与输入电平的电平宽度不同，最终，使得第二电路20产生的第二电平信号随温度变化而变化。
最后，对本申请实施例中温度传感器的电平信号进行说明，如图1中所示的温度传感器，与门输入端作为使能，使能后，两个反相器环中的电平信号相位同时发生翻转，因温度不同而产生两组不同周期的方波即第一电平信号和第二电平信号，其中，第一电平信号与第二电平信号的一种电平变化过程如图4所示：
在温度传感器的使能信号端输入触发电平信号，当触发电平信号为高电平时，温度传感器进入工作状态，触发第一电路10和第二电路20产生不间断翻转180度的高低电平信号，如图4中第一电平信号：其中高电平与低电平的电平宽度是相等的，可以理解，由于第一电路10中产生的电流信号是不随温度变化的，在流经第一反相器11时，电平信号只是相位翻转180度而电平宽度没有改变；同理，如图4所示的第二电平信号：流经第二反相器时，不仅相位翻转了180度，电平宽度也随之改变，使得第二电平信号中的高低电平之间的电平宽度不再相等，最终，异或门30输出如图4所示的电平差值。
本申请实施例还提供了一种SoC芯片，该SoC芯片内部放置有至少一个上述实施例中所述的温度传感器。
需要明确的是，本发明实施例中提到的“随温度变化而变化”和“不随温度变化而变化”均为相对概念。首先，考虑到高温对现有集成电路的剧烈影响，所谓的“不随温度变化而变化”更应该理解成对温度变化不敏感的一种状态，即如上文所述，通过电路设计使得一个电路方案中的由于温度变化带来的信号变化能够互相抵消，从而得到一个整体来说对温度变化不敏感的结果。而所谓的“随温度变化而变化”则是没有专门执行这种温度不敏感的设计手段，让集成电路器件按照正常物理特性受温度影响。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的4系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案范围。

Claims (7)

  1. 一种温度传感器，其特征在于，包括：
    第一电路、第二电路以及异或门电路，所述第一电路包括N个第一反相器，所述N个第一反相器串联成环状结构，所述第二电路包括M个第二反相器，所述M个第二反相器串联成环状结构，M＝N，所述M，N为不小于2的正整数；
    当所述温度传感器处于工作状态时，所述第一电路输出第一电平，在预设温度值范围内，所述第一电平不会随温度变化而变化，所述第二电路输出第二电平，所述第二电平的电平变化与温度之间具有关联关系；
    所述异或门电路用于输入所述第一电平和所述第二电平，输出电平差值，所述电平差值用于确定所述温度传感器的温度值。
  2. 根据权利要求1所述的传感器，其特征在于，所述第一反相器包括：
    第一P沟道金属氧化物半导体场效应PMOS晶体管、第二PMOS晶体管、第三PMOS晶体管、第一N沟道金属氧化物半导体场效应NMOS晶体管、第二NMOS晶体管、第三NMOS晶体管；
    所述第一PMOS晶体管的源极与所述第二PMOS晶体管的漏极连接于电源正极，所述第一PMOS晶体管的栅极与所述第二PMOS晶体管的栅极连接于第一节点，所述第一PMOS晶体管的漏极与所述第一NMOS晶体管的源极连接于第二节点，所述第一节点与所述第二节点相连接；
    所述第一NMOS晶体管的栅极与所述第二NMOS晶体管的栅极连接于第三节点，所述第一NMOS晶体管的漏极与所述第二NMOS晶体管的源极连接于电源负极；
    所述第二NMOS晶体管的漏极与所述第三NMOS晶体管的源极连接，所述第二PMOS晶体管的源极与所述第三PMOS晶体管的漏极连接，所述第三PMOS晶体管的栅极与所述第三NMOS晶体管的栅极连接，所述第三PMOS晶体管的源极与所述第三NMOS晶体管的漏极连接。
  3. 根据权利要求2所述的传感器，其特征在于，所述第一反相器还包括分压电路，所述分压电路用于调节所述第一NMOS管的偏置电压，以使得所述第一电平的电平变化与温度无关，所述偏置电压为所述第一NMOS管的栅极和源极之间的电压差值，所述偏置电压V GS满足以下公式：
    V GS＝V th(T0)+α*(T-T0)+2*(α*T/km)，其中，V th(T0)为温度值为T0对应的MOS管的阈值电压V th，α为阈值电压V th的温度系数，T为温度变量，km为与MOS晶体管制程工艺相关的系数。
  4. 根据权利要求3所述的传感器，其特征在于，所述分压电路包括：
    第四PMOS晶体管和第五PMOS晶体管；
    所述第四PMOS晶体管的栅极连接于所述第三节点，所述第四PMOS晶体管的漏极连接于所述电源正极，所述第四PMOS晶体管的源极与所述第五PMOS晶体管的漏极连接，所述第五PMOS晶体管的栅极和所述第五PMOS晶体管的源极连接于电源负极。
  5. 根据权利要求1至4中任一项所述的传感器，其特征在于，所述温度传感器的温度值为T，T满足以下线性仿真模型：
    T＝f(X,V,P)，其中，X为所述电平差值，V为所述温度传感器的的供电电压值，P 为MOS晶体管的制程参数；所述线性仿真模型由所述电平差值、所述温度传感器的供电电压值和MOS晶体管的制程参数进行大数据拟合训练及建模得到。
  6. 根据权利要求1所述的传感器，其特征在于，所述第二反相器包括：
    第六PMOS晶体管和第四NMOS晶体管；
    所述第六PMOS晶体管的漏极连接于所述电源正极，所述第六PMOS晶体管的源极与所述第四NMOS晶体管的漏极连接，所述第六PMOS晶体管的栅极和所述第四NMOS晶体管的栅极连接，所述第四NMOS晶体管的源极连接于所述电源负极。
  7. 一种系统级SoC芯片，其特征在于，所述SoC芯片内放置有上述权利要求1至6中任一项所述的至少一个温度传感器。
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