WO2019127918A1

WO2019127918A1 - Digital filter and data processing method

Info

Publication number: WO2019127918A1
Application number: PCT/CN2018/079262
Authority: WO
Inventors: 吕辉; 雷文明; 葛卫敏
Original assignee: 京信通信系统（中国）有限公司; 京信通信系统（广州）有限公司; 京信通信技术(广州)有限公司; 天津京信通信系统有限公司
Priority date: 2017-12-29
Filing date: 2018-03-16
Publication date: 2019-07-04
Also published as: CN108228480B; CN108228480A

Abstract

Provided in an embodiment of the present invention are a digital filter and a data processing method, which are used for solving the technical problem in the existing technology wherein the complexity of a digital filter processing digital signals is high. A digital filter may be dynamically configured to be in different channel modes according to a sampling rate of input signal data, and may support input data flows corresponding to various digital signals having different bandwidth combinations in a communication system, which solves the technical problem in the existing technology wherein the complexity of a digital filter processing digital signals is high, thus improving the efficiency of processing digital signals.

Description

Digital filter and data processing method

The present application claims priority to Chinese Patent Application No. 200911481116.1, entitled "A Digital Filter and Data Processing Method", filed on Dec. 29, 2017, the entire contents of which is incorporated herein by reference. In the application.

Technical field

The present invention relates to the field of mobile communications, and in particular, to a digital filter and a data processing method.

Background technique

With the development of mobile communication, the number of mobile communication users is increasing, and the requirements for data services are getting higher and higher. Worldwide Interoperability for Microwave Access (WIMAX), Long Term Evolution (LTE), etc. The application of 3G and 4G is increasing. One difference between WIMAX, LTE and 2G Global System for Mobile Communication (GSM) is that the signal bandwidth of GSM is fixed at 200KHz, while the signal bandwidth of WIMAX and LTE has many possibilities. For example, LTE includes 3MHz and 5MHz. , 10MHz, 15MHz, 20MHz, etc., WIMAX includes 5MHz, 7MHz, 10MHz, 20MHz and so on.

In digital communication systems, a software version is often required to support digital signal processing in multiple formats and multiple bandwidths. At present, digital filters are used mainly for processing signals with fixed bandwidth and fixed data rate input. When there are many possibilities for the bandwidth and data rate of the input signal, multiple digital filters need to be integrated, which increases the complexity of the system, etc., and may even cause the system to fail. There is also a part of the digital filter, although it can cope with the input signal bandwidth and variable data rate, but every time the input signal bandwidth changes, you need to replace the filter processing clock, and reset the system, this way to use the system Stability has a large impact and is more complicated.

In summary, the complexity of the prior art digital filter processing input digital signals is high.

Summary of the invention

The embodiment of the invention provides a digital filter and a data processing method for solving the technical problem of high complexity when the digital filter of the prior art processes the input digital signal.

In a first aspect, an embodiment of the present invention provides a digital filter, including:

a control module for storing at least an access address and a filter coefficient address of the input signal data;

Serially connected M DPRAM modules, wherein a first one of the M DPRAM modules is connected to the control module, at least for receiving input signal data;

a plurality of first adder modules, wherein a first adder module connects two DPRAM modules in a symmetric position of the M DPRAM modules;

a plurality of multiplier modules, wherein a multiplier module is coupled to a first adder module, the number of the multiplier modules being related to a digital filter order, each multiplier multiplexing number, each multiplication The number of times of multiplexing of the module is related to the number of channels corresponding to the digital filter clock, the channel mode of the digital filter, and the sampling rate of the input signal data, and the number of channels is determined by a bandwidth combination corresponding to the input data stream;

a plurality of storage modules, wherein a storage module is coupled to a multiplier module for storing filter coefficients, and the number of filter coefficients stored in each storage module is determined by the number of multiplexing of the multiplier module;

a plurality of second adder modules connected to the plurality of multiplier modules;

A delay module for delaying the digital filter.

In a possible implementation manner, if the channel mode of the digital filter is a single channel mode, the input sampling rate of the single channel is F; or

If the channel mode of the digital filter is a dual channel mode, an input sampling rate of each channel in the dual channel is F/2; or

If the channel mode of the digital filter is a three-channel mode, an input sampling rate of one of the three channels is F/2, and an input sampling rate of each of the other two channels is F/4; or

If the channel mode of the digital filter is a four channel mode, the input sampling rate of each of the four channels is F/4.

In a possible implementation manner, the bandwidth combination corresponding to the input data stream includes at least one of 5 MHz, 10 MHz, 15 MHz, and 20 MHz.

In a second aspect, an embodiment of the present invention provides a data processing method, which is applied to a digital filter, where the digital filter includes M dual-port random access memory DPRAMs, which are sequentially connected, and M is an integer greater than or equal to 2. Among them, the data processing methods include:

When acquiring the jth input signal data among the N input signal data included in the input data stream, reading from the M DPRAMs before receiving the jth input signal data based on a preset bandwidth configuration mode Input signal data, wherein the preset bandwidth configuration mode is related to at least two types of bandwidths corresponding to the input data stream, and is used to indicate an access address of each input signal data in the DPRAM, where N is greater than or equal to An integer of 1, j is an integer less than or equal to N;

Processing the jth input signal data and the plurality of input signal data according to a preset rule to obtain a plurality of output signal components, wherein the preset rule is: placing the M DPRAMs in a symmetrical position The input values of the input signal data having the same filter coefficients in the two DPRAMs are added, and multiplied by the corresponding filter coefficients;

An output signal corresponding to the jth input signal data is determined and output based on the plurality of output signal components.

In a possible implementation, the obtaining rule of each input signal data of the N input signal data included in the input data stream is: acquiring and sequentially storing one input signal data every predetermined number of clocks, wherein The preset number is determined by the number of channels and the sampling rate of the corresponding input signal data, the number of channels being determined by the bandwidth combination corresponding to the input data stream, and the total bandwidth of each bandwidth combination is equal.

In a possible implementation manner, the reading, by using the preset bandwidth configuration mode, the plurality of input signal data received before the jth input signal data from the M DPRAMs, including:

And reading, according to the preset bandwidth configuration mode, the first group of input signal data in the same bandwidth as the jth input signal data from the (1+n)th DPRAM, and from the (Mn) And sequentially reading, in the DPRAM, the second group of input signal data in the same bandwidth as the jth input signal data, wherein the order of the reverse reading is opposite to the storage order corresponding to the preset bandwidth configuration mode. The order of sequential reading is the same as the storage order, the (1+n)th DPRAM and the (Mn)th DPRAM are in a symmetrical position, and the n sequentially takes an integer from 0 to (M-1) ;

The plurality of input signal data is composed of a plurality of the first set of input signal data and a plurality of the second set of input signal data.

In a possible implementation manner, the processing, by using the preset rule, the jth input signal data and the multiple input signal data to obtain a plurality of output signal components, including:

Adding the input values of the jth input signal data, the plurality of the first set of input signal data, and the input signal data having the same filter coefficient among the plurality of the second set of input signal data, and correspondingly The filter coefficients are multiplied to obtain a plurality of output signal components.

In a possible implementation manner, the determining, according to the plurality of output signal components, an output signal corresponding to the jth input signal data, including:

The plurality of output signal components are accumulated to determine an output signal corresponding to the jth input signal data.

In a third aspect, an embodiment of the present invention provides a digital filter, including:

M dual-port random access memory DPRAMs connected in sequence, the M being an integer greater than or equal to 2;

An acquiring module, configured to read the jth input signal from the M DPRAMs based on a preset bandwidth configuration mode when acquiring the jth input signal data of the N input signal data included in the input data stream a plurality of input signal data received before the data, wherein the preset bandwidth configuration mode is associated with at least two types of bandwidths corresponding to the input data stream, and is used to indicate an access address of each input signal data in the DPRAM , N is an integer greater than or equal to 1, and j is an integer less than or equal to N;

a processing module, configured to process the jth input signal data and the plurality of input signal data according to a preset rule, to obtain a plurality of output signal components, where the preset rule is: The input values of the input signal data having the same filter coefficients in the two DPRAMs in the symmetrical position in the DPRAM are added, and multiplied by the corresponding filter coefficients;

And an output module, configured to determine and output an output signal corresponding to the jth input signal data based on the plurality of output signal components.

In a possible implementation manner, the obtaining module acquires an acquisition rule of each input signal data of the N input signal data included in the input data stream: acquiring and sequentially storing one input every predetermined number of clocks The signal data, wherein the preset number is determined by a channel number and a sampling rate of the corresponding input signal data, the channel number being determined by a bandwidth combination corresponding to the input data stream, and a total bandwidth of each bandwidth combination is equal.

In a possible implementation manner, the obtaining module is used to:

Reading, according to the preset bandwidth configuration mode storage order, the first group of input signal data in the same bandwidth as the jth input signal data from the (1+n)th DPRAM, and from the first (Mn) And sequentially reading a second set of input signal data in the same bandwidth as the jth input signal data, wherein the order of the reverse reading is opposite to the storage order corresponding to the preset bandwidth configuration mode, The order of sequential reading is the same as the storage order, the (1+n)th DPRAM and the (Mn)th DPRAM are in a symmetrical position, and the n is taken from 0 to (M-1) in turn. Integer

In a possible implementation manner, the processing module is specifically configured to:

In a possible implementation manner, the output module is specifically configured to:

In a fourth aspect, an embodiment of the present invention provides a computer apparatus, including:

At least one processor, and

a memory, communication interface communicatively coupled to the at least one processor;

Wherein the memory stores instructions executable by the at least one processor, the at least one processor performing the method of the second aspect with the communication interface by executing the instructions stored by the memory.

In a fifth aspect, an embodiment of the present invention provides a computer readable storage medium, including:

The computer readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method of the second aspect.

In the embodiment of the present invention, when acquiring the jth input signal data of the N input signal data included in the input data stream, reading the plurality of input data received before the jth input signal data according to the preset bandwidth configuration mode, and The preset bandwidth configuration mode is related to at least two types of bandwidths corresponding to the input data stream, is used to indicate an access address of each input signal data in the DPRAM, and then the jth input signal data and the plurality of input signals according to a preset rule. The data is processed to obtain a plurality of output signal components, thereby determining and outputting an output signal corresponding to the jth input signal data. That is, the data processing method provided by the embodiment of the present invention can simultaneously process input signals of at least two kinds of bandwidths, which reduces the complexity of processing the input signals by the digital filters.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly described below. It is obvious that the following drawings are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a schematic structural diagram of a digital filter commonly used in the prior art;

2 is a schematic structural diagram of another digital filter in the prior art;

3 is a schematic structural diagram of a digital filter according to an embodiment of the present invention;

4 is a schematic diagram of connection and reading of two DPRAM modules in an embodiment of the present invention;

FIG. 5 is a schematic flowchart diagram of a data processing method according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of another digital filter according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a computer device according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the drawings in the embodiments of the present invention.

First, the digital filters commonly used in the prior art are described as follows.

1 is a schematic structural diagram of a digital filter commonly used in the prior art, wherein Z ^-1 represents a delay, that is, an input signal data is acquired every interval. In FIG. 1, x ₈ can represent the received ninth input signal data, and the received first eight input signal data are x ₇ , x ₆ , x ₅ , x ₄ , x ₃ , x ₂ , x ₁ , x _{0 , respectively.} ; c ₀ , c ₁ , ..., c ₈ denote filter coefficients.

Therefore, when the received input signal data is x ₈ , the corresponding output signal can be expressed as:

Y8=x ₀ *c ₈ +x ₁ *c ₇ +x ₂ *c ₆ +x ₃ *c ₅ +x ₄ *c ₄ +x ₅ *c ₃ +x ₆ *c ₂ +x ₇ *c ₁ + x ₈ *c ₀ .

Since the filter coefficients have symmetry, that is, c ₀ and c ₈ , c ₁ and c ₇ , c ₂ and c ₆ , c ₃ and c ₅ are equal. Therefore, please refer to FIG. 2, which is a structural diagram of another digital filter in the prior art. In Fig. 2, x(n) is the input signal data, y(n) is the corresponding output signal, and a ₀ , a ₁ , a ₂ , a ₃ and a ₄ are filter coefficients.

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiment 1

The configurable bandwidth digital filter in the embodiment of the present invention may use a Field-Programmable Gate Array (FPGA) platform, and may adopt a pulsating finite-length Systolic Finite Impulse Response (SFIR) filter. The architecture is digitally filtered using a high-rate filter clock, which sets the filter clock based on the actual maximum bandwidth required and does not change during the digital filtering process.

The digital filter in the embodiment of the present invention can process channel signals of the type such as LTE and Wideband Code Division Multiple Access (WCDMA).

3 is a schematic structural diagram of a configurable bandwidth digital filter according to an embodiment of the present invention. The digital filter may include a control module 31 and M dual-port random access memory (DPRAM) connected in series. The module 32, the plurality of first adder modules 33, the plurality of storage modules 34, the plurality of multiplier modules 35, the plurality of delay modules 36, the plurality of second adder modules 37, and the accumulator 38, wherein the accumulator 38 The function is to accumulate the results obtained by the plurality of second adder modules 37. X(n) in the figure is the input data stream corresponding to the input signal, and Y(n) is the corresponding output signal, and n can be taken as 0 in sequence. An integer of N, where N is an integer greater than or equal to 1.

The control module 31 can be configured to store an access address of each input signal data in the input data stream, wherein the access address includes a write address and a read address; and can also be used to store a filter coefficient address, and a filter coefficient address can indicate Corresponding filter coefficients are in corresponding storage locations in the storage module; the enabling unit included in the control module 31 has two states, which can be represented by 0 or 1, respectively, that is, when the enable is 1, the digital filter can be input to the input. Signal data, when enabled is 0, the digital filter can be disabled from writing input signal data.

The DPRAM module 32 can include two ports, one port can be used for write timing, another port can be used for reading data, and the depth at which the DPRAM module 32 stores data can be determined by the amount of data of the input data stream that the digital filter needs to process. Decide. In Fig. 3, ten DPRAM modules 32 are shown as an example. As can be seen from FIG. 3, the ten DPRAM modules 32 are serial connections, wherein the DPRAM module 1 of the 10 DPRAM modules 32 is connected to the control module 31 and can be used to receive input signal data. Two DPRAM modules 32 in symmetrical positions among the ten DPRAM modules 32 are connected to the same first adder module 33, such as the DPRAM module 1 and the DPRAM module 10, the DPRAM module 2, and the DPRAM module 9.

To facilitate the understanding of the connection between the two DPRAM modules 32, please refer to FIG. 4, which is a schematic diagram of the connection between the two DPRAM modules 32 in the embodiment of the present invention, with the DPRAM module 1 and the DPRAM module. The connection of 2 is an example. Wherein, when the state of the enabling unit in the control module 32 is 1, that is, the digital filter can be instructed to write the input signal data, the DPRAM module 1 writes an input signal data, and can pass the port 1 according to the preset bandwidth configuration mode. The input signal data is stored to the corresponding write address, and then the previous input signal data (represented by the output signal data in FIG. 4) adjacent to the aforementioned one input signal data is read from the read address through the port 2 as the DPRAM module 2 Input signal data is written.

Since the input signal data is sequentially stored in 10 DPRAMs, different bandwidth configuration modes, the input signal data sequentially written belong to different channels, and the data reading must be read according to the corresponding bandwidth configuration mode.

The five first adder modules 33 are shown in FIG. 3 as an example. As can be seen from FIG. 3, a first adder module 33 can connect two DPRAM modules 32 in symmetric positions of the M DPRAM modules 32, and can be used to correspond to input values of input signal data output by the two DPRAM modules 32. Add together.

For example, the output values of the DPRAM module 1 and the DPRAM module 10, the DPRAM module 2 and the DPRAM module 9, the DPRAM module 3 and the DPRAM module 8, the DPRAM module 4 and the DPRAM module 7, the DPRAM module 5, and the DPRAM module 6 can be connected through corresponding The first adder module 33 is directly added.

In the embodiment of the present invention, the multiplier module 35 can be used at a high load, that is, the high-order digital filtering can be realized using the resources of a few multiplier modules 35. The number of times of multiplexing of one multiplier module 35 can be calculated by the following formula, namely:

Multiplex = filter clock / (number of channels * channel rate)

The number of channels may be related to the bandwidth combination of the input data stream and to the channel mode of the digital filter.

If the channel mode of the digital filter is dual channel mode, the input sampling rate of each channel in the dual channel is F/2; or,

If the channel mode of the digital filter is three-channel mode, the input sampling rate of one channel of the three channels is F/2, and the input sampling rate of each channel of the other two channels is F/4; or

If the channel mode of the digital filter is four-channel mode, the input sample rate of each of the four channels is F/4.

For example, refer to Table 1, which is a channel configuration table corresponding to the channel mode of the digital filter in the embodiment of the present invention.

Table 1

In Table 1, the number of channels of the multi-channel digital filter can be configured to be 4, and when the channel mode of the digital filter is single channel mode, the number of channels that can be accommodated is 1, and the input sampling rate is 1 times the sampling rate. For example, the input sampling rate is F. At this time, the bandwidth combination corresponding to the input data stream can be indicated by the channel resource working mode 0000 as 20 MHz.

When the channel mode of the digital filter is dual channel mode, the number of channels it can accommodate is 2, and the bandwidth combination can include 3/4 sampling rate, that is, 3 MHz/4 15 MHz and 1/4 sampling rate, ie F/ The 5 MHz of 4, the bandwidth combination can be indicated by the channel resource operating mode 0001. Or, when the channel mode of the digital filter is dual channel mode, the number of channels that can be accommodated is 2, and the bandwidth combination can include two 1/4 sampling rates, that is, 10 MHz of 3F/4, and the bandwidth combination can be Channel resource working mode 0101 indicates. Among them, the channel resource working mode can be customized.

For other cases of the channel mode of the digital filter, refer to Table 1, which is not described in detail in the embodiment of the present invention.

The digital filter in the embodiment of the present invention can implement multiple different bandwidth combinations, each bandwidth is within the protocol range, and the total bandwidth of each bandwidth combination is equal. The channel rate is related or equal to the sampling rate of the input signal data.

The number of multiplier modules 35 is related to the number of digital filter stages and the number of times each multiplier module 35 is multiplexed. Therefore, the symmetry of the digital filter coefficients can be utilized, and the number of multiplier modules 35 required in the digital filter can be determined by the following formula, namely:

Number of multiplier modules 35 = order of digital filters / (2 * number of multiplexing)

Among them, the "2" in the formula is determined by the symmetry of the digital filter coefficients.

In the case where the calculation result obtained by the above formula is an integer, the obtained number is taken as the number of the multiplier modules 35; if the calculation result is a decimal number, the number obtained by subtracting the fractional part and adding 1 is taken as the multiplier module 35. The number.

For example, the digital filter clock is 245.76MHz (in megahertz), and the designed digital filter has an order of 79 steps. It implements a 4-channel filter with an input rate of 7.68Msps per channel (unit: 100 10,000 samples/second).

The number of multiplexing of each multiplier is calculated by the number of digital filter clocks and channels, and the channel rate of each channel is 245.76/(4*7.68)=8; using the symmetry of the filter coefficients, the required multiplication can be calculated. The module is 79/(2*8)=4.9375, which requires the use of 5 multiplier modules 35, please still see Figure 3.

In the embodiment of the present invention, the memory module 34 is shown in FIG. 3 as a Read-Only Memory (ROM). As can be seen from FIG. 3, a memory module 34 is connected to a multiplier module 35 for storing filter coefficients, and the number of filter coefficients stored in each memory module 34 can be determined by the number of times of multiplexing by the multiplier module 35, or It can also be determined by the bit width of the filter coefficients, such as 16 bits, where the bit width is related to the input signal data.

In practical applications, the filter coefficients can be in odd symmetrical form. At this time, the filter coefficients that the digital filter needs to store can be determined by the following formula:

Number of filter coefficients = (order of digital filter + 1) / 2

Each of the storage modules 34 can sequentially store the filter coefficients in order.

For example, a digital filter with a degree of digital filter of 79 requires 40 filter coefficients to be implemented, and each memory module 34 can store 8 filter coefficients. As shown in FIG. 3, ROM1 to ROM5 sequentially store filter coefficients in order: ROM 1 stores coefficients 0 to 7, ROM 2 stores coefficients 8 to 15, ROM 3 stores coefficients 16 to 23, and ROM 4 stores coefficients 24 to 31, ROM. 5 storage coefficient 32 ~ 39.

The second adder module 37 in the embodiment of the present invention may be the same as or different from the first adder module 33. As shown in Fig. 3, the second adder module 37 is connected to the multiplier module 35, and the plurality of output signal components obtained by the plurality of multiplier modules 35 can be accumulated to obtain an output signal Y(n).

The delay module 36 can be used for delays in the digital filter during digital filtering. For example, the delay unit can control one clock clock to write an input signal data to the DPRAM module 32, and the number of divisions can be determined by the number of channels and the input data sampling rate.

In the embodiment of the present invention, when the delay module 36 controls one input signal data corresponding to each of the 8 clock write input signals X(n) to the DPRAM module 32, the control module 31 can control to sequentially read two of the symmetric positions. The input signal data stored in the history of the DPRAM module 32; then, the output signal data of the two DPRAM modules 32 can be added by the corresponding first adder module 33, and the filter coefficients of the corresponding storage and storage module 34 A plurality of output signal components are obtained by multiplication by the multiplier module 35; the plurality of output signal components are further accumulated by the second adder module 37 to obtain a corresponding output signal Y(n).

In summary, one or more technical solutions of the embodiments of the present invention have the following technical effects or advantages:

First, the digital filter in the embodiment of the present invention can support the processing of multiple standard signals, and can support real-time online configuration, which is flexible and convenient to use, has a significant filtering effect, and is convenient for maintenance.

Second, since the digital filter in the embodiment of the present invention adopts digital processing, no unnecessary cost is required, and a digital filter is compatible with a plurality of bandwidth combinations, and the effect is stable and the FPGA resources can be saved, that is, the cost is reduced.

Embodiment 2

Based on the same inventive concept, referring to FIG. 5, an embodiment of the present invention provides a data processing method, which can be applied to the digital filter according to the first embodiment. The process of the data processing method can be described as follows:

S501: When acquiring the jth input signal data of the N input signal data included in the input data stream, reading, by the preset bandwidth configuration mode, the plurality of inputs received before the jth input signal data from the M DPRAMs Signal data, wherein the preset bandwidth configuration mode is related to at least two bandwidths corresponding to the input data stream, is used to indicate an access address of each input signal data in the DPRAM, N is an integer greater than or equal to 1, and j is less than or equal to An integer of N;

S502: processing the jth input signal data and the plurality of input signal data according to a preset rule to obtain a plurality of output signal components, wherein the preset rule is: having two DPRAMs in the symmetric positions of the M DPRAMs After the input values of the input signal data of the same filter coefficient are added, multiplied by the corresponding filter coefficients;

S503: Determine and output an output signal corresponding to the jth input signal data based on the plurality of output signal components.

In the embodiment of the present invention, the obtaining rule of each input signal data of the N input signal data included in the input data stream is: acquiring a preset number of clocks and sequentially storing one input signal data, wherein, preset The number is determined by the number of channels and the sampling rate of the corresponding input signal data. The number of channels is determined by the bandwidth combination corresponding to the input data stream, and the total bandwidth of each bandwidth combination is equal. The bandwidth combination may include at least one of 5 MHz, 10 MHz, 15 MHz, 20 MHz.

Assuming that the bandwidth combination corresponding to the input data stream is 15 MHz and 5 MHz, the corresponding channel number is 2. The input signal data includes N input signal data, which can be represented as x0, x1, x2, x3, x4, ..., x28, x29, x30, x31, etc., wherein each of the four input signal data can correspond to one cycle, such as x0. , x1, x2 are different input signal data on the 15MHz bandwidth, and x3 is the input signal data on the 5MHz bandwidth, that is, x0, x1, x2, x3 can correspond to one cycle.

If the depth of the DPRAM is 32, that is, the DPRAM can include 32 addresses for storing data, which can be represented by 0, 1, 2, 3, 4, ..., 28, 29, 30, 31, respectively. The bandwidth is combined into 15MHz and 5MHz input data streams. After a predetermined number of clocks, such as 8clock, acquires and sequentially stores an input signal data, an input signal data can correspond to a storage address, that is, an input signal of 15MHz bandwidth. The data can be stored in DPRAM as 0,1,2,4,5,6,8,9,10,12,13,14,16,17,18,20,21,22,24,25,26 28, 29, 30; correspondingly, the input signal data of the 5 MHz bandwidth is stored in the DPRAM at

addresses

3, 7, 11, 15, 19, 23, 27, 31.

In the embodiment of the present invention, each time an input signal data is acquired, after processing by the digital filter, an output signal corresponding to the input signal data may be correspondingly obtained.

In S501, the preset bandwidth configuration mode is related to at least two types of bandwidths corresponding to the input data stream. For example, the bandwidth corresponding to the input data stream includes 15 MHz and 5 MHz. In this case, the corresponding channel in the bandwidth combination may be used to save the data in the DPRAM. The address is divided into two parts, one for storing input signal data on a 15MHz bandwidth, one for storing input signal data on a 5MHz bandwidth, and the preset bandwidth configuration mode indicating that each input signal data is in the DPRAM. The storage address, it should be noted that the storage address and the corresponding read address are the same address.

Therefore, when acquiring the jth input signal data among the N input signal data included in the input data stream, the plurality of received data before the jth input signal data may be read from the M DPRAMs according to the preset bandwidth configuration mode. Input signal data.

For example, after sequentially acquiring and sequentially storing x0, x1, x2, x3, x4, ..., x28, x29, x30, x31 input data, obtaining the 33rd input signal data through the first DPRAM, that is, x32, First store x32 to the storage address 0 corresponding to x0. Then, a plurality of input signal data received before the 33rd input signal data can be read from the M DPRAMs according to the preset bandwidth configuration mode.

In a possible implementation manner, reading the plurality of input signal data received before the jth input signal data from the M DPRAMs based on the preset bandwidth configuration mode may be performed by, but not limited to, the following manner.

The principle of reading the input signal data in the DPRAM may include: the same channel, that is, the input signal data in the same bandwidth needs to be read in the storage order, and the last stored data should be read first; sequentially read and store each The filter coefficients stored by module 34 correspond to the number of input signal data.

That is, if the jth input signal data is acquired through the first DPRAM of the M DPRAMs, the reverse reading from the (1+n)th DPRAM is in the same bandwidth as the jth input signal data based on the preset bandwidth configuration mode. The first set of input signal data, and the second set of input signal data in the same bandwidth as the jth input signal data are sequentially read from the (Mn) DPRAM.

The above example continues. Please refer to FIG. 3 at the same time. Suppose that after sequentially acquiring and sequentially storing x0, x1, x2, x3, x4, ..., x28, x29, x30, x31 input data, obtain the 33rd through the first DPRAM. When inputting signal data, that is, x32, you can first store x32 to the storage address 0 corresponding to x0.

For input signal data having a bandwidth of 15 MHz, the addresses of the first set of input signal data read from the DRRAM module 1 are: 0, 30, 29, 28, 26, 25, 24, and 22; and from the DRRAM module 10 The addresses of the read second set of input signal data are: 21, 22, 24, 25, 26, 28, 29, and 30, respectively. The addresses of the first set of input signal data read from the DPRAM module 2 are: 1, 0, 30, 29, 28, 26, 25, and 24; the second set of input signal data read from the DPRAM module 9 The addresses are: 22, 24, 25, 26, 28, 29, 30, 0. The output of other DPRAM modules is similar, and will not be described in detail in the embodiments of the present invention.

A plurality of input signal data is composed of a plurality of first sets of input signal data and a plurality of second sets of input signal data.

Then, the process may go to S502, that is, processing the jth input signal data and the plurality of input signal data according to a preset rule to obtain a plurality of output signal components, wherein the preset rule is: placing the M DPRAMs in a symmetrical position The input values of the input signal data having the same filter coefficients in the two DPRAMs are added and multiplied by the corresponding filter coefficients.

In a possible implementation, the processing of the jth input signal data and the plurality of input signal data based on the preset rule to obtain the plurality of output signal components may include:

Adding input values of the jth input signal data, the plurality of first sets of input signal data, and the input signal data of the plurality of second sets of input signal data having the same filter coefficient, and multiplying by the corresponding filter coefficients , obtaining multiple output signal components.

The above example continues, please still refer to FIG. 3, the input values of the input signal data corresponding to 0, 30, 29, 28, 26, 25, 24, and 22, respectively, and 21, 22, 24, 25, 26, 28, 29 The input values of the input signal data corresponding to 30 and 30 are respectively added, and then multiplied by the corresponding filter coefficients to obtain a plurality of output signal components. If the input value of the input signal data corresponding to the address 0 is added to the input value of the input signal data corresponding to the address 21, and multiplied by the filter coefficient corresponding to the filter coefficient address 0 stored in the ROM 1, an output signal component can be obtained; Further, if the input value of the input signal data corresponding to the address 30 is added to the input value of the input signal data corresponding to the address 22, and multiplied by the filter coefficient corresponding to the filter coefficient address 1 stored in the ROM 1, an output signal component can be obtained. . The calculation of the remaining input signal data is similar, and is not described in detail in the embodiments of the present invention.

After obtaining a plurality of output signal components in the above manner, it is possible to proceed to S503, that is, to determine and output an output signal corresponding to the jth input signal data based on the plurality of output signal components.

In a possible implementation manner, the determining, according to the plurality of output signal components, the output signal corresponding to the jth input signal data may include accumulating the plurality of output signal components, determining the data with the jth input signal Corresponding output signal.

Embodiment 3

Based on the same inventive concept, referring to FIG. 6, the embodiment of the present invention provides a digital filter, and the data processing method as described in Embodiment 2 can be applied. The digital filter includes M dual port random access memory DPRAMs, an acquisition module 61, a processing module 62, and an output module 63, which are sequentially connected, and the M is an integer greater than or equal to 2.

The obtaining module 61 is configured to, when acquiring the jth input signal data of the N input signal data included in the input data stream, read from the M DPRAMs in the jth based on a preset bandwidth configuration mode. a plurality of input signal data received before the input signal data, wherein the preset bandwidth configuration mode is related to at least two bandwidths corresponding to the input data stream, and is used to indicate that each input signal data is in the DPRAM Access address, N is an integer greater than or equal to 1, and j is an integer less than or equal to N;

The processing module 62 is configured to process the jth input signal data and the plurality of input signal data according to a preset rule to obtain a plurality of output signal components, where the preset rule is: The input values of the input signal data having the same filter coefficients in the two DPRAMs in the symmetric position in the DPRAM are added, and multiplied by the corresponding filter coefficients;

The output module 63 is configured to determine and output an output signal corresponding to the jth input signal data based on the plurality of output signal components.

In a possible implementation manner, the acquiring module 61 acquires an acquisition rule of each input signal data of the N input signal data included in the input data stream: acquiring and sequentially storing one clock every predetermined number of clocks Input signal data, wherein the preset number is determined by the number of channels and a sampling rate of the corresponding input signal data, the number of channels being determined by a combination of bandwidths corresponding to the input data streams, and the total bandwidth of each bandwidth combination is equal.

In a possible implementation, the obtaining module 61 is configured to:

In a possible implementation, the processing module 62 is specifically configured to:

In a possible implementation manner, the output module 63 is specifically configured to:

Embodiment 4

Referring to FIG. 7, based on the same inventive concept, a computer apparatus is provided in an embodiment of the present invention, including at least one processor 71, and a memory 72 and a communication interface 73 communicatively coupled to the at least one processor 71, in FIG. A processor 71 is shown as an example.

The memory 72 stores instructions executable by the at least one processor 71, and the at least one processor 71 performs the operation of the memory 72 by using the communication interface 73 as in the second embodiment. Said method.

Embodiment 5

Based on the same inventive concept, an embodiment of the present invention provides a computer readable storage medium, where the computer readable storage medium stores computer instructions, when the computer instructions are run on a computer, causing the computer to execute as described in Embodiment 2 Methods.

In a specific implementation process, the computer readable storage medium includes: a universal serial bus flash drive (USB), a mobile hard disk, a read-only memory (Read-OMly PePory, ROP), a random access memory ( RaMdoP Access PePory, RAP), a disk or a disc, and other storage media that can store program code.

The device embodiments described above are merely illustrative, wherein the units/modules described as separate components may or may not be physically separate, and the components displayed as units/modules may or may not be physical units/modules. , can be located in one place, or can be distributed to multiple network units/modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without deliberate labor.

Through the description of the above embodiments, those skilled in the art can clearly understand that the various embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware. Based on such understanding, the above technical solutions may be embodied in the form of software products in essence or in the form of software products, which may be stored in a computer readable storage medium such as ROP/RAP, magnetic Discs, optical discs, etc., include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments or portions of the embodiments.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

A digital filter, comprising:

a control module for storing at least an access address and a filter coefficient address of the input signal data;

Serially connected M DPRAM modules, wherein a first one of the M DPRAM modules is connected to the control module, at least for receiving the input signal data;

a plurality of first adder modules, wherein a first adder module connects two DPRAM modules in a symmetric position of the M DPRAM modules;

a plurality of multiplier modules, wherein a multiplier module is coupled to a first adder module, the number of the multiplier modules being related to a digital filter order, each multiplier multiplexing number, each multiplication The number of times of multiplexing of the module is related to the number of channels corresponding to the digital filter clock, the channel mode of the digital filter, and the sampling rate of the input signal data, and the number of channels is determined by a bandwidth combination corresponding to the input data stream;

a plurality of storage modules, wherein a storage module is coupled to a multiplier module for storing filter coefficients, and the number of filter coefficients stored in each storage module is determined by the number of multiplexing of the multiplier module;

a plurality of second adder modules connected to the plurality of multiplier modules;

A delay module for delaying the digital filter.
The digital filter according to claim 1, wherein if the channel mode of the digital filter is a single channel mode, the input sampling rate of the single channel is F; or

If the channel mode of the digital filter is a dual channel mode, an input sampling rate of each channel in the dual channel is F/2; or

If the channel mode of the digital filter is a three-channel mode, an input sampling rate of one of the three channels is F/2, and an input sampling rate of each of the other two channels is F/4; or

If the channel mode of the digital filter is a four channel mode, the input sampling rate of each of the four channels is F/4.
The digital filter of claim 2 wherein the bandwidth combination corresponding to the input data stream comprises at least one of 5 MHz, 10 MHz, 15 MHz, 20 MHz.
A data processing method is applied to a digital filter, wherein the digital filter comprises M dual-port random access memory DPRAMs connected in sequence, and the M is an integer greater than or equal to 2, the method comprising:

When acquiring the jth input signal data among the N input signal data included in the input data stream, reading from the M DPRAMs before receiving the jth input signal data based on a preset bandwidth configuration mode Input signal data, wherein the preset bandwidth configuration mode is related to at least two types of bandwidths corresponding to the input data stream, and is used to indicate an access address of each input signal data in the DPRAM, where N is greater than or equal to An integer of 1, j is an integer less than or equal to N;

Processing the jth input signal data and the plurality of input signal data according to a preset rule to obtain a plurality of output signal components, wherein the preset rule is: placing the M DPRAMs in a symmetrical position The input values of the input signal data having the same filter coefficients in the two DPRAMs are added, and multiplied by the corresponding filter coefficients;

An output signal corresponding to the jth input signal data is determined and output based on the plurality of output signal components.
The method according to claim 4, wherein the obtaining rule of each input signal data of the N input signal data included in the input data stream is: acquiring and sequentially storing an input signal every predetermined number of clocks. Data, wherein the preset number is determined by a number of channels and a sampling rate of corresponding input signal data, the number of channels being determined by a bandwidth combination corresponding to the input data stream, and a total bandwidth of each bandwidth combination is equal.
The method according to claim 4 or 5, wherein said reading a plurality of input signal data received before said jth input signal data from said M DPRAMs based on a preset bandwidth configuration mode, include:

And reading, according to the preset bandwidth configuration mode, the first group of input signal data in the same bandwidth as the jth input signal data from the (1+n)th DPRAM, and from the (Mn) And sequentially reading, in the DPRAM, the second group of input signal data in the same bandwidth as the jth input signal data, wherein the order of the reverse reading is opposite to the storage order corresponding to the preset bandwidth configuration mode. The order of sequential reading is the same as the storage order, the (1+n)th DPRAM and the (Mn)th DPRAM are in a symmetrical position, and the n sequentially takes an integer from 0 to (M-1) ;

The plurality of input signal data is composed of a plurality of the first set of input signal data and a plurality of the second set of input signal data.
The method according to claim 6, wherein the processing of the jth input signal data and the plurality of input signal data based on a preset rule to obtain a plurality of output signal components comprises:

Adding the input values of the jth input signal data, the plurality of the first set of input signal data, and the input signal data having the same filter coefficient among the plurality of the second set of input signal data, and correspondingly The filter coefficients are multiplied to obtain a plurality of output signal components.
The method of claim 7, wherein the determining an output signal corresponding to the jth input signal data based on the plurality of output signal components comprises:

The plurality of output signal components are accumulated to determine an output signal corresponding to the jth input signal data.
A digital filter, characterized in that the digital filter comprises:

M dual-port random access memory DPRAMs connected in sequence, the M being an integer greater than or equal to 2;

An acquiring module, configured to read the jth input signal from the M DPRAMs based on a preset bandwidth configuration mode when acquiring the jth input signal data of the N input signal data included in the input data stream a plurality of input signal data received before the data, wherein the preset bandwidth configuration mode is associated with at least two types of bandwidths corresponding to the input data stream, and is used to indicate an access address of each input signal data in the DPRAM , N is an integer greater than or equal to 1, and j is an integer less than or equal to N;

a processing module, configured to process the jth input signal data and the plurality of input signal data according to a preset rule, to obtain a plurality of output signal components, where the preset rule is: The input values of the input signal data having the same filter coefficients in the two DPRAMs in the symmetrical position in the DPRAM are added, and multiplied by the corresponding filter coefficients;

And an output module, configured to determine and output an output signal corresponding to the jth input signal data based on the plurality of output signal components.
The digital filter according to claim 9, wherein the obtaining module acquires an acquisition rule of each of the N input signal data included in the input data stream: a predetermined number of clocks per interval Acquiring and sequentially storing an input signal data, wherein the preset number is determined by a channel number and a sampling rate of the corresponding input signal data, the channel number being determined by a bandwidth combination corresponding to the input data stream, each bandwidth combination The total bandwidth is equal.
The digital filter according to claim 9 or 10, wherein the acquisition module is configured to:

Reading, according to the preset bandwidth configuration mode storage order, the first group of input signal data in the same bandwidth as the jth input signal data from the (1+n)th DPRAM, and from the first (Mn) And sequentially reading a second set of input signal data in the same bandwidth as the jth input signal data, wherein the order of the reverse reading is opposite to the storage order corresponding to the preset bandwidth configuration mode, The order of sequential reading is the same as the storage order, the (1+n)th DPRAM and the (Mn)th DPRAM are in a symmetrical position, and the n is taken from 0 to (M-1) in turn. Integer

The plurality of input signal data is composed of a plurality of the first set of input signal data and a plurality of the second set of input signal data.
The digital filter according to claim 11, wherein the processing module is specifically configured to:

Adding the input values of the jth input signal data, the plurality of the first set of input signal data, and the input signal data having the same filter coefficient among the plurality of the second set of input signal data, and correspondingly The filter coefficients are multiplied to obtain a plurality of output signal components.
The digital filter according to claim 12, wherein said output module is specifically configured to:

The plurality of output signal components are accumulated to determine an output signal corresponding to the jth input signal data.
A computer device, comprising:

At least one processor, and

a memory, communication interface communicatively coupled to the at least one processor;

Wherein the memory stores instructions executable by the at least one processor, the at least one processor performing the memory interface to perform any of the claims 4-8 by executing the memory stored instructions Said method.
A computer readable storage medium characterized by:

The computer readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method of any of claims 4-8.