CN116636215A

CN116636215A - Data processing circuit, data processing method, device, equipment and medium

Info

Publication number: CN116636215A
Application number: CN202180004067.0A
Authority: CN
Inventors: 孙高明; 毕育欣; 段欣; 刘蕊
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2023-08-22
Also published as: WO2023115287A1

Abstract

The present disclosure provides a data processing method, and relates to the field of computer technology. The method comprises the following steps: acquiring input data, wherein the input data is M-bit data; converting the input data into output data according to a first mode when the value of the input data is less than or equal to a predetermined threshold, wherein the output data is N-bit data, and M is greater than N; and converting the input data into output data according to the second mode in the case where the value of the input data is greater than the predetermined threshold. The present disclosure also provides a data processing circuit, a data processing apparatus, an electronic device, and a storage medium.

Description

Data processing circuit, data processing method, device, equipment and medium

Technical Field

The disclosure relates to the field of computer technology, and in particular, to a data processing circuit, a data processing method, a data processing device, an electronic device and a storage medium.

Background

EOTF (Electro-Optical Transfer Function, electro-optical conversion function) unit and OETF (Opto-Electronic Transfer Function, photoelectric conversion function) unit are modules required for conversion between linear domain and nonlinear domain. The EOTF unit may map by means of a table look-up to convert the nonlinear domain data into linear domain data.

Disclosure of Invention

The present disclosure provides a digital processing circuit, a digital processing method, an apparatus, an electronic device, and a storage medium.

According to a first aspect, the present disclosure provides a data processing method, comprising: acquiring input data, wherein the input data is M-bit data; converting the input data into output data according to a first mode when the value of the input data is smaller than or equal to a preset threshold value, wherein the output data is N-bit data, and M is larger than N; and converting the input data into the output data according to a second mode when the value of the input data is greater than the predetermined threshold.

For example, in the case where the value of the input data is smaller than a predetermined threshold, converting the input data into output data according to the first mode includes: determining a numerical range of the output data; dividing the numerical range of the output data into a plurality of numerical intervals; determining a target section corresponding to the input data in the plurality of numerical sections according to the size of the input data; and determining the output data according to the lower limit value of the target section.

For example, when the value of the input data is greater than the predetermined threshold, converting the input data into the output data according to the second mode includes: determining a numerical range of the output data; dividing the numerical range of the output data into a plurality of numerical intervals; determining a target section corresponding to the input data in the plurality of numerical sections according to the size of the input data; and determining the output data based on the size of the input data, the lower limit value of the target section, and the upper limit value of the target section.

For example, the plurality of numerical intervals are equally spaced apart.

For example, the plurality of numerical intervals are non-equally spaced apart.

For example, the determining the output data based on the size of the input data, the lower limit value of the target section, and the upper limit value of the target section includes: obtaining a multiplicand according to the input data; calculating a product from a multiplier and a multiplicand by using a difference between an upper limit value of the target section and a lower limit value of the target section as the multiplier; and determining the output data based on the product.

For example, the calculating a product using a difference between the input data and the lower limit value of the target section as a multiplicand and a difference between the upper limit value of the target section and the lower limit value of the target section as a multiplier includes: dividing the multiplicand of M bits into first high-bit data of (M-K) bits and first low-bit data of K bits, K being an integer greater than 1 and less than M; dividing the multiplier of N bits into second high-bit data of (N-L) bits and second low-bit data of L bits, wherein L is an integer greater than 1 and less than N; calculating the product of the first high-bit data and the second high-bit data to obtain first result data; calculating the product of the first high-bit data and the second low-bit data to obtain second result data; calculating the product of the first low-bit data and the second high-bit data to obtain third result data; calculating the product of the first low-bit data and the second low-bit data to obtain fourth result data; and obtaining the product according to the first result data, the second result data, the third result data and the fourth result data.

For example, the obtaining the product according to the first result data, the second result data, the third result data, and the fourth result data includes: shifting the first result data left by (K+L) bits to obtain first shift result data; shifting the second result data left by K bits to obtain second shift result data; shifting the third result data left by L bits to obtain third shift result data; and adding the first shift result data, the second shift result data, the third shift result data and the fourth result data to obtain the product.

For example, the input data includes light intensity data and the output data includes voltage data.

According to a second aspect, the present disclosure provides a data processing circuit comprising: an input sub-circuit for receiving input data, said input data being M-bit data; a conversion sub-circuit for converting the input data into output data according to a first mode when the value of the input data is equal to or less than a predetermined threshold, the output data being N-bit data, wherein M is greater than N; and converting the input data into the output data according to a second mode if the value of the input data is greater than the predetermined threshold; and an output sub-circuit for outputting the output data.

For example, the above-described conversion sub-circuit includes: a first determining unit configured to determine a numerical range of the output data; a dividing unit for dividing the numerical range of the output data into a plurality of numerical intervals; a second determining unit configured to determine a target section corresponding to the input data from among the plurality of numerical sections, based on a size of the input data; and a third determination unit configured to determine the output data based on a lower limit value of the target section.

For example, the above-mentioned conversion sub-circuit further includes: and fourth determining means for determining the output data based on the size of the input data, the lower limit value of the target section, and the upper limit value of the target section.

For example, the dividing unit is used for equally dividing a plurality of numerical intervals.

For example, the dividing unit is configured to divide the plurality of numerical intervals at unequal intervals.

For example, the fourth determining unit is further configured to: obtaining a multiplicand according to the input data; calculating a product from a multiplier and a multiplicand by using a difference between an upper limit value of the target section and a lower limit value of the target section as the multiplier; and determining the output data based on the product.

For example, the fourth determining unit is further configured to: dividing the multiplicand of M bits into first high-bit data of (M-K) bits and first low-bit data of K bits, K being an integer greater than 1 and less than M; dividing the multiplier of N bits into second high-bit data of (N-L) bits and second low-bit data of L bits, wherein L is an integer greater than 1 and less than N; calculating the product of the first high-bit data and the second high-bit data to obtain first result data; calculating the product of the first high-bit data and the second low-bit data to obtain second result data; calculating the product of the first low-bit data and the second high-bit data to obtain third result data; calculating the product of the first low-bit data and the second low-bit data to obtain fourth result data; and obtaining the product according to the first result data, the second result data, the third result data and the fourth result data.

For example, the fourth determining unit is further configured to: shifting the first result data left by (K+L) bits to obtain first shift result data; shifting the second result data left by K bits to obtain second shift result data; shifting the third result data left by L bits to obtain third shift result data; and adding the first shift result data, the second shift result data, the third shift result data and the fourth result data to obtain the product.

For example, the input sub-circuit includes M pins for receiving M bits of light intensity data; the output sub-circuit comprises N pins for outputting N-bit voltage data.

According to a third aspect, the present disclosure also provides a data processing apparatus comprising: the acquisition module is used for acquiring input data, wherein the input data is M-bit data; a first conversion module, configured to convert the input data into output data according to a first mode when the value of the input data is less than or equal to a predetermined threshold, where M is greater than N; and a second conversion module for converting the input data into the output data according to a second mode when the value of the input data is greater than the predetermined threshold.

According to a fourth aspect, the present disclosure also provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the methods provided by the present disclosure.

According to a fifth aspect, the present disclosure also provides a computer readable storage medium having stored thereon executable instructions which, when executed by a processor, cause the processor to implement the method provided by the present disclosure.

According to a sixth aspect, the present disclosure also provides a computer program product comprising a computer program which, when executed by a processor, implements the method provided by the present disclosure.

Drawings

FIG. 1 is a flow chart of a data processing method according to one embodiment of the present disclosure;

FIG. 2 is a flow chart of a data processing method according to another embodiment of the present disclosure;

FIG. 3 is a flow chart of a data processing method according to another embodiment of the present disclosure;

FIG. 4 is a flow chart of a data processing method according to another embodiment of the present disclosure;

FIG. 5 is a block diagram of data processing circuitry according to one embodiment of the present disclosure;

FIG. 6 is a block diagram of data processing circuitry according to one embodiment of the present disclosure;

FIG. 7 is a block diagram of a data processing apparatus according to one embodiment of the present disclosure; and

fig. 8 is a block diagram of an electronic device to which a data processing method may be applied according to one embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments that would be apparent to one of ordinary skill in the art without the benefit of this disclosure are within the scope of this disclosure. It should be noted that throughout the appended drawings, like elements are represented by like or similar reference numerals. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting the disclosure in any way, but are merely examples of embodiments of the disclosure. Conventional structures or configurations will be omitted when may lead to confusion in understanding the present disclosure. It should be noted that the shapes and dimensions of the various components in the figures do not reflect the actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be in a general sense understood by those skilled in the art. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Furthermore, in the description of embodiments of the present disclosure, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. Furthermore, the two components may be connected or coupled by wire or wirelessly.

The data output by the EOTF unit may be used as input data for the OETF unit.

When EOTF units convert data from a linear domain to a non-linear domain, large numerical data needs to be mapped to small numerical data. In addition, since the bit width of the data output from the EOTF unit is varied, the bit width of the input data of the OETF unit is also varied. In the process of processing data by the OETF unit, the data amount of the lookup table is huge due to numerous lookup addresses. If a common table look-up mode is adopted, the data transmission time is longer, and timing violations can be generated, so that the chip works abnormally or the main frequency can not be increased.

FIG. 1 is a flow chart of a data processing method according to one embodiment of the present disclosure.

As shown in fig. 1, the method 100 may include operations S110 to S130.

In operation S110, input data is acquired.

For example, the input data is M-bit data.

For example, M is an integer greater than or equal to 1.

In operation S120, in case that the value of the input data is equal to or less than a predetermined threshold value, the input data is converted into output data according to a first mode.

For example, the output data is N-bit data.

For example, M is greater than N. N is an integer greater than or equal to 1.

For example, according to the first mode, a range of values of the output data may be determined. The input data may be converted into the range of values to obtain output data.

In operation 130, the input data is converted into output data according to the second mode in case the value of the input data is greater than a predetermined threshold.

For example, the output data may be the N-bit data described above.

For example, according to the second mode, a range of values of the output data may be determined. The input data may be converted into the range of values to obtain output data.

By the embodiment of the disclosure, the input data can be accurately converted into the output data.

Fig. 2 is a flow chart of a data processing method according to another embodiment of the present disclosure.

As shown in fig. 2, the method 220 may convert the input data into the output data according to the first mode in a case where the value of the input data is equal to or less than a predetermined threshold, which will be described in detail with reference to operations S221 to S224.

In operation S221, a numerical range of output data is determined.

For example, in the case where the Input Data data_input is less than or equal to the preset threshold Th, one range of values of the output Data may be determined. In one example, the numerical range may be [ v1_0, v1_31]. I.e. the output data is one or more values between v1_0 to v1_31.

In operation S222, the numerical range of the output data is divided into a plurality of numerical intervals.

For example, the plurality of numerical intervals may be equally spaced apart. In one example, the numerical range [ v1_0, v1_31] described above may be divided into 32 equally spaced numerical intervals. For example, one value interval may be [ v1_0, v1_1), and the value interval adjacent thereto may be [ v1_1, v1_2).

Each numerical range includes an upper limit value and a lower limit value. For example, the upper limit value of the numerical value section [ v1_0, v1_1) is v1_1, and the lower limit value is v1_0.

In operation S223, a target section corresponding to the input data among the plurality of numerical sections is determined according to the size of the input data.

For example, each numerical interval corresponds to an address interval. For example, the address section (lv1_0, lv1_1) corresponds to the numerical section [ v1_0, v1_1 ]. The address range (Lv1_10, lv1_11) corresponds to the value range [ v1_10, v1_11 ].

Taking the Input Data Lv1_10.ltoreq.Data_Input < Lv1_11 as an example, the target section may be determined to be [ v1_10, v1_11 ].

In operation S224, output data is determined according to the lower limit value of the target section.

For example, the output data is determined based on the lower limit value v1_10 of the target section [ v1_10, v1_11 ] described above. In one example, v1_10 may be taken as output Data corresponding to the Input Data data_input.

In some embodiments, the plurality of numerical intervals may be non-equally spaced apart, as opposed to the method 200. In one example, the numerical range [ v1_0, v1_31] described above may be divided into less than 32 numerical intervals. For example, one value interval may be [ v1_0, v1_3), and the next value interval adjacent thereto may be [ v1_4, v1_5).

By the embodiment of the disclosure, smaller input data can be quickly converted into output data.

Fig. 3 is a flow chart of a data processing method according to another embodiment of the present disclosure.

As shown in fig. 3, the method 330 may convert the input data into the output data according to the second mode in case that the value of the input data is greater than a predetermined threshold, which will be described in detail with reference to operations S331 to S334.

In operation S331, a numerical range of output data is determined.

For example, in the case where the Input Data data_input is greater than the preset threshold Th, the numerical range of the output Data may be determined. In one example, the numerical range may be [ v2_0, v2_63]. I.e. the output data is one or more values between v2_0 to v2_63.

In the present embodiment, the numerical ranges [ v2_0, v2_63] also correspond to the bit-wide data ranges [ bit_0, bit_63 ].

In operation S332, a numerical range of output data is divided into a plurality of numerical intervals.

For example, the plurality of numerical intervals may be equally spaced apart. In one example, the numerical range [ v2_0, v2_63] described above may be divided into 64 equally spaced numerical intervals. For example, one value interval may be [ v2_0, v2_1), and the value interval adjacent thereto may be [ v2_2, v2_2).

Further, the bit-wide data ranges [ bit_0, bit_63] described above may be divided into 64 equally spaced bit-wide data sections with reference to the manner in which the numerical ranges [ v2_0, v2_63] are divided. Each bit-wide data interval corresponds to a numerical interval. For example, the bit width data interval [ bit_0, bit_1) corresponds to the value interval [ v2_0, v2_1). Bit wide data interval [ bit_20, bit_21) corresponds to the value interval [ v2_20, v2_21).

In operation S333, a target section corresponding to the input data from among a plurality of numerical sections is determined according to the size of the input data.

For example, each numerical interval corresponds to an address interval. For example, the address section (lv2_0, lv2_1) corresponds to the numerical section [ v2_0, v2_1 ]. The address range (lv2_20, lv2_21) corresponds to the value range [ v2_20, v2_21 ].

Taking the Input Data Lv2_20.ltoreq.Data_Input < Lv2_21 as an example, the target section may be determined as [ v2_20, v2_21 ].

In operation S334, the output data is determined according to the size of the input data, the lower limit value of the target section, and the upper limit value of the target section.

In the disclosed embodiments, the multiplicand may be derived from the input data.

For example, the difference between the multiplicand and the lower limit value of the address section is taken as the multiplicand.

In the embodiment of the present disclosure, the difference between the upper limit value of the target section and the lower limit value of the target section is used as a multiplier, and the product is calculated from the multiplicand and the multiplier.

For example, the product may be calculated by the following formula:

Data _Mul ＝(Data _input -Data_Lv_interval _bottom )*(Data_V_interval _top -

Data_V_interval _bottom ) (equation I)

In formula one, data _Mul Is the product, data _input To input Data, data_Lv_interval _bottom data_V_interval is the lower limit value of the address interval _bottom data_V_interval is the lower limit value of the target interval _top Is the upper limit value of the target section.

In one example, as described above, taking the Input Data Lv2_20+_Data_input < Lv2_21 as an example, the target interval may be determined to be [ v2_20, v2_21 ]. In this example, data_V_interval in equation one _bottom Can take V2_20, data_V_interval _top V2-21, data-Lv-interval can be taken _bottom Lv2_20 may be taken.

In an embodiment of the present disclosure, the output data is determined from the product.

For example, the output data may be determined by the following formula:

Data _output to output data, bit_interval _bottom The lower limit value of the bit width data section corresponding to the target section.

In one example, as described above, taking the Input Data Lv2_20+_Data_input < Lv2_21 as an example, the target interval may be determined to be [ v2_20, v2_21 ]. The bit-wide data interval corresponding to the target interval [ v2_20, v2_21) is [ bit_20, bit_21), bit_interval in this example _bottom The value of (2) may be bit 20.

By the embodiment of the disclosure, larger input data can be accurately converted into output data.

In some embodiments, the method 300 differs in that the plurality of numerical intervals may be non-equally spaced apart. In one example, the numerical range [ v2_0, v1_63] described above may be divided into less than 64 numerical intervals. For example, one value interval may be [ v2_0, v2_3), and the next value interval adjacent thereto may be [ v2_4, v2_5). Accordingly, the bit-wide data ranges [ bit_0, bit_63] described above may be divided into less than 64 equally spaced bit-wide data intervals, with reference to the manner in which the value ranges [ v2_0, v2_63] are divided. Each bit-wide data space corresponds to a numerical space.

Fig. 4 is a flow chart of a data processing method according to another embodiment of the present disclosure.

As shown in fig. 4, the method 434 may calculate a product from the multiplier and the multiplicand using a difference between an upper limit value of the target interval and a lower limit value of the target interval as the multiplier. The detailed description will be made with reference to operations S4341 to S4347.

In operation S4341, the multiplicand of M bits is divided into first high-bit data of (M-K) bits and first low-bit data of K bits.

For example, K is an integer greater than 1 and less than M.

For example, the M-bit multiplicand mul_1 may be a 12-bit data, such as 1001_1100_0100. The decimal number corresponding to the multiplicand of the M bits is 2500. In this case, the value of K may be 6. Accordingly, the first high-bit data mul_1_ [11:6 may be 10_0111, the first low bit data mul_1_ [5:0 may be 00_0100. And the first high-bit data mul_1_ [11:6] may be 39. And the first low bit data mul_1_ [5: the decimal number corresponding to 0 may be 4.

In operation S4342, the multiplier of N bits is divided into (N-L) -bit second high-bit data and L-bit second low-bit data.

For example, L is an integer greater than 1 and less than N

For example, the N-bit multiplier mul_2 may be a 10-bit data, such as 11_1100_0110. The decimal number corresponding to the N-bit multiplier is 966. In this case, the value of L may be 5. Correspondingly, the second high-bit data mul_2_ [9:5 may be 1_1110, the second low bit data mul_2_ [4:0 may be 0_0110. And the second highest bit data mul_2_ [9: the decimal number corresponding to 5 may be 30. And the second low-bit data mul_2_ [4: the decimal number corresponding to 0 may be 6.

In operation S4343, a product of the first high-bit data and the second high-bit data is calculated to obtain first result data.

For example, the first high-bit data mul_1_ [11:6] and second highest bit data mul_2_ [9: the product of 5 may be 10_0111×1_1110=100_1001_0010. That is, the first result data is 100_1001_0010, and the decimal number corresponding to the first result data may be 1170.

In operation S4344, a product of the first high-bit data and the second low-bit data is calculated to obtain second result data.

For example, the first high-bit data mul_1_ [11:6] and second low bit data mul_2_ [4: the product of 0 may be 10_0111×0_0110=000_1110_1010. That is, the second result data is 000_1110_1010, and the decimal number corresponding to the second result data may be 234.

In operation S4345, a product of the first low-bit data and the second high-bit data is calculated to obtain third result data.

For example, the first low-bit data mul_1_ [5:0] and second highest bit data mul_2_ [9: the product of 5 may be 00_0100 x 1_1110=000_0111_1000. That is, the third result data is 000_0111_1000, and the decimal number corresponding to the third result data may be 120.

In operation S4346, the product of the first low-bit data and the second low-bit data is calculated to obtain fourth result data.

For example, the first low-bit data mul_1_ [5:0] and second low bit data mul_2_ [4: the product of 0 may be 00_0100×0_0110=000_0001_1000. That is, the fourth result data is 000_0001_1000, and the decimal number corresponding to the second result data may be 24.

In operation S4347, a product is obtained according to the first, second, third, and fourth result data.

In the embodiment of the disclosure, the first result data may be shifted left by (k+l) bits to obtain first shift result data.

For example, the first result data 100_1001_0010 is shifted left by (6+5) bits, and the resulting first shift result data may be 10_0100_1001_0000_0000_0000.

In the embodiment of the disclosure, the second result data may be shifted left by K bits to obtain second shift result data.

For example, the second result data 1110_1010 is shifted left by 6 bits, and the resulting second shift result data may be 0_0011_1010_1000_0000.

In the embodiment of the disclosure, the third result data may be shifted left by L bits to obtain third shift result data.

For example, the third result data 000_0111_1000 is shifted left by 5 bits, and the resulting third shift result data may be 0000_1111_0000_0000.

In the embodiment of the present disclosure, the first shift result data, the second shift result data, the third shift result data, and the fourth result data may be added to obtain a product.

For example, the first shift result data 10_0100_1001_0000_0000 may be added to the fourth result data 000_0001_1000, resulting in a first value of 10_0100_1001_0000_0001_1000. The decimal number corresponding to the first value is 2396184.

The second shift result data 0_0011_1010_1000_0000 and the third shift result data 0000_1111_0000 may be added to obtain a second value 100100110000000. The decimal number corresponding to the second value is 18816.

And adding the first value and the second value to obtain a product. The product may be 1001001101100110011000. The decimal number corresponding to the product is 241500

According to the embodiment of the disclosure, the two large-bit-width data are split into the plurality of small-bit-width data, so that the operation efficiency can be effectively improved, the problem of time sequence violation can be solved, and the working efficiency of the chip is improved.

In some embodiments, the input data may include light intensity data and the output data may include voltage data.

FIG. 5 is a block diagram of a data processing circuit according to one embodiment of the present disclosure.

As shown in fig. 5, the circuit 500 includes an input sub-circuit 510, a conversion sub-circuit 520, and an output sub-circuit 530.

An input sub-circuit 510 for receiving input data, the input data being M-bit data.

A conversion sub-circuit 520 for converting the input data into output data according to a first mode, the output data being N-bit data, where M is greater than N, when the value of the input data is equal to or less than a predetermined threshold value; and converting the input data into the output data according to a second mode when the value of the input data is greater than the predetermined threshold.

An output sub-circuit 530 for outputting the output data.

Fig. 6 is a block diagram of a data processing circuit in another embodiment according to the present disclosure.

As shown in fig. 6, the difference from the circuit 500 is that the number of conversion sub-circuits in the circuit 600 is 3.

As shown in fig. 6, the circuit 600 includes an input sub-circuit 610, a conversion sub-circuit 621, a conversion sub-circuit 622, a conversion sub-circuit 623, and an output sub-circuit 630. The above description of the input sub-circuit 510, the conversion sub-circuit 520, and the output sub-circuit 530 applies equally to the input sub-circuit 610, the conversion sub-circuit 621, the conversion sub-circuit 622, the conversion sub-circuit 623, and the output sub-circuit 630, and the disclosure is not repeated here.

In the disclosed embodiment, the circuit 600 may further include a color matching sub-circuit 641, a color matching sub-circuit 642, and a color matching sub-circuit 643. The color matching sub-circuit 641 is for determining whether the input data is data of a red color channel (R), the color matching sub-circuit 642 is for determining whether the input data is data of a green color channel, and the color matching sub-circuit 643 is for determining whether the input data is data of a blue color channel.

For example, taking as an example the data of which the input data is the red channel, the color matching sub-circuit 641 determines that the input data is the data of the red channel. Next, the input data is converted by the conversion sub-circuit 621 to obtain output data.

In some embodiments, the conversion sub-circuit includes: a first determining unit configured to determine a numerical range of the output data; a dividing unit for dividing the numerical range of the output data into a plurality of numerical intervals; a second determining unit configured to determine a target section corresponding to the input data from among the plurality of numerical sections, based on a size of the input data; and a third determination unit configured to determine the output data based on a lower limit value of the target section.

In some embodiments, the conversion sub-circuit further includes: and fourth determining means for determining the output data based on the size of the input data, the lower limit value of the target section, and the upper limit value of the target section.

In some embodiments, the dividing unit is configured to divide the plurality of numerical intervals at equal intervals.

In some embodiments, the dividing unit is configured to divide the plurality of numerical intervals at unequal intervals.

In some embodiments, the fourth determining unit is further configured to: calculating a product by using a difference between the input data and a lower limit value of the target section as a multiplicand and a difference between an upper limit value of the target section and a lower limit value of the target section as a multiplier; and determining the output data based on the product.

In some embodiments, the fourth determining unit is further configured to: dividing the multiplicand of M bits into first high-bit data of (M-K) bits and first low-bit data of K bits, K being an integer greater than 1 and less than M; dividing the multiplier of N bits into second high-bit data of (N-L) bits and second low-bit data of L bits, wherein L is an integer greater than 1 and less than N; calculating the product of the first high-bit data and the second high-bit data to obtain first result data; calculating the product of the first high-bit data and the second low-bit data to obtain second result data; calculating the product of the first low-bit data and the second high-bit data to obtain third result data; calculating the product of the first low-bit data and the second low-bit data to obtain fourth result data; and obtaining the product according to the first result data, the second result data, the third result data and the fourth result data.

In some embodiments, the fourth determining unit is further configured to: shifting the first result data left by (K+L) bits to obtain first shift result data; shifting the second result data left by K bits to obtain second shift result data; shifting the third result data left by L bits to obtain third shift result data; and adding the first shift result data, the second shift result data, the third shift result data and the fourth result data to obtain the product.

In some embodiments, the input sub-circuit includes M pins for receiving M bits of light intensity data; the output sub-circuit comprises N pins for outputting N-bit voltage data.

Fig. 7 is a block diagram of a data processing apparatus according to one embodiment of the present disclosure.

As shown in fig. 7, the apparatus 700 includes an acquisition module 710, a first conversion module 720, and a second conversion module 730.

The acquisition module 710 is configured to acquire input data, where the input data is M-bit data.

A first conversion module 720, configured to convert the input data into output data according to a first mode when the value of the input data is less than or equal to a predetermined threshold, where M is greater than N.

And a second conversion module 730, configured to convert the input data into the output data according to a second mode when the value of the input data is greater than the predetermined threshold.

In some embodiments, the first conversion module comprises: a first determining sub-module for determining a numerical range of the output data; the first dividing sub-module is used for dividing the numerical range of the output data into a plurality of numerical intervals; the second determining submodule is used for determining a target interval corresponding to the input data in the numerical intervals according to the size of the input data; and a third determining submodule, configured to determine the output data according to a lower limit value of the target interval.

In some embodiments, the second conversion module comprises: a fourth determining submodule for determining a numerical range of the output data; the second dividing sub-module is used for dividing the numerical range of the output data into a plurality of numerical intervals; a fifth determining submodule, configured to determine a target interval corresponding to the input data in the plurality of numerical intervals according to the size of the input data; and a sixth determining submodule, configured to determine the output data according to the size of the input data, the lower limit value of the target section, and the upper limit value of the target section.

In some embodiments, the plurality of numerical intervals are equally spaced apart.

In some embodiments, the plurality of numerical intervals are non-equally spaced apart.

In some embodiments, the sixth determination submodule includes: the obtaining unit is used for obtaining a multiplicand according to the input data; a calculation unit configured to calculate a product from a multiplicand and a multiplier, using a difference between an upper limit value of the target section and a lower limit value of the target section as the multiplier; and a determining unit configured to determine the output data according to the product.

In some embodiments, the computing unit comprises: a first dividing subunit for dividing the multiplicand of M bits into first high-bit data of (M-K) bits and first low-bit data of K bits, K being an integer greater than 1 and less than M; a second dividing subunit for dividing the multiplier of N bits into second high-bit data of (N-L) bits and second low-bit data of L bits, L being an integer greater than 1 and less than N; the first calculating subunit is used for calculating the product of the first high-bit data and the second high-bit data to obtain first result data; a second calculating subunit, configured to calculate a product of the first high-bit data and the second low-bit data to obtain second result data; a third calculation subunit, configured to calculate a product of the first low-bit data and the second high-bit data to obtain third result data; a fourth calculating subunit, configured to calculate a product of the first low-bit data and the second low-bit data to obtain fourth result data; and an obtaining subunit, configured to obtain the product according to the first result data, the second result data, the third result data, and the fourth result data.

In some embodiments, the obtaining subunit is further configured to: shifting the first result data left by (K+L) bits to obtain first shift result data; shifting the second result data left by K bits to obtain second shift result data; shifting the third result data left by L bits to obtain third shift result data; and adding the first shift result data, the second shift result data, the third shift result data and the fourth result data to obtain the product.

In some embodiments, the input data comprises light intensity data and the output data comprises voltage data.

Fig. 8 schematically illustrates a block diagram of an electronic device adapted to implement the above-described method according to an embodiment of the present disclosure. The electronic device shown in fig. 8 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.

As shown in fig. 8, an electronic device 800 according to an embodiment of the present disclosure includes a processor 801 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 802 or a program loaded from a storage section 808 into a Random Access Memory (RAM) 803. The processor 801 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or an associated chipset and/or special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. The processor 801 may also include on-board memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing the different actions of the method flows according to embodiments of the disclosure.

In the RAM 803, various programs and data required for the operation of the electronic device 800 are stored. The processor 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. The processor 801 performs various operations of the method flow according to the embodiments of the present disclosure by executing programs in the ROM 802 and/or the RAM 803. Note that the program may be stored in one or more memories other than the ROM 802 and the RAM 803. The processor 801 may also perform various operations of the method flows according to embodiments of the present disclosure by executing programs stored in the one or more memories.

According to an embodiment of the present disclosure, the electronic device 800 may also include an input/output (I/O) interface 805, the input/output (I/O) interface 805 also being connected to the bus 804. The system 800 may also include one or more of the following components connected to the I/O interface 805: an input portion 806 including a keyboard, mouse, etc.; an output portion 807 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and a speaker; a storage section 808 including a hard disk or the like; and a communication section 809 including a network interface card such as a LAN card, a modem, or the like. The communication section 809 performs communication processing via a network such as the internet. The drive 810 is also connected to the I/O interface 805 as needed. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 810 as needed so that a computer program read out therefrom is mounted into the storage section 808 as needed.

According to embodiments of the present disclosure, the method flow according to embodiments of the present disclosure may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section 809, and/or installed from the removable media 811. The above-described functions defined in the system of the embodiments of the present disclosure are performed when the computer program is executed by the processor 801. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

The present disclosure also provides a computer-readable storage medium that may be embodied in the apparatus/device/system described in the above embodiments; or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs which, when executed, implement methods in accordance with embodiments of the present disclosure.

According to embodiments of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples may include, but are not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

For example, according to embodiments of the present disclosure, the computer-readable storage medium may include ROM 802 and/or RAM 803 and/or one or more memories other than ROM 802 and RAM 803 described above.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be combined in various combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

A data processing method, comprising:

acquiring input data, wherein the input data is M-bit data;

converting the input data into output data according to a first mode under the condition that the value of the input data is smaller than or equal to a preset threshold value, wherein the output data is N-bit data, and M is larger than N; and

and converting the input data into the output data according to a second mode in the case that the value of the input data is larger than the preset threshold value.
The method of claim 1, wherein said converting the input data into output data in a first mode if the value of the input data is less than a predetermined threshold comprises:

Determining a numerical range of the output data;

dividing the numerical range of the output data into a plurality of numerical intervals;

determining a target interval corresponding to the input data in the numerical intervals according to the size of the input data; and

and determining the output data according to the lower limit value of the target interval.
The method of claim 1, wherein said converting said input data into said output data in a second mode if the value of said input data is greater than said predetermined threshold comprises:

determining a numerical range of the output data;

dividing the numerical range of the output data into a plurality of numerical intervals;

determining a target interval corresponding to the input data in the numerical intervals according to the size of the input data; and

and determining the output data according to the size of the input data, the lower limit value of the target interval and the upper limit value of the target interval.
A method according to claim 2 or 3, wherein the plurality of numerical intervals are equally spaced apart.
A method according to claim 2 or 3, wherein the plurality of numerical intervals are non-equally spaced apart.
A method according to claim 3, wherein said determining said output data according to the size of said input data, the lower limit value of said target interval and the upper limit value of said target interval comprises:

obtaining a multiplicand according to the input data;

taking the difference between the upper limit value of the target interval and the lower limit value of the target interval as a multiplier, and calculating a product according to the multiplicand and the multiplier; and

and determining the output data according to the product.
The method of claim 6, wherein the calculating a product using a difference between the input data and a lower value of the target interval as a multiplicand and a difference between an upper value of the target interval and a lower value of the target interval as a multiplier comprises:

dividing the multiplicand of M bits into first high-bit data of (M-K) bits and first low-bit data of K bits, K being an integer greater than 1 and less than M;

dividing the multiplier of N bits into second high-bit data of (N-L) bits and second low-bit data of L bits, wherein L is an integer greater than 1 and less than N;

calculating the product of the first high-bit data and the second high-bit data to obtain first result data;

Calculating the product of the first high-bit data and the second low-bit data to obtain second result data;

calculating the product of the first low-bit data and the second high-bit data to obtain third result data;

calculating the product of the first low-bit data and the second low-bit data to obtain fourth result data; and

and obtaining the product according to the first result data, the second result data, the third result data and the fourth result data.
The method of claim 7, wherein the deriving the product from the first, second, third, and fourth result data comprises:

shifting the first result data left by (K+L) bits to obtain first shift result data;

shifting the second result data left by K bits to obtain second shift result data;

shifting the third result data left by L bits to obtain third shift result data; and

and adding the first shift result data, the second shift result data, the third shift result data and the fourth result data to obtain the product.
The method of claim 1, wherein the input data comprises light intensity data and the output data comprises voltage data.
A data processing circuit, comprising:

an input sub-circuit for receiving input data, the input data being M-bit data;

a conversion sub-circuit for converting the input data into output data according to a first mode, the output data being N-bit data, where M is greater than N, in a case where a value of the input data is equal to or less than a predetermined threshold; and converting the input data into the output data according to a second mode if the value of the input data is greater than the predetermined threshold; and

and the output sub-circuit is used for outputting the output data.
The circuit of claim 10, wherein the conversion sub-circuit comprises:

a first determining unit configured to determine a numerical range of the output data;

a dividing unit for dividing the numerical range of the output data into a plurality of numerical intervals;

a second determining unit configured to determine a target section corresponding to the input data from among the plurality of numerical sections according to a size of the input data; and

and a third determining unit for determining the output data according to the lower limit value of the target section.
The circuit of claim 11, wherein the conversion sub-circuit further comprises:

And a fourth determining unit configured to determine the output data according to the size of the input data, the lower limit value of the target section, and the upper limit value of the target section.
The circuit according to claim 11 or 12, wherein the dividing unit is configured to divide a plurality of numerical intervals at equal intervals.
The circuit of claim 11 or 12, wherein the dividing unit is configured to divide the plurality of numerical intervals at unequal intervals.
The circuit of claim 12, wherein the fourth determination unit is further configured to:

obtaining a multiplicand according to the input data;

taking the difference between the upper limit value of the target interval and the lower limit value of the target interval as a multiplier, and calculating a product according to the multiplicand and the multiplier; and

and determining the output data according to the product.
The circuit of claim 15, wherein the fourth determination unit is further configured to:

dividing the multiplicand of M bits into first high-bit data of (M-K) bits and first low-bit data of K bits, K being an integer greater than 1 and less than M;

dividing the multiplier of N bits into second high-bit data of (N-L) bits and second low-bit data of L bits, wherein L is an integer greater than 1 and less than N;

Calculating the product of the first high-bit data and the second high-bit data to obtain first result data;

calculating the product of the first high-bit data and the second low-bit data to obtain second result data;

calculating the product of the first low-bit data and the second high-bit data to obtain third result data;

calculating the product of the first low-bit data and the second low-bit data to obtain fourth result data; and

and obtaining the product according to the first result data, the second result data, the third result data and the fourth result data.
The circuit of claim 16, wherein the fourth determination unit is further configured to:

shifting the first result data left by (K+L) bits to obtain first shift result data;

shifting the second result data left by K bits to obtain second shift result data;

shifting the third result data left by L bits to obtain third shift result data; and

and adding the first shift result data, the second shift result data, the third shift result data and the fourth result data to obtain the product.
The circuit of claim 10, wherein the input sub-circuit comprises M pins for receiving M bits of light intensity data; the output sub-circuit includes N pins for outputting N-bit voltage data.
A data processing apparatus comprising:

the acquisition module is used for acquiring input data, wherein the input data is M-bit data;

a first conversion module, configured to convert, in a first mode, the input data into output data, where the output data is N-bit data, and M is greater than N, where the value of the input data is equal to or less than a predetermined threshold; and

and the second conversion module is used for converting the input data into the output data according to a second mode under the condition that the numerical value of the input data is larger than the preset threshold value.
An electronic device, comprising:

one or more processors;

a memory for storing one or more programs,

wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any of claims 1 to 9.
A computer readable storage medium having stored thereon executable instructions which, when executed by a processor, cause the processor to implement the method of any of claims 1 to 9.
A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 1 to 9.