CN100550622C - The digital signal filtering apparatus and the method that have down sampling function - Google Patents
The digital signal filtering apparatus and the method that have down sampling function Download PDFInfo
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- CN100550622C CN100550622C CNB2006100262936A CN200610026293A CN100550622C CN 100550622 C CN100550622 C CN 100550622C CN B2006100262936 A CNB2006100262936 A CN B2006100262936A CN 200610026293 A CN200610026293 A CN 200610026293A CN 100550622 C CN100550622 C CN 100550622C
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Abstract
The invention discloses a kind of digital signal filtering apparatus and method that has down sampling function, this digital signal filtering apparatus comprises that signal access address generative circuit, signal storage circuit, filter coefficient read address generating circuit, filter coefficient register circuit, multiplier, accumulator and output control circuit.The present invention can realize the integrated high-efficiency processing of digital signal filter and down-sampling, and can drop to the amount of hardware resources that realizes function of the present invention minimum.
Description
Technical field
The present invention relates to digital signal filter, the effective integrated processing unit and the method for especially a kind of integrated filter and down sampling function.
Background technology
In Digital Signal Processing (DSP), there are a large amount of different digital signal filter devices to be used.In some applications, may occur and to carry out filtering, also will make the situation that down-sampling is handled simultaneously signal signal.Filtering mainly is that signal is handled, thereby changes some characteristics of signal itself, and for example, primary signal possibility noise is bigger, through after the Filtering Processing, noise is diminished.Down-sampling is to change signals sampling speed, for example, the sample rate of primary signal is 50MHz, also be that per second is sampled 5,000 ten thousand times, and may do not need so high sample frequency in the practical application, so, carry out the down-sampling processing and make its frequency drop to needed value, such as, 20MHz, the sample rate of per second 2,000 ten thousand times just.Reduce after the sample rate, the data volume in the unit interval can descend, and therefore under the constant situation of other conditions, needed operand also correspondingly descends.In GPS (Global Position System) (GPS), such demand is just arranged, promptly primary signal is carried out filtering and down-sampling.
Traditional signal processing is after finishing Filtering Processing, carries out down-sampling again and handles, and will take a large amount of hardware resources like this.The FIR filter that with length is n is the example (length of filter, also be the sequence number of unit impulse response function associated therewith), as shown in Figure 1, unit impulse response function is h (n), input signal is X (i), then finish this Filtering Processing process, need n multiplying and the computing of n-1 sub-addition, thereby on hardware circuit is realized, except the register circuit of storage signal and filter factor, also need n multiplier and n-1 adder, to finish Filtering Processing process to input signal X (i), again to through filtered signal Y (i) by a downsampling device carry out down-sampling handle thereafter.
Summary of the invention
Purpose of the present invention, the integrated apparatus that is to provide a kind of digital signal filter and down-sampling to handle, this device can be finished in circuit kit the filtering of input high-frequency digital signal and the efficient processing of down-sampling simultaneously with minimum hardware resource.
The digital signal filtering apparatus that has down sampling function of the present invention comprises:
One signal access address generative circuit is used for correct access signal;
One signal storage circuit is connected with described signal access address generative circuit, is used for the buffer memory input signal, and this signal is exported to subsequent process circuit with the clock frequency of the frequency of different and signal;
One filter coefficient reads address generating circuit, is used for correctly reading the filter coefficient of storage;
One filter coefficient register circuit reads address generating circuit with described filter coefficient and is connected, and is used for the corresponding coefficient of correct storage based on different filters;
One multiplier is connected with described signal storage circuit and filter register circuit, is used for input signal and filter coefficient are multiplied each other;
One accumulator is connected with described multiplier, is used for the result of product of multiplier is added up;
One output control circuit is connected with described accumulator, is used for preserving selectively and exporting accumulation result, to guarantee the correctness through the signal of filtering and down-sampling processing.
Another object of the present invention is to provide a kind of filter and down-sampling incorporate high-efficient treatment method, may further comprise the steps:
1, determines the step of processed clock signal frequency, signal output clock frequency, sign register minimum capacity and filter coefficient register minimum capacity;
2, with the step of filter coefficient writing filtering device coefficient register;
3, produce signal by signal access address generative circuit and write the address and read the address, and this is write the address and read the address and send into sign register and write step with read output signal;
4, in execution in step 3, read address generating circuit by filter coefficient and produce coefficient and read the address, and the step that this address is delivered to the filter coefficient register and read filter coefficient;
5, the signal that above-mentioned steps 3 is read carries out the step of multiplication mutually with the coefficient that step 4 is read;
6, the multiplied result of above-mentioned steps 5 is carried out the step of accumulating operation;
7, utilize the step of accumulation result in the output control circuit output above-mentioned steps 6.
The present invention can realize the integrated high-efficiency processing of digital signal filter and down-sampling, and can drop to the amount of hardware resources that realizes function of the present invention minimum.
Description of drawings
Fig. 1 is the schematic diagram of existing filtering and down-sampling processing procedure;
Fig. 2 is filtering of the present invention and downsampling device schematic diagram;
Fig. 3 is that filtering of the present invention and down sampling function are implemented schematic diagram.
Embodiment
As shown in Figure 1, the digital signal filtering apparatus that has down sampling function of the present invention comprises that signal access address generative circuit, signal storage circuit, filter coefficient read address generating circuit, filter coefficient register circuit, multiplier, accumulator and output control circuit.Signal access address generative circuit is used for correct access signal, signal storage circuit is used for the buffer memory input signal, and this signal exported to subsequent process circuit with the clock frequency of the frequency that is different from input signal, filter coefficient reads the filter coefficient that address generating circuit is used for correctly reading storage, the filter coefficient register circuit reads the address register circuit with filter coefficient and is connected, be used to read the corresponding coefficient of filter, multiplier is connected with the filter coefficient register circuit with signal storage circuit, be used for signal and filter coefficient are multiplied each other, accumulator is connected with multiplier, be used for the result of product of multiplier is added up, output control circuit is connected with accumulator, be used for preserving selectively and exporting accumulation result, to guarantee correctness through the signal of filtering and down-sampling processing.
The capacity of signal storage circuit (bit bit) is by the length N (N is a non-zero positive integer) and the input signal bit wide Ws decision of filter, and here, N also is the address sum of signal storage circuit, and Ws is the bit number of each address.Therefore, the capacity of signal storage circuit is N * Ws bit.
The capacity of filter coefficient register circuit is relevant with the length N of filter and filter coefficient bit wide Wf, and its minimum capacity is N * Wf bit.
Below in conjunction with above device, describe the processing method that filtering of the present invention and down-sampling combine in detail.This method may further comprise the steps:
1, determines the step of processed clock signal frequency (fp), sign register capacity and filter coefficient register length.Comprise step according to input signal sample frequency, down-sampling multiple and filter length decision processed clock signal frequency f p, according to the step of filter length and input signal bit wide decision sign register minimum capacity, and according to the step of filter length and filter coefficient bit wide decision filter coefficient register minimum capacity.
Particularly, if the input signal sample frequency is fin, the down-sampling multiple is M, and filter length is N, and then processed clock signal frequency f p is:
fp＝(fin/M)×N
Wherein M and N are non-zero positive integer.
Chatting as mentioned, is N * Ws bit according to the sign register minimum capacity of filter length N and input signal bit wide Ws decision, is N * Wf bit according to the minimum capacity of the filter coefficient register of filter length N and filter factor signal bit wide Wf decision.
2,, mainly be with filter coefficient writing filtering device coefficient register by CPU or other control devices with the step of filter coefficient writing filtering device coefficient register.
3, produce signal by signal access address generative circuit and write the address, and this is write the step that sign register is sent in the address.Particularly, signal access address generative circuit with signal input clock frequency fin from 0 to N-1 again to 0, produce sign register so again and again and write the address, and it is delivered to the address bus that sign register is write inbound port, simultaneously by this address with the frequency write signal register of current demand signal with fin.
Simultaneously, signal access address generative circuit produces signal with processed clock signal frequency f p and reads the address.Particularly, from a certain initial address i (0＜=i＜=N-1), increase progressively (N is a filter length) N-1 time with step-length 1, also promptly reading the address is i, i+1, i+2..., N-2, N-1,0,1,2...i-1, whenever increase progressively and once all read corresponding data give subordinate's circuit from sign register, this is once circulation.Circulation is so again and again read, and just the initial address of each circulation is the initial address+M mod N of last circulation, i.e. i+M mod N (X mod N is the remainder after X is removed by N, also promptly to the result of X with the N delivery).
Particularly, after the loop ends first time, signal access address generative circuit produces a new initial address, and i+M also is that current initial address has stepped into the M step-length forward.With above-described identical like that, increase progressively with step-length 1 and to produce the address, read the address and be: (i+M) mod N, (i+M+1) mod N, (i+M+2) mod N..., N-2, N-1,0,1..., (i+M-1) modN.
Come out then to read and increase progressively the address and be as the address continuous representation of reading that twice circulation in above-mentioned front and back produced: i, i+1, i+2..., N-2, N-1,0,1,2...i-1, (i+M) mod N, (i+M+1) mod N, (i+M+2) mod N..., (i+M+N-1) mod N.Here, address generating circuit according to the down-sampling multiple after producing one group of N continuation address, at current group N, also promptly work as initial address (for example, N=32, the M=8 that adds (M+1) on last basis, address of last group thereby produce follow-up one group of N continuation address, when last group initial address is 1, add 1 then continuously and reach 31 until the address, and get back to 0, finish when reading of last group of data this moment.Next group data will be since 9, add 1 then continuously and reach 31 until the address, and get back to 0, add 1 more continuously and reach 8 until the address, this is next group data), thereby, simultaneously this address is delivered to sign register and read corresponding signal for the address of reading of realizing that function that filtering and down-sampling are finished simultaneously correctly produces signal.
4, in execution in step 3, read address generating circuit by filter coefficient and produce coefficient and read the address, and the step that this address is delivered to the filter coefficient register and read filter coefficient.Filter coefficient reads address generating circuit and reads the address with processed clock signal frequency f p generation from the coefficient that 0 to N-1 recirculation repeats, and delivers to the filter coefficient register circuit, thereby reads filter coefficient.
5, the coefficient of reading in the above-mentioned signal of reading and the filter coefficient register is carried out the step of multiplication mutually from signal storage circuit, can realize by a multiplier.
6, to carry out the step of accumulating operation through the result of product behind the phase multiplication, can realize by an accumulator.
7, accumulation result is exported the step of above-mentioned accumulation result with the FREQUENCY CONTROL of fout=fin/M (being the down-sampling frequency) by an output control circuit.
Below in conjunction with specific embodiment the method for above-described filtering and down-sampling is described, to enable those skilled in the art to implement more easily the present invention.
This embodiment is applied in the GPS receiver input digital intermediate frequency signal be carried out in the physical circuit of filtering and down-sampling processing.Usually, the GPS receiver receives the radiofrequency signal that comes from global positioning satellite system, converts radiofrequency signal to intermediate-freuqncy signal by a radio circuit, then, again this intermediate-freuqncy signal is carried out filtering and down-sampling processing, and the signal conveys after will handling is in follow-up processing module.
In the present embodiment, the sample frequency fin=16.368MHz of supplied with digital signal, the bit wide of supplied with digital signal is Ws=3bit, filter length is N=16, filter coefficient bit wide Wf=6bit, down-sampling multiple M=4.Thereby according to above-mentioned formula fp=(fin/M) * N, calculate processed clock signal frequency f p=65.472MHz, draw the big or small N * Ws=16 * 3bit of being of sign register according to filter length N and input signal bit wide Ws, this example is selected 16 addresses, the dual ported register of 3 bits is deposited in each address, writing the end clock frequency is fin=16.368MHz, and reading the end clock is fp=65.472MHz.Write termination and receive input signal, read the end output signal, write and read address generating circuit control with read operation by signal and finish to multiplier.
According to filter length and filter factor bit wide decision filter coefficient register size, in the present embodiment, filter coefficient bit wide Wf is 6 bits, then the filter coefficient register size is N * Wf=16 * 6 bits, therefore, can select 16 addresses, the dual ported register of 6 bits is deposited in each address, it writes to hold and is connected with the embedded type CPU bus, and by CPU or other control device writing filtering device coefficients, writing clock frequency is CPU or other control device clock frequencies; Read the end output signal to multiplier, read operation is read address generating circuit control by filter coefficient and is finished, and readout clock is fp=65.472MHz.
Before circuit working, by embedded type CPU with filter coefficient with inverted order mode writing filtering device coefficient register circuit, i.e. N coefficient of address 0 storage, N-1 coefficient stored in address 1, by that analogy, stores the 1st coefficient until address N-1.
After starting working, signal reads address generating circuit and circulates continuously with the frequency of fin=16.368MHz and produce from 0 to 15 the address that writes, thereby control writes input signal to the input signal register circuit; Simultaneously, signal reads address generating circuit, and to produce with 16 continuously with the speed of fp=65.472MHz be one group address, after finishing the generation of a group address, the first address of next addresses jumps to the address of current address+M+1 according to down-sampling multiple M, continue then to read the address, so move in circles with 16 of the frequency generations of fp=65.472MHz.Sign register is read end and is read input signal according to this address, and sends into follow-up multiplier circuit.
Simultaneously, filter coefficient access address generative circuit produces 0 to 15 the address of reading with the frequency of fp=65.472MHz and is sent to the filter coefficient register circuit and reads end, so that correct filter coefficient is sent to follow-up multiplier circuit.
Thereafter, multiplier carries out multiplication mutually with input signal with filter coefficient, and the result is outputed in the accumulator circuit of back.
Accumulator circuit is read the address with the frequency of fp=65.472MHz according to filter coefficient, carries out the accumulating operation of continuous 16 multiplication results.
At last, output control circuit is exported the above-mentioned accumulation result of having finished 16 computings with the clock frequency of fout=4.092MHz, thereby finish the filtering and the down-sampling of input signal is handled.
In sum, the present invention can realize the integrated processing of digital signal filter and down-sampling, and can save hardware resource substantially, in the various occasions that need Digital Signal Processing, especially in Treatment Analysis, have broad application prospects to gps signal.
Should be noted that above embodiment only in order to technical scheme of the present invention to be described, and need not limit scope of the present invention in advance.Although the present invention is described in detail with reference to embodiment; understand easily, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention; therefore, it all should be encompassed in the claim protection range of the present invention.
Claims (9)
1, a kind of digital signal filtering apparatus that has down sampling function is characterized in that, this device comprises:
One signal access address generative circuit is used for correct access signal;
One signal storage circuit is connected with described signal access address generative circuit, is used for the buffer memory input signal, and this signal is exported to subsequent process circuit with the clock frequency of the frequency that is different from input signal;
One filter coefficient reads address generating circuit, is used for correctly reading the filter coefficient of storage;
One filter coefficient register circuit reads address generating circuit with described filter coefficient and is connected, and is used for the corresponding coefficient of correct storage based on different filters;
One multiplier is connected with described signal storage circuit and filter coefficient register circuit, is used for input signal and filter coefficient are multiplied each other;
One accumulator is connected with described multiplier, is used for the result of product of multiplier is added up;
One output control circuit is connected with described accumulator, is used for preserving selectively and exporting accumulation result, to guarantee the correctness through the signal of filtering and down-sampling processing;
Wherein, described signal access address generative circuit produces signal with signal input clock frequency fin and writes the address, produce signal with processed clock signal frequency f p and read the address, and Xun Huan signal reads the initial address of address and steps into the MmodN step-length than the initial address that the last signal that circulates reads the address next time, wherein, M is the down-sampling multiple, and N is a filter length, and mod is for asking modular arithmetic.
2, digital signal filtering apparatus as claimed in claim 1, it is characterized in that, the capacity of described signal storage circuit is by the length of described filter and the bit wide decision of described input signal, and its minimum capacity is the product of described filter length and described input signal bit wide.
3, digital signal filtering apparatus as claimed in claim 1, it is characterized in that, the capacity of described filter coefficient register circuit is relevant with the coefficient bit wide of the length of described filter and described filter, and its minimum capacity is the product of described filter length and described filter coefficient bit wide.
4, digital signal filtering apparatus as claimed in claim 1 is characterized in that, described filter coefficient writes described filter coefficient register circuit by an embedded type CPU or other control devices.
5, the method for a kind of filter and the integrated processing of down-sampling is characterized in that, this method comprises:
(1), determines the step of processed clock signal frequency, signal output clock frequency, sign register capacity and filter coefficient register length;
(2), with the step of filter coefficient writing filtering device coefficient register;
(3), produce signal by signal access address generative circuit and write the address and read the address, and this is write the address and reads the step that sign register is sent in the address;
(4), in execution in step (3), read address generating circuit by filter coefficient and produce coefficient and read the address, and the step that this address is delivered to the filter coefficient register and read filter coefficient;
(5), the signal that above-mentioned steps (3) is read carries out the step of multiplication mutually with the coefficient that step (4) is read;
(6), the multiplied result of above-mentioned steps (5) is carried out the step of accumulating operation;
(7), utilize the step of accumulation result in the output control circuit output above-mentioned steps (6);
Wherein, described signal access address generative circuit produces signal with signal input clock frequency fin and writes the address, produce signal with processed clock signal frequency f p and read the address, and Xun Huan signal reads the initial address of address and steps into the MmodN step-length than the initial address that the last signal that circulates reads the address next time, wherein, M is the down-sampling multiple, and N is a filter length, and mod is for asking modular arithmetic.
6, method as claimed in claim 5 is characterized in that, described processed clock signal frequency f p satisfies equation: fp=(fin/M) * N.
7, method as claimed in claim 5 is characterized in that, the capacity of described sign register is by the length of described filter and the bit wide decision of described input signal, and its minimum capacity is the product of described filter length and described input signal bit wide.
8, method as claimed in claim 5, it is characterized in that, the capacity of described filter coefficient register is relevant with the coefficient bit wide of the length of described filter and described filter, and its minimum capacity is the product of described filter length and described filter coefficient bit wide.
9, method as claimed in claim 5 is characterized in that, described filter coefficient writes described filter coefficient register by an embedded type CPU or other control devices.
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| CN101919706B (en) * | 2009-06-12 | 2014-05-07 | 深圳迈瑞生物医疗电子股份有限公司 | Decimating filtering method and decimating filter |
| CN110212889B (en) * | 2019-05-29 | 2020-11-13 | 北京机电工程研究所 | Digital signal sampling device and method |
| CN112152589B (en) * | 2019-06-28 | 2023-10-13 | 宏碁股份有限公司 | Signal processing device and signal processing method |
| CN110620565A (en) * | 2019-08-09 | 2019-12-27 | 西人马帝言(北京)科技有限公司 | Digital extraction filter |
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Owner name: RDA MICROELECTRONICS( SHANGHAI ) CO., LTD. Free format text: FORMER OWNER: NAWEI MICROELECTRONICS SCIENCE AND TECHNOLOGY( SHANGHAI ) CO., LTD. Effective date: 20100115 |
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Effective date of registration: 20100115 Address after: Room 2, building 690, No. 302 blue wave road, Zhangjiang hi tech park, Shanghai, China Patentee after: RDA Microelectronics (Shanghai) Corp. Ltd. Address before: Room 81, No. 703 Qinzhou South Road, Shanghai Patentee before: NavAsic Microelectronics (Shanghai), Inc. |