WO2019119456A1 - 薄膜晶体管、阵列基板及显示屏 - Google Patents

薄膜晶体管、阵列基板及显示屏 Download PDF

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WO2019119456A1
WO2019119456A1 PCT/CN2017/118130 CN2017118130W WO2019119456A1 WO 2019119456 A1 WO2019119456 A1 WO 2019119456A1 CN 2017118130 W CN2017118130 W CN 2017118130W WO 2019119456 A1 WO2019119456 A1 WO 2019119456A1
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grooves
thin film
film transistor
active layer
source
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French (fr)
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邱昌明
尹翔
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2017/118130 priority Critical patent/WO2019119456A1/zh
Priority to CN201780097389.8A priority patent/CN111433917A/zh
Publication of WO2019119456A1 publication Critical patent/WO2019119456A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

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  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate, and a display screen.
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • TFT Thin Film Transistor
  • the thermal conductivity of the two materials themselves is very low, and the self-heating effect due to the Joule heat of the current is generated when the TFT device operates, and the center position of the channel region is Difficulties cause severe self-heating effects due to heat dissipation, resulting in local overheating, degrading TFT device performance, such as reduced on-state current, increased leakage current, and threshold voltage shift.
  • Embodiments of the present invention provide a thin film transistor, an array substrate, and a display screen that improve heat dissipation.
  • a thin film transistor includes a substrate, a gate electrode on a surface of the substrate, a gate insulating layer covering the gate electrode, an active layer and an etch barrier layer sequentially laminated on the gate insulating layer And a source and a drain disposed at intervals of the etch stop layer;
  • the etch barrier layer is provided with two symmetrically spaced through grooves, and the source and the drain are respectively connected to the active layer through two through grooves; between the two through grooves The length dimension of the pitch is reduced by the center position of the through groove toward the width of the active layer.
  • the thin film transistor of the present invention is provided as a non-linear through groove by connecting a source and a drain to the active layer, and a size of a pitch between the two through grooves is determined by a center position of the through groove
  • the width extension direction of the active layer is reduced, thereby increasing the channel length at the center position of the channel region, enhancing the heat dissipation capability of the center position of the channel region during operation of the TFT device, and improving the performance degradation of the TFT device caused by local overheating.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor provided by the present invention.
  • FIG. 2 is a top plan view showing an embodiment of the thin film transistor shown in FIG. 1;
  • FIG. 3 is a top plan view showing another embodiment of the thin film transistor shown in FIG. 1;
  • FIG. 4 is a top plan view showing a third embodiment of the thin film transistor shown in FIG. 1.
  • Embodiments of the present invention provide a thin film transistor for driving a pixel circuit and a driving circuit of an array substrate.
  • the array substrate may be a substrate of a liquid crystal display or an organic light emitting diode display.
  • a thin film transistor includes a substrate 10 , a gate 11 disposed on an upper surface of the substrate 10 , a substrate 11 and a gate 11 , and covering the gate 11 .
  • the gate insulating layer 12 is sequentially laminated on the active layer 13 (semiconductor layer) of the gate insulating layer 12 and the etching stopper layer 14, and the gate insulating layer 12 can insulate the gate electrode 11 and the active layer 13.
  • the thin film transistor further includes a source 17 and a drain 18 which are disposed at the etch stop layer 14 and are spaced apart.
  • the projection of the gate 11 on the plane of the active layer 13 is covered by the active layer 13 for the purpose that the active layer 13 can completely cover the gate 11 for protecting the gate 11.
  • the source 17 faces the edge of the drain 18 and is flush with one side 111 of the gate 11.
  • the drain 18 faces the edge of the source 17 and the gate. 11 the other side 111 is flush so that the overlapping area between the source 17 and the drain 18 and the gate 11 in the vertical direction is reduced, and the overlap area is reduced, located between the overlapping areas
  • the parasitic capacitance is reduced, which reduces the parasitic capacitance of the thin film transistor and ensures the performance of the thin film transistor.
  • the source 17 and the drain 18 are connected to the active layer 13 at an ohmic contact layer (not shown), and the ohmic contact layer can reduce the source 17 and the drain.
  • the etch barrier layer 14 is provided with two symmetric and spaced apart through grooves 141 which are strip-shaped through holes penetrating the etch stop layer 14 and projected onto the active layer 13.
  • the width direction of the through trench 141 is the direction of the source 17 toward the drain 18, and the two through trenches 141 are symmetrically disposed with the gap between the source 17 and the drain 18, and are more suitable for the active layer 13
  • the middle part dissipates heat through the gap.
  • the source 17 and the drain 18 are connected to the active layer 13 through the two through grooves 141, respectively.
  • the dimension of the spacing between the two through grooves 141 is reduced by the center position of the through groove 141 toward the width of the active layer 13.
  • the size of the spacing between the two through grooves 141 is the width of the channel region of the thin film transistor.
  • the center position of the through groove 141 is also the center position of the active layer 13.
  • the spacing between the two through grooves 141 is also the distance between the source 17 and the drain 18 and the active layer 13 where they are connected.
  • the working principle of the thin film transistor is that when the gate 11 is applied with a positive voltage, the gate voltage 11 generates an electric field in the gate insulating layer 12, and the power line is directed from the gate to the surface of the active layer 13, and generates an induced charge along the surface. As the gate voltage increases, the surface of the active layer 13 will be transformed from a depletion layer to an electron accumulation layer to form an inversion layer. When a strong inversion layer is reached (ie, when the turn-on voltage is reached), a voltage is applied between the source and the drain. The carriers pass through the channel region, so the active layer 13 generates current Joule heat.
  • each of the through slots 141 is in the shape of a circular arc, and the center position of the through slot 141 refers to the linear length between the bottom ends of the arcs of each of the through slots 141.
  • the size of the pitch between the two through grooves 141 is the long dimension of the channel region of the TFT device, and the pitch between the two through grooves 141 is hereinafter referred to as the length.
  • the active layer 13 has a width W and W0 is smaller than W.
  • the length of the distance between the two arc-shaped strip-shaped through grooves 141 is the distance between the top ends of the circular arcs, that is, the center position of the two through grooves 141, and the maximum length is L1, along with the arc
  • the length between the arcuate top ends of the two through grooves 141 gradually decreases toward the bottom end of the circular arc.
  • the lengths L1 and L2 are the channel lengths of the center position and the edge position of the active layer 13, respectively. Since L1 is larger than L2, the width W of the active layer 13 and the length ratio of the region between the two through grooves 141, the width-to-length ratio W/L2 of the groove 141 is larger than the width-to-length ratio W/L1 of the center position.
  • the active layer 13 is located between the two of the through grooves 141, it is not in electrical contact with the source 17 and the drain 18, and is located between the two through grooves 141.
  • the length of the center position of the active layer 13 region is large, that is, the channel length L1 is large, and when the width W of the active layer 13 is the same, and the same voltage is applied, the active layer 13 is located between the two through grooves 141.
  • the smaller the aspect ratio of the portion the smaller the heat generated in the channel region, and the end of the channel region is located at the edge of the thin film transistor, and the heat dissipation to the surrounding is fast, so that the heat generated in the channel region is evenly distributed throughout the thin film transistor.
  • the local overheating of the channel region is avoided, and the performance degradation of the thin film transistor due to the self-heating effect is effectively improved.
  • the surface of the groove wall of the through groove 141 is set as a curved surface to increase the contact area, thereby increasing the heat dissipation area.
  • each of the through grooves 15 includes a first straight line segment 151, a circular arc segment 152 and a second straight line segment 153 which are sequentially connected in the longitudinal direction of the through groove, two The first straight line segments 151 of the through grooves are arranged in parallel or at an angle. Specifically, opposite ends of the circular arc segment 152 are respectively connected to the first straight segment 151 and the second straight segment 153 and communicate with each other to form the strip-shaped through groove 151.
  • the two through grooves 15 are symmetrically disposed, and the distance between the two through grooves 15 is reduced from the middle position to the end positions, that is, the positions of the first straight line segment 151 and the second straight line segment 153 away from the end portion of the circular arc segment 152. Reduced.
  • the arc segments 152 of the two through grooves 15 are curved in opposite directions, and the center position of the spacing (length) between the two through grooves 15 is L1 and the largest, that is, the apex of the two arc segments 152 The length between the lengths is larger than the other positions.
  • first straight line segment 151 and the second straight line segment 153 are disposed in parallel, and the length of the end between the two through grooves 15 is the length between the first straight line segment 151 and the second straight line segment 153. That is, the length of the edge of the channel region.
  • first straight line segment 151 and the second straight line segment 153 are oppositely inclined at an angle, and the first straight line segment 151 is away from the end of the circular arc segment 152 and the second straight line segment 153 is away from the circular arc segment 152. The ends are relatively close.
  • the edge of the thin film transistor has a fast heat dissipation to the periphery, so that the heat generated in the channel region is uniformly distributed throughout the thin film transistor.
  • each of the through grooves 16 includes a first straight line segment 161 and a second straight line segment 162, and the first straight line segment 161 and the second straight line segment 162 One end is connected at an angle, and the angle is greater than 0 degrees and less than 180 degrees.
  • the two through grooves 16 are V-shaped and the bending directions are opposite, and the center portion of the interval (length) between the two through grooves 16 has a length L1 and a largest size.
  • the width to length ratio of the portion of the active layer between the two through grooves 16 is smaller, the heat generation amount is smaller, and the end of the channel region is located at the film. At the edge of the transistor, the heat dissipation to the periphery is fast, so that the heat generated by the active layer is evenly distributed throughout the thin film transistor.
  • the present invention also provides an array substrate comprising a substrate and a plurality of the thin film transistors formed on the substrate, and the plurality of thin film transistors are connected with data lines and gate lines.
  • the invention also provides a display screen comprising the array substrate.
  • the display screen may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display.
  • the thin film transistor used in the display screen of the present invention is provided with a through-groove connecting the source and the drain with the active layer as a non-linear through groove, and the size of the spacing between the two through grooves is determined by the The center position of the through-groove decreases toward the width of the active layer, thereby increasing the channel length at the center of the channel region, enhancing the heat dissipation capability of the central portion of the channel region during operation of the TFT device, and improving the TFT caused by local overheating. Device performance degradation issues.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管，包括衬底（10）、位于衬底表面的栅极（11）、覆盖栅极的栅极绝缘层（12）、依次层叠于栅极绝缘层的有源层（13）和蚀刻阻挡层（14）以及位于蚀刻阻挡层的间隔设置的源极（17）和漏极（18）；蚀刻阻挡层上设有两个对称间隔设置的通槽（141），源极和漏极分别通过两个通槽与有源层连接；两个通槽之间的间距的尺寸，由通槽的中心位置向有源层的宽度延伸方向减小。

Description

薄膜晶体管、阵列基板及显示屏 技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管、阵列基板及显示屏。
背景技术
液晶显示屏(LCD)或是有机发光二极管(OLED)显示屏中，薄膜晶体管(Thin Film Transistor，TFT)作为其实现像素驱动或是外围驱动的核心器件，TFT的性能至关重要。无论是刚性屏的玻璃基板，还是柔性屏的塑料基板，两种材料本身的导热系数都很低，TFT器件工作时会产生由于电流焦耳热引起的自加热效应，且沟道区域的中心位置会困难以散热引起严重的自加热效应，产生局部过热，使TFT器件性能退化，如开态电流减小、漏电流增大、阈值电压偏移等。
发明内容
本发明实施例提供一种提高散热效果的薄膜晶体管、阵列基板及显示屏。
本发明所述的薄膜晶体管，包括衬底、位于所述衬底表面的栅极、覆盖所述栅极的栅极绝缘层、依次层叠于所述栅极绝缘层的有源层和蚀刻阻挡层，以及位于所述蚀刻阻挡层的间隔设置的源极和漏极；
所述蚀刻阻挡层上设有两个对称间隔设置的通槽，所述源极和所述漏极分别通过两个所述通槽与所述有源层连接；两个所述通槽之间的间距的长度尺寸，由所述通槽的中心位置向有源层的宽度延伸方向减小。
本发明的薄膜晶体管通过将源极和漏极与有源层连接的通槽设置成非直线型通槽，两个所述通槽之间的间距的尺寸，由所述通槽的中心位置向有源层的宽度延伸方向减小，从而能够增加沟道区域的中心位置的沟道长度，增强TFT器件工作时沟道区域的中心位置散热能力，改善局部过热造成的TFT器件性能退化问题。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的薄膜晶体管的截面结构示意图；
图2为图1所示的薄膜晶体管的一实施例的俯视示意图；
图3为图1所示的薄膜晶体管的另一实施例的俯视示意图；
图4为图1所示的薄膜晶体管的第三实施例的俯视示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本发明实施例提供一种薄膜晶体管，用于阵列基板的像素电路和驱动电路驱动。所述阵列基板可以是液晶显示屏或者有机发光二极管显示屏的基板。请参阅图1，本实施例中，薄膜晶体管包括衬底10、设置于所述衬底10上表面的栅极11、设置于衬底10以及栅极11上的并覆盖所述栅极11的栅极绝缘层12；依次层叠于所述栅极绝缘层12的有源层13(半导体层)和蚀刻阻挡层14，栅极绝缘层12能够将栅极11以及有源层13相绝缘。薄膜晶体管还包括位于所述蚀刻阻挡层14的并且间隔设置的源极17和漏极18。
本实施例中，栅极11在朝有源层13所在平面的投影被有源层13所覆盖，其目的在于有源层13能够将栅极11完全覆盖用以保护栅极11。
其中，本实施例中，所述源极17朝向所述漏极18的边缘与栅极11的一侧边111平齐，所述漏极18朝向所述源极17的边缘与所述栅极11另一个侧边111平齐，以使所述源极17和漏极18与所述栅极11之间在竖直方向上重叠区域减小，重叠区域的减小，位于重叠区域之间的寄生电容就减小，如此可以减小薄膜晶体管的寄生电容，保证薄膜晶体管性能。进一步的，所述源极17和所述漏极18与所述有源层13连接的位置设有欧姆接触层(图未示)，所述欧姆接触层可以减小源极17和所述漏极18与所述有源层13的接触电阻。
所述蚀刻阻挡层14上设有两个对称且间隔设置的通槽141，所述通槽141 是贯通所述蚀刻阻挡层14的条形通孔，并投影于所述有源层13上。通槽141宽度方向为源极17朝向漏极18的方向，所述两个所述通槽141以所述源极17和漏极18之间的间隙呈对称设置，更适于有源层13中部通过间隙散热。所述源极17和所述漏极18分别通过两个所述通槽141与所述有源层13连接。其中，两个所述通槽141之间的间距的尺寸，由所述通槽141的中心位置向有源层13的宽度延伸方向减小。两个所述通槽141之间的间距的尺寸为薄膜晶体管的沟道区域的宽度。
其中，通槽141的中心位置也是所述有源层13的中心位置。两个所述通槽141之间的间距也是源极17和漏极18与所述有源层13连接位置的间距。
所述薄膜晶体管工作原理为当所述栅极11施以正电压时，栅压11在栅绝缘层12中产生电场，电力线由栅极指向有源层13表面，并在表面处产生感应电荷随着栅电压增加，有源层13表面将由耗尽层转变为电子积累层，形成反型层，当达到强反型层时(即达到开启电压时)源漏极之间加上电压就会有载流子通过沟道区域，因此有源层13会产生电流焦耳热。
请一并参阅图2，本实施例中，每一个所述通槽141为圆弧形条状，所述通槽141的中心位置是指所述每一通槽141圆弧底端之间直线长度W0的对称中心线位置。两个所述通槽141之间的间距的尺寸就是TFT器件的沟道区域长尺寸，以下称两个所述通槽141之间的间距为长度。所述有源层13的宽度为W，W0小于W。两个通槽141圆弧底端之间的长度L2。两个圆弧形条状的通槽141之间间距最大的长度尺寸为圆弧形顶端之间的距离，即两个所述通槽141的中心位置，该最大长度为L1，随着弧线的变化两个通槽141圆弧形顶端之间的长度向圆弧底端方向逐渐减小。其中，所述长度L1和L2分别为有源层13中心位置和边缘位置的沟道长。由于L1大于L2，有源层13的宽度W与位于两个通槽141之间的区域的长度比中，通槽141底端宽长比W/L2大于中心位置的宽长比W/L1。
根据薄膜晶体管的工作原理，由于有源层13位于两个所述通槽141之间的区域是不与源极17和漏极18电接触的，位于两个所述通槽141之间的所述有源层13区域的中心位置的长度大，即沟道长L1大，而在有源层13宽度W相同，接入相同的电压情况下，有源层13位于两个通槽141之间的部分的宽长比越小，沟道区域发热量越小，而且沟道区域端部位于薄膜晶体管的边缘， 散热到周围的速度快，使得沟道区域发热量在整个薄膜晶体管上分布较为均匀，避免了沟道区域局部过热的情况，有效改善了因自加热效应造成的薄膜晶体管性能退化问题。
进一步的，为了可以更好的对有沟道区域进行散热，所述通槽141的槽壁表面设置为曲面，增加接触面积，进而增加散热面积。
请参阅图3，与上述实施例不同的是，每一所述通槽15包括在通槽的长度方向上依次连接的第一直线段151、圆弧段152和第二直线段153，两个所述通槽的第一直线段151平行或者呈夹角设置。具体的，所述圆弧段152的相对两端分别连接第一直线段151和第二直线段153并连通形成所述条状的通槽151。两个所述通槽15对称设置，两个通槽15之间的间距由中部位置向两端位置减小，即第一直线段151和第二直线段153远离圆弧段152的端部位置减小。两个所述通槽15的圆弧段152弧线弯折方向相反，两个通槽15之间间距(长度)的中心位置的长度为L1且尺寸最大，即两个圆弧段152的顶点之间的长度尺寸大于其他位置长度尺寸。本实施例中，所述第一直线段151和第二直线段153平行设置，两个通槽15之间端部的长度就是所述第一直线段151和第二直线段153之间的长度也就是沟道区域边缘的长度。在其它实施方式中，第一直线段151和第二直线段153相对向倾斜成夹角设置，第一直线段151远离圆弧段152的端部与第二直线段153远离圆弧段152的端部相对靠近。而在有源层13长度W相同，接入相同的电压情况下，有源层位于两个通槽141之间的部分的宽长比越小，发热量越小，而且沟道区域端部位于薄膜晶体管的边缘，散热到周围的速度快，使得沟道区域发热量在整个薄膜晶体管上分布较为均匀。
请参阅图4，与上述第一实施例不同的是，每一所述通槽16包括第一直线段161和第二直线段162，所述第一直线段161与所述第二直线段162的一端呈夹角连接，所述夹角大于0度小于180度。俯视图可以看到，两个通槽16的型状为V型，并且弯折方向相反，两个通槽16之间的间距(长度)的中心部分长度为L1且尺寸最大。而在有源层13长度W相同，接入相同的电压情况下，有源层位于两个通槽16之间的部分的宽长比越小，发热量越小而且沟道区域端部位于薄膜晶体管的边缘，散热到周围的速度快，使得有源层发热量在整个薄膜晶体管上分布较为均匀。
本发明还提供一种阵列基板，包括基底和形成于基底上的数个所述薄膜晶体管，数个所述薄膜晶体管连接有数据线和栅极线。本发明还提供一种显示屏，包括所述的阵列基板。所述显示屏可以是液晶显示屏(LCD)或者有机发光二极管(OLED)显示屏。
本发明所述的显示屏采用的薄膜晶体管通过将源极和漏极与有源层连接的通槽设置成非直线型通槽，两个所述通槽之间的间距的尺寸，由所述通槽的中心位置向有源层的宽度延伸方向减小，从而能够增加沟道区域的中心位置的沟道长度，增强TFT器件工作时沟道区域的中心位置散热能力，改善局部过热造成的TFT器件性能退化问题。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (11)

  1. 一种薄膜晶体管，其特征在于，包括衬底、位于所述衬底表面的栅极、覆盖所述栅极的栅极绝缘层、依次层叠于所述栅极绝缘层的有源层和蚀刻阻挡层，以及位于所述蚀刻阻挡层的间隔设置的源极和漏极；
    所述蚀刻阻挡层上设有两个对称间隔设置的通槽，所述源极和所述漏极分别通过两个所述通槽与所述有源层连接；
    两个所述通槽之间的间距的尺寸，由所述通槽的中心位置向有源层的宽度延伸方向减小。
  2. 如权利要求1所述薄膜晶体管，其特征在于，每一个所述通槽在长度方向上为圆弧形条状。
  3. 如权利要求1所述薄膜晶体管，其特征在于，每一所述通槽包括在长度方向上依次连接的第一直线段、圆弧段和第二直线段，两个所述通槽的第一直线段平行或者呈夹角设置。
  4. 如权利要求1所述薄膜晶体管，其特征在于，每一所述通槽包括第一直线段和第二直线段，所述第一直线段与所述第二直线段的一端呈夹角连接，所述夹角大于0度小于180度。
  5. 如权利要求1-4任一项所述薄膜晶体管，其特征在于，每一所述通槽的槽壁表面为曲面。
  6. 如权利要求1-4任一项所述薄膜晶体管，其特征在于，所述源极朝向所述栅极的边缘与漏极朝向所述源极的边缘分别与所述栅极两个相对的侧边平齐。
  7. 如权利要求1-4任一项所述薄膜晶体管，其特征在于，所述源极和所述漏极与所述有源层连接的位置设有欧姆接触层。
  8. 如权利要求1所述薄膜晶体管，其特征在于，两个所述通槽以所述源极和漏极之间的间隙呈对称设置。
  9. 一种阵列基板，包括数个权利要求1-8任一项所述薄膜晶体管。
  10. 一种显示屏，其特征在于，包括权利要求9所述的阵列基板。
  11. 如权利要求10所述显示屏，其特征在于，所述显示屏为液晶显示屏，或者有机发光二极管显示屏。
PCT/CN2017/118130 2017-12-23 2017-12-23 薄膜晶体管、阵列基板及显示屏 Ceased WO2019119456A1 (zh)

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