WO2019113815A1

WO2019113815A1 - Semiconductor structure and manufacturing process thereof

Info

Publication number: WO2019113815A1
Application number: PCT/CN2017/115805
Authority: WO
Inventors: 张立胜; 何宗江; 贾志强
Original assignee: 深圳前海小有技术有限公司; 深圳佑荟半导体有限公司
Priority date: 2017-12-13
Filing date: 2017-12-13
Publication date: 2019-06-20

Abstract

A semiconductor structure sequentially comprises a superlattice transition layer, n-type AlGaN, an active region, an ultra-short period superlattice layer, and p-type BGaN. The ultra-short period superlattice layer is p-BxAlyGa1-x-yN/BmAlnGa1-m-nN, and comprises a plurality of alternately disposed barrier layers and well layers. The barrier layers are p-type BxAlyGa1-x-yN, wherein 0 < x ≤ 0.15, and 0.5 ≤ y ≤0.65. The well layers are p-type BmAlnGa1-m-nN, wherein 0 < m ≤ 0.15, and 0.35 ≤ n ≤ 0.50. One barrier layer and one adjacent well layer form a period, and the thickness of one period is greater than or equal to 1 nm and less than or equal to 2 nm. A process for manufacturing the semiconductor structure is provided. Metal sources B, Al, and Ga in the semiconductor structure perform on-off processing according to a ratio thereof, and a ratio of on and off times and an epitaxy temperature are positively correlated. A pulse mode is formed by on-off alternation. One on time and one adjacent off time together form a pulse period. The semiconductor structure and the process thereof of the present invention improve semiconductor hole injection rates.

Description

Semiconductor structure and manufacturing process thereof

[Technical Field]

The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a fabrication process thereof.

【Background technique】

III-V nitride light-emitting diodes have the advantages of high efficiency, energy saving, environmental protection and long life, and have important applications in solid-state lighting. As the application range of III-V nitride light-emitting diodes increases, the requirements for the photoelectric characteristics of light-emitting diodes become higher and higher.

In the prior art, in the UV-LED, the low concentration of holes in the p-type layer and poor migration ability limit the performance of the UV-LED, and the activation energy of Mg in AlGaN is as high as 180-510 meV, so that the hole concentration at room temperature is obtained. Very low, only a few Mg can be activated. With the increase of Al concentration, the higher the activation energy of Mg in the p-type AlGaN electron blocking layer, the lower the hole concentration, and the more the hole injection can be blocked, which directly affects the luminous efficiency of the light-emitting diode. How to increase the injection rate of holes is an urgent problem to be solved by those skilled in the art.

[Summary of the Invention]

In order to overcome the problems of low hole concentration and poor hole mobility of p-type AlGaN in the prior art, the present invention provides a semiconductor structure and a fabrication process thereof.

The solution to the technical problem of the present invention is to provide a semiconductor structure, which in turn includes a superlattice transition layer, n-type AlGaN, an active region, an ultrashort periodic superlattice layer, and p-type BGaN; the ultrashort periodic supercrystal The grid layer is p-BxAlyGa1-x-yN/BmAlnGa1-m-nN, which includes multiple layers of alternating settings a barrier layer and a well layer, the barrier layer being p-type BxAlyGa1-x-yN, wherein 0<x≤0.15, 0.5≤y≤0.65, and the well layer is p-type BmAlnGa1-m-nN, wherein 0<m ≤0.15, 0.35≤n≤0.50, one barrier layer and one adjacent well layer form a period, and the thickness of one period is greater than or equal to 1 nm and less than or equal to 2 nm.

Preferably, the thickness of the one cycle is 1 nm.

Preferably, the ultra-short period superlattice layer comprises 20-50 cycles.

Preferably, a layer of BAlGaN EBL is further included between the active region and the ultra-short period superlattice layer.

Another aspect of the present invention is to provide a semiconductor structure fabrication process for fabricating the above semiconductor structure, wherein the B, Al, and Ga metal sources in the semiconductor structure are turned on and off in proportion. And the ratio of the on-off time is positively correlated with the epitaxial temperature; the on-off is alternately formed to form a pulse mode, and one pass-time and an adjacent cut-off time together constitute one cycle of the pulse.

Preferably, for the B source, the time of the access is between 5 s and 10 s, and the time for cutting off the flow is between 2 s and 4 s.

Preferably, for the Al source, during the epitaxial layer epitaxy, the access time is between 8s and 12s, and the cut-off flow time is between 2s and 4s; during the well layer epitaxy, the access time is between 5s. Between -10s, the time to cut off the flow is between 2s and 4s.

Preferably, for the Ga source, during the epitaxial layer epitaxy, the access time is between 5 s and 10 s, and the cut-off flow time is between 2 s and 4 s; during the well layer epitaxy, the access time is between 8 s. Between -12s, the time to cut off the flow is between 2s and 4s.

Preferably, when the ultra-short period superlattice is formed, the epitaxial temperature is between 1000 ° C and 1050 ° C.

Preferably, the epitaxial temperature is 1050 °C.

Compared with the prior art, a semiconductor structure according to a first embodiment of the present invention forms an ultra-short period superlattice and has a small thickness of one period, and a microstrip is formed inside the ultra-short period superlattice for cavity formation. Straight path transmission The internal energy band is more conducive to the transport of holes, and the rate at which holes are transported inside is higher, thereby increasing the injection rate of holes. And introducing the B element into the material of the ultra-short period superlattice, greatly increasing the hole concentration of the P-type semiconductor layer, thereby improving the injection rate of holes in the semiconductor; and fabricating the semiconductor structure according to the second embodiment of the present invention The process adopts boundary temperature pulse epitaxy, that is, B, Al, Ga and other metal sources are turned on and off according to the ratio, and the higher the epitaxial temperature, the larger the ratio of on-off time, making it easier for the semiconductor to form ultra-short period super The crystal lattice increases the injection rate of holes inside the semiconductor.

[Description of the Drawings]

1 is a schematic view showing a semiconductor structure according to a first embodiment of the present invention;

2 is a schematic view showing the internal structure of a BAlGaN ultra-short period superlattice in a semiconductor structure according to a first embodiment of the present invention;

3 is a schematic view showing the energy band structure of a p-type layer in a semiconductor structure of a device according to a first embodiment of the present invention;

【Detailed ways】

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to FIG. 1, a semiconductor structure 1 according to a first embodiment of the present invention includes a sapphire substrate 11, an AlN layer 12, a superlattice transition layer 13, an n-type AlGaN 14, an active region 15, and a BAlGaN EBL layer 16 in order from bottom to top. (EBL, electron-blocking layer, electron blocking layer), ultra-short period superlattice layer 17 and p-type BGaN 18 (in all embodiments, upper, lower, left, right, inner, outer, etc. position qualifiers are limited to designation In the present embodiment, the superlattice transition layer 13 is an Al _t Ga _1-t N/AlzGa _1-z N quantum well or an AlN/AlGaN quantum well or AlGaN. Gradient layer, t, z is greater than 0 and less than 1. As a variant, the sapphire substrate 11 in the semiconductor structure 1 can be omitted, that is, the sapphire substrate 11 is peeled off. As another variation, the sapphire substrate 11 may be replaced, that is, the superlattice transition layer 13 may be grown on a semiconductor structure having a sapphire substrate 11, or may be grown on a substrate made of AlN or other materials. The structure of the semiconductor.

Referring to FIG. 2, the ultra-short period superlattice layer 17 is pB _x Al _y Ga _1-xy N/B _m Al _n Ga _1-mn N, which includes a plurality of layers of barrier layers 171 and well layers alternately disposed. 172, the barrier layer 171 is p-type B _x Al _y Ga _1-xy N, where 0 < _x ≤ 0.15, 0.5 _{≤ y} ≤ 0.65, and the well layer 172 is p-type B _m Al _n Ga _1-mn N Where 0 < m ≤ 0.15, 0.35 ≤ n ≤ 0.50. A barrier layer 171 and a neighboring well layer 172 together form a period having a thickness d between 1 nm and 2 nm. In the present embodiment, the period thickness is 1 nm, and the ultrashort period superlattice 17 includes 20-50 cycles with a thickness of 20d-50d.

Referring to FIG. 3, the internal energy band of the ultra-short period superlattice layer 17 includes an A conduction band and a B valence band, wherein the A conduction band is used for electron transport and the B valence band is used for hole transport. The A conduction band and the B valence band are arranged in parallel with an approximate sine wave and the two are transverse waves of equal period, and the distance between the peak of the A conduction band and the trough of the B valence band is L (ie, the A conduction band and the B price) When the strips are integrated with each other, the width of the whole direction perpendicular to the propagation direction is L), and the length of one period of the A conduction band and the B valence band is J1+J2, and the size of L corresponds to the energy band width of the barrier layer 171, J1 The size corresponds to the thickness of the barrier layer 171, and the size of J2 corresponds to the thickness of the well layer 172. In the prior art, the hole has poor transmission capability in the p-type layer, resulting in low hole injection efficiency. In the embodiment, the ultra-short period superlattice layer structure is favorable for forming the microstrip W in the valence band. The longitudinal transmission capability of the hole is enhanced, the injection efficiency of the hole is improved, and the working voltage of the device is lowered, which provides a good foundation for the preparation of the high-power deep ultraviolet LED, and improves the luminous efficiency of the light-emitting diode. Key role. In addition, the introduction of B reduces the difficulty of p-type doping of the barrier layer 171 and the well layer 172 material, and increases the carrier concentration of the p-type.

A second embodiment of the present invention provides a semiconductor structure and a fabricator thereof For the structure mentioned in the following process flow, please refer to the view and number of a semiconductor structure 1 provided by the first embodiment of the present invention, which includes the following steps:

Step S1: providing a substrate. The substrate is a sapphire substrate or an AlN substrate or other suitable material for the substrate.

Step S2: a superlattice transition layer 13, an n-type AlGaN 14, an active region 15, a BAlGaN EBL layer 16, an ultrashort periodic superlattice layer 17, and a p-type BGaN 18 are sequentially formed on the substrate.

In the step S2, the ultra-short period superlattice 17 is implemented by using a boundary temperature pulse epitaxy method to ensure the existence of the interface of the superlattice and the step flow growth of the epitaxial material under different epitaxial flows, in this embodiment. The epitaxial temperature T is between 1000 ° C and 1050 ° C, and the optimum value is 1050 ° C.

In the epitaxial process, the NH ₃ is continuously supplied, and the metal sources such as B, Al, and Ga are turned on and off according to the ratio, and the higher the epitaxial temperature, the larger the ratio of the on-off time, that is, the ratio of the on-off time and The epitaxial temperature is positively correlated. For the B source, the time of the access is between 5s and 10s, the time for cutting off the flow is between 2s and 4s, and the time for the cut-off flow is 2s. The time for the flow and the cut-off flow is between Between 5:2 and 10:2, and the on and off of the B source alternately form a pulse mode, and one access time and an adjacent cut time together constitute one cycle of the pulse. For the Al source, during the epitaxial process of the barrier layer 171, the access time is between 8s and 12s, the time for cutting off the flow is between 2s and 4s, and the optimal time for the cutoff flow is 2s. And the time for cutting off the flow is between 8:2-12:2, and the Al source of the barrier layer 171 alternates with the pulse to form a pulse mode; during the epitaxial process of the well layer 172, the access time is between 5s- Between 10s, the time to cut off the flow is between 2s and 4s, the optimal time for cutting off the flow is 2s, and the time for entering and cutting off the flow is between 5:2 and 10:2. The Al source of the well layer 172 alternately forms a pulse mode, and one pass time and an adjacent cut time together constitute one cycle of the pulse. For the Ga source, during the epitaxial process of the barrier layer 171, the access time is between 5-10s, the time for cutting off the flow is between 2s-4s, and the optimal time for the cutoff flow is 2s, the access is And the time for cutting off the flow is between 5:2 and 10:2, and the Al source of the barrier layer 171 alternates with the pulse to form a pulse mode, and one access time and an adjacent cut time together constitute a pulse. A cycle. During the epitaxial process of the well layer 172, the access time is between 8s and 12s, the time for cutting off the flow is between 2s and 4s, and the time for the cutoff flow is optimally 2s, and the flow rate of the cut-in and cut-off is The time is between 8:2 and 12:2, and the Ga source of the well layer 172 alternates to form a pulse mode, and an access time and an adjacent cut-off time together constitute one cycle of the pulse. By using the boundary temperature pulse epitaxy method, the existence of the interface of the superlattice and the step flow growth of the epitaxial material are ensured under different epitaxial flow rates, so that the periodic thickness of the ultrashort period superlattice 17 in the semiconductor structure 1 is 1 nm.

Compared with the prior art, a semiconductor structure according to a first embodiment of the present invention forms an ultra-short period superlattice and has a small period thickness, and a microstrip is formed inside the ultra-short period superlattice to provide a linear path for holes. The transmission makes its internal energy band more favorable for the transport of holes, the velocity of holes transported inside it is higher, thereby increasing the injection rate of holes, and the introduction of B element greatly increases the cavity ratio and further improves the cavity. Injection rate. According to a second embodiment of the present invention, a semiconductor structure is fabricated by using a boundary temperature pulse epitaxy method, and a metal source such as B, Al, or Ga is turned on and off in proportion, and the higher the epitaxial temperature, the higher the ratio of the on-off time. Larger, it is easier to form an ultra-short period superlattice inside the semiconductor, thereby increasing the injection rate of holes inside the semiconductor.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalents, and improvements made within the principles of the present invention should be included in the scope of the present invention.

Claims

A semiconductor structure, comprising: a superlattice transition layer, an n-type AlGaN, an active region, an ultrashort periodic superlattice layer, and p-type BGaN in sequence; the ultrashort periodic superlattice layer is pB x Al y Ga 1-xy N/B m Al n Ga 1-mn N, which includes a plurality of barrier layers and well layers alternately disposed, the barrier layer being p-type B x Al y Ga 1-xy N, wherein 0< x ≤ 0.15, 0.5 ≤ y ≤ 0.65, the well layer is p-type B m Al n Ga 1-mn N, where 0 < m ≤ 0.15, 0.35 ≤ n ≤ 0.50, one barrier layer and an adjacent well layer The composition is one cycle, and the thickness of one cycle is greater than or equal to 1 nm and less than or equal to 2 nm.
A semiconductor structure according to claim 1, wherein said one period has a thickness of 1 nm.
A semiconductor structure according to claim 1 wherein said ultrashort periodic superlattice layer comprises 20-50 cycles.
A semiconductor structure according to claim 1 further comprising a layer of BAlGaN EBL interposed between the active region and the ultrashort periodic superlattice layer.
A semiconductor structure fabrication process for fabricating a semiconductor structure according to any one of claims 1 to 4, wherein the B, Al, and Ga metal sources in the semiconductor structure are turned on and off in proportion Processing, and the ratio of the on-off time is positively correlated with the epitaxial temperature; the on-and-off alternately forms the pulse mode, and one access time and an adjacent cut-off time together constitute one cycle of the pulse.
The fabrication process of a semiconductor structure according to claim 5, wherein the time for the B source is between 5 s and 10 s, and the time for cutting off the flow is between 2 s and 4 s.
The fabrication process of a semiconductor structure according to claim 5, wherein, for the Al source, during the epitaxial process, the time of the access is between 8s and 12s, and the time for cutting off the flow is between 2s and 4s. During the extension of the well layer, the access time is between 5s and 10s, and the time for cutting off the flow is between 2s and 4s.
The fabrication process of a semiconductor structure according to claim 5, characterized in that, for the Ga source, the time of the access layer is between 5 s and 10 s, and the time for cutting off the flow is between 2 s and 4 s. During the extension of the well layer, the access time is between 8s and 12s, and the time for cutting off the flow is between 2s and 4s.
The fabrication process of a semiconductor structure according to claim 5, wherein when the ultrashort period superlattice is formed, the epitaxial temperature is between 1000 ° C and 1050 ° C.
A fabrication process for a semiconductor structure according to claim 9, wherein said epitaxial temperature is 1050 °C.