WO2019109488A1 - 晶体管及其制作方法 - Google Patents

晶体管及其制作方法 Download PDF

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WO2019109488A1
WO2019109488A1 PCT/CN2018/074059 CN2018074059W WO2019109488A1 WO 2019109488 A1 WO2019109488 A1 WO 2019109488A1 CN 2018074059 W CN2018074059 W CN 2018074059W WO 2019109488 A1 WO2019109488 A1 WO 2019109488A1
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transistor
insulating layer
layer
ions
channel
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PCT/CN2018/074059
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English (en)
French (fr)
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赵瑜
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武汉华星光电半导体显示技术有限公司
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Publication of WO2019109488A1 publication Critical patent/WO2019109488A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the invention belongs to the technical field of transistor fabrication, and in particular to a transistor capable of reducing the drift amplitude of a threshold voltage and a manufacturing method thereof.
  • BTS Bias temperature stress
  • Breakdown Voltage breakdown voltage
  • the main method is to apply a certain voltage to the gate of the thin film transistor to open the channel of the thin film transistor at a certain high temperature, and measure the threshold voltage of the thin film transistor after a period of time, if the thin film transistor
  • the excessive threshold voltage drift causes the on-state current of the thin film transistor to change too much, thereby affecting product quality. If the threshold voltage of the thin film transistor drifts to a certain level, it cannot be used normally.
  • a transistor comprising: a buffer layer on a substrate; a channel layer on the buffer layer; a gate insulating layer on the channel layer; a gate on the gate insulating layer; wherein a corresponding ion is implanted in the buffer layer according to a channel type of the transistor to reduce a drift amplitude of a threshold voltage of the transistor.
  • the buffer layer includes: a first insulating layer on the substrate; a second insulating layer on the first insulating layer; wherein the first insulating layer or the second insulating layer is The corresponding ions are implanted.
  • the transistor when the transistor is an n-channel transistor, positive ions are implanted in the first insulating layer or the second insulating layer, and a threshold voltage of the transistor is moved in a negative direction, thereby The amplitude of the drift of the threshold voltage is reduced.
  • the transistor when the transistor is a p-channel transistor, a negative ion is implanted in the first insulating layer or the second insulating layer, and a threshold voltage of the transistor is moved in a positive direction, so that a threshold of the transistor The amplitude of the voltage drift is reduced.
  • a method of fabricating a transistor includes the steps of: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; and fabricating the channel layer Forming a gate insulating layer; forming a gate on the gate insulating layer; wherein, after forming the buffer layer, implanting corresponding ions in the buffer layer according to a channel type of the transistor, To reduce the drift amplitude of the threshold voltage of the transistor.
  • a specific method of forming a buffer layer on the substrate includes: forming a first insulating layer on the substrate; forming a second insulating layer on the first insulating layer; wherein, in the first insulating layer or The respective ions are implanted in the second insulating layer.
  • the transistor when the transistor is an n-channel transistor, positive ions are implanted in the first insulating layer or the second insulating layer, and a threshold voltage of the transistor is moved in a negative direction, thereby The amplitude of the drift of the threshold voltage is reduced.
  • the transistor when the transistor is a p-channel transistor, a negative ion is implanted in the first insulating layer or the second insulating layer, and a threshold voltage of the transistor is moved in a positive direction, so that a threshold of the transistor The amplitude of the voltage drift is reduced.
  • the negative ions include chloride ions or fluoride ions
  • the positive ions include hydrogen ions
  • the present invention implants corresponding ions according to the channel type of the transistor, thereby reducing the drift amplitude of the threshold voltage of the transistor, thereby improving the reliability of the transistor.
  • FIG. 1 is a schematic structural view of a transistor according to an embodiment of the present invention.
  • FIGS. 2A through 2G are process diagrams of transistors in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a transistor in accordance with an embodiment of the present invention.
  • the structure of the transistor of the present invention is not limited to that shown in FIG.
  • the transistor of the present embodiment may be, for example, a thin film transistor, but the present invention is not limited thereto.
  • a transistor includes: a buffer layer 210 on a substrate 100; a channel layer 220 on the buffer layer 210; a gate insulating layer 230 on the channel layer 220; a gate 240 on the insulating layer 230; a third insulating layer 250 on the gate insulating layer 230 and the gate 240; first vias 261 and second in the third insulating layer 250 and the gate insulating layer 230 a hole 262; a source 271 and a drain 272 on the third insulating layer, the source 271 filling the first via 261 to be in contact with the channel layer 220, and the drain 272 filling the second via 262 to the channel layer 220 contact.
  • the third insulating layer 250 may be, for example, an organic flat layer formed of an organic material, but the present invention is not limited thereto.
  • the buffer layer 210 includes a first insulating layer 211 on the substrate 100, a second insulating layer 212 on the first insulating layer 211, and the channel layer 220 is disposed on the second insulating layer. 212, the second insulating layer 212 on the first insulating layer 211 is implanted with the corresponding ions.
  • the first insulating layer 211 is formed of silicon nitride (SiN x )
  • the second insulating layer 212 is formed of silicon oxide (SiO x ).
  • the channel layer 220 is formed of amorphous silicon ( ⁇ -Si), but the present invention is not limited thereto.
  • corresponding ions are implanted in the first insulating layer 211 or the second insulating layer 212 in the buffer layer 210 according to the channel type of the transistor to reduce the drift amplitude of the threshold voltage of the transistor.
  • the transistor when the transistor is a p-channel transistor, if a transistor is subjected to a BTS test, a negative voltage is applied to the gate 240 to turn on the transistor, and under the voltage of the gate 240, the channel layer 220 is insulated from the gate. A positive defect in layer 230 will move toward gate 240, causing the threshold voltage of the transistor to move in a negative direction.
  • negative ions are implanted in the first insulating layer 211 or the second insulating layer 212.
  • the implanted negative ions trap holes as traps, and when a negative voltage is applied to the gate 240, it is trapped. The holes are attracted to the channel layer 220, thereby moving the threshold voltage in the positive direction, thereby achieving the purpose of reducing the drift amplitude of the threshold voltage, thereby improving the reliability of the transistor.
  • the transistor When the transistor is an n-channel transistor, if a transistor is subjected to a BTS test, a positive voltage is applied to the gate 240 to turn on the transistor, and under the voltage of the gate 240, the channel layer 220 and the gate insulating layer 230 are The negative defect will move toward the gate 240, causing the threshold voltage of the transistor to move in the positive direction.
  • positive ions are implanted in the first insulating layer 211 or the second insulating layer 212, and the normally implanted positive ions trap the electrons as a trap, and when a positive voltage is applied to the gate 240, it is trapped.
  • the resident electrons are attracted to the channel layer 220, thereby moving the threshold voltage in the negative direction, thereby achieving the purpose of reducing the drift amplitude of the threshold voltage, thereby improving the reliability of the transistor.
  • FIGS. 2A through 2G are process diagrams of transistors in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 2A, a buffer layer 210 is formed on the substrate 100. Further, the method for fabricating the buffer layer 210 includes: forming a first insulating layer 211 on the substrate 100; and forming a second insulating layer 212 on the first insulating layer 211. As still another embodiment of the present invention, after the first insulating layer 211 is completed, positive ions or negative ions may be implanted in the first insulating layer 211. As still another embodiment of the present invention, after the second insulating layer 212 is completed, positive ions or negative ions may be implanted in the second insulating layer 212.
  • Step 2 Referring to FIG. 2B, a channel layer 220 is formed on the second insulating layer 212.
  • Step 3 Referring to FIG. 2C, a gate insulating layer 230 is formed on the channel layer 220.
  • the gate insulating layer 230 may be formed of an oxide of silicon and/or a nitride of silicon.
  • Step 4 Referring to FIG. 2D, a gate 240 is formed on the gate insulating layer 230.
  • a third insulating layer 250 is formed on the gate insulating layer 230 and the gate 240.
  • the third insulating layer 250 may be, for example, an organic flat layer formed of an organic material.
  • Step 6 Referring to FIG. 2F, a first via hole 261 and a second via hole 262 are formed in the third insulating layer 250 and the gate insulating layer 230 to expose the semiconductor layer 223.
  • Step 7 referring to FIG. 2G, a source 271 and a drain 272 are formed on the third insulating layer 250.
  • the source 271 fills the first via 261 to contact the channel layer 220, and the drain 272 fills the second via 262. In contact with the channel layer 220.
  • the negative ions may be, for example, chloride ions, fluorine ions, or the like; and the positive ions may be, for example, hydrogen ions or the like, but the present invention is not limited thereto.
  • corresponding ions are implanted according to the channel type of the transistor, thereby reducing the drift amplitude of the threshold voltage of the transistor, thereby improving the reliability of the transistor.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种晶体管，其包括：在基板上的缓冲层；在所述缓冲层上的沟道层；在所述沟道层上的栅极绝缘层；以及在所述栅极绝缘层上的栅极；其中，根据所述晶体管的沟道类型在所述缓冲层中植入相应的离子，以降低所述晶体管的阈值电压的漂移幅度。本发明还公开了一种晶体管的制作方法。本发明根据晶体管的沟道类型而植入相应的离子，以此来降低晶体管的阈值电压的漂移幅度，从而提高晶体管的可靠性。

Description

晶体管及其制作方法 技术领域
本发明属于晶体管制作技术领域，具体地讲，涉及一种能够降低阈值电压的漂移幅度的晶体管及其制作方法。
背景技术
在显示产业中，器件可靠性一直是关乎产品寿命的关键，一般会使用偏压温度应力(Bias Temperature Stress，简称BTS)、击穿电压(BreakdownVoltage)等来判断薄膜晶体管(TFT)的可靠性。
在对薄膜晶体管进行BTS模拟产品使用时，主要做法是在一定高温下，薄膜晶体管的栅极被施加一定电压使薄膜晶体管的沟道开启，经过一段时间后测量薄膜晶体管的阈值电压，若薄膜晶体管的阈值电压漂移过大会导致薄膜晶体管的导通电流变化过大，从而影响产品品质。若薄膜晶体管的阈值电压漂移到一定程度后则不能正常使用。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种能够降低阈值电压的漂移幅度的晶体管及其制作方法。
根据本发明的一方面，提供了一种晶体管，其包括：在基板上的缓冲层；在所述缓冲层上的沟道层；在所述沟道层上的栅极绝缘层；以及在所述栅极绝缘层上的栅极；其中，根据所述晶体管的沟道类型在所述缓冲层中植入相应的离子，以降低所述晶体管的阈值电压的漂移幅度。
进一步地，所述缓冲层包括：在所述基板上的第一绝缘层；在所述第一绝缘层上的第二绝缘层；其中，所述第一绝缘层或所述第二绝缘层被植入所述相应的离子。
进一步地，当所述晶体管为n沟道晶体管时，所述第一绝缘层或所述第二 绝缘层中被植入正离子，所述晶体管的阈值电压向负方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
进一步地，当所述晶体管为p沟道晶体管时，所述第一绝缘层或所述第二绝缘层中被植入负离子，所述晶体管的阈值电压向正方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
根据本发明的另一方面，还提供了一种晶体管的制作方法，其包括步骤：在基板上制作形成缓冲层；在所述缓冲层上制作形成沟道层；在所述沟道层上制作形成栅极绝缘层；在所述栅极绝缘层上制作形成栅极；其中，在制作形成所述缓冲层之后，根据所述晶体管的沟道类型在所述缓冲层中植入相应的离子，以降低所述晶体管的阈值电压的漂移幅度。
进一步地，在基板上制作形成缓冲层的具体方法包括：在基板上制作形成第一绝缘层；在所述第一绝缘层上制作形成第二绝缘层；其中，在所述第一绝缘层或所述第二绝缘层中植入所述相应的离子。
进一步地，当所述晶体管为n沟道晶体管时，在所述第一绝缘层或所述第二绝缘层中植入正离子，所述晶体管的阈值电压向负方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
进一步地，当所述晶体管为p沟道晶体管时，在所述第一绝缘层或所述第二绝缘层中植入负离子，所述晶体管的阈值电压向正方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
进一步地，所述负离子包括氯离子或氟离子，所述正离子包括氢离子。
本发明的有益效果：本发明根据晶体管的沟道类型而植入相应的离子，以此来降低晶体管的阈值电压的漂移幅度，从而提高晶体管的可靠性。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的晶体管的结构示意图；
图2A至图2G是根据本发明的实施例的晶体管的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚起见，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
图1是根据本发明的实施例的晶体管的结构示意图。这里，仅示出了晶体管的一种实施结构，本发明的晶体管的结构并不以图1所示为限。此外，本实施例的晶体管可例如是薄膜晶体管，但本发明并不限制于此。
参照图1，根据本发明的实施例的晶体管包括：在基板100上的缓冲层210；在缓冲层210上的沟道层220；在沟道层220上的栅极绝缘层230；在栅极绝缘层230上的栅极240；在栅极绝缘层230和栅极240上的第三绝缘层250；在第三绝缘层250和栅极绝缘层230中的第一过孔261和第二过孔262；在第三绝缘层上的源极271和漏极272，源极271填充第一过孔261以与沟道层220接触，漏极272填充第二过孔262以与沟道层220接触。此外，第三绝缘层250可例如是由有机材料制作形成的有机平坦层，但本发明并不限制于此。
进一步地，在本实施例中，缓冲层210包括在基板100上的第一绝缘层211；在第一绝缘层211上的第二绝缘层212；其中，沟道层220设置于第二绝缘层212上，第一绝缘层211上的第二绝缘层212被植入所述相应的离子。在本实施例中，第一绝缘层211由硅的氮化物(SiN x)制作形成，而第二绝缘层212由硅的氧化物(SiO x)制作形成。此外，沟道层220由非晶硅(α-Si)制作形成，但本发明并不限制于此。
在本实施例中，根据晶体管的沟道类型在缓冲层210中的第一绝缘层211或第二绝缘层212中植入相应的离子，以降低晶体管的阈值电压的漂移幅度。
具体地，当所述晶体管为p沟道晶体管时，若对晶体管进行BTS测试时会对栅极240施加负电压使晶体管开启，在栅极240的电压作用下，沟道层220与栅极绝缘层230中的正缺陷会向栅极240移动，从而使晶体管的阈值电压向负方向移动。而在本实施例中，在第一绝缘层211或第二绝缘层212中植入负离子，通常植入的负离子会作为陷阱而困住空穴，当在栅极240施加负电压时，困住的空穴会受吸引进入沟道层220，从而使阈值电压向正方向移动，进而达到降低阈值电压的漂移幅度的目的，提高晶体管的可靠性。
当所述晶体管为n沟道晶体管时，若对晶体管进行BTS测试时会对栅极240施加正电压使晶体管开启，在栅极240的电压作用下，沟道层220与栅极绝缘层230中的负缺陷会向栅极240移动，从而使晶体管的阈值电压向正方向移动。而在本实施例中，在第一绝缘层211或第二绝缘层212中植入正离子，通常植入的正离子会作为陷阱而困住电子，当在栅极240施加正电压时，困住的电子会受吸引进入沟道层220，从而使阈值电压向负方向移动，进而达到降低阈值电压的漂移幅度的目的，提高晶体管的可靠性。
图2A至图2G是根据本发明的实施例的晶体管的制程图。
根据本发明的实施例的晶体管的制作方法包括：
步骤一：参照图2A，在基板100上制作形成缓冲层210。进一步地，缓冲层210的制作方法包括：在基板100上制作形成第一绝缘层211；在第一绝缘层211上制作形成第二绝缘层212。作为本发明的又一实施方式，在制作完成第一绝缘层211之后，可以在第一绝缘层211中植入正离子或者负离子。作为本发明的又一实施方式，在制作完成第二绝缘层212之后，可以在第二绝缘层212中植入正离子或者负离子。
步骤二：参照图2B，在第二绝缘层212上制作形成沟道层220。
步骤三：参照图2C，在沟道层220上制作形成栅极绝缘层230。栅极绝缘层230可以由硅的氧化物和/或硅的氮化物制作形成。
步骤四：参照图2D，在栅极绝缘层230上制作形成栅极240。
步骤五：参照图2E，在栅极绝缘层230和栅极240上制作形成第三绝缘 层250。第三绝缘层250可例如是由有机材料制作形成的有机平坦层。
步骤六：参照图2F，在第三绝缘层250和栅极绝缘层230中制作形成第一过孔261和第二过孔262，以暴露半导体层223。
步骤七，参照图2G，在第三绝缘层250上制作形成源极271和漏极272，源极271填充第一过孔261以与沟道层220接触，漏极272填充第二过孔262以与沟道层220接触。
此外，在本实施例中，负离子可例如是氯离子、氟离子等；而正离子可例如是氢离子等，但本发明并不限制于此。
综上所述，根据本发明的实施例，根据晶体管的沟道类型而植入相应的离子，以此来降低晶体管的阈值电压的漂移幅度，从而提高晶体管的可靠性。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (10)

  1. 一种晶体管，其中，包括：
    在基板上的缓冲层；
    在所述缓冲层上的沟道层；
    在所述沟道层上的栅极绝缘层；以及
    在所述栅极绝缘层上的栅极；
    其中，根据所述晶体管的沟道类型在所述缓冲层中植入相应的离子，以降低所述晶体管的阈值电压的漂移幅度。
  2. 根据权利要求1所述的晶体管，其中，所述缓冲层包括：
    在所述基板上的第一绝缘层；
    在所述第一绝缘层上的第二绝缘层；
    其中，所述第一绝缘层或所述第二绝缘层被植入所述相应的离子。
  3. 根据权利要求2所述的晶体管，其中，当所述晶体管为n沟道晶体管时，所述第一绝缘层或所述第二绝缘层中被植入正离子，所述晶体管的阈值电压向负方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
  4. 根据权利要求3所述的晶体管，其中，当所述晶体管为p沟道晶体管时，所述第一绝缘层或所述第二绝缘层中被植入负离子，所述晶体管的阈值电压向正方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
  5. 根据权利要求4所述的晶体管，其中，所述负离子包括氯离子或氟离子，所述正离子包括氢离子。
  6. 一种晶体管的制作方法，其中，包括步骤：
    在基板上制作形成缓冲层；
    在所述缓冲层上制作形成沟道层；
    在所述沟道层上制作形成栅极绝缘层；
    在所述栅极绝缘层上制作形成栅极；
    其中，在制作形成所述缓冲层之后，根据所述晶体管的沟道类型在所述缓冲层中植入相应的离子，以降低所述晶体管的阈值电压的漂移幅度。
  7. 根据权利要求6所述的晶体管的制作方法，其中，在基板上制作形成缓冲层的具体方法包括：
    在基板上制作形成第一绝缘层；
    在所述第一绝缘层上制作形成第二绝缘层；
    其中，在所述第一绝缘层或所述第二绝缘层中植入所述相应的离子。
  8. 根据权利要求7所述的晶体管的制作方法，其中，当所述晶体管为n沟道晶体管时，在所述第一绝缘层或所述第二绝缘层中植入正离子，所述晶体管的阈值电压向负方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
  9. 根据权利要求8所述的晶体管的制作方法，其中，当所述晶体管为p沟道晶体管时，在所述第一绝缘层或所述第二绝缘层中植入负离子，所述晶体管的阈值电压向正方向移动，从而所述晶体管的阈值电压的漂移幅度被降低。
  10. 根据权利要求9所述的晶体管的制作方法，其中，所述负离子包括氯离子或氟离子，所述正离子包括氢离子。
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