WO2019109477A1 - 显示面板的Mura补偿数据的更新方法 - Google Patents

显示面板的Mura补偿数据的更新方法 Download PDF

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Publication number
WO2019109477A1
WO2019109477A1 PCT/CN2018/073092 CN2018073092W WO2019109477A1 WO 2019109477 A1 WO2019109477 A1 WO 2019109477A1 CN 2018073092 W CN2018073092 W CN 2018073092W WO 2019109477 A1 WO2019109477 A1 WO 2019109477A1
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Prior art keywords
control chip
timing control
mura compensation
memory
spi
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PCT/CN2018/073092
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English (en)
French (fr)
Inventor
张华�
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/752,143 priority Critical patent/US10726763B2/en
Publication of WO2019109477A1 publication Critical patent/WO2019109477A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a method for updating Mura compensation data of a display panel.
  • the driver code of the timing control chip (TCON IC) is generally stored in a small-capacity flash memory, and the Mura (light and dark unevenness) of the display panel compensates for a large amount of data and needs to be stored.
  • the drive code of the TCON IC and the Mura compensation data of the display panel can be placed in the same large-capacity flash memory, and the location areas of the respective memories are defined, and the timing control chip can simultaneously read the drive through the same line. Code and Mura compensation data.
  • the driver code of the timing control chip is fixed, so it is pre-burned into the flash memory in batches, and does not occupy the production time of the display panel; and the Mura compensation data of each display panel is different, and needs to be produced in the display panel.
  • each step is indispensable and requires a certain production time.
  • the erasing step is to prevent the old or erroneous Mura compensation data from being stored in the flash memory, which affects the shooting of the original Mura.
  • the SPI Serial Peripheral Interface
  • the timing control chip Only after the erase step is completed, the timing control chip is powered back on, thereby restoring the connection timing control chip.
  • the timing control chip With the SPI line between the flash memory, the timing control chip reads the drive code in the flash memory (the old or the wrong Mura compensation data has been erased), and the display panel displays the original picture without Mura compensation before it can start. Subsequent operations, such as the generation and storage of new Mura compensation data. It can be seen that the time required for the erasing step cannot be effectively utilized, which is disadvantageous for the improvement of the manufacturing efficiency of the display panel.
  • a method for updating Mura compensation data of a display panel comprising the steps of: turning off a Mura compensation function of a timing control chip connected to a memory to cause the display panel to display no Mura compensation The original picture; disconnecting the connection between the timing control chip and the memory; erasing the original Mura compensation data stored in the memory, and acquiring new Mura compensation data according to the original picture displayed by the display panel; The new Mura compensation data is written to the memory.
  • the method of “turning off the Mura compensation function of the timing control chip connected to the memory” includes: changing the setting register configuration data in the buffer of the timing control chip by using the I2C interface fixture to make the timing The Mura compensation function of the control chip is turned off; wherein the setting register configuration data is used to control whether the Mura compensation function of the timing control chip is turned on or off.
  • the timing control chip is connected to the memory via an SPI line;
  • the method of "breaking the connection between the timing control chip and the memory” includes: providing an SPI to the timing control chip The SPI enable signal of the enable terminal is converted from a high potential to a low potential to disconnect the SPI line;
  • the method of "recovering the connection between the timing control chip and the memory” includes: providing to the The SPI enable signal of the SPI enable terminal of the timing control chip is converted from a low potential to a high potential to recover the SPI line.
  • the method of “restarting the timing control chip” includes the steps of: converting a signal supplied to a restart end of the timing control chip from a high potential to a low potential; after a predetermined time, providing to the timing control chip The signal on the restart side is converted from a low potential to a high potential.
  • the updating method further includes the steps of: restoring a connection between the timing control chip and the memory; restarting the timing control chip
  • a method for updating Mura compensation data of a display panel comprising the steps of: disconnecting a connection between a timing control chip and a memory; and Mura of the timing control chip
  • the compensation function is turned off to cause the display panel to display the original picture without Mura compensation; the original Mura compensation data stored in the memory is erased, and new Mura compensation data is acquired according to the original picture displayed by the display panel; the new Mura is Compensating data is written into the memory; restoring a connection between the timing control chip and the memory; turning on a Mura compensation function of the timing control chip; and the timing control chip re-reading data in the memory.
  • the timing control chip is connected to the memory via an SPI line to read data in the memory;
  • the method of "breaking the connection between the timing control chip and the memory” includes: providing the The SPI enable signal of the SPI enable terminal of the timing control chip is switched from a high potential to a low potential to disconnect the SPI line;
  • the method of "recovering the connection between the timing control chip and the memory” includes : Converting the SPI enable signal supplied to the SPI enable terminal of the timing control chip from a low potential to a high potential to restore the SPI line.
  • the method of “turning off the Mura compensation function of the timing control chip” includes: when the timing control chip detects that the SPI enable signal is converted from a high potential to a low potential, the timing control The chip automatically turns off the Mura compensation function; the method of “turning on the Mura compensation function of the timing control chip” includes: when the timing control chip detects that the SPI enable signal is converted from a low potential to a high potential, The timing control chip automatically turns on the Mura compensation function.
  • the method of “the timing control chip re-reads data in the memory” includes: when the timing control chip detects that a signal supplied to its restart terminal is switched from a high potential to a low potential, The timing control chip re-reads the data in the memory.
  • the updating method further includes: when a signal supplied to the restart end of the timing control chip is converted from a low potential to a high potential, The timing control chip turns on the signal detection function.
  • the erasure of the original Mura compensation data stored in the memory is performed simultaneously with the formation of the new Mura compensation data, so that the formation of the new Mura compensation data is performed during the erasing period, thereby effectively utilizing the rubbing
  • the production efficiency of the display panel is improved.
  • FIG. 1 is a schematic structural diagram of a compensation system of Mura compensation data of a display panel according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method of updating a compensation system of Mura compensation data of a display panel according to an embodiment of the present invention
  • FIG. 3 is a timing diagram of a SPI enable signal and a restart signal in accordance with an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a compensation system for Mura compensation data of a display panel according to another embodiment of the present invention.
  • FIG. 5 is a flowchart of a method of updating a compensation system of Mura compensation data of a display panel according to another embodiment of the present invention.
  • FIG. 6 is a timing diagram of an SPI enable signal and a detect control signal in accordance with another embodiment of the present invention.
  • FIG. 1 is a block diagram showing a compensation system of Mura compensation data of a display panel according to an embodiment of the present invention.
  • a compensation system for Mura compensation data of a display panel includes: a timing control chip (TCON IC) 10, an SPI (Serial Peripheral Interface) line 20, a memory 30, and an I2C (Inter-Integrated) Circuit) interface fixture 40.
  • TCON IC timing control chip
  • SPI Serial Peripheral Interface
  • I2C Inter-Integrated Circuit
  • a timing control chip (TCON IC) 10 is disposed on the PCB board 120, the memory 30 is disposed on the XB (horizontal substrate) PCB board 130, and the XBPCB board 130 is connected to the display panel 110.
  • the memory 30 may be, for example, a flash memory, but the present invention is not limited thereto.
  • the timing control chip 10 includes a connection end 11, an SPI enable end 12, and a restart end 13.
  • the connection terminal 11 is connected to the memory 30 via the SPI line 20 to cause the timing control chip 10 to read the data of the memory 30.
  • the SPI enable terminal 12 is configured to receive an SPI enable signal that is used to control the disconnection of the SPI line 20. For example, when the SPI enable signal is high, the SPI line 20 is connected; when the SPI enable signal is low, the SPI line 20 is turned off.
  • the restart terminal 13 is configured to receive a restart signal for turning off or turning on the timing control chip 10.
  • the Mura compensation data and the drive code of the timing control chip 10 are stored in the memory 30.
  • the drive code has set register configuration data for controlling whether the Mura compensation function of the timing control chip 10 is turned on or off.
  • the timing control chip 10 has a buffer; after the timing control chip 10 reads the drive code from the memory 30 via the SPI line 20, the timing control chip 10 stores the set register configuration data in its buffer, thus changing the timing control chip
  • the setting register configuration data in the buffer 10 enables the Mura compensation function of the timing control chip 10 to be turned on or off. Generally, under normal circumstances, the timing control chip 10 turns on the Mura compensation function by default.
  • FIG. 2 is a flow chart of a method of updating a compensation system of Mura compensation data of a display panel according to an embodiment of the present invention.
  • 3 is a timing diagram of a SPI enable signal and a restart signal in accordance with an embodiment of the present invention.
  • a method for updating a compensation system for Mura compensation data of a display panel includes:
  • Step S210 Turn off the Mura compensation function of the timing control chip 10 so that the display panel 110 displays the original picture without Mura compensation. This step corresponds to the Mura compensation off phase T1 in FIG.
  • the method of implementing step S210 includes: changing the setting register configuration data in the buffer of the timing control chip 10 by using the I2C interface jig 40 to turn off the Mura compensation function of the timing control chip 10.
  • Step S220 Disconnect the connection between the timing control chip 10 and the memory 30.
  • the method of implementing step S220 includes converting the SPI enable signal supplied to the SPI enable terminal 12 of the timing control chip 10 from a high level to a low level to turn off the SPI line 20.
  • Step S230 erasing the original Mura compensation data stored in the memory 30 while acquiring new Mura compensation data according to the original picture displayed on the display panel 110.
  • the SPI enable signal is always kept at a low level, and the Mura compensation function of the timing control chip 10 is always kept off, and the display panel 110 is kept.
  • the original picture without Mura compensation is displayed. It is known from step S230 that the original Mura compensation data stored in the erasing memory 30 is simultaneously performed with the formation of the new Mura compensation data, so that the formation of the new Mura compensation data is performed during the erasing step, thereby effectively utilizing the erasing period.
  • Step S240 Write the new Mura compensation data into the memory 30.
  • the SPI enable signal is always kept low, and the time (T3+T4) at which the new Mura compensation data and the new Mura compensation data are written into the memory 30 is greater than the erase memory 30 storage.
  • Step S250 Restoring the connection between the timing control chip 10 and the memory 30.
  • the method of implementing step S250 includes converting the SPI enable signal supplied to the SPI enable terminal 12 of the timing control chip 10 from a low potential to a high potential to communicate with the SPI line 20.
  • Step S260 Restart the timing control chip 10. This step corresponds to the restart phase T5 in FIG. It should be noted that after the timing control chip 10 is restarted, the timing control chip 10 turns on the Mura compensation function by default.
  • the method of implementing step S260 includes: converting a signal supplied to the restart terminal 13 of the timing control chip 10 from a high potential to a low potential; after a predetermined time, converting a signal supplied to the restart terminal 13 of the timing control chip 10 from a low potential to High potential. It should be noted that the predetermined time is short.
  • steps S210 to S240 have completed the update process of the Mura compensation data
  • steps S250 and S260 are the process of resuming the connection between the timing control chip 10 and the memory 30 and restarting the timing control chip 10, thus In another embodiment of the present invention, step S250 and step S260 may also be omitted.
  • FIG. 4 is a schematic structural diagram of a compensation system of Mura compensation data of a display panel according to another embodiment of the present invention.
  • a compensation system for Mura compensation data of a display panel includes a timing control chip (TCON IC) 10, an SPI (Serial Peripheral Interface) line 20, and a memory 30.
  • TCON IC timing control chip
  • SPI Serial Peripheral Interface
  • a timing control chip (TCON IC) 10 is disposed on the PCB board 120, the memory 30 is disposed on the XB (horizontal substrate) PCB board 130, and the XBPCB board 130 is connected to the display panel 110.
  • the memory 30 may be, for example, a flash memory, but the present invention is not limited thereto.
  • the timing control chip 10 includes a connection end 11, an SPI enable end 12, and a restart end 13.
  • the connection terminal 11 is connected to the memory 30 via the SPI line 20 to cause the timing control chip 10 to read the data of the memory 30.
  • the SPI enable terminal 12 is configured to receive an SPI enable signal that is used to control the disconnection of the SPI line 20. For example, when the SPI enable signal is high, the SPI line 20 is connected; when the SPI enable signal is low, the SPI line 20 is turned off.
  • the restarting terminal 13 is configured to receive a detection control signal, which is used to turn off or turn on the signal detection function of the control chip 10.
  • the Mura compensation data and the drive code of the timing control chip 10 are stored in the memory 30.
  • the sequence control chip 10 reads the drive code or Mura compensation data from the memory 30 via the SPI line 20.
  • the timing control chip 10 also automatically turns off or turns on the Mura compensation function according to the detected SPI enable signal.
  • FIG. 5 is a flowchart of a method of updating a compensation system of Mura compensation data of a display panel according to another embodiment of the present invention.
  • 6 is a timing diagram of an SPI enable signal and a detect control signal in accordance with another embodiment of the present invention.
  • a method for updating a compensation system for Mura compensation data of a display panel includes:
  • Step S510 Disconnect the connection between the timing control chip 10 and the memory 30.
  • the method of implementing step S510 includes converting the SPI enable signal supplied to the SPI enable terminal 12 of the timing control chip 10 from a high level to a low level to turn off the SPI line 20.
  • Step S520 Turn off the Mura compensation function of the timing control chip 10 to cause the display panel 110 to display the original picture without Mura compensation.
  • the method of implementing step S520 includes: when the timing control chip 10 detects that the SPI enable signal is converted from a high level to a low level, the timing control chip 10 automatically turns off the Mura compensation function.
  • Step S530 erasing the original Mura compensation data stored in the memory 30 while acquiring new Mura compensation data according to the original picture displayed on the display panel 110.
  • the SPI enable signal is always kept low, and the Mura compensation function of the timing control chip 10 is always kept off, and the display panel 110 displays Original picture without Mura compensation.
  • the original Mura compensation data stored in the erasing memory 30 is simultaneously performed with the formation of the new Mura compensation data, so that the formation of the new Mura compensation data is performed in the period of the erasing step, thereby effectively utilizing the erasing period.
  • Step S540 Write the new Mura compensation data into the memory 30.
  • the SPI enable signal is always kept low, and the time (T3+T4) at which the new Mura compensation data and the new Mura compensation data are written into the memory 30 is greater than the erase memory 30 storage.
  • Step S550 Restoring the connection between the timing control chip 10 and the memory 30.
  • the method of implementing step S550 includes converting the SPI enable signal supplied to the SPI enable terminal 12 of the timing control chip 10 from a low potential to a high potential to restore the SPI line 20.
  • Step S560 Turn on the Mura compensation function of the timing control chip 10.
  • the method of implementing step S560 includes: when the timing control chip 10 detects that the SPI enable signal is converted from a low level to a high level, the timing control chip 10 automatically turns on the Mura compensation function.
  • Step S570 The timing control chip 10 re-reads the data (drive code and new Mura data) in the memory 30. This step corresponds to the time period T5 in FIG.
  • the method of implementing step S570 includes: when the timing control chip 10 detects that the detection control signal supplied to its restart terminal 13 is switched from a high level to a low level, the timing control chip 10 re-reads the data in the memory 30.
  • the timing control chip 10 turns off the signal detecting function.
  • step S510 when the detection control signal supplied to the restart terminal 13 of the timing control chip 10 is switched from the low potential to the high potential, the timing control chip 10 turns on the signal detection function. This step corresponds to the T1 time period in FIG.
  • the erasure of the original Mura compensation data stored in the memory is performed simultaneously with the formation of the new Mura compensation data, so that the formation of the new Mura compensation data is performed during the erasing period, Thereby, the erasing period is effectively utilized, thereby improving the production efficiency of the display panel.

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  • Physics & Mathematics (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板的Mura补偿数据的更新方法，所述更新方法包括步骤：将与存储器（30）连接的时序控制芯片（10）的Mura补偿功能关闭，以使显示面板显示无Mura补偿的原始画面（S210，S520）；断开所述时序控制芯片（10）与所述存储器（30）之间的连接（S220，S510）；将所述存储器（30）存储的原始Mura补偿数据擦除，同时根据所述显示面板显示的原始画面获取新Mura补偿数据（S230，S530）；将所述新Mura补偿数据写入所述存储器（30）（S240，S540）。方法中存储器（30）存储的原始Mura补偿数据的擦除与形成新Mura补偿数据同时进行，这样在擦除的时间段内进行新Mura补偿数据的形成，从而有效利用擦除时间段，从而提高显示面板的生产效率。

Description

显示面板的Mura补偿数据的更新方法 技术领域
本发明属于显示技术领域，具体地讲，涉及一种显示面板的Mura补偿数据的更新方法。
背景技术
在显示面板中，时序控制芯片(TCON IC)的驱动代码(code)一般存放在较小容量的闪存(flash)里面，而显示面板的Mura(亮暗不均匀)补偿数据量较大，需要存放在较大容量的闪存中。通常为了降低成本，可以将TCON IC的驱动代码和显示面板的Mura补偿数据放在同一较大容量的闪存中，定义好各自存储的位置区域，时序控制芯片即可通过同一线路同时读取到驱动代码和Mura补偿数据。
时序控制芯片的驱动代码是固定的，所以是预先批量烧录到闪存中的，不会占用显示面板的生产时间；而每片显示面板的Mura补偿数据都是不同的，需要在显示面板的生产过程中，经过Mura修补系统的擦除、原始Mura拍摄、数据处理及计算后，再烧录到闪存中，每一步过程都是不可缺少的，需要占用一定的生产时间。
擦除步骤是为了防止闪存中存有旧的或者错误的Mura补偿数据，对原始Mura的拍摄造成影响。在进行擦除步骤时，需要断开时序控制芯片与闪存之间的SPI(串行外设接口)线路连接，只有在擦除步骤完成之后，时序控制芯片重新上电，从而恢复连接时序控制芯片与闪存之间的SPI线路，时序控制芯片再读取闪存中的驱动代码(旧的或者错误的Mura补偿数据已经被擦除)，此时显示面板显示无Mura补偿的原始画面，然后才能开始进行后续的操作，诸如新Mura补偿数据的产生及存储。由此可知，擦除步骤需要的时间无法有效地利用起来，从而不利于显示面板的制造效率的提升。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种能够提高显示面板的制造效率的显示面板的Mura补偿数据的更新方法。
根据本发明的一方面，提供了一种显示面板的Mura补偿数据的更新方法，所述更新方法包括步骤：将与存储器连接的时序控制芯片的Mura补偿功能关闭，以使显示面板显示无Mura补偿的原始画面；断开所述时序控制芯片与所述存储器之间的连接；将所述存储器存储的原始Mura补偿数据擦除，同时根据所述显示面板显示的原始画面获取新Mura补偿数据；将所述新Mura补偿数据写入所述存储器。
进一步地，所述“将与存储器连接的时序控制芯片的Mura补偿功能关闭”的方法包括：利用I2C接口治具更改所述时序控制芯片的缓存内的设定寄存器配置数据，以使所述时序控制芯片的Mura补偿功能关闭；其中，所述设定寄存器配置数据用于控制所述时序控制芯片的Mura补偿功能开启或关闭。
进一步地，所述时序控制芯片经由SPI线路连接到所述存储器；所述“断开所述时序控制芯片与所述存储器之间的连接”的方法包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由高电位转换成低电位，以断开所述SPI线路；所述“恢复所述时序控制芯片与所述存储器之间的连接”的方法包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由低电位转换成高电位，以恢复所述SPI线路。
进一步地，所述“重启所述时序控制芯片”的方法包括步骤：将提供至所述时序控制芯片的重启端的信号由高电位转换成低电位；预定时间之后，将提供至所述时序控制芯片的重启端的信号由低电位转换成高电位。
进一步地，所述更新方法还包括步骤：恢复所述时序控制芯片与所述存储器之间的连接；重启所述时序控制芯片
根据本发明的另一方面，还提供了一种显示面板的Mura补偿数据的更新方法，所述更新方法包括步骤：断开时序控制芯片与存储器之间的连接；将所述时序控制芯片的Mura补偿功能关闭，以使显示面板显示无Mura补偿的原始画面；将所述存储器存储的原始Mura补偿数据擦除，同时根据所述显示面板显示的原始画面获取新Mura补偿数据；将所述新Mura补偿数据写入所述 存储器；恢复所述时序控制芯片与所述存储器之间的连接；将所述时序控制芯片的Mura补偿功能开启；所述时序控制芯片重新读取所述存储器中的数据。
进一步地，所述时序控制芯片经由SPI线路连接到所述存储器，以读取所述存储器中的数据；所述“断开时序控制芯片与存储器之间的连接”的方法包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由高电位转换成低电位，以断开所述SPI线路；所述“恢复所述时序控制芯片与所述存储器之间的连接”的方法包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由低电位转换成高电位，以恢复所述SPI线路。
进一步地，所述“将所述时序控制芯片的Mura补偿功能关闭”的方法包括：当所述时序控制芯片侦测到所述SPI使能信号由高电位转换成低电位时，所述时序控制芯片自动关闭Mura补偿功能；所述“将所述时序控制芯片的Mura补偿功能开启”的方法包括：当所述时序控制芯片侦测到所述SPI使能信号由低电位转换成高电位时，所述时序控制芯片自动开启Mura补偿功能。
进一步地，所述“所述时序控制芯片重新读取所述存储器中的数据”的方法包括：当所述时序控制芯片侦测到提供至其重启端的信号由高电位转换为低电位时，所述时序控制芯片重新读取所述存储器中的数据。
进一步地，在步骤“断开时序控制芯片与存储器之间的连接”之前，所述更新方法还包括：当提供至所述时序控制芯片的重启端的信号由低电位转换为高电位时，所述时序控制芯片开启信号侦测功能。
本发明的有益效果：在本发明中，存储器存储的原始Mura补偿数据的擦除与形成新Mura补偿数据同时进行，这样在擦除的时间段内进行新Mura补偿数据的形成，从而有效利用擦除时间段，从而提高显示面板的生产效率。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的显示面板的Mura补偿数据的补偿系统的结构示意图；
图2是根据本发明的实施例的显示面板的Mura补偿数据的补偿系统的更新方法的流程图；
图3是根据本发明的实施例的SPI使能信号和重启信号的时序图；
图4是根据本发明的另一实施例的显示面板的Mura补偿数据的补偿系统的结构示意图；
图5是根据本发明的另一实施例的显示面板的Mura补偿数据的补偿系统的更新方法的流程图；
图6是根据本发明的另一实施例的SPI使能信号和侦测控制信号的时序图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚起见，夸大了层和区域的厚度。相同的标号在附图中始终表示相同的元件。
图1是根据本发明的实施例的显示面板的Mura补偿数据的补偿系统的结构示意图。
参照图1，根据本发明的实施例的显示面板的Mura补偿数据的补偿系统包括：时序控制芯片(TCON IC)10、SPI(串行外设接口)线路20、存储器30、I2C(Inter-Integrated Circuit)接口治具40。
具体地，时序控制芯片(TCON IC)10设置在PCB板120上，存储器30设置在XB(横基板)PCB板130上，XBPCB板130连接到显示面板110上。在本实施例中，存储器30可例如是闪存(flash)，但本发明并不限制于此。
时序控制芯片10包括：连接端11、SPI使能端12以及重启端13。连接端 11经由SPI线路20连接到存储器30，以使时序控制芯片10读取存储器30的数据。SPI使能端12用于接收SPI使能信号，该SPI使能信用用于控制SPI线路20的断开与否。例如，当SPI使能信号为高电位时，SPI线路20连通；当SPI使能信号为低电位时，SPI线路20断开。重启端13用于接收重启信号，该重启信号用于关闭或者开启时序控制芯片10。
存储器30中存储Mura补偿数据和时序控制芯片10的驱动代码(code)。该驱动代码中具有设定寄存器配置数据，该设定寄存器配置数据用于控制时序控制芯片10的Mura补偿功能开启或关闭。时序控制芯片10中具有缓存；当时序控制芯片10经由SPI线路20从存储器30中读取到驱动代码之后，时序控制芯片10将设定寄存器配置数据存储在其缓存中，这样通过更改时序控制芯片10缓冲中的设定寄存器配置数据，能够开启或关闭时序控制芯片10的Mura补偿功能。一般在正常情况下，时序控制芯片10默认开启Mura补偿功能。
图2是根据本发明的实施例的显示面板的Mura补偿数据的补偿系统的更新方法的流程图。图3是根据本发明的实施例的SPI使能信号和重启信号的时序图。
一并参照图1至图3，根据本发明的实施例的显示面板的Mura补偿数据的补偿系统的更新方法包括：
步骤S210：将时序控制芯片10的Mura补偿功能关闭，以使显示面板110显示无Mura补偿的原始画面。该步骤对应图3中的Mura补偿关闭阶段T1。
实现步骤S210的方法包括：利用I2C接口治具40更改时序控制芯片10的缓存内的设定寄存器配置数据，以使时序控制芯片10的Mura补偿功能关闭。
步骤S220：断开时序控制芯片10与存储器30之间的连接。
实现步骤S220的方法包括：将提供至时序控制芯片10的SPI使能端12的SPI使能信号由高电位转换成低电位，以断开SPI线路20。
步骤S230：将存储器30存储的原始Mura补偿数据擦除，同时根据显示面板110显示的原始画面获取新Mura补偿数据。在图3中，在该步骤进行的 擦除阶段T2以及获取新Mura补偿数据的阶段T3中，SPI使能信号始终保持低电位，而时序控制芯片10的Mura补偿功能始终保持关闭，显示面板110显示无Mura补偿的原始画面。从步骤S230可知，擦除存储器30存储的原始Mura补偿数据与形成新Mura补偿数据同时进行，这样在擦除步骤的时间段内进行新Mura补偿数据的形成，从而有效利用擦除时间段。
步骤S240：将所述新Mura补偿数据写入存储器30。在图3中，在数据写入阶段T4中，SPI使能信号始终保持低电位，而获取新Mura补偿数据与新Mura补偿数据写入存储器30的时间(T3+T4)大于擦除存储器30存储的原始Mura补偿数据的时间(T2)。
步骤S250：恢复时序控制芯片10与存储器30之间的连接。
实现步骤S250的方法包括：将提供至时序控制芯片10的SPI使能端12的SPI使能信号由低电位转换成高电位，以连通SPI线路20。
步骤S260：重启时序控制芯片10。该步骤对应图3中的重启阶段T5。需要说明的是，重启时序控制芯片10后，时序控制芯片10默认开启Mura补偿功能。
实现步骤S260的方法包括：将提供至时序控制芯片10的重启端13的信号由高电位转换成低电位；预定时间之后，将提供至时序控制芯片10的重启端13的信号由低电位转换成高电位。需要说明的是，所述预定时间较短。
需要说明的是，上述步骤S210至步骤S240已经完成了Mura补偿数据的更新过程，步骤S250和步骤S260是回复时序控制芯片10与存储器30之间的连接和重启时序控制芯片10的过程，因此作为本发明的另一实施方式，步骤S250和步骤S260也可以被省略。
图4是根据本发明的另一实施例的显示面板的Mura补偿数据的补偿系统的结构示意图。
参照图4，根据本发明的另一实施例的显示面板的Mura补偿数据的补偿系统包括：时序控制芯片(TCON IC)10、SPI(串行外设接口)线路20、存储器30。
具体地，时序控制芯片(TCON IC)10设置在PCB板120上，存储器30设置在XB(横基板)PCB板130上，XBPCB板130连接到显示面板110上。在本实施例中，存储器30可例如是闪存(flash)，但本发明并不限制于此。
时序控制芯片10包括：连接端11、SPI使能端12以及重启端13。连接端11经由SPI线路20连接到存储器30，以使时序控制芯片10读取存储器30的数据。SPI使能端12用于接收SPI使能信号，该SPI使能信用用于控制SPI线路20的断开与否。例如，当SPI使能信号为高电位时，SPI线路20连通；当SPI使能信号为低电位时，SPI线路20断开。重启端13用于接收侦测控制信号，该侦测控制信号用于关闭或者开启控制芯片10的信号侦测功能。
存储器30中存储Mura补偿数据和时序控制芯片10的驱动代码(code)。序控制芯片10经由SPI线路20从存储器30中读取到驱动代码或Mura补偿数据。此外，在本实施例中，时序控制芯片10还根据其侦测到的SPI使能信号自动关闭或者开启Mura补偿功能。
图5是根据本发明的另一实施例的显示面板的Mura补偿数据的补偿系统的更新方法的流程图。图6是根据本发明的另一实施例的SPI使能信号和侦测控制信号的时序图。
一并参照图4至图6，根据本发明的另一实施例的显示面板的Mura补偿数据的补偿系统的更新方法包括：
步骤S510：断开时序控制芯片10与存储器30之间的连接。
实现步骤S510的方法包括：将提供至时序控制芯片10的SPI使能端12的SPI使能信号由高电位转换成低电位，以断开SPI线路20。
步骤S520：将时序控制芯片10的Mura补偿功能关闭，以使显示面板110显示无Mura补偿的原始画面。
实现步骤S520的方法包括：当时序控制芯片10侦测到SPI使能信号由高电位转换成低电位时，时序控制芯片10自动关闭Mura补偿功能。
步骤S530：将存储器30存储的原始Mura补偿数据擦除，同时根据显示 面板110显示的原始画面获取新Mura补偿数据。在图6中，在该步骤的擦除阶段T2以及获取新Mura补偿数据的阶段T3中，SPI使能信号始终保持低电位，而时序控制芯片10的Mura补偿功能始终保持关闭，显示面板110显示无Mura补偿的原始画面。从步骤S530可知，擦除存储器30存储的原始Mura补偿数据与形成新Mura补偿数据同时进行，这样在擦除步骤的时间段内进行新Mura补偿数据的形成，从而有效利用擦除时间段。
步骤S540：将所述新Mura补偿数据写入存储器30。在图6中，在数据写入阶段T4中，SPI使能信号始终保持低电位，而获取新Mura补偿数据与新Mura补偿数据写入存储器30的时间(T3+T4)大于擦除存储器30存储的原始Mura补偿数据的时间(T2)。
步骤S550：恢复时序控制芯片10与存储器30之间的连接。
实现步骤S550的方法包括：将提供至时序控制芯片10的SPI使能端12的SPI使能信号由低电位转换成高电位，以恢复SPI线路20。
步骤S560：将时序控制芯片10的Mura补偿功能开启。
实现步骤S560的方法包括：当时序控制芯片10侦测到SPI使能信号由低电位转换成高电位时，时序控制芯片10自动开启Mura补偿功能。
步骤S570：时序控制芯片10重新读取存储器30中的数据(驱动代码以及新的Mura数据)。该步骤对应图6中的时间段T5。
实现步骤S570的方法包括：当时序控制芯片10侦测到提供至其重启端13的侦测控制信号由高电位转换为低电位时，时序控制芯片10重新读取存储器30中的数据。这里，需要说明的是，当提供至时序控制芯片10的重启端13的信号由高电位转换为低电位时，时序控制芯片10关闭信号侦测功能。
此外，进一步地，在步骤S510之前，当提供至时序控制芯片10的重启端13的侦测控制信号由低电位转换为高电位时，时序控制芯片10开启信号侦测功能。该步骤对应图6中的T1时间段。
综上所述，在根据本发明的各实施例中，存储器存储的原始Mura补偿数 据的擦除与形成新Mura补偿数据同时进行，这样在擦除的时间段内进行新Mura补偿数据的形成，从而有效利用擦除时间段，从而提高显示面板的生产效率。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (12)

  1. 一种显示面板的Mura补偿数据的更新方法，其中，所述更新方法包括步骤：
    将与存储器连接的时序控制芯片的Mura补偿功能关闭，以使显示面板显示无Mura补偿的原始画面；
    断开所述时序控制芯片与所述存储器之间的连接；
    将所述存储器存储的原始Mura补偿数据擦除，同时根据所述显示面板显示的原始画面获取新Mura补偿数据；
    将所述新Mura补偿数据写入所述存储器。
  2. 根据权利要求1所述的显示面板的Mura补偿数据的更新方法，其中，将与存储器连接的时序控制芯片的Mura补偿功能关闭的步骤包括：利用12C接口治具更改所述时序控制芯片的缓存内的设定寄存器配置数据，以使所述时序控制芯片的Mura补偿功能关闭；
    其中，所述设定寄存器配置数据用于控制所述时序控制芯片的Mura补偿功能开启或关闭。
  3. 根据权利要求1所述的显示面板的Mura补偿数据的更新方法，其中，所述时序控制芯片经由SPI线路连接到所述存储器；
    断开所述时序控制芯片与所述存储器之间的连接的步骤包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由高电位转换成低电位，以断开所述SPI线路；
    所述恢复所述时序控制芯片与所述存储器之间的连接的步骤包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由低电位转换成高电位，以恢复所述SPI线路。
  4. 根据权利要求2所述的显示面板的Mura补偿数据的更新方法，其中， 所述时序控制芯片经由SPI线路连接到所述存储器；
    断开所述时序控制芯片与所述存储器之间的连接的步骤包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由高电位转换成低电位，以断开所述SPI线路；
    所述恢复所述时序控制芯片与所述存储器之间的连接的步骤包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由低电位转换成高电位，以恢复所述SPI线路。
  5. 根据权利要求1所述的显示面板的Mura补偿数据的更新方法，其中，重启所述时序控制芯片的步骤包括：
    将提供至所述时序控制芯片的重启端的信号由高电位转换成低电位；
    预定时间之后，将提供至所述时序控制芯片的重启端的信号由低电位转换成高电位。
  6. 根据权利要求1所述的显示面板的Mura补偿数据的更新方法，其中，所述更新方法还包括步骤：
    恢复所述时序控制芯片与所述存储器之间的连接；
    重启所述时序控制芯片。
  7. 一种显示面板的Mura补偿数据的更新方法，其中，所述更新方法包括步骤：
    断开时序控制芯片与存储器之间的连接；
    将所述时序控制芯片的Mura补偿功能关闭，以使显示面板显示无Mura补偿的原始画面；
    将所述存储器存储的原始Mura补偿数据擦除，同时根据所述显示面板显示的原始画面获取新Mura补偿数据；
    将所述新Mura补偿数据写入所述存储器；
    恢复所述时序控制芯片与所述存储器之间的连接；
    将所述时序控制芯片的Mura补偿功能开启；
    所述时序控制芯片重新读取所述存储器中的数据。
  8. 根据权利要求7所述的Mura补偿数据的更新方法，其中，所述时序控制芯片经由SPI线路连接到所述存储器，以读取所述存储器中的数据；
    断开时序控制芯片与存储器之间的连接的步骤包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由高电位转换成低电位，以断开所述SPI线路；
    恢复所述时序控制芯片与所述存储器之间的连接的步骤包括：将提供至所述时序控制芯片的SPI使能端的SPI使能信号由低电位转换成高电位，以恢复所述SPI线路。
  9. 根据权利要求8所述的Mura补偿数据的更新方法，其中，将所述时序控制芯片的Mura补偿功能关闭的步骤包括：当所述时序控制芯片侦测到所述SPI使能信号由高电位转换成低电位时，所述时序控制芯片自动关闭Mura补偿功能；
    将所述时序控制芯片的Mura补偿功能开启的步骤包括：当所述时序控制芯片侦测到所述SPI使能信号由低电位转换成高电位时，所述时序控制芯片自动开启Mura补偿功能。
  10. 根据权利要求8所述的Mura补偿数据的更新方法，其中，所述时序控制芯片重新读取所述存储器中的数据的步骤包括：当所述时序控制芯片侦测到提供至其重启端的信号由高电位转换为低电位时，所述时序控制芯片重新读取所述存储器中的数据。
  11. 根据权利要求9所述的Mura补偿数据的更新方法，其中，在断开时序控制芯片与存储器之间的连接的步骤之前，所述更新方法还包括：当提供至所述时序控制芯片的重启端的信号由低电位转换为高电位时，所述时序控制芯片开启信号侦测功能。
  12. 根据权利要求10所述的Mura补偿数据的更新方法，其中，在断开时序控制芯片与存储器之间的连接的步骤之前，所述更新方法还包括：当提供至所述时序控制芯片的重启端的信号由低电位转换为高电位时，所述时序控制芯片开启信号侦测功能。
PCT/CN2018/073092 2017-12-06 2018-01-17 显示面板的Mura补偿数据的更新方法 Ceased WO2019109477A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246469A (zh) * 2019-07-29 2019-09-17 深圳市华星光电技术有限公司 统一格式的demura数据应用方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831393B (zh) * 2018-06-27 2020-12-22 深圳市华星光电半导体显示技术有限公司 液晶显示面板Mura补偿优化方法及优化系统
TWI692099B (zh) * 2019-04-23 2020-04-21 大陸商北京集創北方科技股份有限公司 顯示面板驅動電路之軟性錯誤檢測與重啟方法及顯示裝置
CN110827777B (zh) * 2019-10-18 2020-11-24 深圳市华星光电技术有限公司 显示面板驱动装置及其配置方法
CN110910848A (zh) * 2019-11-28 2020-03-24 Tcl华星光电技术有限公司 液晶显示器的驱动电路及驱动方法
CN111145699A (zh) * 2019-12-26 2020-05-12 深圳市华星光电半导体显示技术有限公司 代码读取方法、时序控制器和计算机可读存储介质
CN111629263A (zh) * 2020-05-13 2020-09-04 深圳市华星光电半导体显示技术有限公司 显示画面补偿方法、装置、电子设备及存储介质
CN111681585B (zh) * 2020-06-05 2023-10-13 Tcl华星光电技术有限公司 一种显示面板的驱动电路及显示装置
CN113327533B (zh) * 2021-05-20 2023-06-27 Tcl华星光电技术有限公司 显示装置的补偿数据修复方法及补偿数据修复装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001886A1 (en) * 2006-06-30 2008-01-03 Jang-Hwan Kim Circuit for stabilizing common voltage of a liquid crystal display device
CN102855856A (zh) * 2012-08-30 2013-01-02 南京中电熊猫液晶显示科技有限公司 一种消除液晶显示器Mura的驱动方法及其液晶显示器
CN105244004A (zh) * 2015-11-23 2016-01-13 深圳市华星光电技术有限公司 控制板及具有该控制板的液晶显示器
CN105390111A (zh) * 2015-12-14 2016-03-09 深圳市华星光电技术有限公司 时序控制器的检测方法及检测装置
CN107170415A (zh) * 2017-05-10 2017-09-15 深圳市华星光电技术有限公司 横基板和控制板合并架构的LCD面板及其mura修补控制方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446479B (zh) * 2010-10-12 2014-04-30 群康科技(深圳)有限公司 显示器及其驱动方法
KR102023940B1 (ko) * 2012-12-27 2019-11-04 엘지디스플레이 주식회사 표시장치용 구동회로 및 이의 구동방법
CN105427822B (zh) * 2015-12-29 2017-12-29 深圳市华星光电技术有限公司 灰阶补偿数据重置装置及方法
KR102519371B1 (ko) * 2016-01-20 2023-04-10 삼성디스플레이 주식회사 Ela 얼룩 보상 방법 및 이를 채용한 표시 장치
CN106847224A (zh) * 2017-04-06 2017-06-13 深圳市华星光电技术有限公司 Lcd面板数据烧录治具并联方法及系统
CN106910483B (zh) * 2017-05-03 2019-11-05 深圳市华星光电技术有限公司 一种显示面板的mura现象补偿方法及显示面板
CN106898327B (zh) * 2017-05-03 2019-11-05 深圳市华星光电技术有限公司 一种显示面板的mura现象补偿方法及显示面板
US20190088195A1 (en) * 2017-09-15 2019-03-21 Synaptics Incorporated Mura correction for an led display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001886A1 (en) * 2006-06-30 2008-01-03 Jang-Hwan Kim Circuit for stabilizing common voltage of a liquid crystal display device
CN102855856A (zh) * 2012-08-30 2013-01-02 南京中电熊猫液晶显示科技有限公司 一种消除液晶显示器Mura的驱动方法及其液晶显示器
CN105244004A (zh) * 2015-11-23 2016-01-13 深圳市华星光电技术有限公司 控制板及具有该控制板的液晶显示器
CN105390111A (zh) * 2015-12-14 2016-03-09 深圳市华星光电技术有限公司 时序控制器的检测方法及检测装置
CN107170415A (zh) * 2017-05-10 2017-09-15 深圳市华星光电技术有限公司 横基板和控制板合并架构的LCD面板及其mura修补控制方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246469A (zh) * 2019-07-29 2019-09-17 深圳市华星光电技术有限公司 统一格式的demura数据应用方法

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