WO2019100284A1

WO2019100284A1 - Phase locking method, apparatus and device

Info

Publication number: WO2019100284A1
Application number: PCT/CN2017/112562
Authority: WO
Inventors: 唐疑军; 刘鹏飞; 邓向钖; 刘晓红; 杨冬梅; 吴壬华
Original assignee: 深圳欣锐科技股份有限公司
Priority date: 2017-11-23
Filing date: 2017-11-23
Publication date: 2019-05-31
Also published as: CN109075796B; CN109075796A

Abstract

A phase locking method, apparatus and device. The method comprises: circularly sampling power grid voltage information in a quarter cycle of a power grid voltage signal wave; setting an array with the length of L, L being jointly determined by a frequency of a power grid voltage and a sampling frequency; setting a first variable S1 and a second variable S2, S2=S1+1; generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2; and performing voltage Park conversion on the first signal wave Ua and the second signal wave Ub, so as to implement phase locking. A phase difference free component is obtained by means of an array, phase angle tracking is implemented in combination with Park conversion, the computing amount is small, and the reliability is high.

Description

Phase locking method, device and device

Technical field

The present application relates to the field of power electronic control, and in particular, to a phase locking method, device and device.

Background technique

With the development of modern industry, the widespread application of power electronic devices and non-linear loads has generated a large number of harmonics, resulting in rapid growth of harmonic current components in power systems, distortion of current waveforms, and increased loss of line losses and electrical equipment. The system power factor is drastically reduced, which seriously affects the power quality of the grid.

Pulse Width Modulation (PWM) rectifiers can realize sinusoidal current on the grid side and operate in unity power factor state, and have the function of bidirectional energy feedback. Therefore, the PWM rectifier is widely used in the case of AC-converted DC and DC-converted AC.

An important performance indicator of a PWM rectifier is the unity power factor at the AC input side. However, due to the hardware delay detection error, voltage input harmonics, phase and frequency fluctuations, the general phase-locking method is difficult to achieve real-time effective tracking of the phase, the dynamic response speed is slow, and the anti-disturbance capability is poor. Therefore, in order to achieve the unit power factor, it is necessary to realize the real-time tracking of the grid input voltage by the grid input current, that is, to achieve the same frequency in phase of the input current and the input voltage. Moreover, since the single-phase grid has only one degree of freedom component, for single-phase PWM rectification, the dq coordinate transformation cannot be directly performed like the three-phase PWM rectification. If the dq coordinate transformation is used to continue phase locking in single-phase PWM rectification, another free component with a phase difference of 90 degrees needs to be virtualized, and the voltage Park tracking is used to process the phase angle tracking, but the method is computationally intensive and inaccurate.

Summary of the invention

The embodiment of the present application provides a phase locking method, device and device, in order to provide a phase locking method suitable for single phase PWM rectification, which has small calculation amount and high precision.

A first aspect of the embodiments of the present application provides a phase locking method, including:

Cycle sampling the grid voltage signal within a quarter of the grid voltage signal wave;

Setting an array of length L, wherein the L is determined by the frequency of the grid voltage and the sampling frequency; setting the first variable S1 and the second variable S2, wherein S2=S1+1;

Generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2;

The first signal wave Ua and the second signal wave Ub are subjected to voltage Park conversion to achieve phase locking.

With reference to the first aspect of the embodiments of the present application, in a first implementation manner of the first aspect of the embodiments of the present application, before the setting an array of length L, the method further includes: determining a value of the array length L.

With reference to the first implementation manner of the first aspect of the embodiment of the present application, in the second implementation manner of the first aspect of the embodiment, the determining the value of the array length L includes:

Determining a period of the signal wave according to a frequency of the grid voltage signal wave;

Determining, according to a period of the signal wave, a duration of a quarter period of the signal wave;

Determining the sampling period according to the sampling frequency;

The number of sampling points in the quarter period of the signal wave, that is, the value of the length L, is determined according to the length of time occupied by the quarter period of the signal wave and the sampling period.

With reference to the first aspect of the embodiments of the present application, in a third implementation manner of the first aspect of the embodiment, the first signal wave Ua is generated according to the first variable S1, and generated according to the second variable S2. The second signal wave Ub includes:

And causing the first variable S1 to cyclically sample in a quarter cycle of the signal wave, and buffering element information sampled by the first variable S1;

Causing the element information sampled by the second variable S2 according to the cyclic sampling of the first variable S1;

The first signal wave Ua is generated according to the element information sampled by the first variable S1, and the second signal wave Ub is generated according to the element information sampled by the second variable S2.

With reference to the first aspect of the embodiments of the present application, in a fourth implementation manner of the first aspect of the embodiments, the element information includes at least angle information and voltage value information.

A second aspect of the embodiments of the present application provides a phase locking device, including:

a sampling module for cyclically sampling a grid voltage signal within a quarter cycle of a grid voltage signal wave;

a first setting module, configured to set an array of length L, wherein the L is determined by a common frequency and a sampling frequency of the grid voltage;

a second setting module, configured to set a first variable S1 and a second variable S2, wherein S2=S1+1;

a generating module, configured to generate a first signal wave Ua according to the first variable S1, and generate a second signal wave Ub according to the second variable S2;

And a transform module, configured to perform voltage Park conversion on the first signal wave Ua and the second signal wave Ub to implement phase locking.

With reference to the second aspect of the embodiments of the present application, in a first implementation manner of the second aspect of the embodiments, the apparatus further includes a determining module, configured to set a length L in the first setting module. Before the array, determine the value of the array length L.

With reference to the first implementation manner of the second aspect of the embodiment of the present application, in the second implementation manner of the second aspect of the embodiment, the determining module includes:

a first determining unit, configured to determine a period of the signal wave according to a frequency of the grid voltage signal wave;

a second determining unit, configured to determine, according to a period of the signal wave, a duration of a quarter period of the signal wave;

a third determining unit, configured to determine the sampling period according to the sampling frequency;

a fourth determining unit, configured to determine, according to a duration occupied by a quarter period of the signal wave and the sampling period, a number of sampling points in a quarter period of the signal wave, that is, a value of the length L .

With reference to the second aspect of the embodiments of the present application, in a third implementation manner of the second aspect of the embodiments, the generating module includes:

a first buffer unit, configured to: cyclically sample the first variable S1 in a quarter cycle of the signal wave, and buffer element information sampled by the first variable S1;

a second buffer unit, configured to buffer element information sampled by the second variable S2 according to the cyclic sampling of the first variable S1;

And a generating unit, configured to generate a first signal wave Ua according to the element information sampled by the first variable S1, and generate a second signal wave Ub according to the element information sampled by the second variable S2.

With reference to the second aspect of the embodiments of the present application, in a fourth implementation manner of the second aspect of the embodiments of the present application, the element information includes at least angle information and voltage value information.

A third aspect of the embodiments of the present application provides a phase locking device, including:

a memory for storing a phase lock program instruction;

The processor is configured to invoke the phase lock program instruction, and execute the phase lock method in the first aspect of the embodiment of the present application or the implementation manner in any one of the first aspect.

Embodiments of the present application may be configured to cyclically sample a grid voltage signal within a quarter cycle of a grid voltage signal wave; and simultaneously set an array of length L according to the frequency and sampling frequency of the grid voltage; a first variable S1 and a second variable S2, wherein S2=S1+1; generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2; The first signal wave Ua and the second signal wave Ub are subjected to voltage Park conversion to achieve phase locking, so that the phase locking method shown in the embodiment of the present application has a small calculation amount and high reliability.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

FIG. 1 is a flowchart of a phase locking method according to an embodiment of the present application;

2 is a flowchart of a method for generating a first signal wave and a second signal wave according to an embodiment of the present application;

3 is a flowchart of a phase locking method according to another embodiment of the present application;

4 is a flowchart of a method for determining an L value according to an embodiment of the present application;

FIG. 5 is a structural diagram of a phase lock device according to an embodiment of the present application;

6 is a structural diagram of a phase lock device according to another embodiment of the present application;

FIG. 7 is a structural diagram of a determining module according to an embodiment of the present application;

FIG. 8 is a structural diagram of a generation module according to an embodiment of the present application;

FIG. 9 is a structural diagram of a phase lock device according to an embodiment of the present application.

Detailed ways

The terms "comprising" and "having", and any variations thereof, appearing in the specification, the claims, and the drawings are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or alternatively For these processes, methods, products or Other steps or units inherent to the device.

The flowcharts that may be used in the embodiments of the present application are first described below with reference to the related drawings.

As shown in FIG. 1 , FIG. 1 is a phase locking method provided by an embodiment of the present application, and may include at least the following steps:

S101: Cycle sampling the grid voltage information in a quarter cycle of the grid voltage signal wave.

Specifically, the frequency of the grid voltage is 50 Hz±0.2 Hz, and the signal wave may be a sinusoidal signal or a cosine signal, and the frequency is 47-63 Hz. The sampling range is one quarter of the period of the grid voltage signal.

S102: Set an array of length L.

Specifically, the L is determined by the frequency of the grid voltage and the sampling frequency.

Specifically, L signal points are acquired on a quarter cycle of the grid voltage signal according to a preset sampling frequency. These L signal points are sequentially stored in the array.

S103: Set the first variable S1 and the second variable S2, where S2=S1+1.

In particular, the first variable S1 can be a pointer to the current grid voltage sample value stored in the array. The second variable S2 can be a pointer, and the element pointed to by the variable S2 is the element indicated by S1+1. For example, when S1 points to the first element, S2 points to the second element; when S1 points to the Lth element, S2 points to the first element. The sampled grid voltage data is cyclically stored in the array, that is, if the current sampled data is stored at the end of the array, the next sampled data is stored at the beginning of the array. It can be known that the phase difference between the Nth element indicated by S1 and the Nth element indicated by S2 is 90°, where 1≤N≤L.

S104: Generate a first signal wave Ua according to the first variable S1, and generate a second signal wave Ub according to the second variable S2.

Specifically, the first variable S1 and the second variable S2 may be pointers. Since S2=S1+1, the phase difference between the Nth element indicated by S1 and the Nth element indicated by S2 is 90°. Therefore, the phase difference between the first signal wave Ua generated according to the first variable S1 and the second signal wave Ub generated according to the second variable S2 is 90°.

Please refer to FIG. 2. FIG. 2 is a method for generating a first signal wave and a second signal wave, and at least includes the following steps:

S1041: Looping the first variable S1 in a quarter cycle of the signal wave, and The element information sampled by the first variable S1 is buffered.

Specifically, the first variable S1 is cyclically sampled in a quarter cycle of the signal wave, and after sampling the Lth point, the first sample point is returned, sampling is continued, and all elements of the first variable S1 are buffered. Element information.

Specifically, the element information may include at least angle information corresponding to the element and corresponding voltage value information.

S1042: Cache the element information sampled by the second variable S2 according to the cyclic sampling of the first variable S1.

Specifically, the first variable S1 always points to the current element stored in the array (ie, the sample value of the current grid voltage), S2=S1+1, and the element pointed to by the variable S2 is the element indicated by S1+1. In particular, when S1 points to the last element in the array, S2 now points to the first element in the array. The element information of each element in the array pointed to by the second variable S2 is cached.

S1043: Generate a first signal wave Ua according to the element information sampled by the first variable S1, and generate a second signal wave Ub according to the element information sampled by the second variable S2.

Specifically, the angle information of the element indicated by the first variable S1 is different from the angle information of the element indicated by the second variable S2 by 90° and remains unchanged. For example, assume that the angle information of the element indicated by the first variable S1 is α, and the angle information of the element indicated by the second variable S2 is β. Then, when the angle information α of the element indicated by the first variable S1 is 0°, the angle information β of the element indicated by the second variable S2 is −90°; then the angle information α of the element indicated by the first variable S1 is 90°. The angle information β of the element indicated by the second variable S2 is 0°.

Specifically, the element information sampled by the first variable S1 constitutes a digital signal, and the analog signal Ua is generated according to the digital signal; the element information sampled by the second variable S2 constitutes a digital signal, and the analog signal Ub is generated according to the digital signal.

Specifically, since S2=S1+1, the phase difference between the Nth element indicated by S1 and the Nth element indicated by S2 is 90°. Therefore, the phase difference between the first signal wave Ua generated according to the first variable S1 and the second signal wave Ub generated according to the second variable S2 is 90°.

S105: performing voltage Park conversion on the first signal wave Ua and the second signal wave Ub to implement phase locking.

Specifically, the phase difference between the first signal wave Ua and the second signal wave Ub is 90°, and Park transformation is performed on Ua and Ub, and converted into Ud and Uq components in the dq coordinate system to realize phase angle tracking.

As shown in FIG. 3, FIG. 3 is a phase locking method according to another embodiment of the present application, and may include at least the following steps:

S201: Cycle sampling the grid voltage signal in a quarter cycle of the grid voltage signal wave.

It is consistent with S101 and will not be described here.

S202: Determine the value of the array length L.

Specifically, the value of L is determined by the frequency of the grid voltage and the sampling frequency. According to the Shannon sampling theorem, in order to recover the analog signal without distortion, the sampling frequency should be no less than twice the highest frequency in the spectrum of the analog signal. It can be known that the sinusoidal signal of the grid voltage is an analog signal, and the frequency of the sinusoidal signal wave is 47-63 Hz, and a certain adaptive frequency range needs to be extended. In the present application, the frequency range is extended to 40-70 Hz, then when sine When the frequency of the signal wave is 40 Hz, the sampling frequency is not less than 80 Hz to ensure the undistorted recovery of the analog signal. When the frequency of the sinusoidal signal wave is 70 Hz, the sampling frequency is not less than 140 Hz to ensure the undistorted recovery of the analog signal. The higher the sampling frequency, the higher the accuracy of acquiring analog signals. In the embodiment of the present application, the sampling frequency is set to 30 kHz, and the frequency of the signal wave is assumed to be 40 Hz.

Please refer to Figure 4. FIG. 4 is a method for determining an L value according to an embodiment of the present application, which may include at least the following steps:

S2021: Determine a period of the signal wave according to a frequency of the grid voltage signal wave.

Specifically, the frequency fs of the grid voltage signal wave is 40 Hz, and the period of the grid voltage signal wave is 25 ms.

S2022: Determine a duration of a quarter period of the signal wave according to a period of the signal wave.

Specifically, the period of the grid voltage signal wave is 25 ms, and the period of the quarter period is 6250 us.

S2023: Determine the sampling period according to the sampling frequency.

Specifically, the sampling frequency is set to 30 kHz, and the sampling period is 33.33 us.

S2024: Determine, according to the duration of the quarter period of the signal wave and the sampling period, the number of sampling points in the quarter period of the signal wave, that is, the value of the length L.

Specifically, the quarter period takes 6250us and the sampling period is 33.33us, and the number of sampling points in the quarter period of the signal wave is at least 6250us/33.33us=188. Therefore, the value of the length L is greater than 188.

It can be known that the higher the frequency of the signal wave, the smaller the period. The fewer the number of samples in the quarter cycle of the signal wave at a fixed sampling frequency. Therefore, the number of sampling points in the case where the signal wave frequency is the lowest is calculated, and the sampling condition in the entire frequency range can be covered.

S203: Set an array of length L.

It is consistent with S102 and will not be described here.

S204: Set the first variable S1 and the second variable S2, where S2=S1+1.

It is consistent with S103 and will not be described here.

S205: Generate a first signal wave Ua according to the first variable S1, and generate a second signal wave Ub according to the second variable S2.

It is consistent with S104 and will not be described here.

S206: Perform voltage phase conversion on the first signal wave Ua and the second signal wave Ub to implement phase locking.

It is consistent with S105 and will not be described here.

Embodiments of the present application may be configured to cyclically sample a grid voltage signal within a quarter cycle of a grid voltage signal wave; and simultaneously set an array of length L according to the frequency and sampling frequency of the grid voltage; a first variable S1 and a second variable S2, wherein S2=S1+1; generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2; The first signal wave Ua and the second signal wave Ub are subjected to voltage Park conversion to realize phase locking, so that the phase locking method, device and device shown in the embodiment of the present application have small calculation amount and high reliability.

The embodiment of the present application correspondingly provides a phase lock device. As shown in FIG. 5, the phase locking device 10 can include at least a sampling module 110, a first setting module 120, a second setting module 130, a generating module 140, and a transform module 150, where:

The sampling module 110 is configured to cyclically sample the grid voltage information in a quarter cycle of the grid voltage signal wave.

The first setting module 120 is configured to set an array of length L, wherein the L is determined by the frequency of the grid voltage and the sampling frequency.

The second setting module 130 is configured to set the first variable S1 and the second variable S2, where S2=S1+1.

The generating module 140 is configured to generate a first signal wave Ua according to the first variable S1, and generate a second signal wave Ub according to the second variable S2.

The conversion module 150 is configured to perform voltage Park conversion on the first signal wave Ua and the second signal wave Ub to implement phase locking.

In a possible embodiment, as shown in FIG. 6 , the phase lock device 10 may include, in addition to the sampling module 110 , the first setting module 120 , the second setting module 130 , the generating module 140 , and the transform module 150 . The determining module 160 is configured to determine the value of the array length L before the first setting module 120 sets an array of length L.

In one possible embodiment, the determining module 160 may include a first determining unit 1610, a second determining unit 1620, a third determining unit 1630, and a fourth determining unit 1640, as shown in FIG.

a first determining unit 1610, configured to determine a period of the signal wave according to a frequency of the grid voltage signal wave;

a second determining unit 1620, configured to determine, according to a period of the signal wave, a duration of a quarter period of the signal wave;

a third determining unit 1630, configured to determine the sampling period according to the sampling frequency;

a fourth determining unit 1640, configured to determine, according to a duration occupied by a quarter period of the signal wave and the sampling period, a number of sampling points in a quarter period of the signal wave, that is, the length L value.

In a possible embodiment, the generating module 140 may include a first buffer unit 1410, a second buffer unit 1420, and a generating unit 1430, as shown in FIG.

The first buffer unit 1410 is configured to cyclically sample the first variable S1 in a quarter cycle of the signal wave, and buffer the element information sampled by the first variable S1.

The second buffer unit 1420 is configured to buffer element information sampled by the second variable S2 according to the cyclic sampling of the first variable S1.

The generating unit 1430 is configured to generate a first signal wave Ua according to the element information sampled by the first variable S1, and generate a second signal wave Ub according to the element information sampled by the second variable S2.

In a possible embodiment, the element information includes at least angle information and voltage value information.

It is to be understood that the functions of the functional modules of the phase-locking device 10 of the present embodiment may be specifically implemented according to the method in the foregoing method embodiments, and details are not described herein again.

Embodiments of the present application may be configured to cyclically sample grid voltage information within a quarter cycle of a grid voltage signal wave; and simultaneously set an array of length L according to the frequency and sampling frequency of the grid voltage; a first variable S1 and a second variable S2, wherein S2=S1+1; generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2; The first signal wave Ua and the second signal wave Ub are subjected to voltage Park conversion to achieve phase locking, so that the phase locking method shown in the embodiment of the present application has a small calculation amount and high reliability.

The embodiment of the present application correspondingly provides a phase lock device. As shown in FIG. 9, the phase locking device 20 can include at least:

a memory 210, configured to store a phase lock program;

The processor 220 is configured to call a phase lock program stored in the memory 210, and execute:

Circulating sampling grid voltage information within a quarter of a period of the grid voltage signal wave;

Setting an array of length L, wherein the L is determined by the frequency of the grid voltage and the sampling frequency;

Setting a first variable S1 and a second variable S2, wherein S2=S1+1;

In a possible embodiment, before setting an array of length L, the processor 220 is further configured to: determine the value of the array length L.

In a possible embodiment, the processor 220 determines the value of the array length L, including:

Determining the sampling period according to the sampling frequency;

In a possible embodiment, the processor 220 generates the first signal wave Ua according to the first variable S1, and generates the second signal wave Ub according to the second variable S2, including:

Embodiments of the present application may be configured to cyclically sample grid voltage information within a quarter cycle of a grid voltage signal wave; and simultaneously set an array of length L according to the frequency and sampling frequency of the grid voltage; a first variable S1 and a second variable S2, wherein S2=S1+1; generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2; The first signal wave Ua and the second signal wave Ub are subjected to voltage Park conversion to realize phase locking, so that the phase locking method, device and device shown in the embodiment of the present application have small calculation amount and high reliability.

The steps in the method of the embodiment of the present application may be sequentially adjusted, merged, and deleted according to actual needs.

The modules in the apparatus of the embodiment of the present application may be combined, divided, and deleted according to actual needs.

The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the embodiments are modified, or some of the technical features are replaced by equivalents; and the modifications or substitutions do not deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

A phase locking method, comprising:

Circulating sampling grid voltage information within a quarter of a period of the grid voltage signal wave;

Setting an array of length L, wherein the L is determined by the frequency of the grid voltage and the sampling frequency;

Setting a first variable S1 and a second variable S2, wherein S2=S1+1;

Generating a first signal wave Ua according to the first variable S1, and generating a second signal wave Ub according to the second variable S2;

The first signal wave Ua and the second signal wave Ub are subjected to voltage Park conversion to achieve phase locking.
The method of claim 1 wherein said method further comprises: determining a value of an array length L prior to said setting an array of length L.
The method of claim 2 wherein said determining a value of an array length L comprises:

Determining a period of the signal wave according to a frequency of the grid voltage signal wave;

Determining, according to a period of the signal wave, a duration of a quarter period of the signal wave;

Determining the sampling period according to the sampling frequency;

The number of sampling points in the quarter period of the signal wave, that is, the value of the length L, is determined according to the length of time occupied by the quarter period of the signal wave and the sampling period.
The method according to claim 1, wherein the generating the first signal wave Ua according to the first variable S1 and generating the second signal wave Ub according to the second variable S2 comprises:

And causing the first variable S1 to cyclically sample in a quarter cycle of the signal wave, and buffering element information sampled by the first variable S1;

Causing the element information sampled by the second variable S2 according to the cyclic sampling of the first variable S1;

Generating a first signal wave Ua according to the element information sampled by the first variable S1, and according to the first The element information sampled by the two variables S2 generates a second signal wave Ub.
The method of claim 4 wherein said element information comprises at least angle information and voltage value information.
A phase locking device, comprising:

a sampling module for cyclically sampling grid voltage information within a quarter cycle of a grid voltage signal wave;

a first setting module, configured to set an array of length L, wherein the L is determined by a common frequency and a sampling frequency of the grid voltage;

a second setting module, configured to set a first variable S1 and a second variable S2, wherein S2=S1+1;

a generating module, configured to generate a first signal wave Ua according to the first variable S1, and generate a second signal wave Ub according to the second variable S2;

And a transform module, configured to perform voltage Park conversion on the first signal wave Ua and the second signal wave Ub to implement phase locking.
The apparatus according to claim 6, wherein said apparatus further comprises a determining module for determining a value of the array length L before said first setting module sets an array of length L.
The apparatus of claim 7, wherein the determining module comprises:

a first determining unit, configured to determine a period of the signal wave according to a frequency of the grid voltage signal wave;

a second determining unit, configured to determine, according to a period of the signal wave, a duration of a quarter period of the signal wave;

a third determining unit, configured to determine the sampling period according to the sampling frequency;

a fourth determining unit, configured to determine, according to a duration occupied by a quarter period of the signal wave and the sampling period, a number of sampling points in a quarter period of the signal wave, that is, a value of the length L .
The apparatus of claim 6, wherein the generating module comprises:

a first buffer unit, configured to: cyclically sample the first variable S1 in a quarter cycle of the signal wave, and buffer element information sampled by the first variable S1;

a second buffer unit, configured to buffer element information sampled by the second variable S2 according to the cyclic sampling of the first variable S1;

And a generating unit, configured to generate a first signal wave Ua according to the element information sampled by the first variable S1, and generate a second signal wave Ub according to the element information sampled by the second variable S2.
The apparatus according to claim 9, wherein said element information includes at least angle information and voltage value information.
A phase locking device, comprising:

a memory for storing a phase lock program instruction;

And a processor, configured to invoke the phase locked program instruction, and perform the phase locking method according to any one of claims 1-5.