CN111082691B

CN111082691B - Method and system for generating SPWM wave by utilizing FPGA

Info

Publication number: CN111082691B
Application number: CN201911392811.XA
Authority: CN
Inventors: 刘三军; 宋鹏龙; 来国红; 谭建军; 孙先波; 朱黎; 李绍武; 高仕红; 徐建; 胡俊鹏
Original assignee: Hubei University for Nationalities
Current assignee: Hubei University for Nationalities
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2021-01-01
Anticipated expiration: 2039-12-30
Also published as: CN111082691A

Abstract

The invention discloses a method and a system for generating an SPWM wave by utilizing an FPGA (field programmable gate array), which comprise an external ADC (analog to digital converter) sampling module and a self-defined IP (Internet protocol) core, wherein the self-defined IP core comprises an SPWM wave generating module and a phase control register group, and the SPWM wave generating module comprises a triangular wave generating module, a sine wave generating module, a phase-locked loop and an SPWM wave generating logic module. The system self-defines an Avalon bus interface configured by an IP core, so that the selection of sine waves and the phase of a generated signal can be conveniently set by a CPU (central processing unit) in a register access mode. The IP core designed by the scheme has the advantages of high precision, convenience in use, good generated SPWM waveform, less occupied resources and the like, and the SPWM wave is independently generated in the whole process to release the processor.

Description

Method and system for generating SPWM wave by utilizing FPGA

Technical Field

The invention relates to the technical field of power electronics, in particular to a method and a system for generating an SPWM wave by utilizing an FPGA.

Background

With the gradual depletion of fossil energy such as coal, petroleum and the like and the continuous deterioration of human living environment, the development and utilization of renewable natural resources such as solar energy, wind energy and the like are generally regarded as important at home and abroad in recent years, and many countries make decisions and plans for popularizing the development and utilization of renewable energy such as solar energy and the like on a large scale. For the existing new energy power generation, the defects of poor stability, difficulty in continuous work, large influence of environmental factors and the like still restrict the development of the new energy power generation to a certain extent, so that a reliable and efficient energy conversion mode is imperatively found. The inverter can convert direct current into alternating current and realize grid-connected power generation, so the inverter becomes a core device of a new energy system, is an indispensable important device in the technical fields of photovoltaic power generation, wind power generation and the like, and has important research value.

At present, most inverters in the market adopt the SPWM technology to realize frequency conversion control, the SPWM technology is used for realizing output of approximate sine waves, and various civil products and military products adopt the control technology to realize sine wave output with adjustable frequency, so that the inverter has a very good use effect. However, the generation of the SPWM wave usually needs some special DSP chips, and is usually used in some occasions with very high requirements on waveform indexes, and this basic SPWM control technology cannot meet the influence on the output waveform after the load changes, and the function of controlling the photovoltaic inverter to convert the dc electric energy into the sine wave ac current with the same frequency and phase as the power grid and to access the power grid to realize grid-connected power generation in the current market is usually very tedious, and the reaction is not fast enough, and the hysteresis effect is very obvious.

In order to solve the problems, a method and a system for generating SPWM waves by utilizing an FPGA are provided. The self-defined IP core is applied to the inverter, the inverter can realize the output of approximate sine waves through the SPWM technology, and can also adjust the phase of the generated sine waves in real time, thereby realizing the perfect photovoltaic grid connection and adjustment functions. The main idea of the scheme is that paired SPWM and SPWM non-signals are generated through a well-designed logic circuit, the phase detection module is matched to detect the phase of sine waves on a power grid, real-time phase information is fed back to a NiosII CPU, the NiosII CPU controls the delay time of the SPWM signals in an IP core by using a C language, so that an inverter outputs sine signals in phase with the power grid, and accurate inversion grid connection is realized. When the IP core is called to generate the SPWM wave, a special chip is not needed to be purchased, so the IP core designed by the patent has the advantages of convenience in use, high precision, low development cost, convenience in FPGA system integration and the like.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides the method and the system for generating the SPWM wave by utilizing the FPGA, which do not need to separately purchase a special chip, have convenient use, high precision and low development cost and are convenient for the integration of the FPGA system.

The utility model provides an utilize system of FPGA generation SPWM ripples, includes outside ADC sampling module, self-defined IP core includes SPWM ripples generation module, phase control register group, SPWM ripples generation module includes triangle wave generation module, sine wave generation module, phase-locked loop and SPWM ripples generation logic module, wherein:

the external ADC sampling module is used for collecting an external sine wave signal and sending the external sine wave signal to the SPWM wave generation logic module;

a clock generating module is arranged in the phase-locked loop, and the clock generating module respectively sends corresponding clock signals to the triangular wave generating module and the sine wave generating module according to the external sine wave signal;

the triangular wave generation module is used for generating a triangular wave signal according to the received clock signal and sending the triangular wave signal to the SPWM wave generation logic module;

the sine wave generation module is used for generating a sine wave signal according to the received clock signal and sending the sine wave signal to the SPWM wave generation logic module;

the SPWM wave generation logic module is used for comparing the triangular wave signal with the sine wave signal to output a preliminary SPWM wave signal and sending the preliminary SPWM wave signal to the phase control register group;

and the phase control register group is used for outputting the SPWM wave signal after the preliminary SPWM wave signal is subjected to phase adjustment.

The SPWM wave generation by the IP core is completed through the modules, and the system is convenient to use, high in precision, low in development cost and convenient for FPGA system integration.

Further, the system also comprises a starting control register, and the starting control register is used for controlling the starting or stopping of the self-defined IP core.

The system further comprises a NiosII processor and an Avalon bus, wherein the user-defined IP core further comprises an Avalon read-write control logic module, and the NiosII processor controls the user-defined IP core through the Avalon bus.

Furthermore, a plurality of clock generation modules with different frequencies are arranged in the phase-locked loop.

Further, the sine wave generation module comprises a numerically controlled oscillator IP core and/or an ADC sampling module.

Further, an ADC sampling module in the sine wave generation module employs a channel of the external ADC sampling module.

The method for generating the SPWM wave by utilizing the FPGA comprises an inverter and a power grid, and according to the system for generating the SPWM wave by utilizing the FPGA, the method comprises the following steps:

collecting a power grid sine wave signal of a power grid through the external ADC sampling module, and sending the power grid sine wave signal to the SPWM wave generation logic module of the user-defined IP core;

a clock generation module arranged in the phase-locked loop respectively sends corresponding clock signals to a triangular wave generation module and a sine wave generation module according to the external sine wave signals;

the triangular wave generation module and the sine wave generation module respectively generate triangular wave signals and sine wave signals and send the triangular wave signals and the sine wave signals to the SPWM wave generation logic module;

the SPWM wave generation logic module outputs a preliminary SPWM wave signal by comparing the triangular wave signal with the sine wave signal and sends the preliminary SPWM wave signal to the phase control register group;

and after the phase control register group carries out phase adjustment on the preliminary SPWM wave signal, the SPWM wave signal is output.

Further, when the system is off-grid, the sine wave generation module is a numerically controlled oscillator IP core, and the numerically controlled oscillator IP core adjusts the frequency and the amplitude through an Avalon bus carried by the numerically controlled oscillator IP core.

Further, when the system is connected to the grid, the sine wave generation module is an ADC sampling module.

The self-defined IP core is an IP core with an Avalon bus, can be easily hung on a NiosII processor, and enables a NiosII soft core to control the self-defined IP core through the Avalon bus, so that the IP core generates the needed SPWM wave according to the user requirement. The IP core mainly comprises an initial control register, a sine wave selection register group, an SPWM wave generation logic module, a phase control register group module and an Avalon read-write control logic module. The SPWM wave with high precision, convenient real-time control and adjustable phase can be output, wherein the initial control register is used for controlling whether the IP core starts to work or stops working; the IP core comprises two sine wave generation methods, when a user uses an off-grid power generation system, an NCO core of the system can be used for generating sine waves, and when a user uses a grid-connected power generation system, high-speed ADC sampling can be used for generating sine waves. The IP core comprises a sine wave selection register set used for selecting a mode used by the NiosII processor to generate the sine wave, and the system also comprises a phase control register set which can be used by a user to control the phase of the SPWM wave, so that the phase of the sine wave output by the inverter can be adjusted between 0 and 360 degrees.

The self-defined SPWM wave generation IP core mainly comprises a phase-locked loop, triangular wave generation logic, an NCO (numerical control oscillator IP core for generating a sine wave sequence with set frequency), an ADC (analog to digital converter) sampling module, SPWM wave generation logic, a phase control register group and the like. The principle of generating the SPWM wave by the IP core is that firstly, an NCO core or a high-speed ADC sampling method is used for obtaining a sine wave, then a customized high-speed triangular wave generator is used for generating a triangular wave, the triangular wave is compared with the sine wave to obtain a preliminary SPWM wave signal, and finally the SPWM is subjected to phase adjustment through an adjustable shift register so as to obtain the SPWM wave consistent with the phase on a power grid. When the system is off-grid, the sine wave generated by the NCO core can be selected through CPU configuration, the frequency and the amplitude of the sine wave can be adjusted through an Avalon bus in the IP core, and when the system needs grid-connection operation, a power grid voltage sequence collected by the ADC can be selected to be used as a sine wave source through the adjustment of the CPU.

The invention has the beneficial effects that:

1. the generation mode of the sine wave can be flexibly selected by a user;

2. when ADC sampling is used for generating sine waves, delay of the phase of SPWM can be controlled in advance through a NiosII CPU by using C language, so that the phase of the sine waves output by the inverter is the same as that of the sine waves of the power grid;

3. in the scheme, the phase-locked loop directly provides a clock for the triangular wave module, and the clock frequency output by the phase-locked loop can be defined by a user, so that the resolution and the frequency of the triangular wave can be flexibly adjusted by the user;

4. the SPWM wave is independently generated in the whole process without CPU interference, and the processor is released.

Drawings

In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.

FIG. 1 is a schematic diagram of the overall system framework;

FIG. 2 is a schematic diagram of SPWM wave generation logic;

FIG. 3 is a schematic diagram of a setup interface for invoking an NCO core (numerically controlled oscillator IP core);

FIG. 4 is a schematic of a triangle wave collected using an embedded logic analyzer;

fig. 5 is a schematic diagram of an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.

It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.

Example 1

As shown in the general system framework of FIG. 1, the custom IP core of the present invention is an IP core with an Avalon bus, which can be easily attached to a NiosII processor, and the NiosII soft core controls the custom IP core through the Avalon bus, so that the IP core generates the needed SPWM wave according to the user's requirement. The self-defined SPWM wave generation IP core is a core part of the FPGA system and is also the key of the patent. The IP core mainly comprises an initial control register, a sine wave selection register group, an SPWM wave generation logic module, a phase control register group module and an Avalon read-write control logic module. The SPWM wave with high precision, convenient real-time control and adjustable phase can be output, wherein the initial control register is used for controlling whether the IP core starts to work or stops working; the IP core comprises two sine wave generation methods, when a user uses an off-grid power generation system, an NCO core of the system can be used for generating sine waves, and when a user uses a grid-connected power generation system, high-speed ADC sampling can be used for generating sine waves. The IP core comprises a sine wave selection register set used for selecting a mode used by the NiosII processor to generate the sine wave, and the system also comprises a phase control register set which can be used by a user to control the phase of the SPWM wave, so that the phase of the sine wave output by the inverter can be adjusted between 0 and 360 degrees. The working principle and design scheme of the IP core will be described in detail in the following aspects.

The SPWM wave generation method is realized by the user-defined IP core:

as shown in the SPWM wave generation logic of fig. 2, the IP core generated by the customized SPWM wave of the present invention is mainly composed of modules such as a phase-locked loop, a triangle wave generation logic, an NCO (numerically controlled oscillator IP core, for generating a sine wave sequence of a set frequency), an ADC sampling module, an SPWM wave generation logic, and a phase control register set. The principle of generating the SPWM wave by the IP core is that firstly, an NCO core or a high-speed ADC sampling method is used for obtaining a sine wave, then a customized high-speed triangular wave generator is used for generating a triangular wave, the triangular wave is compared with the sine wave to obtain a preliminary SPWM wave signal, and finally the SPWM is subjected to phase adjustment through an adjustable shift register so as to obtain the SPWM wave consistent with the phase on a power grid. When the system is off-grid, the sine wave generated by the NCO core can be selected through CPU configuration, the frequency and the amplitude of the sine wave can be adjusted through an Avalon bus in the IP core, and when the system needs grid-connection operation, a power grid voltage sequence collected by the ADC can be selected to be used as a sine wave source through the adjustment of the CPU.

The clock frequencies used by the triangular wave generation logic module, the NCO core and the plug-in high-speed parallel ADC which are contained in the IP core are respectively provided by phase-locked loops. When a user uses the IP core to control the inverter to generate sine wave alternating current with high precision and 50hz for grid-connected power generation, because the sine wave frequency Fsin of the power grid is about 50hz generally, when the ADC samples the sine wave on the power grid, the sampling frequency Fadc of the ADC is Fsin M, and the value is obtained by setting the frequency division coefficient and the frequency multiplication coefficient of a certain channel of the phase-locked loop. Assuming that M is 200, the sampling frequency of the external high-speed parallel ADC is equal to 10KHz, and if the input clock frequency of the phase-locked loop is 50MHz, the frequency division coefficient of a certain channel should be set to 5000. Since the ratio of the triangular wave frequency Ftri to the sine wave frequency is the carrier ratio, that is, Ftri/Fsin is equal to K, the accuracy of outputting SPWM waves is also higher as the theoretical carrier ratio is larger, but an excessively large carrier ratio also means an extremely high switching frequency, so the IP core can obtain the triangular wave frequency Ftri is equal to Fsin is equal to 100, and the frequency Ftri is equal to 50, 100 is equal to 5000hz by taking the optimal carrier ratio as 100 through various tradeoffs. The triangular wave also includes a plurality of sampling points, and assuming that the number of sampling points in each period in the triangular wave is 200, the sampling frequency Fs of the triangular wave needs to be set to Ftri 200 Mhz 1Mhz, and the sampling frequency is also generated by setting a certain path of the phase-locked loop.

In a conventional SPWM wave generation scheme, a CPU usually uses a C language to generate a triangular wave, which results in a heavy burden on the CPU, affects system performance, and brings a large switching loss. In a traditional scheme for generating an SPWM signal by comparing a sine modulation wave with a triangular wave, the phase of the generated SPWM signal is often nonadjustable, which makes it difficult for the phase of the sine wave output by an inverter to be synchronized with the phase of the sine wave on a power grid. The following describes the specific design scheme of the IP core from four aspects:

sine wave generation scheme:

the sine wave generation method of the present invention includes the following two methods:

A. the sine wave is generated by calling the NCO kernel that the system carries itself. The method has the advantages of simple operation and setting the amplitude and the frequency of the sine wave to be generated on the calling NCO core interface. When the off-grid power generation system used by a user generates the same alternating current as the power grid, the NCO core can be used for generating a sine wave signal with the frequency of 50 hz. As shown in fig. 3 calling an NCO core setting interface, when an NCO core is called to generate a sine wave signal with a Frequency of 50hz, firstly, a Clock Rate provided by a phase-locked loop to the NCO core is set at a Clock Rate option in a Frequency menu, the sampling Frequency is generated by setting a certain channel of the phase-locked loop, and through a large number of experimental tests, a sine wave sequence generated when the Clock Frequency is set to 2Mhz is set to be the best in effect, so that the Clock Frequency is set to 2Mhz here. The Frequency of the sine wave that the user desires to generate is then set at Desired Qutput Frequency, which should be set to 0.00005Mhz here because a sine wave signal with a Frequency of 50hz is to be obtained. Setting the bit width value to be N, wherein the bit width value is the same as the bit width of the triangular wave.

B. A peripheral sine wave is sampled by one channel of a plug-in high-speed parallel ADC module, and then the sine wave data obtained by collection is sent to an FPGA for processing. The method has the advantages that external sine waves can be sampled in real time, and meanwhile, the voltage phase of the power grid is obtained, so that the inverter is controlled to realize the grid-connected function. When the IP core is suitable for the grid-connected single inverter, the variable name of one channel of the ADC module is set, the variable name is assumed to be adca _ d, and the bit width is designated to be N. Then, a certain channel of the phase-locked loop is set to generate a clock clk2 to drive the high-speed parallel ADC module to sample a sine wave on the power grid, and the clock clk2 is obtained by dividing or multiplying the frequency of the phase-locked loop, and how to set the frequency is the same as that described above, it is not described in detail here. This results in a sine wave signal adca _ d having a bit width N.

The way in which the sine wave is generated is selected is set by the avalon bus, the design of which is described later.

Generation scheme of triangular wave:

if a triangular wave is generated, a commonly used method uses a 555 timer to generate a square wave, and then the obtained square wave is used by an integrating circuit to generate the triangular wave, or the DDS and signal generator are realized by special chips. Therefore, the mode is complicated, a special chip needs to be purchased independently, the triangular wave generation mode provided by the scheme is that a program is written by using a Verilog language, and the triangular wave with adjustable resolution, frequency and amplitude can be realized only by using the FPGA. The operation is simple, and a special chip is not required to be purchased. The specific implementation method comprises the following steps:

firstly, a variable of an output triangular wave is set, a variable name is Tri _ Out, the bit width of the variable is designated to be N, N is equal to the bit width of an ADC (analog-to-digital converter) module, and the variable is defined by a reg statement.

Secondly, setting the highest peak of the triangular wave not to exceed a certain value, the value is determined as Tri _ Hi, the lowest peak cannot be lower than-Tri _ Hi, and defining the constant by using a parameter statement.

Let Tri _ Out change value once at the rising edge of each sampling clock Fs, Tri _ Out increases for a while, decreases for a while, and the time length occupied by the increase and decrease is the same and is equal to half of the triangle wave period, we use a variable Tri _ AddSub to determine whether Tri _ Out increases or decreases, where Tri _ AddSub is 1 to represent triangle wave rising, and when Tri _ AddSub is 0 to represent triangle wave falling.

When the Tri _ AddSub is equal to 1 and the Tri _ Out does not reach the Tri _ Hi yet, the Tri _ Out will increase by a certain magnitude at the next rising edge of Fs, and we define the magnitude of the increment magnitude by a special variable step. If the Tri _ Out has exceeded the Tri _ Hi, the Tri _ AddSub changes from 1 to 0 in the next clock cycle and the Tri _ Out starts to subtract.

When the Tri _ AddSub is 0 and the Tri _ Out is not lower than-Tri _ Hi, the Tri _ Out will decrease by a certain amplitude at the next rising edge of Fs, and the magnitude of the decreased amplitude is step. If the Tri _ Out is already below-Tri _ Hi, the Tri _ AddSub changes from 0 to 1 in the next clock cycle and the Tri _ Out starts adding.

The specific hardware description language is (program group 1):

in the triangular wave logic, the triangular wave required by a user can be generated by changing the sampling clock frequency step, the stepping step and the amplitude Tri _ Hi of the triangular wave. The triangular wave generated by the present triangular wave logic is shown in fig. 4 as the triangular wave collected using an embedded logic analyzer.

SPWM wave generation scheme:

to generate the SPWM wave, we compare the sine wave to the triangular wave, and their intersection determines the pulse output of the SPWM wave. We compare the sine wave signal and the triangular wave signal obtained from the above, and when the amplitude of the sine wave is greater than that of the triangular wave, the SPWM takes a high level, whereas when the amplitude of the sine wave is less than that of the triangular wave, the SPWM takes a low level. The specific hardware description language is (program group 2):

the SPWM wave signal generated by the code is used, but the phase of the sine wave signal output by the inverter controlled by the SPWM wave signal is often different from the phase of the sine wave signal on the grid, and at this time, the sine wave signal output by the inverter needs to be phase-shifted to be the same as the phase of the sine wave signal on the grid to be connected to the grid, and the specific implementation method is as follows:

delay method to generate SPWM wave phase:

after the generated SPWM _ early signal is input into a phase control register group of a system, the SPWM signal is obtained by performing phase delay operation through the phase control register group. Assuming that N shift registers are in total in the phase control register group, each register is driven by the same clock Fs, the clock period of Fs is set as Fs, and assuming that the SPWM signal is set by the Avalon read-write control logic to be taken from the output of the nth shift register, the delay time of SPWM is second with respect to SPWM _ early. It is obvious that the maximum delay time difference reflects the accuracy of the delay time, and N is set to be sufficiently large to realize a sufficiently long delay time. When writing the functionality of an IP core in a hardware description language such as Verilog, the macro definition can be implemented for N using the parameter keywords, i.e., parameter N ═ 100, etc. (in this case, N ═ 100 is assumed).

In summary, in practical applications, the system uses the ADC to sample the sine wave on the power grid to obtain the phase a of the sine wave on the power grid, and at the same time, uses the ADC to sample the sine wave generated by the inverter to obtain the phase B of the sine wave on the inverter, so that the phase difference phi is | a-B |, and at this time, the Nios II processor can delay the phase of the SPWM _ early signal by phi registers.

Avalon interface design:

the customized IP core is an IP core design based on an Avalon bus. The Avalon bus is a bus technology developed by Altera corporation for connecting Nios II processors and various IP core modules. In order to integrate the controller into the Nios II system, it must be packaged with an Avalon interface that meets the signal and timing requirements defined in the Avalon interface specification. The Avalon interface of the controller mainly comprises an Avalon memory map (Avalon-MM) slave interface, a Conduit (Conduit) interface, an interrupt (interrupt _ sender) interface, a clock input interface and a reset input interface. The slave interface contains Avalon signals for chip select, address, read-write and read-write data, etc. for interacting with the Nios II processor, and the pipe interface contains the signals required for connection to the outside. The controller, through interaction between the slave interface and the Nios II processor, reads sine wave select data from the register; writing sine wave selection Data into CPU _ RD _ Data; and sending a zero clearing command.

The generation method for selecting the sine wave is as follows: firstly, an Avalon bus interface added to an IP core can enable a user to write any positive integer n into a sine wave selection register by using a C instruction in a NiosII processor, and then a CPU processor chip selection signal CPU _ CS, a reading signal CPU _ RD and an address signal CPU _ Addr are defined in a self-defined IP core; suppose three sine wave selection registers are defined, and the register names of the sine wave selection registers are reg _ NCO, reg _ adca _ d and reg _ adcb _ d respectively, wherein the reg _ NCO is used for controlling the NCO core to generate sine waves, the reg _ adca _ d register is used for controlling the A channel work of the ADC module, and the reg _ adcb _ d register is used for controlling the B channel work of the ADC module. The specific implementation process of the write command control logic of the IP core is as follows (program group 3):

the code is that the chip selection signal of the CPU processor, the CPU reading signal and the address code of the sine wave selection register are controlled, then a numerical value n is written into registers reg _ nco, reg _ adca _ d and reg _ adcb _ d to be used as a mark, n can be any positive integer, if n is 1, when the chip selection signal of the CPU processor is 1 and the CPU reading signal is 1, if the address of the register is 0, 1 is written into the reg _ nco register; otherwise, if the address of the register is 1, writing 1 into the reg _ adca _ d register; if the address of the register is 2, 1 is written into the reg _ adcb _ d register. The specific implementation process of the read command control logic of the IP core is as follows (program group 4):

as shown in the above program, when the CPU address signal CPU _ Addr is 0 and the register reg _ NCO is 1, we use the sine wave generated by the NCO core in the custom IP core; when a CPU address signal CPU _ Addr is 1 and a register reg _ adca _ d is 1, the method represents that external data are collected by using an A channel of a high-speed parallel double-channel ADC; when the CPU address signal CPU _ Addr is 2 and the register reg _ adcb _ d is 1, it indicates that external data is collected using the B channel of the high-speed parallel two-channel ADC. We can write any positive integer n into the select register using the C instruction IOWR _32DIRECT (IP _ BASE, CPU _ Addr, n) inside the NiosII processor, where IP _ BASE represents the BASE address of the custom IP core in the NiosII CPU. Assuming we need to collect external data using the B channel of the high-speed parallel two-channel ADC, the B channel collection of external data using the high-speed parallel two-channel ADC can be achieved by writing n into the register reg _ adcb _ d using the C command IOWR _32DIRECT (IP _ BASE,2, n).

Example 2

In this embodiment, a specific design scheme and parameters of the IP core provided in this patent are explained by taking an example of controlling an inverter grid connection of a three-phase inverter circuit, so that firstly, we sample a power grid to obtain a sine wave signal by controlling the IP core to use an externally-mounted high-speed parallel ADC to sample a peripheral circuit through a Nios II processor. It is assumed that a clock clk0 with a frequency of 1mhz can be set for the triangle wave generation module to generate a triangle wave with a frequency of 10khz, and a clock clk2 with a frequency of 10khz is set for the high-speed parallel ADC to sample the sine wave on the power grid. The system samples specific alternating current circuits through an ADC module to obtain SIN1, SIN2 and SIN3, and an IP core designed by the patent is required to be utilized to generate corresponding SPWM waves: SPWM1, SPWM1_ NOT, SPWM2, SPWM2_ NOT, SPWM3 and SPWM3_ NOT signals. For this reason, to successfully control six IGBTs (insulated gate transistors) of three legs on an inverter, we use three custom SPWM on an FPGA to generate an IP core to generate the above six control signals to modulate the three-phase inverter synchronously. The specific control structure is shown in fig. 5 as follows, wherein three IP cores control one inverter to realize inversion grid connection.

As shown in fig. 5, the three IP cores control one inverter to realize the inverter in the inverter grid connection, and the inverter has six thyristors VT 1-VT 6, wherein VT1 and VT4 are in the same bridge arm, VT3 and VT6 are in the same bridge arm, and VT5 and VT2 are in the same bridge arm. The system processes data collected by the ADC module, and then compares the processed data with a triangular wave generated by a user-defined mode to generate SPWM _ early 1, SPWM _ early 2 and SPWM _ early 3 signals, then controls a phase register to delay the SPWM _ early signal through a Nios II processor according to a phase difference fed back by a phase difference detection module to obtain SPWM1, SPWM2 and SPWM3 signals required by people, and obtains SPWM1_ NOT, SPWM2_ NOT and SPWM3_ NOT signals after inverting the obtained SPWM wave signals. Finally, the six output signals are respectively connected with G poles of six thyristors VT 1-VT 6.

Theoretically, the higher the triangular wave frequency, the closer the output waveform is to a sine wave. In fact, although the on-off change of the switching tube is fast, a certain time is still needed, in this time period, the switching tube needs to bear the impact of high voltage and large current, the power consumption is large, and the high-frequency switching not only increases the loss and reduces the power efficiency, but also can cause the tube to be heated and burnt. Generally, the carrier frequency of the inverter is about several kilohertz, the frequency of the low power is higher, and the frequency of the high power inverter is lower.

In this case, the three-phase inverter is controlled to realize inversion grid connection, so that the sine wave alternating current on the power grid is collected in real time by the ADC module. Given that the alternating current frequency of the power grid in China is 50 hertz, assuming that the system clock Fs is equal to 50Mhz, in order to match the sine wave alternating current generated by the inversion of the SPWM wave controlled three-phase inverter generated by the people with the sine wave alternating current collected by the power grid, through the calculation in the foregoing, a clock clk0 with the frequency of 1MHz is set to be used for the triangular wave generation module to generate the triangular wave with the frequency of 10 kHz. Meanwhile, a 10K clock is designed to drive the ADC module to collect sine wave signals with the frequency of 50hz on the power grid. Subsequently, an SPWM wave signal is obtained. The sine wave signal generated by the inverter and the sine wave signal on the power grid generally have a phase difference, and at the moment, the NiosII CPU control system SPWM wave is used for moving N phases, so that the sine wave with the same phase as the power grid can be obtained. The specific operation scheme is not described above.

In some cases, instead of using a grid-connected power generation system, an NCO core is required to generate a sine wave signal, in order to realize the adjustable way of generating the sine wave and to control the start and stop of the IP core by using a CPU, a sine wave selection register set is defined inside the IP core, and the register set receives data and control commands from the Nios II processor by using an Avalon bus, and the specific implementation logic is shown as a program set 3.

Assuming that the name of the custom IP core we add to the Nios II processor system is called SPWM, then SPWM _ BASE in the Nios II Software Build Tools for Eclipse development environment of FPGA is the BASE address of the IP core, whose name consists of the capital of the IP core name plus the suffix of "_ BASE".

After the IP core is successfully designed, the IP core can be added into an SOPC system in a Platform Designer or a Qsys development environment of an Intel FPGA in a mode of double-clicking the name of the IP core, and can be normally used after standard development processes such as compiling, locking pins, downloading, solidifying and the like.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.

Claims

1. A system for generating SPWM waves by utilizing an FPGA is characterized in that: including outside ADC sampling module, custom IP core and displacement register, the custom IP core includes SPWM ripples generation module, phase control register group, SPWM ripples generation module includes triangle ripples generation module, sine wave generation module, phase-locked loop and SPWM ripples generation logic module, wherein:

the sine wave generation module comprises an NCO core, and the NCO core is used for generating sine wave signals;

the phase control register group is used for outputting SPWM wave signals after the preliminary SPWM wave signals are subjected to phase adjustment;

and the shift register is used for carrying out phase adjustment on the SPWM wave signal.

2. The system for SPWM wave generation with an FPGA of claim 1 further comprising a start control register for controlling the starting or stopping of said custom IP core.

3. The system for generating SPWM waves using FPGA of claim 1, wherein: the system also comprises a NiosII processor and an Avalon bus, wherein the user-defined IP core also comprises an Avalon read-write control logic module, and the NiosII processor controls the user-defined IP core through the Avalon bus.

4. The system for generating SPWM waves using FPGA of claim 1, wherein: and a plurality of clock generation modules with different frequencies are arranged in the phase-locked loop.

5. The system for generating SPWM waves using FPGA of claim 1, wherein: the sine wave generation module comprises a numerically controlled oscillator IP core and/or an ADC sampling module.

6. The system for generating SPWM waves using FPGA of claim 5, wherein: and an ADC (analog to digital converter) sampling module in the sine wave generating module adopts a channel of the external ADC sampling module.

7. Method for generating SPWM waves with FPGA, comprising inverter, grid, characterized in that a system for generating SPWM waves with FPGA according to any of claims 1 to 6, comprising the following steps:

or respectively generating a triangular wave signal and a sine wave signal by the triangular wave generation module and the sine wave generation module and sending the triangular wave signal and the sine wave signal to the SPWM wave generation logic module;

the sine wave generation module comprises an NCO core, wherein the NCO core generates a sine wave signal and sends the sine wave signal to the SPWM wave generation logic module;

the phase control register group outputs an SPWM wave signal after performing phase adjustment on the preliminary SPWM wave signal;

controlling the length of the delay shift register to adjust the SPWM wave signal, and specifically comprising the following steps:

the SPWM wave signal is output from the nth shift register, the delay time is N × T, N is a natural number, and N is a natural number which is greater than zero and less than or equal to N.

8. The method of generating SPWM waves using FPGA of claim 7, wherein: and when the system is off-network, the sine wave generation module is a numerically controlled oscillator IP core.

9. The method of generating SPWM waves using FPGA of claim 8, wherein: the digital controlled oscillator IP core adjusts the frequency and the amplitude through an Avalon bus of the digital controlled oscillator IP core.

10. The method of generating SPWM waves using FPGA of claim 7, wherein: when the system is connected to the grid, the sine wave generation module is an ADC sampling module.