WO2019097971A1 - Élément d'imagerie à l'état solide et son procédé de fabrication - Google Patents

Élément d'imagerie à l'état solide et son procédé de fabrication Download PDF

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Publication number
WO2019097971A1
WO2019097971A1 PCT/JP2018/039594 JP2018039594W WO2019097971A1 WO 2019097971 A1 WO2019097971 A1 WO 2019097971A1 JP 2018039594 W JP2018039594 W JP 2018039594W WO 2019097971 A1 WO2019097971 A1 WO 2019097971A1
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Prior art keywords
photodiode
metal electrode
solid
state imaging
imaging device
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PCT/JP2018/039594
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English (en)
Japanese (ja)
Inventor
能純 原口
盛介 福田
博一 池田
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マッハコーポレーション株式会社
国立研究開発法人宇宙航空研究開発機構
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Publication of WO2019097971A1 publication Critical patent/WO2019097971A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • the present invention relates to a solid-state imaging device and a method of forming the same, and more particularly to a solid-state imaging device suitable for preventing deterioration in image quality caused by irradiation of radiation and a method of forming the same.
  • Patent Document 1 discloses a technique related to a solid-state imaging device used for a high-performance camera.
  • the photosensitive element (solid-state imaging element) disclosed in Patent Document 1 includes a photodiode formed of a P well formed on a semiconductor substrate and an N type photosensitive region formed on the surface, and a photodiode formed on the surface of the photosensitive region.
  • ITO indium tin oxide
  • a P-type pinning layer is formed on the surface of the photosensitive region by applying a negative voltage from the transparent conductive layer to the photosensitive region.
  • this photosensitive element can sweep dark current generated by thermal excitation at the interface between the photosensitive region and the transparent insulating layer to the ground via the pinning layer, thus improving the quality of the image.
  • Patent 3049015 gazette
  • the fixed positive charge is fixed in the insulating film by the ionizing action of the total dose effect generated by irradiation of radiation such as gamma rays.
  • the total dose effect generated by irradiation of radiation such as gamma rays.
  • the fixed positive charge is accumulated in the transparent insulating layer by the ionizing action of the total dose effect generated by the irradiation of the radiation.
  • the pinning layer is inverted to N-type, and the pinning layer does not function properly.
  • dark current is accumulated at the interface between the photosensitive region and the transparent insulating layer, there is a problem that deterioration of the image quality such as whiteout occurs.
  • the solid-state imaging device includes a semiconductor substrate, a PN junction photodiode formed on the surface of the semiconductor substrate, and a surface of the semiconductor substrate including the surface on which the photodiode is formed.
  • the formed insulating film and the plurality of wiring layers stacked on the insulating film it is formed in a wiring layer higher than the first wiring layer adjacent to the photodiode, and a negative voltage is applied. And a first metal electrode.
  • a PN junction type photodiode is formed on the surface of a semiconductor substrate, and insulation is provided on the surface of the semiconductor substrate including the formation surface of the photodiode.
  • Forming a film, forming a first metal electrode in a wiring layer higher than the first wiring layer adjacent to the photodiode among the plurality of wiring layers stacked on the insulating film, and forming the first metal Apply a negative voltage to the electrode.
  • a solid-state imaging device and a method of forming the same can be provided, for example, which is suitable for preventing deterioration in image quality caused by irradiation of radiation.
  • FIG. 2 is a diagram showing a basic circuit configuration of a pixel unit used in the CMOS image sensor according to the first embodiment.
  • FIG. 2 is a plan layout view of a basic part of the pixel unit shown in FIG. It is a cross-sectional schematic diagram of the fundamental part of the pixel part shown in FIG.
  • FIG. 5 is a plan layout view of the second wiring layer and below of the pixel portion of the CMOS image sensor according to the first embodiment.
  • FIG. 6 is a plan layout view of a third wiring layer of the pixel portion of the CMOS image sensor according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of a pixel portion of the CMOS image sensor according to the first embodiment.
  • FIG. 13 is a plan layout view of the second wiring layer and below of the pixel portion of the CMOS image sensor according to the second embodiment.
  • FIG. 7 is a plan layout view of a third wiring layer of a pixel portion of a CMOS image sensor according to Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view of a pixel portion of a CMOS image sensor according to a second embodiment. It is a cross-sectional schematic diagram of an embedded photodiode. It is a figure for demonstrating the subject at the time of irradiating a radiation to the embedded photodiode shown in FIG.
  • the constituent elements are not necessarily essential unless specifically stated and when it is considered to be obviously essential in principle.
  • the shapes, positional relationships and the like of components etc. when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above-described numbers and the like (including the number, the numerical value, the amount, the range, and the like).
  • CMOS image sensor solid-state imaging device
  • FIG. 10 is a schematic cross-sectional view of the embedded photodiode.
  • N-type diffusion region N - region
  • the N-type diffusion region is formed by doping the surface of the P well with an N-type impurity.
  • a PN junction type photodiode is configured by the P well and the N type diffusion region.
  • an element isolation region (STI; Shallow Trench Isolation) is formed at a distance from the N-type diffusion region.
  • STI Shallow Trench Isolation
  • a P-type pinning layer is formed on the surface of the active region surrounded by the element isolation region, including the surface of the N-type diffusion region. The pinning layer is formed by doping the surface of the active region surrounded by the element isolation region with a P-type impurity.
  • a SiO 2 insulating film (PMD; Pre Metal Dielectric) is formed on the surface.
  • the ordinary photodiode has no pinning layer, and has a structure in which the surface of the N type diffusion region is directly covered with PMD.
  • dark current electrons are generated by thermal excitation in addition to signal electrons excited by an optical signal.
  • the output of this dark current electron is better as it approaches 0, and the increase of the dark current causes the deterioration of the image quality.
  • the pinning layer is not limited to the case where it is formed by doping a P-type impurity on the surface of the active region.
  • the pinning layer may be formed, for example, by applying a negative voltage to the photosensitive region (active region) from the ITO transparent conductive layer formed on the substrate, as disclosed in Patent Document 1 .
  • the P-type pinning layer formed on the surface of the embedded photodiode may be inverted to N-type. In that case, the effect of dark current suppression by the pinning layer may be lost.
  • CMOS image sensor solid-state imaging device
  • Embodiment 1 First, the basic configuration of the pixel portion of the surface-illuminated CMOS image sensor (solid-state image sensor) will be described with reference to FIGS. 1, 2 and 3.
  • FIG. 1 the basic configuration of the pixel portion of the surface-illuminated CMOS image sensor (solid-state image sensor) will be described with reference to FIGS. 1, 2 and 3.
  • FIG. 1 the basic configuration of the pixel portion of the surface-illuminated CMOS image sensor (solid-state image sensor) will be described with reference to FIGS. 1, 2 and 3.
  • FIG. 1 the basic configuration of the pixel portion of the surface-illuminated CMOS image sensor (solid-state image sensor) will be described with reference to FIGS. 1, 2 and 3.
  • FIG. 1 is a diagram showing a basic circuit configuration of a pixel unit used in the CMOS image sensor according to the first embodiment.
  • the pixel section 1 of the CMOS image sensor shown in FIG. 1 is a pixel section of a typical four-transistor type CMOS image sensor also called a so-called APS (Active Pixel Sensor).
  • the pixel unit 1 includes four N-channel MOS transistors TR1 to TR4 and a photodiode PD1.
  • the four N-channel MOS transistors TR1 to TR4 are also referred to as a transfer transistor TR1, a reset transistor TR2, an amplification transistor TR3, and a row selection transistor TR4, respectively.
  • the anode of the photodiode PD1 is connected to the ground voltage line GND, and the cathode of the photodiode PD1 is connected to the source of the transfer transistor TR1.
  • the drain (TR1_D) is connected to the node N1
  • the gate (TR1_G) is connected to the transfer gate drive line 4 on which the transfer gate drive signal ⁇ TG propagates.
  • the source (TR2_S) is connected to the node N1
  • the drain (TR2_D) is connected to the power supply voltage line VDD
  • the gate (TR2_G) is connected to the reset signal line 5 on which the reset signal ⁇ R propagates .
  • the source (TR3_S) is connected to the node N2
  • the drain (TR3_D) is connected to the power supply voltage line VDD
  • the gate (TR3_G) is connected to the node N1. That is, the drain of the transfer transistor TR1, the source of the reset transistor TR2, and the gate of the amplification transistor TR3 are connected to each other at the node N1. Further, a floating diffusion layer capacitance FD1 is formed at the node N1.
  • row selection transistor TR4 the source (TR4_S) is connected to output signal line VOUT along with a plurality of other pixels provided in the column direction, the drain is connected to node N2, and the gate (TR4_G) is row selection signal ⁇ SEL. Are connected to the propagating row selection signal line 6 of FIG.
  • the photodiode PD1 converts the received light signal into an electrical signal.
  • the transfer transistor TR1 is turned on when the transfer gate drive signal ⁇ TG becomes active, and transfers the electric signal converted from the light signal by the photodiode PD1 to the node N1. As a result, a charge corresponding to the electrical signal from the photodiode PD1 is accumulated in the floating diffusion layer capacitance FD1 formed at the node N1.
  • the amplification transistor TR3 drives the voltage of the node N1 and outputs it to the node N2.
  • the row selection transistor TR4 turns on when the row selection signal ⁇ SEL becomes active, and outputs the voltage of the node N2 (ie, the electrical signal converted from the light signal by the photodiode PD1) to the output signal line VOUT.
  • FIG. 2 is a plan layout view showing a basic portion of the pixel unit 1 shown in FIG. 1 as a pixel unit 1B.
  • FIG. 3 is a schematic cross-sectional view of a portion III-III in the plan layout view shown in FIG.
  • a rectangular photodiode PD1 is formed in a region that occupies most of the pixel section 1B in plan view, and the metal of the transfer gate driving line 4 is formed so as to surround the outer periphery thereof. .
  • transistors TR1 to TR4 are formed in the peripheral region (upper part of the sheet of FIG. 2) on one side of the rectangular photodiode PD1 in plan view. Further, in plan view, the ground voltage line GND, the power supply voltage line VDD and the output signal line VOUT are disposed in parallel with the photodiode PD1 and the transistors TR1 to TR4 interposed therebetween.
  • an N-type diffusion region 103 is formed on the surface of a P-well 101 formed in a semiconductor substrate 100.
  • the N type diffusion region 103 is formed by doping the surface of the P well 101 with an N type impurity.
  • the P well 101 and the N type diffusion region 103 constitute a PN junction type photodiode PD1.
  • an element isolation region (STI) 102 is formed spaced apart from the N-type diffusion region 103.
  • a P-type pinning layer 104 is formed on the surface of the active region surrounded by the element isolation region 102 including the surface of the N-type diffusion region 103.
  • the pinning layer 104 is formed by doping the surface of the active region surrounded by the element isolation region 102 with a P-type impurity.
  • the outer periphery of the N-type diffusion region 103 (in other words, the outer periphery of the photodiode PD1) is indicated by a dashed dotted line 11 in FIG. Also, the boundary between the element isolation region 102 and the active region surrounded by it is indicated by a solid line 10 in FIG. However, among the boundaries between the element isolation region 102 and the active region surrounded by the device isolation region 102, the boundaries hidden in the wiring layer are indicated by the broken line 10.
  • a P-type diffusion region 105 is formed on the surface of the P well 101 separately from the N-type diffusion region 103.
  • the P type diffusion region 105 is formed by doping the surface of the P well 101 with a P type impurity.
  • a transparent insulating film 106 (not shown) such as SiO 2 is formed by, eg, CVD (Chemical Vapor Deposition).
  • the metal of the transfer gate driving line 4 described above is a photodiode in plan view in the first wiring layer adjacent (closest to) the semiconductor substrate 100. It is formed so as to surround the outer circumference of the PD 1 (the outer circumference of the N-type diffusion region 103). Thereby, stray light can be prevented from entering the photodiode PD1 from the periphery.
  • the ground voltage line GND, the power supply voltage line VDD and the output signal line VOUT described above are arranged in parallel with the photodiode PD1 and the transistors TR1 to TR4 interposed therebetween in plan view.
  • the ground voltage line GND, the power supply voltage line VDD and the output signal line VOUT arranged in the second wiring layer are also referred to as a ground voltage line GND_2, a power supply voltage line VDD_2 and an output signal line VOUT_2, respectively.
  • the ground voltage line GND_2 arranged in the second wiring layer is connected to the ground voltage line GND_1 arranged in the first wiring layer via the via V1.
  • the ground voltage line GND_1 arranged in the first wiring layer is connected to the P-type diffusion region 105 via the contact CT1.
  • FIG. 4 and FIG. 5 are plan layout views of a configuration in which one of the features of the present invention is added to the basic portion of the pixel section 1 shown in FIG. 4 shows only the first and second wiring layers among the plurality of wiring layers, and FIG. 5 shows only the third wiring layer among the plurality of wiring layers.
  • FIG. 6 is a schematic cross-sectional view of a VI-VI portion of the plan layout views shown in FIGS. 4 and 5.
  • the metal electrode MTL is It is further formed.
  • metal electrodes MTL_2 and MTL_3 are formed in the second and third wiring layers, respectively, and they are electrically connected by vias V2.
  • a metal electrode MTL is configured by the metal electrodes MTL_2 and MTL_3 and the via V2.
  • the metal electrode MTL_2 is formed in a ring shape so as to surround the outer periphery of the photodiode PD1 (the outer periphery of the N-type diffusion region 103) in plan view in the second wiring layer.
  • the metal electrode MTL_3 is formed to surround the outer periphery of the photodiode PD1 (the outer periphery of the N-type diffusion region 103) in plan view in the third wiring layer. Therefore, the light received by the photodiode PD1 is not blocked by the metal electrodes MTL_2 and MTL_3.
  • a negative voltage is applied to the metal electrode MTL (metal electrodes MTL_2 and MTL_3). Therefore, even if fixed positive charges are accumulated in the insulating film 106 by the ionizing action of the total dose effect generated by irradiation of radiation such as gamma rays, an electric field is generated in the photodiode PD1 using the negative voltage of the metal electrode MTL. Thus, the influence of the fixed positive charge to which the pinning layer 104 is subjected can be offset. Thereby, since the function of the pinning layer 104 is maintained, the dark current generated by thermal excitation at the interface between the N-type diffusion region 103 and the insulating film 106 is swept to the ground via the pinning layer 104. As a result, the quality deterioration of the image displayed by the pixel unit 1 is suppressed.
  • the distance between the metal electrode MTL and the photodiode PD1 becomes too close. It will In this case, an electric field is generated near the periphery near the metal electrode MTL in the formation region of the photodiode PD1 in plan view, but an electric field is hardly generated at the center. Therefore, in the central portion of the photodiode PD1, the influence of the fixed positive charge received by the pinning layer 104 can not be sufficiently offset. This problem becomes more pronounced as the formation region of the photodiode PD1 increases.
  • the metal formed in the wiring layer higher than the first wiring layer is employed as the metal electrode MTL.
  • the distance between the metal electrode MTL and the photodiode PD1 is appropriately separated, so that an electric field is generated relatively uniformly not only in the periphery but also in the center of the photodiode PD1 in plan view. Therefore, in the photodiode PD1, the influence of the fixed positive charge received by the pinning layer 104 can be offset over the entire surface.
  • the pixel unit 1 of the CMOS image sensor according to the present embodiment can cause the pinning layer 104 to function with high accuracy, so that the increase of dark current can be suppressed, and as a result, the deterioration of the image quality is suppressed. can do.
  • a negative voltage is applied to surround the outer periphery of the formation region of the photodiode PD1 in plan view in a layer higher than the first wiring layer.
  • the metal electrode MTL is formed.
  • the pixel unit 1 of the CMOS image sensor according to the present embodiment can cause the pinning layer 104 to function with high accuracy, so that the increase of dark current can be suppressed, and as a result, the deterioration of the image quality is suppressed. can do.
  • the metal electrode MTL is formed in the wiring layer, unlike the case where the ITO transparent conductive layer is formed as disclosed in Patent Document 1, , No special manufacturing process is required. Therefore, it is possible to suppress the manufacturing problems and the increase in the process cost associated with the addition of the ITO transparent electrode.
  • the photodiode PD1 has a buried type structure covered in advance with the pinning layer 104
  • the photodiode PD1 may have a structure not previously covered with the pinning layer 104.
  • a P-type diffusion region corresponding to the pinning layer 104 can be formed on the surface of the N-type diffusion region 103 by increasing the negative voltage applied to the metal electrode MTL.
  • the present invention is not limited to this.
  • the metal electrode MTL may be formed only in one wiring layer higher than the first wiring layer, or may be formed across three or more wiring layers higher than the first wiring layer.
  • Second Embodiment 7 and 8 are plan layout views of the pixel section 2 of the surface-illuminated CMOS image sensor according to the second embodiment. 7 shows only the first and second wiring layers among the plurality of wiring layers, and FIG. 8 shows only the third wiring layer among the plurality of wiring layers.
  • FIG. 9 is a schematic cross-sectional view of a portion IX-IX in the plan layout views shown in FIGS. 7 and 8.
  • the pixel unit 2 further includes a metal electrode MTL_2a in comparison with the pixel unit 1.
  • the metal electrode MTL_2a is formed to overlap a part of the formation region of the photodiode PD1 in plan view in the second wiring layer.
  • the metal electrode MTL_2a is formed in a band shape from one side of the metal electrode MTL2 to the other side opposed to the central portion of the formation region of the photodiode PD1 in plan view in the second wiring layer .
  • the metal electrode MTL_2a is electrically connected to the metal electrode MTL_2. Therefore, a negative voltage is also applied to the metal electrode MTL_2a.
  • the other structure of the pixel unit 2 is the same as that of the pixel unit 1, and thus the description thereof is omitted.
  • a negative voltage is applied to surround the outer periphery of the formation region of the photodiode PD1 in plan view in a layer higher than the first wiring layer.
  • the metal electrode MTL is formed.
  • the pixel unit 2 of the CMOS image sensor according to the present embodiment can cause the pinning layer 104 to function with high accuracy, so that the increase of dark current can be suppressed, and as a result, the deterioration of the image quality is suppressed. can do.
  • the pixel unit 2 of the CMOS image sensor in a layer higher than the first wiring layer, it overlaps with a part (in particular, the central part) of the formation region of the photodiode PD1 in plan view.
  • a metal electrode MTL_2a to which a negative voltage is applied is formed.
  • the pixel unit 2 can generate a strong electric field not only in the peripheral portion of the top surface of the photodiode PD1 but also in the central portion. That is, the pixel unit 2 can generate an electric field more uniformly over the entire top surface of the photodiode PD1.
  • the pixel unit 2 can more accurately offset the influence of the fixed positive charge that the pinning layer 104 receives.
  • the pixel section 2 of the CMOS image sensor according to the present embodiment can function the pinning layer 104 more accurately, and therefore, the increase in dark current can be further suppressed, and as a result, the image quality is degraded. Can be further suppressed.
  • the present invention is not limited thereto.
  • a single metal electrode MTL_2a may be provided. Even in such a case, by forming the metal electrode MTL_2a in the wiring layer higher than the first wiring layer, the distance between the metal electrode MTL_2a and the photodiode PD1 can be appropriately separated, so the photodiode PD1 is formed. An electric field can be generated relatively uniformly over the entire top surface.
  • the metal electrode MTL_2a is formed so as to overlap with a part of the formation region of the photodiode PD1 in plan view, but the metal electrode MTL_2a has another narrowest wiring width.
  • the metal electrode MTL_2a is formed in a band shape from one side of the formation region of the rectangular photodiode PD1 to the other side opposed in plan view, but the present invention is not limited thereto.
  • the metal electrode MTL_2a may have any shape as long as it can generate an electric field uniformly over the entire upper surface of the photodiode PD1 and can suppress the decrease in sensitivity of the photodiode PD1 due to light shielding within an acceptable range. Good.
  • the metal electrode MTL_2a may be disposed in any wiring layer as long as it is a layer higher than the first wiring layer.
  • the photodiode PD1 has a buried type structure covered in advance with the pinning layer 104
  • the present invention is not limited thereto.
  • the photodiode PD1 may have a structure not previously covered with the pinning layer 104.
  • a P-type diffusion region corresponding to the pinning layer 104 can be formed on the surface of the N-type diffusion region 103 by increasing the negative voltage applied to the metal electrode MTL.
  • the conductivity type of each MOS transistor may be replaced with P-type to N-type and N-type to P-type, respectively.
  • the present invention can be suitably applied to a solid-state imaging device used for a high-performance camera.

Abstract

La présente invention concerne, selon un mode de réalisation, un élément d'imagerie à l'état solide pourvu : d'un substrat semi-conducteur (100) ; d'une photodiode à jonction PN (PD1) qui est formée dans la surface du substrat semi-conducteur (100) ; un film isolant (106) qui est formé sur la surface du substrat semi-conducteur (100) comprenant la région de surface où la photodiode (PD1) est formée ; et une électrode métallique (MTL) qui est formée dans une couche de câblage qui est à une position plus élevée qu'une première couche de câblage qui est adjacente à la photodiode (PD1) parmi une pluralité de couches de câblage qui sont stratifiées sur le film isolant (106), et auxquelles une tension négative est appliquée.
PCT/JP2018/039594 2017-11-14 2018-10-25 Élément d'imagerie à l'état solide et son procédé de fabrication WO2019097971A1 (fr)

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JP2017219194A JP7078919B2 (ja) 2017-11-14 2017-11-14 固体撮像素子及びその形成方法
JP2017-219194 2017-11-14

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CN110930356B (zh) * 2019-10-12 2023-02-28 上海交通大学 一种工业二维码无参考质量评估系统及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012117931A1 (fr) * 2011-03-02 2012-09-07 ソニー株式会社 Dispositif d'imagerie à semi-conducteurs et son procédé de fabrication, et instrument électronique
JP2013012556A (ja) * 2011-06-28 2013-01-17 Sony Corp 固体撮像装置とその製造方法、および電子機器
WO2017018258A1 (fr) * 2015-07-30 2017-02-02 ソニーセミコンダクタソリューションズ株式会社 Dispositif de prise de vues à semi-conducteurs et appareil électronique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012117931A1 (fr) * 2011-03-02 2012-09-07 ソニー株式会社 Dispositif d'imagerie à semi-conducteurs et son procédé de fabrication, et instrument électronique
JP2013012556A (ja) * 2011-06-28 2013-01-17 Sony Corp 固体撮像装置とその製造方法、および電子機器
WO2017018258A1 (fr) * 2015-07-30 2017-02-02 ソニーセミコンダクタソリューションズ株式会社 Dispositif de prise de vues à semi-conducteurs et appareil électronique

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