WO2019085879A1 - 一种比特块处理方法及节点 - Google Patents

一种比特块处理方法及节点 Download PDF

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Publication number
WO2019085879A1
WO2019085879A1 PCT/CN2018/112599 CN2018112599W WO2019085879A1 WO 2019085879 A1 WO2019085879 A1 WO 2019085879A1 CN 2018112599 W CN2018112599 W CN 2018112599W WO 2019085879 A1 WO2019085879 A1 WO 2019085879A1
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Prior art keywords
bit block
data bit
field
tag
sequence number
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PCT/CN2018/112599
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English (en)
French (fr)
Inventor
查敏
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18874572.3A priority Critical patent/EP3694125B1/en
Publication of WO2019085879A1 publication Critical patent/WO2019085879A1/zh
Priority to US16/862,170 priority patent/US11388101B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/34—Flow control; Congestion control ensuring sequence integrity, e.g. using sequence numbers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/36—Flow control; Congestion control by determining packet size, e.g. maximum transfer unit [MTU]

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a bit block processing method and a node.
  • Ethernet technology is widely used.
  • New services such as 5G mobile bearer and industrial Internet have put forward new demands on Ethernet, such as higher requirements for low latency, certainty and high reliability.
  • the Ethernet frame preemption technique is adopted to reduce the delay of the critical traffic, but the delay is limited by the shortest packet of the Ethernet, and the delay is limited.
  • the bit block cannot be performed at the physical layer. Truncated.
  • the embodiment of the invention provides a bit block processing method and a node, which are used to solve the problem that the bit block can not be truncated at the physical layer.
  • a method for processing a bit block includes: sequentially receiving, by a first port, a first tag bit block and N data bit blocks, where the first tag bit block includes a first length field; a tag bit block and M data bit blocks out of N data bit blocks; sequentially transmitting the second tag bit block and the L data bit blocks in the remaining NM data bit blocks of the N data bit blocks through the second port
  • the second tag bit block includes a second length field, and the value of the first length field is greater than the value of the second length field, where M, N, and L are integers greater than or equal to zero.
  • a tag bit block is added, and the tag bit block carries a length field, and the tag bit block and the following data bit block form a bit block segment, and when the bit block segment is forwarded, the bit block segment can be
  • the block segment is truncated into at least two block segments, each truncated block segment including a tag block, the value of the length field of the tag block being related to the number of truncated data blocks.
  • the method further includes: acquiring the third label bit block And 0 data bit blocks, where O is an integer greater than or equal to 0; the third tag bit block and the O data bit blocks are sequentially transmitted through the second port.
  • the first label bit block further includes a first connection identifier field
  • the first label bit block and the M data bit blocks of the N data bit blocks are sequentially sent by the second port
  • the method further includes: The first connection identification field is searched for the second port.
  • the second tag bit block further includes a second connection identifier field, and the value of the first connection identifier field is the same as the value of the second connection identifier field.
  • the first tag bit block further includes a first sequence number field
  • the second tag bit block further includes a second sequence number field
  • the value of the first sequence number field and the second sequence number field have the same value
  • the first tag bit block further includes a first sequence number start field, and is used to identify whether the first data bit block of the N data bit blocks is the first data bit block corresponding to the sequence number.
  • the second tag bit block further includes a second sequence number start field for identifying whether the first data bit block of the L data bit blocks is the first data bit block corresponding to the sequence number.
  • the method when the first label bit block and the M data bit blocks of the N data bit blocks are sequentially transmitted through the second port, the method further includes: storing a value of the first length field; and transmitting each data bit block , decrement the value of the stored first length field by one.
  • the value of the second length field is the value of the stored first length field.
  • the stored first length field is released.
  • sequentially receiving the first label bit block and the N data bit blocks through the first port includes: sequentially receiving the first label bit block, the N data bit blocks, and the first label end bit through the first port. And after the sending, by the second port, the second label bit block and the L data bit blocks in the remaining NM data bit blocks in the N data bit blocks, the method further includes: sending, by using the second port, the first label end bit block , release the first length field of the store.
  • a method for processing a bit block includes: generating a first tag bit block, the first tag bit block includes a first length field; acquiring N data bit blocks to be sent; and transmitting the first through the first port A tag bit block and N data bit blocks, where N is an integer greater than or equal to zero.
  • the value of the first length field is N.
  • the value of the first length field is a first preset value
  • sequentially sending the first label bit block and the N data bit blocks through the first port includes: sequentially sending the first label bit through the first port Block, N data bit blocks and a first tag end bit block.
  • the first tag bit block further includes at least one of a first connection identifier field, a first sequence number field, and a first sequence number start field, where the first connection identifier field is used for the first label bit
  • the block and the N data bit blocks are used for routing, the first sequence number field is used to identify the sequence number corresponding to the N data bit blocks, and the first sequence number start field is used to identify the first data bit block in the N data bit blocks. Whether it is the first data bit block corresponding to the serial number.
  • the first tag bit block further includes a first sequence number field
  • the first tag end bit block further includes a first end sequence number field, a value of the first sequence number field, and a first end sequence number field. The values are the same.
  • a third aspect a method for processing a bit block, comprising: sequentially receiving a first tag bit block and N data bit blocks, where the first tag bit block includes a first length field; and sequentially receiving the second tag bit block and M data a bit block, the second tag bit block includes a second length field; if the value of the first length field is greater than the value of the second length field, N data bit blocks and M data bit blocks are associated, wherein N and M is an integer greater than or equal to zero.
  • the first tag bit block further includes a first sequence number field
  • the second tag bit block further includes a second sequence number field, if the value of the first length field is greater than the value of the second length field.
  • Correlating the N data bit blocks and the M data bit blocks includes: if the value of the first length field is greater than the value of the second length field by N and the value of the first sequence number field and the value of the second sequence number field Similarly, N data bit blocks and M data bit blocks are associated.
  • the first tag bit block further includes a first sequence number start field
  • the second tag bit block further includes a second sequence number start field
  • the method further includes: if the value of the second length field is M, determining that the last data bit block of the M data bit blocks is the last data data block corresponding to the sequence number.
  • sequentially receiving the second tag bit block and the M data bit blocks includes: sequentially receiving the second tag bit block, the M data bit block and the second tag end bit block, and ending the bit according to the second tag.
  • the block determines that the last one of the M data bit blocks is the last one data bit block corresponding to the sequence number.
  • a node in a fourth aspect, includes: a receiving module, configured to sequentially receive a first label bit block and N data bit blocks through a first port, where the first label bit block includes a first length field; and a sending module is configured to pass The second port sequentially sends the first label bit block and the M data bit blocks of the N data bit blocks, and is further configured to sequentially send the second label bit block and the remaining NM data in the N data bit blocks through the second port.
  • L data bit blocks in the bit block, the second tag bit block includes a second length field, the value of the first length field being greater than the value of the second length field, where M, N and L are integers greater than or equal to 0 .
  • the receiving module is further configured to obtain a third tag bit block and 0 data bit blocks, where O is an integer greater than or equal to 0; the sending module sequentially sends the second tag bit block and the second port through the second port.
  • the L data bit blocks of the remaining NM data bit blocks in the N data bit blocks are also used to sequentially transmit the third tag bit block and the O data bit blocks through the second port.
  • the first tag bit block further includes a first connection identifier field
  • the node further includes a processing module
  • the processing module is configured to obtain the second port according to the first connection identifier field.
  • the second tag bit block further includes a second connection identifier field, and the value of the first connection identifier field is the same as the value of the second connection identifier field.
  • the first tag bit block further includes a first sequence number field
  • the second tag bit block further includes a second sequence number field
  • the value of the first sequence number field and the second sequence number field have the same value
  • the first tag bit block further includes a first sequence number start field, and is used to identify whether the first data bit block of the N data bit blocks is the first data bit block corresponding to the sequence number.
  • the second tag bit block further includes a second sequence number start field for identifying whether the first data bit block of the L data bit blocks is the first data bit block corresponding to the sequence number.
  • the node further includes a processing module, where the sending module is configured to store the first length by sequentially transmitting the first label bit block and the M data bit blocks of the N data bit blocks through the second port. The value of the field; each time a block of data bits is sent, the value of the stored first length field is decremented by one.
  • the value of the second length field is the value of the first length field stored by the processing module.
  • the stored first length field is released.
  • the receiving module is configured to sequentially receive the first label bit block, the N data bit block and the first label end bit block through the first port;
  • the processing module is further configured to release the stored first length field.
  • a processing node of a bit block includes: a processing module, configured to generate a first label bit block, where the first label bit block includes a first length field, and is further configured to obtain N data bit blocks to be sent; And a sending module, configured to sequentially send the first label bit block and the N data bit blocks through the first port, where N is an integer greater than or equal to 0.
  • the value of the first length field is N.
  • the value of the first length field is a first preset value
  • sequentially sending the first label bit block and the N data bit blocks through the first port includes: sequentially sending the first label bit through the first port Block, N data bit blocks and a first tag end bit block.
  • the first tag bit block further includes at least one of a first connection identifier field, a first sequence number field, and a first sequence number start field, where the first connection identifier field is used for the first label bit
  • the block and the N data bit blocks are used for routing, the first sequence number field is used to identify the sequence number corresponding to the N data bit blocks, and the first sequence number start field is used to identify the first data bit block in the N data bit blocks. Whether it is the first data bit block corresponding to the serial number.
  • the first tag bit block further includes a first sequence number field
  • the first tag end bit block further includes a first end sequence number field, a value of the first sequence number field, and a first end sequence number field. The values are the same.
  • a processing node of a bit block includes: a receiving module, configured to sequentially receive a first label bit block and N data bit blocks, where the first label bit block includes a first length field, and is further configured to receive the first a second tag bit block and a M data bit block, the second tag bit block includes a second length field; and a processing module, configured to: if the value of the first length field is greater than the value of the second length field, N data bit blocks Correlation processing is performed with M data bit blocks, where N and M are integers greater than or equal to zero.
  • the first tag bit block further includes a first sequence number field
  • the second tag bit block further includes a second sequence number field
  • the processing module is specifically configured to: if the value of the first length field is longer than the second length The value of the field is large N and the value of the first sequence number field is the same as the value of the second sequence number field, and the N data bit blocks and the M data bit blocks are associated.
  • the first tag bit block further includes a first sequence number start field
  • the second tag bit block further includes a second sequence number start field
  • the processing module is further configured to start the value of the field according to the first sequence number.
  • the value of the second sequence number start field determines the first data bit block corresponding to the sequence number.
  • the processing module is further configured to determine, if the value of the second length field is M, the last data bit block of the M data bit blocks as the last data data block corresponding to the sequence number.
  • the receiver is specifically configured to sequentially receive the second tag bit block, the M data bit block and the second tag end bit block
  • the processing module is further configured to determine the M data according to the second tag end bit block.
  • the last block of data bits in the block is the last block of data bits corresponding to the sequence number.
  • a seventh aspect is a processing device for a bit block, the device comprising a processing module and a memory, the memory for storing a program, the processing module calling a program stored in the memory to perform the method provided by the first aspect of the invention.
  • a processing apparatus for a bit block comprising a processing module and a memory, the memory for storing a program, and the processing module calling a program stored in the memory to perform the method provided by the second aspect of the present invention.
  • a ninth aspect is a processing device for a bit block, the device comprising a processing module and a memory, the memory for storing a program, the processing module calling a program stored in the memory to perform the method provided by the third aspect of the invention.
  • a service data transmission apparatus includes at least one processing element (or chip) for performing the method of the above first aspect.
  • a service data transmission apparatus includes at least one processing element (or chip) for performing the method of the above second aspect.
  • a twelfth aspect a service data transmission apparatus comprising at least one processing element (or chip) for performing the method of the above third aspect.
  • a thirteenth aspect a computer storage medium comprising a program for performing the method of the above first aspect.
  • a fourteenth aspect a computer storage medium comprising a program for performing the method of the above second aspect.
  • a fifteenth aspect a computer storage medium comprising a program for performing the method of the above third aspect.
  • FIG. 1 is a schematic structural diagram of a system according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a code pattern definition of a PCS layer coding according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart diagram of a method for processing a bit block according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart diagram of another method for processing a bit block according to an embodiment of the present disclosure
  • FIG. 5A is a schematic diagram of a bit block segment preemption according to an embodiment of the present invention.
  • FIG. 5B is a schematic flowchart diagram of still another method for processing a bit block according to an embodiment of the present disclosure
  • FIG. 6 is a schematic flowchart diagram of still another method for processing a bit block according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a bit block processing node according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another bit block processing node according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of still another bit block processing node according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a bit block processing apparatus according to an embodiment of the present invention.
  • a schematic structural diagram of a system includes a transmitting node 101 and 102, switching nodes 103 and 104, and receiving nodes 105 and 106.
  • the sending node, the switching node, and the receiving node may be the same type of device, but the processing of the specific service flow is different for different service flows, for example, the sending node 101 may be a switching node for some service flows, It can be a receiving node.
  • the transmitting node 101 sends a first Ethernet frame to the switching node 103, which needs to be forwarded by the switching node 103 to the switching node 104, and forwarded to the receiving node 105 via the switching node 104; the transmitting node 102 to the switching node 103 transmits a second Ethernet frame that needs to be forwarded by the switching node 103 to the switching node 104 and forwarded to the receiving node 106 via the switching node 104.
  • the switching node 103 forwards the first Ethernet frame to the switching node 104, if during the sending of the first Ethernet frame, receives the second Ethernet frame, and the second Ethernet frame The priority is higher, and the delay is also required.
  • the preemptive transmission of the service can be performed, that is, the first Ethernet frame can be preempted for the second Ethernet frame transmission, and the prior art can adopt the Ethernet frame preemption technology.
  • the first Ethernet frame is truncated, but the first Ethernet frame has a limitation of the shortest message, that is, it needs to wait for the length of the transmitted first Ethernet frame to meet the truncation requirement before truncating and performing the second etheric
  • the transmission of the network frame after the second Ethernet frame is sent, the remaining part of the first Ethernet frame may be sent.
  • the first Ethernet frame belongs to Best effort traffic, which is a service that only needs the minimum performance guarantee service, and only requires the network to maximize the possibility.
  • the packet is sent, but there is no requirement for performance such as delay and reliability.
  • the second Ethernet frame belongs to critical traffic, which is a traffic that requires delay and determinism.
  • bit block coding In order to transmit Ethernet frames in the communication network, it is necessary to perform bit block coding at the physical layer to form a coded bit block. For example, a combination of 8B/10B coding and NRZ coding is adopted in Gigabit Ethernet. 10Gigabit Ethernet uses 64B/66B encoding. These 8B/10B coded blocks or 64B/66B coded blocks of the Ethernet physical layer are coded bit blocks.
  • the receiving end needs to recover the clock information from the received data to ensure synchronization. This requires that the binary stream transmitted in the line has enough transitions, that is, there cannot be too many consecutive high levels or lows. Level, otherwise the clock information cannot be extracted, which is why the physical layer performs bit block coding.
  • FIG. 2 is a schematic diagram of a code pattern definition of a PCS layer coding according to an embodiment of the present invention.
  • Figure 2 shows the 64B/66B encoding, where the two Bit “10" or "01" of the header are 64B/66B bit block sync header bits, and the last 64 Bit is used to carry payload data or protocols.
  • Each row represents a pattern definition of a bit block, where D0 to D7 represent data bytes, C0 to C7 represent control bytes, S0 represents a start byte, and T0 to T7 represent end bytes.
  • the sync header bit of the first line is "01", the following bytes are all data bytes; the sync bits of the 2nd, 3rd, and 4th lines are "10", and the second line is mainly used as the frequency offset adaptation, wherein 3, 4 rows of bit blocks are no longer supported at 40GE and higher; 5th, 6th, and 8th are ordered set (O) coded bit blocks, and the synchronization bit is "10", which is mainly used for operation and maintenance management. Bits 5 and 6 are no longer supported at 40GE and higher.
  • the seventh behavior starts the bit block, the sync header bit is "10"; the ninth through sixteenth behaviors are eight end bit blocks, and the sync header bit is "10".
  • the bit block mentioned in the embodiment of the present invention is an M1/M2 bit block, and M1/M2bit represents an encoding mode, where M1 represents the number of payload bits in each bit block, and M2 represents the bit number of each bit block after encoding.
  • M1 represents the number of payload bits in each bit block
  • M2 represents the bit number of each bit block after encoding.
  • the total number of bits, M1 and M2 are positive integers, and M2>M1.
  • the preemption of the priority is based on the bit block of the physical layer, rather than the Ethernet frame truncation based on the MAC layer.
  • a method for processing a bit block according to an embodiment of the present invention may be applied to the sending nodes 101 and 102.
  • the first label bit block and the N data bit blocks are sequentially sent by using a first port.
  • An embodiment of the present invention provides a tag bit block, where the tag bit block carries a length field, and the tag bit block can be followed by a plurality of data bit blocks, and then another tag bit block and a plurality of tags following the other tag bit block.
  • the data bit block, the length field is associated with a number of data bit blocks that follow.
  • the block segment can be truncated according to the tag block to form at least two new blocks.
  • the bit block segments each of which includes a tag bit block.
  • the transmitting nodes 101 and 102 are host devices, the data bit block can be directly acquired. If the transmitting nodes 101 and 102 are intermediate conversion devices, the message can be converted into data bit blocks after receiving the message from other nodes, for example, from Ethernet, A node of a network such as an Optical Transport Network (OTN) network or a Synchronous Digital Hierarchy (SDH) network receives a message.
  • OTN Optical Transport Network
  • SDH Synchronous Digital Hierarchy
  • the steps S301 and S302 may have no sequence, that is, after the N data bit blocks to be sent are acquired, the corresponding first tag bit block may be generated, or may be performed simultaneously.
  • the value of the first length field may be set to N.
  • the value of the first length field may be set to a first preset value, for example, The bits of the first length field are all set to 1, that is, the value of the first length field is set to a maximum value that can be set.
  • the first tag end bit block may be transmitted after transmitting the last bit block of the N data bit blocks. That is, step 303 is specifically to sequentially send the first label bit block by using the first port, the N data bit block and the first label end bit block.
  • the first label bit block may further include at least one of a first connection identifier field, a first sequence number field, and a first sequence number start field, where the first connection identifier field is used to the first label bit
  • the block and the N data bit blocks are used for routing, the first sequence number field is used to identify a sequence number corresponding to the N data bit blocks, and the first sequence number start field is used to identify the N data bit blocks. Whether the first data bit block is the first data bit block corresponding to the sequence number.
  • the first tag bit block further includes a first sequence number field, where the first tag end bit block further includes a first end sequence number field, a value of the first sequence number field, and the first end sequence number field
  • the values are the same.
  • the tag end bit block may also not include the first end sequence number field, and it is also possible to indicate only the type of the bit block.
  • a tag bit block is provided in an embodiment of the present invention.
  • the bit block uses an O code bit block in the eighth row of FIG. 2, where D1 and D2 bytes are connection identifier fields (connection identity). , Conn_id), the D3 byte includes the first tag field (First Tag, Ft) and the length field (Length, Len), the O code is set to 4, the C4 and C5 bytes are the sequence number field (Sequence Num), C6 and C7 words. The section is reserved (reserved).
  • the bit block of the other coding mode can also be used to generate the tag bit block, wherein the length field is mandatory, and other fields are optional, which is not limited in the embodiment of the present invention.
  • a tag end bit block is provided in an embodiment of the present invention.
  • the bit block uses an O code bit block in the 8th line of FIG. 2, where D1 and D2 bytes are connection identifier fields (connection Identity, Conn_id), D3 byte is reserved field, O code is set to 5, C4 and C5 bytes are sequence number field (Sequence Num), and C6 and C7 bytes are reserved field (reserved).
  • connection Identity connection Identity
  • Conn_id connection Identity
  • D3 byte is reserved field
  • O code is set to 5
  • C4 and C5 bytes are sequence number field (Sequence Num)
  • C6 and C7 bytes are reserved field (reserved).
  • the bit block of the other coding mode may be used to generate the tag end bit block, where only one field may be used to indicate that the tag end block belongs to one tag, and other fields are optional, which is not limited in the embodiment of the present invention.
  • a method for processing a bit block according to an embodiment of the present invention may be applied to the switching nodes 103 and 104.
  • S401 Receive, by using a first port, a first label bit block and an N data bit block, where the first label bit block includes a first length field.
  • the first label bit block and the M data bit blocks of the N data bit blocks are sequentially sent through the second port.
  • the second label bit block and the L data bit blocks in the remaining NM data bit blocks in the N data bit blocks are sequentially sent by the second port, where the second label bit block includes a second length field, where The value of the first length field is greater than the value of the second length field, where M, N, and L are integers greater than or equal to zero.
  • the received first label bit block and the N data bit blocks form a bit block segment
  • the switching node may intercept the bit block segment to generate at least two bit block segments, that is, generate the first tag bit.
  • a first block block composed of blocks of M data bits and N data bit blocks, and also generates L data bits of the second tag bit block and the remaining NM data bit blocks of the N data bit blocks a second block segment composed of blocks
  • the first tag bit block includes a value of a first length field that is greater than a value of a second length field included in the second tag bit block, thus receiving a node or other node in need, such as
  • the reassembly node can combine the bit block segments according to the value of the length field.
  • the switching node intercepts the received bit block segment, that is, can preempt traffic for sending other services, for example, can send critical traffic, and another bit block segment can be continuously preempted by multiple critical traffic multiple times, or intermittently preempted. Many times, the embodiment of the present invention does not limit this.
  • the block segment may be truncated based on other requirements, such as a user setting a length limit for a particular node's bit block segment, and the like.
  • a third tag bit block and an O data bit block may be obtained, where O is an integer greater than or equal to 0, and the M data in the first tag bit block and the N data bit blocks are sequentially transmitted through the second port.
  • the third tag bit block and the O data bit block may be sequentially sent through the second port, that is, preemptive transmission is performed.
  • the specific implementation of obtaining the third tag bit block and the O data bit block may be: sequentially receiving the third tag bit block and the O data bit block through a third port, where the node may receive the Ethernet according to the received Generating the third tag bit block and the O data bit block, or generating the third tag bit block and the O data bit block according to local service, of course, other technologies may be used to generate the The three-label bit block and the O data bit block are not limited in this embodiment of the present invention.
  • the traffic preempting the transmitted other traffic may also include no tag bit block, only the data bit block.
  • a schematic diagram of a bit block segment preemption includes two upper and lower parts, the upper part is a received bit block segment, and the lower part is a transmitted bit block segment.
  • the received bit block segment includes a first tag bit block, and the length field has a value of 11.
  • the received bit block segment is divided into two tag bit block segments when transmitted, and the first tag bit block segment includes a first tag bit block and The next 4 data bit blocks, the second tag bit block segment includes a second tag bit block and a subsequent 7 data bit blocks, which are preemptively transmitted by 1 third tag bit block and 2 gray data bit blocks.
  • the received bit block segment can also be divided into more tag bit block segments when transmitting, and the two tag bit block segments that are sent out can be truncated again in the processing of subsequent nodes, of course, The combination is restored to a block of bits.
  • the number of data bit blocks transmitted in step S402 may be 0, the number of data bit blocks transmitted in step S403 may also be 0, and the number of data bit blocks received in the step may also be 0.
  • the number of O may also be zero because it may also be preempted by higher priority services.
  • the switching node After receiving the first label bit block and the N data bit blocks in step 401, the switching node needs to determine which port to forward through, and the received first label bit block may further include a first connection identifier field, which may be searched according to the field. Obtain the second port, and you can obtain the second port by looking up the table or other means.
  • the first connection identification field can be implemented by the connection identification fields of D1 and D2 bytes in Table 1. If the connection identifier field is not included in the first label bit block, the second port may be obtained through pre-configuration or network management configuration.
  • the second tag bit block in step 403 may also include a second connection identifier field, a value of the first connection identifier field, and a second connection identifier.
  • the values of the fields are the same.
  • the first tag bit block may further include a first sequence number field
  • the second tag bit block may further include a second sequence number field, a value of the first sequence number field, and the second serial number The values of the fields are the same.
  • the first tag bit block may further include a first sequence number start field, configured to identify whether the first data bit block of the N data bit blocks is the first data bit block corresponding to the sequence number;
  • the tag bit block may further include a second sequence number start field, configured to identify whether the first data bit block of the L data bit blocks is the first data bit block corresponding to the sequence number.
  • the first label bit block may be stored, or the value of the first length field may be stored.
  • the value of the stored first length field is decremented by one for each data bit block transmitted.
  • the second value of the stored first length field may be directly used to generate the second Tag bit block.
  • the stored first length field can be released.
  • the stored first length field may be released.
  • a method for processing a bit block according to an embodiment of the present invention may be applied to the switching nodes 103 and 104.
  • S501 Receive a bit block segment of the traffic of the best effort service, and find and obtain an output port according to the connection identifier field in the tag bit block.
  • step S504 it is determined whether there is a preemption signal. If there is a preemption signal, step S505 is performed, and if there is no preemption signal, step S507 is performed. That is, if there is a preemption signal, the traffic of the best effort service is stopped, and the preemptive key traffic is sent, and after the preemptive key traffic is sent, the execution continues from step S503.
  • S505 Send a preemption signal.
  • step S506 the preemption signal transmission ends, and then step S503 is performed.
  • step S509 Determine whether the length field in the storage tag bit block is 0. If it is 0, execute step S510. If not, execute step S504.
  • a method for processing a bit block according to an embodiment of the present invention may be applied to the receiving nodes 105 and 106.
  • S602. Receive a second tag bit block and M data bit blocks in sequence, where the second tag bit block includes a second length field.
  • the first label bit block may further include a first sequence number field
  • the second label bit block may further include a second sequence number field, if the value of the first length field is greater than the value of the second length field A large N and the value of the first sequence number field and the value of the second sequence number field are the same, and the N data bit blocks and the M data bit blocks are associated.
  • the first tag bit block may further include a first sequence number start field
  • the second tag bit block may further include a second sequence number start field, according to the first sequence number start field value and the second sequence number start field The value determines the first block of data bits corresponding to the sequence number.
  • the last one of the M data bit blocks is the last one data bit block corresponding to the sequence number.
  • the last data bit block of the M data bit blocks may be determined according to the second tag end bit block.
  • the last data bit block corresponding to the serial number.
  • after receiving a block segment it may first determine, according to the value of the sequence number field of the tag bit block, whether a bit block having the same sequence number has been received before;
  • bit block segment can be sent up, for example, can be sent to the Ethernet layer for upper layer processing, and if not included, the bit block segment can be temporarily stored.
  • bit block segment is a block segment that is expected to be received according to the value of the length field of the tag bit block, if the bit block segment is a bit that is expected to be received.
  • the block segment can be sent up, and if the block segment is not the desired block segment, the block segment can be temporarily stored.
  • multiple bit block segments belonging to the same sequence number are reassembled into one bit segment, or only the data bit block is recombined, and then Uploaded to the Ethernet layer for processing.
  • a block block is added to a series of bit blocks in a bit block, and a bit block segment is formed.
  • the bit block segment can be truncated by the length field of the tag bit block.
  • the bit block segment can be routed through the connection identifier field of the tag bit block; the sequence number field corresponding to the data bit block in the bit block segment can be identified by the sequence number field of the tag bit block; the start field can be started by the sequence number of the tag bit block. It is identified whether the data bit block in the bit block segment contains the first data bit block corresponding to the sequence number, so that the bit node can be quickly reassembled at the receiving node.
  • the value of the length field in the tag bit block is the determined number of bit blocks, or is only a preset value, the switching node does not care, the processing manner may be the same, and the switching node is not Need to sort, the processing is very simple.
  • FIG. 7 is a schematic structural diagram of a bit block processing node according to an embodiment of the present invention, including:
  • the receiving module 701 is configured to sequentially receive the first label bit block and the N data bit blocks by using the first port, where the first label bit block includes a first length field;
  • the sending module 702 is configured to sequentially send, by using the second port, the first label bit block and the M data bit blocks of the N data bit blocks, and is further configured to sequentially send the second label bit block and the N data bits through the second port.
  • L data bit blocks in the remaining NM data bit blocks in the block, the second tag bit block includes a second length field, the value of the first length field being greater than the value of the second length field, where M, N and L Both are integers greater than or equal to zero.
  • the receiving module 701 is further configured to acquire a third tag bit block and 0 data bit blocks, where O is an integer greater than or equal to 0; the sending module sequentially sends the second tag bit block through the second port. And L data bit blocks out of the remaining NM data bit blocks of the N data bit blocks are also used to sequentially transmit the third tag bit block and the O data bit blocks through the second port.
  • the first tag bit block further includes a first connection identifier field
  • the node further includes a processing module
  • the processing module is configured to obtain the second port according to the first connection identifier field.
  • the second tag bit block further includes a second connection identifier field, and the value of the first connection identifier field is the same as the value of the second connection identifier field.
  • the first tag bit block further includes a first sequence number field
  • the second tag bit block further includes a second sequence number field
  • the value of the first sequence number field and the second sequence number field have the same value
  • the first tag bit block further includes a first sequence number start field, and is used to identify whether the first data bit block of the N data bit blocks is the first data bit block corresponding to the sequence number.
  • the second tag bit block further includes a second sequence number start field for identifying whether the first data bit block of the L data bit blocks is the first data bit block corresponding to the sequence number.
  • the node further includes a processing module, where the sending module is configured to store the first length by sequentially transmitting the first label bit block and the M data bit blocks of the N data bit blocks through the second port. The value of the field; each time a block of data bits is sent, the value of the stored first length field is decremented by one.
  • the value of the second length field is the value of the first length field stored by the processing module.
  • the stored first length field is released.
  • the receiving module is configured to sequentially receive the first label bit block, the N data bit block and the first label end bit block through the first port;
  • the processing module is further configured to release the stored first length field.
  • a schematic structural diagram of a bit block processing node according to an embodiment of the present invention includes:
  • the processing module 801 is configured to generate a first label bit block, where the first label bit block includes a first length field, and is further used to obtain N data bit blocks to be sent.
  • the sending module 802 is configured to sequentially send the first label bit block and the N data bit blocks through the first port.
  • the value of the first length field is N.
  • the value of the first length field is a first preset value
  • sequentially sending the first label bit block and the N data bit blocks through the first port includes: sequentially sending the first label bit through the first port Block, N data bit blocks and a first tag end bit block.
  • the first tag bit block further includes at least one of a first connection identifier field, a first sequence number field, and a first sequence number start field, where the first connection identifier field is used for the first label bit
  • the block and the N data bit blocks are used for routing, the first sequence number field is used to identify the sequence number corresponding to the N data bit blocks, and the first sequence number start field is used to identify the first data bit block in the N data bit blocks. Whether it is the first data bit block corresponding to the serial number.
  • the first tag bit block further includes a first sequence number field
  • the first tag end bit block further includes a first end sequence number field, a value of the first sequence number field, and a first end sequence number field. The values are the same.
  • a schematic structural diagram of a bit block processing node according to an embodiment of the present invention includes:
  • the receiving module 901 is configured to sequentially receive the first label bit block and the N data bit blocks, where the first label bit block includes a first length field, and is further configured to sequentially receive the second label bit block and the M data bit blocks, and second The tag bit block includes a second length field;
  • the processing module 902 is configured to process the N data bit blocks and the M data bit blocks if the value of the first length field is greater than the value of the second length field.
  • the first tag bit block further includes a first sequence number field
  • the second tag bit block further includes a second sequence number field
  • the processing module is specifically configured to: if the value of the first length field is longer than the second length The value of the field is large N and the value of the first sequence number field is the same as the value of the second sequence number field, and the N data bit blocks and the M data bit blocks are associated.
  • the first tag bit block further includes a first sequence number start field
  • the second tag bit block further includes a second sequence number start field
  • the processing module is further configured to start the value of the field according to the first sequence number.
  • the value of the second sequence number start field determines the first data bit block corresponding to the sequence number.
  • the processing module is further configured to determine, if the value of the second length field is M, the last data bit block of the M data bit blocks as the last data data block corresponding to the sequence number.
  • the receiver is specifically configured to sequentially receive the second tag bit block, the M data bit block and the second tag end bit block
  • the processing module is further configured to determine the M data according to the second tag end bit block.
  • the last block of data bits in the block is the last block of data bits corresponding to the sequence number.
  • the sending module in the foregoing embodiment may be a transmitter
  • the receiving module may be a receiver
  • the processing module may be a processor
  • each module of the above device is only a division of a logical function, and the actual implementation may be integrated into one physical entity in whole or in part, or may be physically separated.
  • these modules can all be implemented by software in the form of processing component calls; or all of them can be implemented in hardware form; some modules can be realized by processing component calling software, and some modules are realized by hardware.
  • the sending module may be a separately set component, or may be integrated in one of the devices of the above device, or may be stored in the memory of the device in the form of program code, and is called by one of the processing devices of the device. And perform the above to determine the function of the module.
  • the implementation of other modules is similar.
  • all or part of these modules can be integrated or implemented independently.
  • the processing elements described herein can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules may be completed by an integrated logic circuit of hardware in the processor element or an instruction in a form of software.
  • the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (Digital) Signal Processor, DSP), or one or more Field Programmable Gate Arrays (FPGAs).
  • ASICs Application Specific Integrated Circuits
  • DSP Digital Signal Processor
  • FPGAs Field Programmable Gate Arrays
  • the processing component can be a general purpose processor, such as a central processing unit (CPU) or other processor that can invoke program code.
  • these modules can be integrated and implemented in the form of a system-on-a-chip (SOC).
  • SOC system-on-a-chip
  • FIG. 10 is a schematic structural diagram of a bit block processing apparatus according to an embodiment of the present invention.
  • the apparatus may be the node 101, 102, 103, 104, 105 or 106 in FIG. 1.
  • the apparatus includes a memory 10 and a processor 11.
  • the memory 10 can be a separate physical unit and can be connected to the processor 11 via a bus.
  • the memory 10 and the processor 11 can also be integrated together, implemented by hardware or the like.
  • the memory 10 is used to store a program for implementing the above method embodiments, or the modules of the embodiment shown in FIG. 7 to FIG. 9, and the processor 11 calls the program to perform the operations of the above method embodiments.
  • the foregoing apparatus may also include only a processor.
  • the memory for storing the program is located outside the access device, and the processor is connected to the memory through the circuit/wire for reading and executing the program stored in the memory.
  • the processor may be a Central Processing Unit (CPU), a Network Processor (NP) or a combination of a CPU and an NP.
  • CPU Central Processing Unit
  • NP Network Processor
  • the processor may further include a hardware chip.
  • the hardware chip may be an Application-specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof.
  • the PLD may be a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a Generic Array Logic (GAL), or any combination thereof.
  • the memory may include a volatile memory such as a random access memory (RAM); the memory may also include a non-volatile memory such as a flash memory.
  • RAM random access memory
  • non-volatile memory such as a flash memory.
  • HDD hard disk drive
  • SSD solid state drive
  • the memory may also include a combination of the above types of memories.
  • the embodiment of the present invention further provides a computer storage medium, which is stored with a computer program, and is used to execute the service data transmission method provided by the foregoing embodiment.
  • the embodiment of the invention further provides a computer program product comprising instructions, which when executed on a computer, causes the computer to execute the service data transmission method provided by the above embodiment.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本发明实施例提供了一种比特块的处理方法，包括：通过第一端口依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段；通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块；通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，第二标签比特块包括第二长度字段，第一长度字段的值比第二长度字段的值大M，其中M，N和L均为大于等于0的整数。采用本发明实施例提供的方法，标签比特块和跟随的数据比特块组成了一个比特块段，转发该比特块段时，将该比特块段截断为至少两个比特块段，每个截断后的比特块段都包括一个标签比特块。

Description

一种比特块处理方法及节点 技术领域
本发明涉及通信技术领域，特别涉及一种比特块处理方法及节点。
背景技术
目前以太网技术应用十分广泛，5G移动承载、工业互联网等未来新业务对以太网提出了新的需求，例如对低时延、确定性和高可靠性提出了更高的需求。
现有技术中采用以太网帧抢占技术来降低关键流量的时延，但是在时延上受到以太网最短报文的限制，对时延的降低有限，现有技术中在物理层无法进行比特块截断。
发明内容
本发明实施例提供一种比特块处理方法及节点，用以解决在物理层无法进行比特块截断的问题。
第一方面，一种比特块的处理方法，包括：通过第一端口依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段；通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块；通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，第二标签比特块包括第二长度字段，第一长度字段的值比第二长度字段的值大M，其中M，N和L均为大于等于0的整数。
采用本发明实施例提供的方法，增加了标签比特块，并且标签比特块携带了长度字段，标签比特块和跟随的数据比特块组成了一个比特块段，转发该比特块段时，可以将该比特块段截断为至少两个比特块段，每个截断后的比特块段都包括一个标签比特块，该标签比特块的长度字段的值和截断的数据比特块的数量相关。
在一种可能的设计中，通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块之前还包括：获取第三标签比特块和O个数据比特块，其中O为大于等于0的整数；通过第二端口依次发送第三标签比特块和O个数据比特块。
在一种可能的设计中，第一标签比特块还包括第一连接标识字段，通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块之前还包括：根据第一连接标识字段查找获得第二端口。
在一种可能的设计中，第二标签比特块还包括第二连接标识字段，第一连接标识字段的值和第二连接标识字段的值相同。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第二标签比特块还包括第二序列号字段，第一序列号字段的值和第二序列号字段的值相同。
在一种可能的设计中，第一标签比特块还包括第一序列号开始字段，用于标识N个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块；第二标签比特块还包括第二序列号开始字段，用于标识L个数据比特块中的第1个数据比特块是否为序列 号对应的第1个数据比特块。
在一种可能的设计中，通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块时还包括：存储第一长度字段的值；每发送一个数据比特块，将存储的第一长度字段的值减一。
在一种可能的设计中，第二长度字段的值为存储的第一长度字段的值。
在一种可能的设计中，如果存储的第一长度字段的值为零，则释放存储的第一长度字段。
在一种可能的设计中，通过第一端口依次接收第一标签比特块和N个数据比特块包括：通过第一端口依次接收第一标签比特块，N个数据比特块和第一标签结束比特块；通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块后还包括：通过第二端口发送第一标签结束比特块后，释放存储的第一长度字段。
第二方面，一种比特块的处理方法，包括:生成第一标签比特块，第一标签比特块包括第一长度字段；获取待发送的N个数据比特块；通过第一端口依次发送第一标签比特块和N个数据比特块，其中N为大于等于0的整数。
在一种可能的设计中，第一长度字段的值为N。
在一种可能的设计中，第一长度字段的值为第一预设值，通过第一端口依次发送第一标签比特块和N个数据比特块包括：通过第一端口依次发送第一标签比特块，N个数据比特块和第一标签结束比特块。
在一种可能的设计中，第一标签比特块还包括第一连接标识字段，第一序列号字段，第一序列号开始字段中的至少一个，第一连接标识字段用于对第一标签比特块和N个数据比特块进行路由，第一序列号字段用于标识N个数据比特块对应的序列号，第一序列号开始字段用于标识N个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第一标签结束比特块还包括第一结束序列号字段，第一序列号字段的值和第一结束序列号字段的值相同。
第三方面，一种比特块的处理方法，包括:依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段；依次接收第二标签比特块和M个数据比特块，第二标签比特块包括第二长度字段；如果第一长度字段的值比第二长度字段的值大N，将N个数据比特块和M个数据比特块进行关联处理，其中N和M为大于等于0的整数。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第二标签比特块还包括第二序列号字段，如果第一长度字段的值比第二长度字段的值大N，将N个数据比特块和M个数据比特块进行关联处理包括：如果第一长度字段的值比第二长度字段的值大N且第一序列号字段的值和第二序列号字段的值相同，将N个数据比特块和M个数据比特块进行关联处理。
在一种可能的设计中，第一标签比特块还包括第一序列号开始字段，第二标签比特块还包括第二序列号开始字段，还包括：根据第一序列号开始字段的值和第二序列号开始字段的值确定序列号对应的第1个数据比特块。
在一种可能的设计中，还包括：如果第二长度字段的值为M，则确定M个数据比特块中的最后一个数据比特块为序列号对应的最后1个数据比特块。
在一种可能的设计中，依次接收第二标签比特块和M个数据比特块包括：依次接收第二标签比特块，M个数据比特块和第二标签结束比特块，根据第二标签结束比特块确定M个数据比特块中的最后一个数据比特块为序列号对应的最后1个数据比特块。
第四方面，一种节点，包括：接收模块，用于通过第一端口依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段；发送模块，用于通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块，还用于通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，第二标签比特块包括第二长度字段，第一长度字段的值比第二长度字段的值大M，其中M，N和L均为大于等于0的整数。
在一种可能的设计中，接收模块还用于获取第三标签比特块和O个数据比特块，其中O为大于等于0的整数；发送模块在通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块之前还用于通过第二端口依次发送第三标签比特块和O个数据比特块。
在一种可能的设计中，第一标签比特块还包括第一连接标识字段，节点还包括处理模块，处理模块用于根据第一连接标识字段查找获得第二端口。
在一种可能的设计中，第二标签比特块还包括第二连接标识字段，第一连接标识字段的值和第二连接标识字段的值相同。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第二标签比特块还包括第二序列号字段，第一序列号字段的值和第二序列号字段的值相同。
在一种可能的设计中，第一标签比特块还包括第一序列号开始字段，用于标识N个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块；第二标签比特块还包括第二序列号开始字段，用于标识L个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块。
在一种可能的设计中，节点还包括处理模块，发送模块通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块时，处理模块用于存储第一长度字段的值；每发送一个数据比特块，将存储的第一长度字段的值减一。
在一种可能的设计中，第二长度字段的值为处理模块存储的第一长度字段的值。
在一种可能的设计中，如果存储的第一长度字段的值为零，则释放存储的第一长度字段。
在一种可能的设计中，接收模块用于通过第一端口依次接收第一标签比特块，N个数据比特块和第一标签结束比特块；
发送模块通过第二端口发送第一标签结束比特块后，处理模块还用于释放存储的第一长度字段。
第五方面，一种比特块的处理节点，包括:处理模块，用于生成第一标签比特块，第一标签比特块包括第一长度字段，还用于获取待发送的N个数据比特块；发送模块，用于通过第一端口依次发送第一标签比特块和N个数据比特块，其中N为大于等于0的整数。
在一种可能的设计中，第一长度字段的值为N。
在一种可能的设计中，第一长度字段的值为第一预设值，通过第一端口依次发送第一标签比特块和N个数据比特块包括：通过第一端口依次发送第一标签比特块，N个数据比 特块和第一标签结束比特块。
在一种可能的设计中，第一标签比特块还包括第一连接标识字段，第一序列号字段，第一序列号开始字段中的至少一个，第一连接标识字段用于对第一标签比特块和N个数据比特块进行路由，第一序列号字段用于标识N个数据比特块对应的序列号，第一序列号开始字段用于标识N个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第一标签结束比特块还包括第一结束序列号字段，第一序列号字段的值和第一结束序列号字段的值相同。
第六方面，一种比特块的处理节点，包括:接收模块，用于依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段，还用于依次接收第二标签比特块和M个数据比特块，第二标签比特块包括第二长度字段；处理模块，用于如果第一长度字段的值比第二长度字段的值大N，将N个数据比特块和M个数据比特块进行关联处理，其中N和M为大于等于0的整数。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第二标签比特块还包括第二序列号字段，处理模块具体用于如果第一长度字段的值比第二长度字段的值大N且第一序列号字段的值和第二序列号字段的值相同，将N个数据比特块和M个数据比特块进行关联处理。
在一种可能的设计中，第一标签比特块还包括第一序列号开始字段，第二标签比特块还包括第二序列号开始字段，处理模块还用于根据第一序列号开始字段的值和第二序列号开始字段的值确定序列号对应的第1个数据比特块。
在一种可能的设计中，处理模块还用于如果第二长度字段的值为M，则确定M个数据比特块中的最后一个数据比特块为序列号对应的最后1个数据比特块。
在一种可能的设计中，接收机具体用于依次接收第二标签比特块，M个数据比特块和第二标签结束比特块，处理模块还用于根据第二标签结束比特块确定M个数据比特块中的最后一个数据比特块为序列号对应的最后1个数据比特块。
第七方面，一种比特块的处理装置，所述装置包括处理模块和存储器，存储器用于存储程序，处理模块调用存储器存储的程序，以执行本发明第一方面提供的方法。
第八方面，一种比特块的处理装置，所述装置包括处理模块和存储器，存储器用于存储程序，处理模块调用存储器存储的程序，以执行本发明第二方面提供的方法。
第九方面，一种比特块的处理装置，所述装置包括处理模块和存储器，存储器用于存储程序，处理模块调用存储器存储的程序，以执行本发明第三方面提供的方法。
第十方面，一种业务数据传输装置，包括用于执行以上第一方面的方法的至少一个处理元件(或芯片)。
第十一方面，一种业务数据传输装置，包括用于执行以上第二方面的方法的至少一个处理元件(或芯片)。
第十二方面，一种业务数据传输装置，包括用于执行以上第三方面的方法的至少一个处理元件(或芯片)。
第十三方面，一种计算机存储介质，包括程序，所述程序用于执行以上第一方面的方法。
第十四方面，一种计算机存储介质，包括程序，所述程序用于执行以上第二方面的方法。
第十五方面，一种计算机存储介质，包括程序，所述程序用于执行以上第三方面的方法。
附图说明
图1为本发明实施例提供的一种系统结构示意图；
图2为本发明实施例提供的一种PCS层编码的码型定义示意图；
图3为本发明实施例提供的一种比特块的处理方法的流程示意图；
图4为本发明实施例提供的另一种比特块的处理方法的流程示意图；
图5A为本发明实施例提供的一种比特块段抢占示意图；
图5B为本发明实施例提供的再一种比特块的处理方法的流程示意图；
图6为本发明实施例提供的再一种比特块的处理方法的流程示意图；
图7为本发明实施例提供的一种比特块处理节点的结构示意图；
图8为本发明实施例提供的另一种比特块处理节点的结构示意图；
图9为本发明实施例提供的再一种比特块处理节点的结构示意图；
图10为本发明实施例提供的一种比特块处理装置的结构示意图。
具体实施方式
下面结合附图，对本发明的实施例进行描述。
如图1所示，为本发明实施例提供的一种系统结构示意图，包括发送节点101和102，交换节点103和104，以及接收节点105和106。其中发送节点，交换节点以及接收节点可以是相同类型的设备，只是对于具体业务流，不同的节点对具体业务流的处理不同，例如其中发送节点101对于某些业务流，可以是交换节点，也可以是接收节点。
假设发送节点101向交换节点103发送第一以太网帧，该第一以太网帧需要经过交换节点103的转发到达交换节点104，并经过交换节点104转发到接收节点105；发送节点102向交换节点103发送第二以太网帧，该第二以太网帧需要经过交换节点103的转发到达交换节点104，并经过交换节点104转发到接收节点106。交换节点103接收第一以太网帧后，将第一以太网帧转发到交换节点104，如果在第一以太网帧的发送过程中，接收到第二以太网帧，并且第二以太网帧的优先级较高，对时延的要求也较高，此时可以进行业务的抢占发送，即可以抢占第一以太网帧进行第二以太网帧的发送，现有技术可以采用以太网帧抢占技术，例如对第一以太网帧进行截断，但是第一以太网帧有最短报文的限制，即需要等待已发送的第一以太网帧的长度满足截断要求后，才能进行截断并进行第二以太网帧的发送，待第二以太网帧发送完成后，可以发送第一以太网帧的剩余部分。
对于业务的抢占发送，进行以下举例，第一以太网帧属于尽力服务的流量(Best effort traffic)，该流量是一种只需要最小性能保证的服务的流量，只要求网络尽最大的可能性来发送报文，但对时延、可靠性等性能没有要求；第二以太网帧属于关键流量(Critical traffic)，该流量是一种要求保证时延和确定性的流量。
为了在通信网络中发送以太网帧，需要在物理层进行比特块(Bit block)编码，形成一 个个编码后的比特块，例如千兆以太网中采用的是8B/10B编码与NRZ编码组合方式；万兆以太网用的是64B/66B编码。以太网物理层的这些8B/10B的编码块或64B/66B的编码块就是编码后的比特块。在通信网络中，接收端需要从接收数据中恢复出时钟信息来保证同步，这就需要线路中所传输的二进制码流有足够多的跳变，即不能有过多连续的高电平或低电平，否则无法提取时钟信息，这也是物理层进行比特块编码的原因。
如图2所示，为本发明实施例提供的一种PCS层编码的码型定义示意图。图2所示的是64B/66B编码，其中首部的2个Bit“10”或“01”是64B/66B比特块同步头比特，后64Bit用于承载净荷数据或协议。每一行代表一种比特块的码型定义，其中，D0～D7代表数据字节，C0～C7代表控制字节，S0代表开始字节，T0～T7代表结束字节。第1行的同步头比特为“01”，后面的字节均为数据字节；第2、3、4行的同步比特为“10”，其中第2行主要用作频偏适配，其中3、4行比特块在40GE以及更高速率不再支持；第5、6、8行为有序集合(Ordered set，O)码比特块，同步比特为“10”，主要用于操作维护管理，第5、6行比特块在40GE以及更高速率不再支持。第7行为开始比特块，同步头比特为“10”；第9至第16行为8种结束比特块，同步头比特为“10”。
本发明实施例中提到的比特块为M1/M2比特块，M1/M2bit代表一种编码方式，其中，M1表示每个比特块中的净荷比特数，M2表示编码后每个比特块的总比特数，M1、M2为正整数，M2＞M1。
本发明实施例中，优先级的抢占是基于物理层的比特块，而不是基于MAC层的以太网帧截断。
如图3所示，为本发明实施例提供的一种比特块的处理方法，该方法可以应用于发送节点101和102。
S301，生成第一标签比特块，所述第一标签比特块包括第一长度字段；
S302，获取待发送的N个数据比特块；
S303，通过第一端口依次发送所述第一标签比特块和所述N个数据比特块。
本发明实施例提供了一种标签比特块，该标签比特块携带长度字段，标签比特块后面可以跟随若干个数据比特块，然后是另一个标签比特块及跟随该另一个标签比特块的若干个数据比特块，长度字段和跟随的若干个数据比特块相关。我们把标签比特块以及后面跟随的若干个数据比特块称为一个比特块段，在发送或转发一个比特块段时，可以根据标签比特块将这个比特块段进行截断发送，形成至少两个新的比特块段，每个新的比特块段都包括一个标签比特块。
如果发送节点101和102是主机设备，则可以直接获取数据比特块，如果发送节点101和102是中间转换设备，则可以从其它节点接收报文后转换为数据比特块，例如可以从以太网、光传送网(Optical Transport Network，OTN)网络、同步数字体系(Synchronous Digital Hierarchy，SDH)网络等网络的节点接收报文。
本发明实施例中，步骤S301和S302可以不存在先后顺序，即也可以在获取待发送的N个数据比特块后，生成对应的第一标签比特块，也可以同时进行。
可选地，如果在生成第一标签比特块时，能够获取数据比特块的数量，则在生成第一标签比特块时，可以设置第一长度字段的值为N。
可选地，如果在生成第一标签比特块时，不能够获取数据比特块的数量，则在生成第 一标签比特块时，可以设置第一长度字段的值为第一预设值，例如可以将第一长度字段的比特全部设置为1，即设置第一长度字段的值为可以设置的最大值。此时，为了接收节点能够识别出最后一个比特块，可以在发送所述N个数据比特块的最后一个比特块后发送第一标签结束比特块。即步骤303具体为通过第一端口依次发送所述第一标签比特块，所述N个数据比特块和第一标签结束比特块。
可选地，第一标签比特块还可以包括第一连接标识字段，第一序列号字段，第一序列号开始字段中的至少一个，其中第一连接标识字段用于对所述第一标签比特块和所述N个数据比特块进行路由，第一序列号字段用于标识所述N个数据比特块对应的序列号，第一序列号开始字段用于标识所述N个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块。
可选地，第一标签比特块还包括第一序列号字段，第一标签结束比特块还包括第一结束序列号字段，所述第一序列号字段的值和所述第一结束序列号字段的值相同。当然，标签结束比特块也可以不包括第一结束序列号字段，仅仅指示比特块的类型也是可以的。
如表1所示，为本发明实施例提供的一种标签比特块，该比特块采用的是图2中第8行的O码比特块，其中D1和D2字节为连接标识字段(connection identity,Conn_id)，D3字节包括首标签字段(First Tag,Ft)和长度字段(Length,Len)，O码设置为4，C4和C5字节为序列号字段(Sequence Num)，C6和C7字节为预留字段(reserved)。当然也可以采用其它编码方式的比特块来生成标签比特块，其中长度字段是必选的，其它字段可选，本发明实施例对此不作限定。
Figure PCTCN2018112599-appb-000001
表1
如表2所示，为本发明实施例提供的一种标签结束比特块，该比特块采用的是图2中第8行的O码比特块，其中D1和D2字节为连接标识字段(connection identity,Conn_id)，D3字节为预留字段(reserved)，O码设置为5，C4和C5字节为序列号字段(Sequence Num)，C6和C7字节为预留字段(reserved)。当然也可以采用其它编码方式的比特块来生成标签结束比特块，其中可以仅包含一个字段用来指示属于一个标签结束比特块，其它字段可选，本发明实施例对此不作限定。
Figure PCTCN2018112599-appb-000002
表2
如图4所示，为本发明实施例提供的一种比特块的处理方法，该方法可以应用于交换节点103和104。
S401，通过第一端口依次接收第一标签比特块和N个数据比特块，所述第一标签比特块包括第一长度字段；
S402，通过第二端口依次发送所述第一标签比特块和N个数据比特块中的M个数据比特块；
S403，通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，所述第二标签比特块包括第二长度字段，所述第一长度字段的值比所述第二长度字段的值大M，其中M，N和L均为大于等于0的整数。
本发明实施例中，接收的第一标签比特块和N个数据比特块组成一个比特块段，交换节点可以将该比特块段进行截断，生成至少两个比特块段，即生成第一标签比特块和N个数据比特块中的M个数据比特块组成的第一比特块段，还生成了第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块组成的第二比特块段，第一标签比特块包括的第一长度字段的值比第二标签比特块包括的第二长度字段的值大M，因此接收节点或其它有需要的节点，例如重组节点可以根据长度字段的值将比特块段进行合并。
可选地，交换节点将接收的比特块段进行了截断，即可以抢占发送其他业务的流量，例如可以发送关键流量，此外一个比特块段可以被多个关键流量连续抢占多次，或间断抢占多次，本发明实施例对此不作限定。在一些实施例中，可以基于其它需求对比特块段进行截断，例如用户设定特定节点的比特块段的长度限制等。
可选地，可以获取第三标签比特块和O个数据比特块，其中O为大于等于0的整数，在通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块之后，可以通过第二端口依次发送所述第三标签比特块和所述O个数据比特块，即进行了抢占发送。其中获取第三标签比特块和O个数据比特块的具体实现可以是通过第三端口依次接收所述第三标签比特块和所述O个数据比特块，可以是本节点根据接收到的以太网帧生成所述第三标签比特块和所述O个数据比特块，或者是根据本地业务生成所述第三标签比特块和所述O个数据比特块，当然也可以采用其它技术生成所述第三标签比特块和所述O个数据比特块，本发明实施例对此不作限定。在一些实施例中，抢占发送的其它业务的流量也可以不包括标签比特块，仅包括数据比特块。
如图5A所示，为本发明实施例提供的一种比特块段抢占示意图，包括上下两部分，上面部分为接收的比特块段，下面部分为发送的比特块段。接收的比特块段中包括第一标签比特块，长度字段的值为11，接收的比特块段在发送时分为两个标签比特块段，第一个标签比特块段包括第一标签比特块和随后的4个数据比特块，第二个标签比特块段包括第二标签比特块和随后的7个数据比特块，中间被1个第三标签比特块和2个灰色的数据比特块抢占发送。可以知道的是，接收的比特块段在发送时也可以分为更多个标签比特块段，发送出去的两个标签比特块段在后续节点的处理中，可以被再次截断，当然也可以被组合恢复成一个比特块段。
因为进行了抢占，所以步骤S402发送的数据比特块的数量可能为0，步骤S403发送的数据比特块的数量也可能为0，步骤接收的数据比特块的数量也可能为0。此外，对于抢占发送的第三标签比特块和O个数据比特块，因为其也可能被更高优先级的业务抢占，因此O的数量也可能为0。
通过步骤401接收第一标签比特块和N个数据比特块后，交换节点需要确定通过哪个端口进行转发，接收的第一标签比特块中还可以包括一个第一连接标识字段，可以根据该字段查找获得第二端口，可以通过查表或者其他方式获得第二端口。第一连接标识字段可以通过表1中的D1和D2字节的连接标识字段来实现。如果第一标签比特块中不包括连接标识字段时，可以通过预先配置或网管配置等方式获得第二端口。
为了使得通过第二端口转发的至少两个比特块段能够顺利到达接收节点，步骤403中的第二标签比特块也可以包括第二连接标识字段，第一连接标识字段的值和第二连接标识字段的值相同。
可选地，第一标签比特块还可以包括第一序列号字段，所述第二标签比特块还可以包括第二序列号字段，所述第一序列号字段的值和所述第二序列号字段的值相同。
第一标签比特块还可以包括第一序列号开始字段，用于标识所述N个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块；第二标签比特块还可以包括第二序列号开始字段，用于标识所述L个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块。
可选地，通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块之前，可以存储第一标签比特块，或者可以存储第一长度字段的值。在通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块时，每发送一个数据比特块，将存储的第一长度字段的值减一。
当需要通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块时，可以直接使用存储的第一长度字段的值生成第二标签比特块。
如果存储的第一长度字段的值为零，则可以释放存储的第一长度字段。
如果通过第一端口依次接收第一标签比特块，N个数据比特块和第一标签结束比特块；在通过第二端口发送所述第一标签结束比特块后，可以释放存储的第一长度字段。
如图5B所示，为本发明实施例提供的一种比特块的处理方法，该方法可以应用于交换节点103和104。
S501，收到一个尽力服务的流量的比特块段，根据标签比特块中的连接标识字段查找得到出端口；
S502，存储该比特块段的标签比特块。
S503，发送存储的标签比特块。
S504，判断是否有抢占信号，如果有抢占信号，则执行步骤S505，如果没有抢占信号，则执行步骤S507。即如果有抢占信号，则停止发送该尽力服务的流量，转而发送抢占关键流量，抢占关键流量发送完毕后，继续从步骤S503开始执行。
S505，发送抢占信号。
S506，抢占信号发送结束，然后执行步骤S503。
S507，发送当前数据比特块，并将存储的标签比特块中的长度字段减1。
S508，判断下一个比特块是否为标签结束比特块，如果是标签结束比特块，则执行步骤S511，如果不是标签结束比特块，则执行步骤S509。
S509，判断存储标签比特块中的长度字段是否为0，如果是0，则执行步骤S510，如果不是0，则执行步骤S504。
S510，释放存储的标签比特块，发送结束。
S511，发送标签结束比特块。
如图6所示，为本发明实施例提供的一种比特块的处理方法，该方法可以应用于接收节点105和106。
S601，依次接收第一标签比特块和N个数据比特块，所述第一标签比特块包括第一长度字段；
S602，依次接收第二标签比特块和M个数据比特块，所述第二标签比特块包括第二长度字段；
S603，如果所述第一长度字段的值比所述第二长度字段的值大N，将所述N个数据比特块和所述M个数据比特块进行关联处理。
可选地，第一标签比特块还可以包括第一序列号字段，第二标签比特块还可以包括第二序列号字段，如果所述第一长度字段的值比所述第二长度字段的值大N且所述第一序列号字段的值和所述第二序列号字段的值相同，将所述N个数据比特块和所述M个数据比特块进行关联处理。
第一标签比特块还可以包括第一序列号开始字段，第二标签比特块还可以包括第二序列号开始字段，根据所述第一序列号开始字段的值和所述第二序列号开始字段的值确定所述序列号对应的第1个数据比特块。
如果第二长度字段的值为M，则确定所述M个数据比特块中的最后一个数据比特块为所述序列号对应的最后1个数据比特块。
如果依次接收第二标签比特块，M个数据比特块和第二标签结束比特块，则可以根据所述第二标签结束比特块确定所述M个数据比特块中的最后一个数据比特块为所述序列号对应的最后1个数据比特块。
在一个具体的实施例中，收到一个比特块段后，可以首先根据标签比特块的序列号字段的值判断之前是否收到过具有相同的序列号的比特块；
如果之前没有收到过具有相同的序列号的比特块，则根据标签比特块的序列号开始字段的值判断该比特块段是否包括该序列号对应的第1个数据比特块，如果包括，则可以将该比特块段上送，例如可以上送到以太网层进行上层处理，如果不包括，则可以暂时存储该比特块段。
如果之前收到过具有相同的序列号的比特块，则根据标签比特块的长度字段的值判断该比特块段是否为期望收到的比特块段，如果该比特块段是期望收到的比特块段，则可以将该比特块段上送，如果该比特块段不是期望收到的比特块段，则可以暂时存储该比特块段。
在一个具体的实施例中，也可以将一个序列号的所有数据比特块接收后，将属于相同的序列号的多个比特块段重组成一个比特段，或者仅将数据比特块重组，然后再上送到以太网层进行处理。
本发明实施例中，在物理层，以比特块为单位，在一系列的比特块加入了一个标签比特块组成了一个比特块段，通过标签比特块的长度字段，可以将比特块段截断为多个比特块段，每个比特块段均包括一个标签比特块。此外通过标签比特块的连接标识字段可以对比特块段进行路由；通过标签比特块的序列号字段可以识别比特块段中的数据比特块对应的序列号；通过标签比特块的序列号开始字段可以识别比特块段中的数据比特块是否包含序列号对应的第1个数据比特块，从而可以在接收节点进行比特块的快速重组。
本发明实施例中，对于标签比特块中的长度字段的值是确定的比特块的数量，或者仅仅是一个预设值，交换节点并不关心，处理方式也可以相同，此外交换节点也并不需要进 行排序，处理方式十分简单。
如图7所示，为本发明实施例提供一种比特块处理节点的结构示意图，包括：
接收模块701，用于通过第一端口依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段；
发送模块702，用于通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块，还用于通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，第二标签比特块包括第二长度字段，第一长度字段的值比第二长度字段的值大M，其中M，N和L均为大于等于0的整数。
在一种可能的设计中，接收模块701还用于获取第三标签比特块和O个数据比特块，其中O为大于等于0的整数；发送模块在通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块之前还用于通过第二端口依次发送第三标签比特块和O个数据比特块。
在一种可能的设计中，第一标签比特块还包括第一连接标识字段，节点还包括处理模块，处理模块用于根据第一连接标识字段查找获得第二端口。
在一种可能的设计中，第二标签比特块还包括第二连接标识字段，第一连接标识字段的值和第二连接标识字段的值相同。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第二标签比特块还包括第二序列号字段，第一序列号字段的值和第二序列号字段的值相同。
在一种可能的设计中，第一标签比特块还包括第一序列号开始字段，用于标识N个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块；第二标签比特块还包括第二序列号开始字段，用于标识L个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块。
在一种可能的设计中，节点还包括处理模块，发送模块通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块时，处理模块用于存储第一长度字段的值；每发送一个数据比特块，将存储的第一长度字段的值减一。
在一种可能的设计中，第二长度字段的值为处理模块存储的第一长度字段的值。
在一种可能的设计中，如果存储的第一长度字段的值为零，则释放存储的第一长度字段。
在一种可能的设计中，接收模块用于通过第一端口依次接收第一标签比特块，N个数据比特块和第一标签结束比特块；
发送模块通过第二端口发送第一标签结束比特块后，处理模块还用于释放存储的第一长度字段。
如图8所示，为本发明实施例提供一种比特块处理节点的结构示意图，包括：
处理模块801，用于生成第一标签比特块，第一标签比特块包括第一长度字段，还用于获取待发送的N个数据比特块；
发送模块802，用于通过第一端口依次发送第一标签比特块和N个数据比特块。
在一种可能的设计中，第一长度字段的值为N。
在一种可能的设计中，第一长度字段的值为第一预设值，通过第一端口依次发送第一标签比特块和N个数据比特块包括：通过第一端口依次发送第一标签比特块，N个数据比 特块和第一标签结束比特块。
在一种可能的设计中，第一标签比特块还包括第一连接标识字段，第一序列号字段，第一序列号开始字段中的至少一个，第一连接标识字段用于对第一标签比特块和N个数据比特块进行路由，第一序列号字段用于标识N个数据比特块对应的序列号，第一序列号开始字段用于标识N个数据比特块中的第1个数据比特块是否为序列号对应的第1个数据比特块。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第一标签结束比特块还包括第一结束序列号字段，第一序列号字段的值和第一结束序列号字段的值相同。
如图9所示，为本发明实施例提供一种比特块处理节点的结构示意图，包括：
接收模块901，用于依次接收第一标签比特块和N个数据比特块，第一标签比特块包括第一长度字段，还用于依次接收第二标签比特块和M个数据比特块，第二标签比特块包括第二长度字段；
处理模块902，用于如果第一长度字段的值比第二长度字段的值大N，将N个数据比特块和M个数据比特块进行关联处理。
在一种可能的设计中，第一标签比特块还包括第一序列号字段，第二标签比特块还包括第二序列号字段，处理模块具体用于如果第一长度字段的值比第二长度字段的值大N且第一序列号字段的值和第二序列号字段的值相同，将N个数据比特块和M个数据比特块进行关联处理。
在一种可能的设计中，第一标签比特块还包括第一序列号开始字段，第二标签比特块还包括第二序列号开始字段，处理模块还用于根据第一序列号开始字段的值和第二序列号开始字段的值确定序列号对应的第1个数据比特块。
在一种可能的设计中，处理模块还用于如果第二长度字段的值为M，则确定M个数据比特块中的最后一个数据比特块为序列号对应的最后1个数据比特块。
在一种可能的设计中，接收机具体用于依次接收第二标签比特块，M个数据比特块和第二标签结束比特块，处理模块还用于根据第二标签结束比特块确定M个数据比特块中的最后一个数据比特块为序列号对应的最后1个数据比特块。
上述装置用于执行前述方法实施例，其实现原理和技术效果类似，在此不再赘述。此外，上述实施例中的发送模块可以为发送机，接收模块可以为接收机，处理模块可以为处理器，在此不再赘述。
需要说明的是，应理解以上设备的各个模块的划分仅仅是一种逻辑功能的划分，实际实现时可以全部或部分集成到一个物理实体上，也可以物理上分开。且这些模块可以全部以软件通过处理元件调用的形式实现；也可以全部以硬件的形式实现；还可以部分模块通过处理元件调用软件的形式实现，部分模块通过硬件的形式实现。例如，发送模块可以为单独设立的元件，也可以集成在上述设备的某一个芯片中实现，此外，也可以以程序代码的形式存储于上述设备的存储器中，由上述设备的某一个处理元件调用并执行以上确定模块的功能。其它模块的实现与之类似。此外这些模块全部或部分可以集成在一起，也可以独立实现。这里所述的处理元件可以是一种集成电路，具有信号的处理能力。在实现过程中，上述方法的各步骤或以上各个模块可以通过处理器元件中的硬件的集成逻辑电路或者软件形式的指令完成。
例如，以上这些模块可以是被配置成实施以上方法的一个或多个集成电路，例如：一个或多个特定集成电路(Application Specific Integrated Circuit，ASIC)，或，一个或多个微处理器(Digital Signal Processor，DSP)，或，一个或者多个现场可编程门阵列(Field Programmable Gate Array，FPGA)等。再如，当以上某个模块通过处理元件调度程序代码的形式实现时，该处理元件可以是通用处理器，例如中央处理器(Central Processing Unit，CPU)或其它可以调用程序代码的处理器。再如，这些模块可以集成在一起，以片上系统(system-on-a-chip，SOC)的形式实现。
应理解，本文中涉及的第一、第二、第三、第四以及各种数字编号仅为描述方便进行的区分，并不用来限制本发明实施例的范围。
图10为本发明实施例提供的比特块处理装置的结构示意图，该装置可以是图1中的节点101,102,103,104,105或106。如图10所示，该装置包括：存储器10和处理器11。
存储器10可以是独立的物理单元，与处理器11可以通过总线连接。存储器10、处理器11也可以集成在一起，通过硬件实现等。
存储器10用于存储实现以上方法实施例，或者图7-图9所示实施例各个模块的程序，处理器11调用该程序，执行以上方法实施例的操作。
可选地，当上述实施例的业务数据传输方法中的部分或全部通过软件实现时，上述装置也可以只包括处理器。用于存储程序的存储器位于接入设备之外，处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的程序。
处理器可以是中央处理器(Central Processing Unit，CPU)，网络处理器(Network Processor，NP)或者CPU和NP的组合。
处理器还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(Application-specific Integrated Circuit，ASIC)，可编程逻辑器件(Programmable Logic Device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)，现场可编程逻辑门阵列(Field-programmable Gate Array，FPGA)，通用阵列逻辑(Generic Array Logic，GAL)或其任意组合。
存储器可以包括易失性存储器(volatile memory)，例如随机存取存储器(Random-Access Memory，RAM)；存储器也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(Hard Disk Drive，HDD)或固态硬盘(Solid-State Drive，SSD)；存储器还可以包括上述种类的存储器的组合。
本发明实施例还提供了一种计算机存储介质，存储有计算机程序，该计算机程序用于执行上述实施例提供的业务数据传输方法。
本发明实施例还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述实施例提供的业务数据传输方法。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和 /或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。

Claims (40)

  1. 一种比特块的处理方法，其特征在于，包括：
    通过第一端口依次接收第一标签比特块和N个数据比特块，所述第一标签比特块包括第一长度字段；
    通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块；
    通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，所述第二标签比特块包括第二长度字段，所述第一长度字段的值比所述第二长度字段的值大M，其中M，N和L均为大于等于0的整数。
  2. 如权利要求1所述的方法，其特征在于，所述通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块之前还包括：
    获取第三标签比特块和O个数据比特块，其中O为大于等于0的整数；
    通过第二端口依次发送所述第三标签比特块和所述O个数据比特块。
  3. 如权利要求1所述的方法，其特征在于，所述第一标签比特块还包括第一连接标识字段，所述通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块之前还包括：
    根据所述第一连接标识字段查找获得第二端口。
  4. 如权利要求3所述的方法，其特征在于，所述第二标签比特块还包括第二连接标识字段，所述第一连接标识字段的值和所述第二连接标识字段的值相同。
  5. 如权利要求1所述的方法，其特征在于，所述第一标签比特块还包括第一序列号字段，所述第二标签比特块还包括第二序列号字段，所述第一序列号字段的值和所述第二序列号字段的值相同。
  6. 如权利要求5所述的方法，其特征在于，所述第一标签比特块还包括第一序列号开始字段，用于标识所述N个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块；所述第二标签比特块还包括第二序列号开始字段，用于标识所述L个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块。
  7. 如权利要求1所述的方法，其特征在于，所述通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块时还包括：
    存储第一长度字段的值；
    每发送一个数据比特块，将存储的第一长度字段的值减一。
  8. 如权利要求7所述的方法，其特征在于，所述第二长度字段的值为存储的第一长度字段的值。
  9. 如权利要求7所述的方法，其特征在于,如果存储的第一长度字段的值为零，则释放存储的第一长度字段。
  10. 如权利要求7所述的方法，其特征在于，通过第一端口依次接收第一标签比特块和N个数据比特块包括：通过第一端口依次接收第一标签比特块，N个数据比特块和第一标签结束比特块；
    通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块后还包括：
    通过第二端口发送所述第一标签结束比特块后，释放存储的第一长度字段。
  11. 一种比特块的处理方法，其特征在于，包括:
    生成第一标签比特块，所述第一标签比特块包括第一长度字段；
    获取待发送的N个数据比特块；
    通过第一端口依次发送所述第一标签比特块和所述N个数据比特块。
  12. 如权利要求11所述的方法，其特征在于，所述第一长度字段的值为N，其中N为大于等于0的整数。
  13. 如权利要求11所述的方法，其特征在于，所述第一长度字段的值为第一预设值，所述通过第一端口依次发送所述第一标签比特块和所述N个数据比特块包括：通过第一端口依次发送所述第一标签比特块，所述N个数据比特块和第一标签结束比特块。
  14. 如权利要求11所述的方法，其特征在于，所述第一标签比特块还包括第一连接标识字段，第一序列号字段，第一序列号开始字段中的至少一个，所述第一连接标识字段用于对所述第一标签比特块和所述N个数据比特块进行路由，所述第一序列号字段用于标识所述N个数据比特块对应的序列号，所述第一序列号开始字段用于标识所述N个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块。
  15. 如权利要求13所述的方法，其特征在于，所述所述第一标签比特块还包括第一序列号字段，所述第一标签结束比特块还包括第一结束序列号字段，所述第一序列号字段的值和所述第一结束序列号字段的值相同。
  16. 一种比特块的处理方法，其特征在于，包括:
    依次接收第一标签比特块和N个数据比特块，所述第一标签比特块包括第一长度字段；
    依次接收第二标签比特块和M个数据比特块，所述第二标签比特块包括第二长度字段；
    如果所述第一长度字段的值比所述第二长度字段的值大N，将所述N个数据比特块和所述M个数据比特块进行关联处理，其中N和M为大于等于0的整数。
  17. 如权利要求16所述的方法，其特征在于，所述第一标签比特块还包括第一序列号字段，所述第二标签比特块还包括第二序列号字段，所述如果所述第一长度字段的值比所述第二长度字段的值大N，将所述N个数据比特块和所述M个数据比特块进行关联处理包括：
    如果所述第一长度字段的值比所述第二长度字段的值大N且所述第一序列号字段的值和所述第二序列号字段的值相同，将所述N个数据比特块和所述M个数据比特块进行关联处理。
  18. 如权利要求17所述的方法，其特征在于，所述第一标签比特块还包括第一序列号开始字段，所述第二标签比特块还包括第二序列号开始字段，还包括：
    根据所述第一序列号开始字段的值和所述第二序列号开始字段的值确定所述序列号对应的第1个数据比特块。
  19. 如权利要求18所述的方法，其特征在于，还包括：
    如果第二长度字段的值为M，则确定所述M个数据比特块中的最后一个数据比特块为所述序列号对应的最后1个数据比特块。
  20. 如权利要求18所述的方法，其特征在于，所述依次接收第二标签比特块和M个数据比特块包括：
    依次接收第二标签比特块，M个数据比特块和第二标签结束比特块，根据所述第二标签结束比特块确定所述M个数据比特块中的最后一个数据比特块为所述序列号对应的最后1个数据比特块。
  21. 一种比特块的处理节点，其特征在于，包括：
    接收模块，用于通过第一端口依次接收第一标签比特块和N个数据比特块，所述第一标签比特块包括第一长度字段；
    发送模块，用于通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块，还用于通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块，所述第二标签比特块包括第二长度字段，所述第一长度字段的值比所述第二长度字段的值大M，其中M，N和L均为大于等于0的整数。
  22. 如权利要求21所述的节点，其特征在于，所述接收模块还用于获取第三标签比特块和O个数据比特块，其中O为大于等于0的整数；
    所述发送模块在通过第二端口依次发送第二标签比特块和N个数据比特块中剩余的N-M个数据比特块中的L个数据比特块之前还用于通过第二端口依次发送所述第三标签比特块和所述O个数据比特块。
  23. 如权利要求21所述的节点，其特征在于，所述第一标签比特块还包括第一连接标识字段，所述节点还包括处理模块，所述处理模块用于根据所述第一连接标识字段查找获得第二端口。
  24. 如权利要求23所述的节点，其特征在于，所述第二标签比特块还包括第二连接标识字段，所述第一连接标识字段的值和所述第二连接标识字段的值相同。
  25. 如权利要求21所述的节点，其特征在于，所述第一标签比特块还包括第一序列号字段，所述第二标签比特块还包括第二序列号字段，所述第一序列号字段的值和所述第二序列号字段的值相同。
  26. 如权利要求25所述的节点，其特征在于，所述第一标签比特块还包括第一序列号开始字段，用于标识所述N个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块；所述第二标签比特块还包括第二序列号开始字段，用于标识所述L个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块。
  27. 如权利要求21所述的节点，其特征在于，所述节点还包括处理模块，所述发送模块通过第二端口依次发送第一标签比特块和N个数据比特块中的M个数据比特块时，所述处理模块用于存储第一长度字段的值；每发送一个数据比特块，将存储的第一长度字段的值减一。
  28. 如权利要求27所述的节点，其特征在于，所述第二长度字段的值为所述处理模块存储的第一长度字段的值。
  29. 如权利要求27所述的节点，其特征在于,如果存储的第一长度字段的值为零，则释放存储的第一长度字段。
  30. 如权利要求27所述的节点，其特征在于，所述接收模块用于通过第一端口依次接收第一标签比特块，N个数据比特块和第一标签结束比特块；
    所述发送模块通过第二端口发送所述第一标签结束比特块后，所述处理模块还用于释放存储的第一长度字段。
  31. 一种比特块的处理节点，其特征在于，包括:
    处理模块，用于生成第一标签比特块，所述第一标签比特块包括第一长度字段，还用于获取待发送的N个数据比特块，其中N为大于等于0的整数；
    发送模块，用于通过第一端口依次发送所述第一标签比特块和所述N个数据比特块。
  32. 如权利要求31所述的节点，其特征在于，所述第一长度字段的值为N。
  33. 如权利要求31所述的节点，其特征在于，所述第一长度字段的值为第一预设值，所述通过第一端口依次发送所述第一标签比特块和所述N个数据比特块包括：通过第一端口依次发送所述第一标签比特块，所述N个数据比特块和第一标签结束比特块。
  34. 如权利要求31所述的节点，其特征在于，所述第一标签比特块还包括第一连接标识字段，第一序列号字段，第一序列号开始字段中的至少一个，所述第一连接标识字段用于对所述第一标签比特块和所述N个数据比特块进行路由，所述第一序列号字段用于标识所述N个数据比特块对应的序列号，所述第一序列号开始字段用于标识所述N个数据比特块中的第1个数据比特块是否为所述序列号对应的第1个数据比特块。
  35. 如权利要求33所述的节点，其特征在于，所述所述第一标签比特块还包括第一序列号字段，所述第一标签结束比特块还包括第一结束序列号字段，所述第一序列号字段的值和所述第一结束序列号字段的值相同。
  36. 一种比特块的处理节点，其特征在于，包括:
    接收模块，用于依次接收第一标签比特块和N个数据比特块，所述第一标签比特块包括第一长度字段，还用于依次接收第二标签比特块和M个数据比特块，所述第二标签比特块包括第二长度字段；
    处理模块，用于如果所述第一长度字段的值比所述第二长度字段的值大N，将所述N个数据比特块和所述M个数据比特块进行关联处理，其中N和M为大于等于0的整数。
  37. 如权利要求36所述的节点，其特征在于，所述第一标签比特块还包括第一序列号字段，所述第二标签比特块还包括第二序列号字段，所述处理模块具体用于如果所述第一长度字段的值比所述第二长度字段的值大N且所述第一序列号字段的值和所述第二序列号字段的值相同，将所述N个数据比特块和所述M个数据比特块进行关联处理。
  38. 如权利要求37所述的节点，其特征在于，所述第一标签比特块还包括第一序列号开始字段，所述第二标签比特块还包括第二序列号开始字段，所述处理模块还用于根据所述第一序列号开始字段的值和所述第二序列号开始字段的值确定所述序列号对应的第1个数据比特块。
  39. 如权利要求38所述的节点，其特征在于，所述处理模块还用于如果第二长度字段的值为M，则确定所述M个数据比特块中的最后一个数据比特块为所述序列号对应的最后1个数据比特块。
  40. 如权利要求38所述的节点，其特征在于，所述接收机具体用于依次接收第二标签比特块，M个数据比特块和第二标签结束比特块，所述处理模块还用于根据所述第二标签结束比特块确定所述M个数据比特块中的最后一个数据比特块为所述序列号对应的最后1个数据比特块。
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