WO2019085605A1 - 一种基于cpu+gpu+fpga架构的自动光学检测系统 - Google Patents

一种基于cpu+gpu+fpga架构的自动光学检测系统 Download PDF

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WO2019085605A1
WO2019085605A1 PCT/CN2018/102154 CN2018102154W WO2019085605A1 WO 2019085605 A1 WO2019085605 A1 WO 2019085605A1 CN 2018102154 W CN2018102154 W CN 2018102154W WO 2019085605 A1 WO2019085605 A1 WO 2019085605A1
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image
data
module
unit
camera
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PCT/CN2018/102154
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English (en)
French (fr)
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沈亚非
欧昌东
邓标华
汪舟
梅林海
董文忠
唐文天
李波
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武汉精测电子集团股份有限公司
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Priority to KR1020207015690A priority Critical patent/KR102243499B1/ko
Priority to JP2020540625A priority patent/JP6867555B2/ja
Publication of WO2019085605A1 publication Critical patent/WO2019085605A1/zh
Priority to US16/862,610 priority patent/US11080840B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/01—Arrangements or apparatus for facilitating the optical investigation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0428—Safety, monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/0014—Image feed-back for automatic industrial control, e.g. robot with camera
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2656—Instrumentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30168—Image quality inspection

Definitions

  • the invention belongs to the technical field of automatic optical detection, and particularly relates to an automatic optical detection system based on CPU+GPU+FPGA architecture.
  • AOI automatic optical inspection involves optical systems, mechanism control systems, point screen control systems, software control systems, image processing systems, and more.
  • the traditional AOI equipment is based on the image acquisition card + PC, the acquisition card and PC are many, the cost is high, the coordination is difficult, the system stability is poor, the expansion is inconvenient, it is difficult to be used for large-scale module detection; and each TFT-LCD AOI automatic optics Testing equipment manufacturers have only one or two areas of technology accumulation and research and development capabilities, basically can not fully cover all areas, can only build a complete AOI automatic optical test system through 2-3 products together, the equipment The overall responsibility is usually to master the unit based on machine vision image processing algorithms.
  • the dot screen signal and the image acquisition processing unit are two different system schemes, and another main control unit is required to cooperatively control the dot screen signal and the image acquisition processing unit, thereby bringing about an overall system efficiency degradation; each image acquisition
  • the card can only be connected to a 1-way camera.
  • most image acquisition cards use the PCIE interface to communicate with the PC.
  • Such a PC can support a limited number of acquisition cards at the same time, and will use a large number of image acquisition cards and increase the number of PCs.
  • the PCs are coordinated and controlled by the master PC. The complexity and system stability are difficult to control, and the PC image processing and processing capabilities are poor.
  • the existing AOI detection equipment scheme, dot screen signal, light source and AOI detection The system is an independent system unit, which requires the total control unit to coordinate the control point screen signal generation, light source, AOI detection system image acquisition and processing, the control process is complex, and the tact time is long.
  • the object of the present invention is to solve the deficiencies of the above background art, and provide an automatic system based on CPU+GPU+FPGA architecture capable of supporting multiple cameras and realizing integration of dot screen signal generation, light source control, image acquisition and image calculation processing.
  • Optical inspection system Optical inspection system.
  • an automatic optical detection system based on CPU + GPU + FPGA architecture, comprising an image storage unit, an image calculation unit and an image acquisition unit, the image storage unit having a first communication interface and a second communication An interface, the image computing unit has a first fiber interface, a second fiber interface, a third fiber interface, and a fourth fiber interface, the image acquisition unit having a third communication interface and a camera interface;
  • the image storage unit sends configuration parameters and test commands to the image computing unit through the first communication interface, and receives test results sent by the image calculation unit, and receives data of the collection unit through the second communication interface;
  • the image computing unit receives the configuration parameters and test commands sent by the image storage unit through the first fiber interface, sends the test result to the image storage unit, receives the data of the image acquisition unit through the second fiber interface, and sends the configuration parameters to the image acquisition unit.
  • the test command controls the dot screen signal generation through the third fiber interface, and controls the IO light source through the fourth fiber interface;
  • the image acquisition unit outputs image data, receives configuration parameters, and test commands through the third communication interface, receives camera data through the camera interface, and transmits configuration parameters and test commands to the camera.
  • the image storage unit includes
  • the main control PC is configured to perform parameter configuration, output configuration parameters and test commands through human-computer interaction, and is used for receiving the test result of the FPGA storage platform and reporting the result;
  • the FPGA storage platform is configured to receive image acquisition unit data, perform lossless compression on the received data, and send the data to the disk array for receiving the test result of the image calculation unit and outputting the output configuration parameter to the image acquisition unit. For performing image data retrieval based on stored data;
  • a disk array for storing data.
  • the FPGA storage platform includes
  • a data interaction module configured to receive configuration parameters sent by the master PC, and used to feed back the test result of the received image calculation unit to the master PC;
  • An image data receiving/transmitting module configured to receive the image capturing unit data and output the data to the data lossless compression module, configured to receive the configuration parameter and send the configuration parameter to the image collecting module, and receive the test result of the image computing unit;
  • a data lossless compression module configured to perform lossless compression on the received data and store the data to the disk array through the disk storage management unit;
  • a data disk storage management module that manages the storage and reading functions of the disk array.
  • the FPGA storage platform further includes
  • An image retrieval management module for controlling a read disk array
  • the image data exchange control module has a fourth communication interface for communicating with an external server to implement image retrieval data exchange and data communication control.
  • the image computing unit includes an FPGA computing platform and a computing PC, and the first fiber interface, the second fiber interface, the third fiber interface, and the fourth fiber interface are all disposed on an FPGA computing platform, and the FPGA computing platform further has A fifth fiber interface coupled to the computing PC and an expansion interface that implements cascading expansion of the FPGA computing platform.
  • the FPGA computing platform includes a central controller, an image processing accelerator, a data summary sending module, and DDR memory.
  • the central controller is configured to send a control command to the computing PC and the image processing accelerator respectively according to the set instruction;
  • the calculating PC is configured to read part of the image data from the DDR memory according to the control command, perform a calculation process, and send the processing result to the data summary sending module;
  • the image processing accelerator is configured to read a partial image from the DDR memory according to the control command, perform a calculation process, and send the calculation result to the data summary sending module;
  • the data summary sending module is configured to summarize the processing results of the computing PC and the image processing accelerator to form a final test result and send the result to the image storage module;
  • the DDR memory is used to store image data and test results that need to be processed.
  • the FPGA computing platform further includes a receiving configuration parameter module, a data receiving/parameter configuration module, a signal expansion module, and an IO control module.
  • the receiving configuration parameter module is configured to receive configuration parameters and test commands and send them to a central controller
  • the central controller is further configured to send the received configuration parameters to the data receiving/parameter configuration module, and respectively distribute the received test commands to the data receiving/parameter configuration module, the IO control module, and the signal expansion module;
  • the data receiving/parameter configuration module is configured to receive image data of the image capturing unit and store it in the DDR memory, and send the received configuration parameter and the test command to the image collecting unit;
  • the signal expansion module is configured to implement point screen signal generation and control according to the test command
  • the IO control module is configured to implement IO light source control according to a test command.
  • the image acquisition unit includes
  • a protocol parsing module configured to receive camera data, and parse the camera data according to a protocol to send valid image data to a DDR physical memory for storage as original image data
  • DDR physical memory for storing raw image data and processing image data
  • the image quality evaluation and pre-processing module is configured to read original image data from the DDR physical memory according to the control unit control command, perform image pre-processing on the original image data, and send the pre-processed data to the DDR physical memory for storage. Processing image data;
  • the main control unit sends a control command to the image quality evaluation and pre-processing and reading DDR data format conversion according to the set instruction;
  • the DDR data format conversion module is configured to read the original image data and/or process the image data from the DDR physical memory according to the configuration command of the main control unit, and send the data to the high-speed interface data packet module.
  • a high speed interface data encapsulation module for transmitting the received raw image data and/or processed image data to an image storage unit and an image computing unit.
  • the image acquisition unit further includes an automatic alignment focus exposure module and a camera configuration module.
  • the high speed interface data encapsulation module is further configured to receive configuration parameters and test commands and send the same to the main control unit;
  • the protocol parsing module is further configured to receive camera data, and parse the camera data according to a protocol to send valid image data to the DDR physical memory; and send the camera configuration parameter to the camera;
  • the image quality evaluation and pre-processing module is further configured to perform image collection quality evaluation on the camera data according to the control unit control command, and send the quality evaluation result to the main control unit.
  • the main control unit is further configured to send the received configuration parameter, the test command, and the quality evaluation result to the automatic registration focus exposure module;
  • the automatic alignment focus exposure module is configured to implement camera parameter setting according to configuration parameters and quality evaluation results, and send configuration parameters and test commands to the camera configuration module;
  • the camera configuration module is configured to send camera configuration parameters and test commands to the protocol parsing module.
  • the protocol parsing module includes a Camera link protocol parsing module, a Gige Vision protocol parsing module, and a CLHS protocol parsing module, where the interfacing interface includes multiple Camera Link interfaces, multiple Gige interfaces, and multiple CLHS interfaces.
  • the plurality of Camera Link interfaces are connected to the Camera link protocol parsing module, and the plurality of Gige interfaces are connected to the Gige Vision protocol parsing module, and the plurality of CLHS interfaces are connected to the CLHS protocol parsing module.
  • the invention has the beneficial effects that the image storage unit, the image calculation unit and the image acquisition unit cooperate with each other, and can realize image storage and retrieval, and has the functions of human-computer interaction, main control and display, processing result analysis and reporting; It can realize dot screen signal generation and signal expansion, light source, image acquisition, camera integrated control function, short tact time, communication and data interaction between each unit through optical fiber, and data transmission speed is fast; image calculation unit can also pass level
  • the connection method expands the computing processing capability; and the image computing unit uses the CPU+GPU+FPGA architecture to fully expand the CPU+GPU unit to enhance the processing power of the GPU; and the FPGA as the central controller, the processing data needs to be distributed to different GPU processing units.
  • the FPGA itself realizes the image acceleration processor, fully utilizes the parallel processing capability of the FPGA, and performs image processing segmentation and FPGA+ GPUs to coordinate processing, which effectively improves the image processing computing capability;
  • Camera interface support automatic alignment, focus, automatic exposure parameter setting An image quality evaluation, image preprocessing functions.
  • the whole system architecture has the advantages of simple structure, low cost, good stability, good coordination ability and strong computing and processing capability.
  • Figure 1 is a schematic block diagram of the present invention.
  • FIG. 2 is a flow chart of the tuning machine of the present invention.
  • Figure 3 is a flow chart of the test of the present invention.
  • FIG. 4 is a schematic block diagram of an image storage unit of the present invention.
  • Figure 5 is a flow chart showing the operation of the image storage unit of the present invention.
  • Figure 6 is a schematic block diagram of an image calculation unit of the present invention.
  • Figure 7 is a flow chart showing the operation of the image computing unit of the present invention.
  • Figure 8 is a schematic block diagram of an image acquisition unit of the present invention.
  • Figure 9 is a flow chart showing the operation of the image acquisition unit of the present invention.
  • 1-image storage unit 1.1-master PC, 1.2-FPGA storage platform; 1.3-disk array; 1.4-data interaction module; 1.5-image data receiving/transmitting module; 1.6-data lossless compression module; Data disk storage management module; 1.8-image retrieval management module; 1.9-image data exchange control module;
  • 2-image computing unit 2.1-FPGA computing platform; 2.2-computing PC; 2.3-data receiving/parameter configuration module; 2.4-write DDR data format conversion module; 2.5-signal expansion module; 2.6-IO control module; Controller; 2.8-image processing accelerator; 2.9-receive configuration parameter module; 2.10-configuration register; 2.11-data summary transmission module; 2.12-read DDR data format conversion module; 2.13-data transmission module; 2.14-AXI bus interconnection module 2.14 ; 2.15-DDR controller 2.15; 2.16-DDR memory 2.16;
  • 3-Image acquisition unit 3.1-Protocol resolution module; 3.2-Valid data extraction module; 3.3-Write DDR data format conversion module; 3.4-AXI bus interconnection; 3.5-DDR control module; 3.6-DDR physical memory; 3.7-Image quality Evaluation and pre-processing module; 3.8-master unit; 3.9-register configuration module; 3.10-read DDR data format conversion module; 3.11-high-speed interface data packet module; 3.12-automatic alignment focus exposure module; 3.13-camera configuration module;
  • the present invention includes an image storage unit 1, an image calculation unit 2, and an image acquisition unit 3 having a first communication interface and a second communication interface, the image calculation unit 2 having a a fiber optic interface, a second fiber optic interface, a third fiber optic interface, and a fourth fiber optic interface, the image acquisition unit 3 having a third communication interface and a camera interface;
  • the image storage unit 1 performs parameter configuration by human-computer interaction, and sends a configuration parameter and a test command to the image computing unit through the first communication interface, and the test result sent by the image computing unit is reported and reported, and the configuration parameters sent by the image storage unit include Pattern list, dot screen parameters, camera parameters, detection parameters, etc.; receiving data of the acquisition unit through the second communication interface and storing;
  • the image computing unit 2 receives configuration parameters and test commands sent by the image storage unit through the first fiber interface, sends test results to the image storage unit, receives data of the image acquisition unit through the second fiber interface, and sends configuration parameters to the image collection unit. And the test command, through the third fiber optic interface control point screen signal generation (control signal expansion unit 7 lighting module), through the fourth fiber optic interface control IO light source (related light source 9 [backlight and side light]);
  • the image acquisition unit outputs image data, receives configuration parameters, and test commands through the third communication interface, receives camera data through the camera interface, and transmits configuration parameters and test commands to the camera.
  • the tuning refers to the adjustment of the working distance of the camera, the focusing parameter, the exposure parameter, the gain parameter, the white balance parameter, the brightness of the backlight, etc.
  • the tuning process is as shown in FIG. 2:
  • Device initialization including camera and lens parameters, Panel parameters, Panel transmittance parameters, backlight parameters, etc.
  • This automatic tuning device and solution usually takes only a few minutes to complete the camera adjustment work; the traditional adjustment method usually takes hours or even days; and through this automatic adjustment device scheme, the image consistency is higher. .
  • the main control unit sets a one-button test start command.
  • Image pre-processing including brightness correction, vignetting correction, ROI area extraction and cutting, background suppression, moiré removal, grayscale stretching, and the like.
  • the detection result is reported, and the report includes the data storage part sent to the customer MCMQ system and the timely display part is sent to the customer CIM 6 system through the PLC 5.
  • the image storage unit 1 includes a host PC 1.1, an FPGA storage platform (an FPGA-based storage processing board) 1.2, and a disk array 1.3, an FPGA storage platform 1.3, and a data interaction module 1.4.
  • the image data receiving/transmitting module 1.6, the data lossless compression module 1.6, the data disk storage management module 1.7, the image retrieval management module 1.8, and the image data exchange control module 1.9, the image storage unit is responsible for image storage and retrieval, and also has both Human-computer interaction, master control and display, processing result analysis and reporting.
  • the main control PC and the FPGA storage platform communicate and interact with each other through the PCIE x8 mode.
  • the first communication interface and the second communication interface are both located on the FPGA storage platform, that is, between the FPGA storage platform and the image computing unit and the image acquisition unit. Data communication and interaction are carried out through optical fibers, and the optical fiber connection network is used to facilitate image storage and retrieval.
  • the storage unit is mainly used to store the original image data and/or the processed image data sent by the image acquisition unit, and the processing result data of the image calculation unit is not saved to the local server, and is directly uploaded to the system of the client MCMQ 4.
  • the images saved to the local are used for subsequent data analysis and retrieval, and have high requirements on storage space, storage and retrieval efficiency.
  • each module of the image storage unit is as follows:
  • the main control PC 1.1 is used for parameter configuration, output configuration parameters and test commands through human-computer interaction, and is used for receiving the test result of the FPGA storage platform 1.2 and reporting it, for connecting with the customer MCMQ, reporting the defect data, reporting the defect image, The test result XML data is reported.
  • Disk array 1.3 for storing data.
  • the data interaction module 1.4 is configured to receive configuration parameters sent by the master PC for feeding back the test result of the received image calculation unit to the master PC.
  • the image data receiving/transmitting module 1.5 is configured to receive the image capturing unit data and output the data to the data lossless compression module, and receive the configuration parameters and send the configuration parameters to the image capturing module for receiving the test result of the image computing unit.
  • the data lossless compression module 1.6 is configured to perform lossless compression on the received data and store it to the disk array through the disk storage management unit; the lossless compression of the data can greatly improve the storage space utilization and the pressure on the retrieval bandwidth.
  • the data disk storage management module 1.7 is used to manage the storage and reading functions of the disk array.
  • the image retrieval management module 1.8 is configured to control the read disk array.
  • the image data exchange control module 1.9 has a fourth communication interface for communicating with an external server, and implementing image retrieval data exchange and data communication control under an external server command.
  • the search is performed, the required image data is read out locally, and transmitted to the search server through the optical fiber exchange network, and the search server can perform non-destructive decompression on the image.
  • the data processing flow of the image storage unit is as follows:
  • the compressed image data is stored
  • the image computing unit 2 includes an FPGA computing platform 2.1 (an FPGA-based computing processing board) and a computing PC 2.2, a first fiber interface, a second fiber interface, a third fiber interface, and a fourth
  • the optical fiber interfaces are all disposed on the FPGA computing platform, and the FPGA computing platform further has a fifth optical fiber interface connected to the computing PC, and an extended interface for implementing cascade expansion of the FPGA computing platform.
  • the FPGA computing platform 2.1 includes a data receiving/parameter configuration module 2.3, a write DDR data format conversion module 2.4, a signal expansion module 2.5, an IO control module 2.6, a central controller 2.7, an image processing accelerator 2.8, a receiving configuration parameter module 2.9, and a configuration.
  • Register 2.10, data summary transmission module 2.11, data transmission module 2.13, AXI bus interconnection module 2.14, DDR controller 2.15 and DDR memory 2.16, computing PC 2.2 consists of CPU and GPU.
  • the image calculation unit also has dot screen signal generation and signal expansion, and integrated light source control functions.
  • An FPGA computing platform consists of 12 QSFP+ fiber interfaces, which can connect up to 6 computing PCs. Multiple computing PCs can be switched between 16 KVM 8 devices, FPGA computing platform and computing PC, image storage unit, and image acquisition.
  • the unit, the signal expansion unit 7, and the IO light source control unit communicate and exchange data through the optical fiber mode; the FPGA computing platform supports the expansion and expansion of the calculation processing capability through the fiber interface cascading expansion.
  • the FPGA computing platform forms the CPU+GPU+FPGA computing architecture together with the CPU and GPU that make up the computing PC. According to the image data stream mode, Pipeline structure processing, FPGA image pre-processing, and CPU+GPU image post-processing, the calculation speed is fully improved.
  • each module of the image calculation unit is as follows:
  • the calculation PC 2.2 is configured to read part of the image data from the DDR memory according to the control command, perform calculation processing, and send the processing result to the data summary sending module.
  • the data receiving/parameter configuration module 2.3 is configured to receive image data of the image capturing unit, and convert the image into a DDR memory after being converted by the DDR data format conversion module, and configured to send the received configuration parameter and the test command to the image collecting unit.
  • the DDR data format conversion module 2.4 is written to perform format conversion on the received data.
  • the signal expansion module 2.5 is configured to implement point screen signal generation and control according to the test command.
  • the IO control module 2.6 is configured to implement IO light source control according to the test command.
  • the central controller 2.7 is configured to send a control command to the computing PC and the image processing accelerator respectively according to the set instruction; for transmitting the received configuration parameter to the data receiving/parameter configuration module, and respectively distributing the received test command to the data receiving /Parameter configuration module, IO control module and signal expansion module.
  • the image processing accelerator 2.8 is configured to read a partial image from the DDR memory according to the control command for calculation processing, and send the calculation result to the data summary sending module.
  • the receiving configuration parameter module 2.9 is configured to receive configuration parameters and test commands of the image storage unit and send the same to the central controller.
  • Configuration register 2.10 completes the relevant register configuration.
  • the data summary sending module 2.11 is configured to summarize the processing results of the computing PC and the image processing accelerator to form a final test result and send the result to the image storage module.
  • the DDR data format conversion module 2.12 is read to perform format conversion on the received data.
  • a data sending module 2.13 configured to send part of data that needs to be processed to a computing PC
  • the AXI bus interconnect module 2.14 is used to read and write image data to the DDR memory under the control of the central controller.
  • DDR controller 2.15 used to control read and write image data and test results.
  • DDR memory 2.16 used to store image data and test results that need to be processed.
  • the image acquisition unit 3 includes a protocol parsing module 3.1, an effective data extracting module 3.2, a write DDR data format conversion module 3.3, an AXI bus interconnect 3.4, a DDR control module 3.5, a DDR physical memory 3.6, and an image.
  • the image acquisition sheet supports multiple camera interfaces, supports multiple cameras, supports automatic alignment, focus, automatic exposure parameter setting, image quality evaluation, and better image consistency [according to backlight brightness, panel transmittance, lens distortion) ⁇ Automatically adjust exposure time, gain, brightness correction and vignetting correction to improve image quality and consistency; can perform image pre-processing, including: brightness correction, vignetting correction, ROI area extraction and cutting, background suppression, moiré removal , grayscale stretching, etc.
  • each module of the image acquisition unit 3 is as follows:
  • the protocol parsing module 3.1 is configured to receive camera data, and parse the camera data according to the protocol, and validate the image data according to the protocol, send the DDR data format conversion module to the DDR physical memory, and store the data as the original image data; After receiving the camera data, and parsing the camera data according to the protocol, the valid image data is sent to the DDR physical memory through the effective data extraction module and the write DDR data format conversion module, and the parsed image data includes 24 bit image data and a frame control signal.
  • VS/HS/DE used to send camera configuration parameters to the camera.
  • the protocol parsing module includes a Camera link protocol parsing module, a Gige Vision protocol parsing module, and a CLHS protocol parsing module.
  • the mating interface includes a plurality of Camera Link interfaces, a plurality of Gige interfaces, and a plurality of CLHS interfaces, and the plurality of Camera Link interfaces and The Camera link protocol parsing module is connected, and the plurality of Gige interfaces are connected to the Gige Vision protocol parsing module, and the plurality of CLHS interfaces are connected to the CLHS protocol parsing module.
  • the effective data extraction module 3.2 extracts valid image data portions according to the configuration parameters of the main control unit; the 24-bit data is extracted from the protocol analysis module, and valid data bits are extracted according to the configuration of the main control unit.
  • Write DDR data format conversion module 3.3 save the received data to physical memory; format the camera's valid image data, and convert it to AXI4 write Memory data format.
  • AXI bus interconnect 3.4 is used to read and write image data to DDR physical memory under the control of the main control unit.
  • the DDR control module 3.5 is used to control reading and writing image data.
  • DDR physical memory 3.6 for storing raw image data and processing image data.
  • the image quality evaluation and pre-processing module 3.7 is configured to read original image data from the DDR physical memory according to the CPU control command, perform image pre-processing on the original image data, and send the pre-processed data to the DDR physical memory for processing.
  • Image data, pre-processing includes vignetting correction, brightness correction, AOI area automatic extraction and cutting, perspective transformation, morie pattern removal and other image processing functions; for quality evaluation of camera data according to the control unit control command, quality assessment results Send to the master unit.
  • the main control unit 3.8 sends a control command to the image quality evaluation and pre-processing and read DDR data format conversion according to the set instruction; and is configured to send the received configuration parameter, the test command and the quality evaluation result to the automatic registration focus exposure module.
  • Register Configuration Module 3.9 completes the relevant register configuration.
  • the DDR data format conversion module 3.10 is configured to read raw image data and/or process image data from the DDR physical memory according to the configuration command of the main control unit and send the data to the high speed interface data packet module.
  • the high speed interface data packet module 3.11 is configured to send the received raw image data and/or processed image data to the image storage unit and the image computing unit. Used to receive configuration parameters and test commands and send them to the main control unit.
  • the automatic registration focus exposure module 3.12 is configured to implement camera parameter setting according to configuration parameters and quality evaluation results, and send configuration parameters and test commands to the camera configuration module.
  • the camera configuration module 3.13 is configured to send camera configuration parameters and test commands to the protocol parsing module.
  • the data processing flow of the image computing unit is as follows:
  • the command includes the tuning command and the image capturing command; the receiving tuning command will enter the tuning mode, and when the image capturing command is received, the normal capturing mode will be entered.
  • adjustment mode here the adjustment refers to the camera working distance, focus parameters, exposure parameters, gain parameters, white balance parameters, backlight brightness and other adjustments:
  • test standard If the test standard is not met, adjust the working distance of the camera, that is, the alignment, according to the configuration parameters, and then adjust the camera's focal length, exposure time, gain and white balance; then repeat the above actions until the image is satisfied. Testing standards.
  • image pre-processing including image correction such as brightness correction, vignetting correction, AOI area extraction and cutting, background suppression, moiré removal, etc.;
  • the invention has the ability to manage data acquisition and processing of up to 20 cameras at the same time, greatly optimizes the system complexity of the high-resolution and large-size panel automatic detection system, the Tact Time of the compressed image acquisition, and the stability of the system; It integrates camera automatic alignment, focusing, image quality detection and integration, automatically realizes camera image quality management, and greatly facilitates on-site adjustment; through the self-developed image quality evaluation system, it can quickly realize line body adjustment and image consistency. Good; based on FPGA image storage management system, improve image storage efficiency and facilitate image retrieval; provide necessary source images for machine learning and intelligent detection.

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Abstract

一种基于CPU+GPU+FPGA架构的自动光学检测系统。它包括图像存储单元（1）、图像计算单元（2）和图像采集单元（3），图像存储单元（1）具有第一通信接口和第二通信接口，图像计算单元（2）具有第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口，图像采集单元（3）具有第三通信接口和相机接口；图像计算单元（2）通过第一光纤接口接收图像存储单元（1）发送的配置参数及测试命令、向图像存储单元（1）发送测试结果，通过第二光纤接口接收图像采集单元（3）的数据、向图像采集单元（3）发送配置参数及测试命令，通过第三光纤接口控制点屏信号生成，通过第四光纤接口控制IO光源。该系统具有结构简单、成本低、稳定性好，协调能力好，计算处理能力强等优点。

Description

一种基于CPU+GPU+FPGA架构的自动光学检测系统 技术领域
本发明属于自动光学检测技术领域，具体涉及一种基于CPU+GPU+FPGA架构的自动光学检测系统。
背景技术
AOI自动光学检测，涉及到光学系统、机构控制系统、点屏控制系统、软体控制系统、图像处理系统等。传统AOI设备基于图像采集卡+PC机的方式，采集卡、PC多，成本高、协调困难，系统稳定性差，扩展不方便，难以用于大尺寸模组检测；并且各TFT-LCD AOI自动光学检测设备厂商仅在一两个领域有技术积累和研发能力，基本上不能完全覆盖全部领域，只能通过2-3家的产品组合在一起搭建成一套完整的AOI自动光学测试系统，该设备的总体负责通常为掌握基于机器视觉图像处理算法的单位。因此，他们均采用的是基于计算机网络的分散控制方案，利用局域网将各设备单元简单集成在一起，如为了满足产线检测TT(Tact Time，每片检测的节拍时间)，均采用多台计算机阵列分担负荷进行运算处理，数量一般都会达到10多台。因此，这种简单的系统集成方案不仅系统复杂、成本高，而且稳定性差、效率低，实际达不到预期效果，且几乎不具备可扩展性，已越来越不受面板生产厂商的青睐。
现有技术中点屏信号与图像采集处理单元是两个不同系统方案，需要有另外的主控单元，协同控制点屏信号与图像采集处理单元，这样带来整体系统效率下降；每张图像采集卡只能连接1路相机，目前大部分图像采集卡，使用PCIE接口方式与PC通信，这样一台PC能同时支持的采集卡数量有限，会使用大量的图像采集卡及增加PC的数量，不同的PC之间通过主控PC协调与控制，复杂度、系统稳定性都较难以控制，且各PC图像计算处理能力都较差；同时现有AOI检测设备方案，点屏信号、光源与AOI检测系统之间均是独立的系统单元，需要总控制单元协调控制点屏信号生成、光源、AOI检测系统图像采集与处理，控制过程复杂，节拍时间长。
发明内容
本发明的目的就是为了解决上述背景技术存在的不足，提供一种能够支持多相机，并实现点屏信号生成、光源控制、图像采集、图像计算处理一体化的基于CPU+GPU+FPGA架构的自动光学检测系统。
本发明采用的技术方案是：一种基于CPU+GPU+FPGA架构的自动光学检测系统，包括图像存储单元、图像计算单元和图像采集单元，所述图像存储单元具有第一通信接口和第二通信接口，所述图像计算单元具有第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口，所述图像采集单元具有第三通信接口和相机接口；
所述图像存储单元通过第一通信接口向图像计算单元下发配置参数和测试命令、接收图像计算单元发送的测试结果，通过第二通信接口接收采集单元的数据；
所述图像计算单元通过第一光纤接口接收图像存储单元发送的配置参数及测试命令、向图像存储单元发送测试结果，通过第二光纤接口接收图像采集单元的数据、向图像采集单元发送配置参数及测试命令，通过第三光纤接口控制点屏信号生成，通过第四光纤接口控制IO光源；
所述图像采集单元通过第三通信接口输出图像数据、接收配置参数及测试命令，通过相机接口接收相机数据、向相机发送配置参数和测试命令。
进一步地，所述图像存储单元包括
主控PC，用于通过人机交互进行参数配置、输出配置参数及测试命令，用于接收FPGA存储平台的测试结果并上报；
FPGA存储平台，用于接收图像采集单元数据、将接收的数据进行无损压缩后发送至磁盘阵列，用于接收图像计算单元的测试结果并输出，用于将接收的配置参数输出至图像采集单元，用于根据存储的数据进行图像数据检索；
磁盘阵列，用于存储数据。
进一步地，所述FPGA存储平台包括
数据交互模块，用于接收主控PC发送的配置参数，用于将接收的图像计算单元的测试结果反馈至主控PC；
图像数据接收/发送模块，用于接收图像采集单元数据并输出至数据无损压缩模块， 用于接收配置参数并发送至图像采集模块，用于接收图像计算单元的测试结果；
数据无损压缩模块，用于对接收的数据进行无损压缩后经磁盘存储管理单元存储至磁盘阵列；
数据磁盘存储管理模块，用于管理磁盘阵列的存储、读取功能。
进一步地，所述FPGA存储平台还包括
图像检索管理模块，用于控制读磁盘阵列；
图像数据交换控制模块，具有第四通信接口，用于与外部服务器通信，实现图像检索数据交换、数据通信控制。
进一步地，所述图像计算单元包括FPGA计算平台和计算PC，所述第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口均设置于FPGA计算平台上，FPGA计算平台还具有与所述计算PC连接的第五光纤接口，以及实现FPGA计算平台级联扩展的扩展接口。
进一步地，所述FPGA计算平台包括中央控制器、图像处理加速器、数据汇总发送模块和DDR内存，
所述中央控制器用于根据设定的指令分别向计算PC和图像处理加速器发送控制命令；
所述计算PC，用于根据控制命令从DDR内存中读取部分图像数据进行计算处理并将处理结果发送至数据汇总发送模块；
所述图像处理加速器用于根据控制命令从DDR内存中读取部分图像进行计算处理，将计算结果发送至数据汇总发送模块；
所述数据汇总发送模块用于将计算PC和图像处理加速器的处理结果进行汇总形成最终的测试结果发送至图像存储模块；
所述DDR内存用于存储需要处理的图像数据及测试结果。
进一步地，所述FPGA计算平台还包括接收配置参数模块、数据接收/参数配置模块、信号扩展模块和IO控制模块，
所述接收配置参数模块用于接收配置参数及测试命令并发送至中央控制器；
所述中央控制器还用于将接收的配置参数发送至数据接收/参数配置模块，将接收的 测试命令分别分配至数据接收/参数配置模块、IO控制模块和信号扩展模块；
所述数据接收/参数配置模块用于接收图像采集单元图像数据并存储至DDR内存中，将接收的配置参数及测试命令发送至图像采集单元；
所述信号扩展模块用于根据测试命令实现点屏信号生成与控制；
所述IO控制模块用于根据测试命令实现IO光源控制。
进一步地，所述图像采集单元包括
协议解析模块，用于接收相机数据，并将相机数据按照协议解析出有效的图像数据发送至DDR物理内存中存储为原始图像数据；
DDR物理内存，用于存储原始图像数据和处理图像数据；
图像质量评估与前处理模块，用于根据主控单元控制命令从DDR物理内存中读取原始图像数据，对原始图像数据进行图像前处理，将前处理后的数据发送至DDR物理内存中存储为处理图像数据；
主控单元，根据设定的指令向图像质量评估与前处理和读DDR数据格式转换发送控制命令；
读DDR数据格式转换模块，用于根据主控单元的配置命令从DDR物理内存中读取原始图像数据和/或处理图像数据发送至高速接口数据封包模块，
高速接口数据封包模块，用于将接收的原始图像数据和/或处理图像数据发送至图像存储单元和图像计算单元。
进一步地，所述图像采集单元还包括自动对位对焦曝光模块和相机配置模块，
所述高速接口数据封包模块还用于接收配置参数及测试命令并发送至主控单元；
所述协议解析模块还用于接收相机数据，并将相机数据按照协议解析出有效的图像数据发送至DDR物理内存；将相机配置参数发送至相机；
所述图像质量评估与前处理模块还用于根据主控单元控制命令对相机数据进行图像采集质量评估，将质量评估结果发送至主控单元，
所述主控单元还用于将接收的配置参数、测试命令及质量评估结果发送至自动对位对焦曝光模块；
所述自动对位对焦曝光模块，用于根据配置参数及质量评估结果实现相机参数设置， 并将配置参数及测试命令发送至相机配置模块；
所述相机配置模块，用于将相机配置参数及测试命令发送至协议解析模块。
更进一步地，所述协议解析模块包括Camera link协议解析模块、Gige Vision协议解析模块和CLHS协议解析模块，所述相接接口包括多个Camera Link接口、多个Gige接口和多个CLHS接口，所述多个Camera Link接口与Camera link协议解析模块连接，所述多个Gige接口与Gige Vision协议解析模块连接，所述多个CLHS接口与CLHS协议解析模块连接。
本发明的有益效果是：图像存储单元、图像计算单元、图像采集单元之间相互配合，能实现图像的存储与检索、兼具人机交互、主控与显示、处理结果分析与上报等功能；能够实现点屏信号生成与信号扩展、光源、图像采集、相机一体化控制功能，节拍时间短，各单元之间通过光纤方式进行通信与数据交互，数据传输速度快；图像计算单元还可以通过级联方式扩展计算处理能力；且图像计算单元使用CPU+GPU+FPGA架构，充分扩展CPU+GPU单元，增强GPU的处理能力；以FPGA为中心控制器，将需要处理数据分发到不同的GPU处理单元中，分布式处理架构；同时FPGA本身实现图像加速处理器，充分利用FPGA的并行处理能力，将图像处理分割与FPGA+各GPU之间进行协调处理，有效提高了图像处理计算能力；能支持多种相机接口，支持自动对位、对焦、自动进行曝光参数设置，具有图像质量评估、图像前处理等功能。整个系统架构具有结构简单、成本低、稳定性好，协调能力好，计算处理能力强等优点。
附图说明
图1为本发明的原理框图。
图2为本发明调机的流程图。
图3为本发明测试的流程图。
图4为本发明图像存储单元的原理框图。
图5为本发明图像存储单元工作的流程图。
图6为本发明图像计算单元的原理框图。
图7为本发明图像计算单元工作的流程图。
图8为本发明图像采集单元的原理框图。
图9为本发明图像采集单元工作的流程图。
图中：1-图像存储单元；1.1-主控PC、1.2-FPGA存储平台；1.3-磁盘阵列；1.4-数据交互模块；1.5-图像数据接收/发送模块；1.6-数据无损压缩模块；1.7-数据磁盘存储管理模块；1.8-图像检索管理模块；1.9-图像数据交换控制模块；
2-图像计算单元；2.1-FPGA计算平台；2.2-计算PC；2.3-数据接收/参数配置模块；2.4-写DDR数据格式转换模块；2.5-信号扩展模块；2.6-IO控制模块；2.7-中央控制器；2.8-图像处理加速器；2.9-接收配置参数模块；2.10-配置寄存器；2.11-数据汇总发送模块；2.12-读DDR数据格式转换模块；2.13-数据发送模块；2.14-AXI总线互联模块2.14；2.15-DDR控制器2.15；2.16-DDR内存2.16；
3-图像采集单元；3.1-协议解析模块；3.2-有效数据提取模块；3.3-写DDR数据格式转换模块；3.4-AXI总线互联；3.5-DDR控制模块；3.6-DDR物理内存；3.7-图像质量评估与前处理模块；3.8-主控单元；3.9-寄存器配置模块；3.10-读DDR数据格式转换模块；3.11-高速接口数据封包模块；3.12-自动对位对焦曝光模块；3.13-相机配置模块；
4-客户MCMQ；5-PLC；6-CIM；7-信号扩展单元；8-16口KVM；9-光源。
具体实施方式
下面结合附图和具体实施例对本发明作进一步的详细说明，便于清楚地了解本发明，但它们不对本发明构成限定。
如图1所示，本发明包括包括图像存储单元1、图像计算单元2和图像采集单元3，所述图像存储单元1具有第一通信接口和第二通信接口，所述图像计算单元2具有第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口，所述图像采集单元3具有第三通信接口和相机接口；
所述图像存储单元1通过人机交互进行参数配置，通过第一通信接口向图像计算单元下发配置参数和测试命令、接收图像计算单元发送的测试结果并上报，图像存储单元发送的配置参数包括Pattern列表、点屏参数、相机参数、检测参数等；通过第二通信接口接收采集单元的数据并存储；
所述图像计算单元2通过第一光纤接口接收图像存储单元发送的配置参数及测试命令、向图像存储单元发送测试结果，通过第二光纤接口接收图像采集单元的数据、向图像采集单元发送配置参数及测试命令，通过第三光纤接口控制点屏信号生成(控制信号扩展单元7点亮模组)，通过第四光纤接口控制IO光源(相关光源9【背光及侧光】)；
所述图像采集单元通过第三通信接口输出图像数据、接收配置参数及测试命令，通过相机接口接收相机数据、向相机发送配置参数和测试命令。
本发明的系统工作时，先进行调机，调机是指相机工作距离、对焦参数、曝光参数、增益参数、白平衡参数、背光源亮度等调节，调机流程如图2所示：
1)设备初始化，包括相机及镜头参数、Panel参数、Panel透光率参数、背光源参数等。
2)人机界面发送调机开始命令。
3)将点屏Pattern设置为白画面。
4)点屏信号生成及点亮模组。
5)触发相机取图。
6)对所取图进行质量评估，评估维度包括：亮度、清晰度及锐利度、有效区域大小、摩尔纹等。
7)若所取图像符合检测标准，测结束调机。
8)若所取图像不符合检测标准，则根据评估的结果调整相机的工作距离、对焦参数及背光源亮度。
9)重复步骤5到8的过程，直到图像满足要求为止。
此自动调机设备与方案，通常只需要数分钟时间，即可完成相机调节工作；而传统调节方式通常需要数小时甚至数天的时间；并且通过此自动调节设备方案，图像的一致性更高。
调机完成后，再进行测试，测试流程如图3所示：
1)设备初始化。
2)主控单元设置一键测试开始命令。
3)根据设置的Pattern顺序，生成点屏信号及完成切图命令。
4)根据设置的光源顺序，通过IO控制端，点亮不同的光源信号。
5)设置相机的曝光、增益及白平衡参数。
6)触发相机。
7)接收相机数据。
8)图像前处理，包括亮度矫正、暗角矫正、ROI区域提取与切割、背景抑制、摩尔纹去除、灰度拉伸等。
9)进行图像后处理，缺陷检测、识别、判断。
10)检测结果上报，上报包括资料存储部分发送到客户MCMQ系统以及及时显示部分通过PLC 5发送到客户CIM 6系统。
11)原始图像压缩与存储。
上述方案中，如图4所示，图像存储单1元包括主控PC 1.1、FPGA存储平台(基于FPGA的存储处理板卡)1.2和磁盘阵列1.3，FPGA存储平台1.3、包括数据交互模块1.4、图像数据接收/发送模块1.6、数据无损压缩模块1.6、数据磁盘存储管理模块1.7、图像检索管理模块1.8和图像数据交换控制模块1.9，图像存储单元一方面负责图像的存储与检索，另外还兼具人机交互、主控与显示、处理结果分析与上报等功能。主控PC与FPGA存储平台之间通过PCIE x8方式进行数据通信与交互，第一通信接口和第二通信接口均设在于FPGA存储平台上，即FPGA存储平台与图像计算单元、图像采集单元之间均通过光纤进行数据通信与交互，使用光纤连接布网方式，方便图像存储与检索。
存储单元主要用于存储图像采集单元发送的原始图像数据和/或处理图像数据，图像计算单元的处理结果数据不保存到本地服务器，会直接上传到客户MCMQ 4的系统。保存到本地的图片用于后续的数据分析与检索，对存储空间、存储及检索效率有较高要求。
图像存储单元的各模块的功能如下：
主控PC 1.1，用于通过人机交互进行参数配置、输出配置参数及测试命令，用于接收FPGA存储平台1.2的测试结果并上报，用于与客户MCMQ连接，缺陷资料上报、缺陷图片上报、检测结果XML资料上报。
磁盘阵列1.3，用于存储数据。
数据交互模块1.4，用于接收主控PC发送的配置参数，用于将接收的图像计算单元的测试结果反馈至主控PC。
图像数据接收/发送模块1.5，用于接收图像采集单元数据并输出至数据无损压缩模块，用于接收配置参数并发送至图像采集模块，用于接收图像计算单元的测试结果。
数据无损压缩模块1.6，用于对接收的数据进行无损压缩后经磁盘存储管理单元存储至磁盘阵列；对数据进行无损压缩后可以极大地提升存储空间利用率以及对检索带宽需求压力。
数据磁盘存储管理模块1.7，用于管理磁盘阵列的存储、读取功能。
图像检索管理模块1.8，用于控制读磁盘阵列。
图像数据交换控制模块1.9，具有第四通信接口，用于与外部服务器通信，在外部服务器命令下实现图像检索数据交换、数据通信控制。检索时先从本地读出需要的图像数据，通过光纤交换网络传输到检索服务器端，检索服务器端对图像进行无损解压后方可以使用。
如图5所示，图像存储单元的数据处理流程如下：
1)、初始化；
2)、参数配置；
3)、发送一键测试命令；
4)、等待接收原始图像数据；
5)、对原始图像数据进行压缩；
6)、压缩后的图像数据进行存储；
7)、等待接收检测结果；
8)、检测结果分析并上报；
9)、结束。
上述方案中，如图6所示，图像计算单元2包括FPGA计算平台2.1(基于FPGA的计算处理板卡)和计算PC 2.2，第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口均设置于FPGA计算平台上，FPGA计算平台还具有与所述计算PC连接的第 五光纤接口，以及实现FPGA计算平台级联扩展的扩展接口。所述FPGA计算平台2.1包括数据接收/参数配置模块2.3、写DDR数据格式转换模块2.4、信号扩展模块2.5、IO控制模块2.6、中央控制器2.7、图像处理加速器2.8、接收配置参数模块2.9、配置寄存器2.10、数据汇总发送模块2.11、数据发送模块2.13、AXI总线互联模块2.14、DDR控制器2.15和DDR内存2.16，计算PC 2.2由CPU和GPU组成。图像计算单元除了图像计算加速之外，其中的FPGA计算平台还具备点屏信号生成与信号扩展、光源一体化控制功能。一个FPGA计算平台包括12个QSFP+光纤接口，可以连接多达6台计算PC，多台计算PC之间可以通过16口KVM 8设备进行切换控制，FPGA计算平台与计算PC、图像存储单元、图像采集单元、信号扩展单元7、IO光源控制单元之间均通过光纤方式进行通信与数据交互；FPGA计算平台支持通过光纤接口级联扩展，扩展计算处理能力。FPGA计算平台与构成计算PC的CPU和GPU一起形成CPU+GPU+FPGA计算架构，根据图像数据流方式，Pipeline结构处理，FPGA图像前处理，CPU+GPU图像后处理，充分提升计算速度。
图像计算单元的各模块的功能如下：
计算PC 2.2，用于根据控制命令从DDR内存中读取部分图像数据进行计算处理并将处理结果发送至数据汇总发送模块。
数据接收/参数配置模块2.3，用于接收图像采集单元图像数据，经写DDR数据格式转换模块转换后存储至DDR内存中，用于将接收的配置参数及测试命令发送至图像采集单元。
写DDR数据格式转换模块2.4，对接收的数据进行格式转换。
信号扩展模块2.5，用于根据测试命令实现点屏信号生成与控制。
IO控制模块2.6，用于根据测试命令实现IO光源控制。
中央控制器2.7，用于根据设定的指令分别向计算PC和图像处理加速器发送控制命令；用于将接收的配置参数发送至数据接收/参数配置模块，将接收的测试命令分别分配至数据接收/参数配置模块、IO控制模块和信号扩展模块。
图像处理加速器2.8，用于根据控制命令从DDR内存中读取部分图像进行计算处理，将计算结果发送至数据汇总发送模块。
接收配置参数模块2.9，用于接收图像存储单元的配置参数及测试命令并发送至中央控制器。
配置寄存器2.10，完成相关寄存器配置。
数据汇总发送模块2.11，用于将计算PC和图像处理加速器的处理结果进行汇总形成最终的测试结果发送至图像存储模块。
读DDR数据格式转换模块2.12，对接收的数据进行格式转换。
数据发送模块2.13，用于将部分需要计算处理的数据发送至计算PC；
AXI总线互联模块2.14，用于在中央控制器的控制下向DDR内存读写图像数据。
DDR控制器2.15，用于控制读写图像数据及测试结果。
DDR内存2.16，用于存储需要处理的图像数据及测试结果。
如图7所示，图像计算单元的数据处理流程如下：
1)、初始化；
2)、接收一键测试命令；
3)、判断当前处理pattern数是否与设置pattern总数相等，若相等，则认为处理一键测试完成，结束流程；
4)、若一键测试未完成，根据pattern列表，点亮被测模组；
5)、根据pattern配置列表，点亮光源；
6)、触发相机进行图像采集；
7)、接收采集单元图像数据，同时返回进行触发次数判断；
8)、对收到数据进行处理，判断被测模组是否有缺陷，及判断缺陷等级；
9)、检测结果上报；
上述方案中，如图8所示，图像采集单元3包括协议解析模块3.1、有效数据提取模块3.2、写DDR数据格式转换模块3.3、AXI总线互联3.4、DDR控制模块3.5、DDR物理内存3.6、图像质量评估与前处理模块3.7、主控单元3.8、寄存器配置模块3.9、读DDR数据格式转换模块3.10、高速接口数据封包模块3.11、自动对位对焦曝光模块3.12和相机配置模块3.13，图像采集单元使用Xilinx的SOC芯片作为主控单元，支持8个 Cameralink接口、8个Gige接口、4个CLHS接口；与FPGA计算平台之间通过光纤接口方式连接，通过自定制协议进行数据通信和交互。图像采集单支持多种相机接口，支持多只相机，支持自动对位、对焦、自动进行曝光参数设置，能进行图像质量评估，图像一致性更佳【根据背光亮度、面板透光率、镜头畸变】自动调整曝光时间，增益，通过亮度矫正及暗角矫正，提升图像质量及一致性；能进行图像前处理，包括：亮度矫正、暗角矫正、ROI区域提取与切割、背景抑制、摩尔纹去除、灰度拉伸等。
图像采集单元3的各模块的功能如下：
协议解析模块3.1，用于接收相机数据，并将相机数据按照协议解析出有效的图像数据，经有效数据提取模块、写DDR数据格式转换模块后发送至DDR物理内存中存储为原始图像数据；用于接收相机数据，并将相机数据按照协议解析出有效的图像数据经有效数据提取模块、写DDR数据格式转换模块后发送至DDR物理内存，解析之后的图像数据包括24bit的图像数据以及帧控制信号VS/HS/DE；用于将相机配置参数发送至相机。
协议解析模块包括Camera link协议解析模块、Gige Vision协议解析模块和CLHS协议解析模块，上述相接接口包括多个Camera Link接口、多个Gige接口和多个CLHS接口，所述多个Camera Link接口与Camera link协议解析模块连接，所述多个Gige接口与Gige Vision协议解析模块连接，所述多个CLHS接口与CLHS协议解析模块连接。
有效数据提取模块3.2，根据主控单元配置参数，提取有效的图像数据部分；从协议解析模块出来是24bit数据，根据主控单元配置，提取有效的数据位。
写DDR数据格式转换模块3.3，将接收数据保存到物理内存中；将相机有效的图像数据进行格式转换，转换为AXI4写Memory的数据格式。
AXI总线互联3.4，用于在主控单元的控制下向DDR物理内存读写图像数据。
DDR控制模块3.5，用于控制读写图像数据。
DDR物理内存3.6，用于存储原始图像数据和处理图像数据。
图像质量评估与前处理模块3.7，用于根据CPU控制命令从DDR物理内存中读取原始图像数据，对原始图像数据进行图像前处理，将前处理后的数据发送至DDR物理内存中存储为处理图像数据，前处理包括暗角矫正、亮度矫正、AOI区域自动提取与切割、透视变换、morie纹去除等图像处理功能；用于根据主控单元控制命令对相机数据 进行质量评估，将质量评估结果发送至主控单元。
主控单元3.8，根据设定的指令向图像质量评估与前处理和读DDR数据格式转换发送控制命令；用于将接收的配置参数、测试命令及质量评估结果发送至自动对位对焦曝光模块。
寄存器配置模块3.9，完成相关寄存器配置。
读DDR数据格式转换模块3.10，用于根据主控单元的配置命令从DDR物理内存中读取原始图像数据和/或处理图像数据发送至高速接口数据封包模块。
高速接口数据封包模块3.11，用于将接收的原始图像数据和/或处理图像数据发送至图像存储单元和图像计算单元。用于接收配置参数及测试命令并发送至主控单元。
自动对位对焦曝光模块3.12，用于根据配置参数及质量评估结果实现相机参数设置，并将配置参数及测试命令发送至相机配置模块。
相机配置模块3.13，用于将相机配置参数及测试命令发送至协议解析模块。
如图9所示，图像计算单元的数据处理流程如下：
1)、上电初始化：设备初始化、相机初始化设置、对位对焦电机等的初始化。
2)、接收主控单元配置参数：包括相机参数、Panel尺寸及分辨率及透光率信息、背光亮度、工作模式等参数。
3)、接收主控单元触发命令：命令包括调机命令及取像命令；接收调机命令则会进入到调机模式，接收到取像命令，则会进入到正常的取像模式。
4)、调机模式，此处调机是指相机工作距离、对焦参数、曝光参数、增益参数、白平衡参数、背光源亮度等调节：
a)首先触发相机拍图；
b)对所得图像进行评估，判断是否符合检测标准；
c)若符合检测标准，则记录当前调节参数并退出流程；
d)若不符合检测标准，则根据配置参数，先调节相机的工作距离即对位，然后调节相机的焦距、曝光时间、增益及白平衡等参数；然后重复上述动作，直到判断所拍图像满足检测标准。
5)、取像模式：
a)配置相机参数，包括曝光时间、增益及白平衡；
b)触发相机；
c)接收相机数据；
d)图像前处理，包括亮度矫正、暗角矫正、AOI区域提取及切割、背景抑制、摩尔纹去除等图像前处理；
e)从DDR内存中读出数据并通过光纤发送到前端，进行下一步处理。
本发明具备管理多达20只相机同时进行数据采集、处理的能力，极大优化了高分辨率及大尺寸面板自动检测系统的系统复杂度、压缩图像采集的Tact Time、提升系统稳定性；同时，集相机自动对位、对焦、图像质量检测与一体，自动实现相机图像质量管理，极大的方便现场调机；通过自主开发的图像质量评估系统，可以快速实现线体调机，图像一致性好；基于FPGA图像存储管理系统，提升图像存储效率，方便图像检索；为机器学习与智能检测提供必要的源图片。
使用CPU+GPU+FPGA的星形网络并行加速计算系统，充分发挥GPU与FPGA的并行处理特征，提升系统的整体计算能力；根据数据流的方向，利用pipeline结构，在FPGA端加速图像前处理，然后在CPU及GPU端实现图像后处理；使用此加速系统，图像计算处理能力提升达到50％以上。
本说明书中未作详细描述的内容属于本领域专业技术人员公知的现有技术。

Claims (10)

  1. 一种基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：包括图像存储单元、图像计算单元和图像采集单元，所述图像存储单元具有第一通信接口和第二通信接口，所述图像计算单元具有第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口，所述图像采集单元具有第三通信接口和相机接口；
    所述图像存储单元通过第一通信接口向图像计算单元下发配置参数和测试命令、接收图像计算单元发送的测试结果，通过第二通信接口接收采集单元的数据；
    所述图像计算单元通过第一光纤接口接收图像存储单元发送的配置参数及测试命令、向图像存储单元发送测试结果，通过第二光纤接口接收图像采集单元的数据、向图像采集单元发送配置参数及测试命令，通过第三光纤接口控制点屏信号生成，通过第四光纤接口控制IO光源；
    所述图像采集单元通过第三通信接口输出图像数据、接收配置参数及测试命令，通过相机接口接收相机数据、向相机发送配置参数和测试命令。
  2. 根据权利要求1所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述图像存储单元包括
    主控PC，用于通过人机交互进行参数配置、输出配置参数及测试命令，用于接收FPGA存储平台的测试结果并上报；
    FPGA存储平台，用于接收图像采集单元数据、将接收的数据进行无损压缩后发送至磁盘阵列，用于接收图像计算单元的测试结果并输出，用于将接收的配置参数输出至图像采集单元，用于根据存储的数据进行图像数据检索；
    磁盘阵列，用于存储数据。
  3. 根据权利要求2所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述FPGA存储平台包括
    数据交互模块，用于接收主控PC发送的配置参数，用于将接收的图像计算单元的测试结果反馈至主控PC；
    图像数据接收/发送模块，用于接收图像采集单元数据并输出至数据无损压缩模块，用于接收配置参数并发送至图像采集模块，用于接收图像计算单元的测试结果；
    数据无损压缩模块，用于对接收的数据进行无损压缩后经磁盘存储管理单元存储至磁盘阵列；
    数据磁盘存储管理模块，用于管理磁盘阵列的存储、读取功能。
  4. 根据权利要求2所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述FPGA存储平台还包括
    图像检索管理模块，用于控制读磁盘阵列；
    图像数据交换控制模块，具有第四通信接口，用于与外部服务器通信，实现图像检索数据交换、数据通信控制。
  5. 根据权利要求1所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述图像计算单元包括FPGA计算平台和计算PC，所述第一光纤接口、第二光纤接口、第三光纤接口和第四光纤接口均设置于FPGA计算平台上，FPGA计算平台还具有与所述计算PC连接的第五光纤接口，以及实现FPGA计算平台级联扩展的扩展接口。
  6. 根据权利要求1或5所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述FPGA计算平台包括中央控制器、图像处理加速器、数据汇总发送模块和DDR内存，
    所述中央控制器用于根据设定的指令分别向计算PC和图像处理加速器发送控制命令；
    所述计算PC，用于根据控制命令从DDR内存中读取部分图像数据进行计算处理并将处理结果发送至数据汇总发送模块；
    所述图像处理加速器用于根据控制命令从DDR内存中读取部分图像进行计算处理，将计算结果发送至数据汇总发送模块；
    所述数据汇总发送模块用于将计算PC和图像处理加速器的处理结果进行汇总形成最终的测试结果发送至图像存储模块；
    所述DDR内存用于存储需要处理的图像数据及测试结果。
  7. 根据权利要求6所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述FPGA计算平台还包括接收配置参数模块、数据接收/参数配置模块、信号 扩展模块和IO控制模块，
    所述接收配置参数模块用于接收配置参数及测试命令并发送至中央控制器；
    所述中央控制器还用于将接收的配置参数发送至数据接收/参数配置模块，将接收的测试命令分别分配至数据接收/参数配置模块、IO控制模块和信号扩展模块；
    所述数据接收/参数配置模块用于接收图像采集单元图像数据并存储至DDR内存中，将接收的配置参数及测试命令发送至图像采集单元；
    所述信号扩展模块用于根据测试命令实现点屏信号生成与控制；
    所述IO控制模块用于根据测试命令实现IO光源控制。
  8. 根据权利要求1所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述图像采集单元包括
    协议解析模块，用于接收相机数据，并将相机数据按照协议解析出有效的图像数据发送至DDR物理内存中存储为原始图像数据；
    DDR物理内存，用于存储原始图像数据和处理图像数据；
    图像质量评估与前处理模块，用于根据主控单元控制命令从DDR物理内存中读取原始图像数据，对原始图像数据进行图像前处理，将前处理后的数据发送至DDR物理内存中存储为处理图像数据；
    主控单元，根据设定的指令向图像质量评估与前处理和读DDR数据格式转换发送控制命令；
    读DDR数据格式转换模块，用于根据主控单元的配置命令从DDR物理内存中读取原始图像数据和/或处理图像数据发送至高速接口数据封包模块，
    高速接口数据封包模块，用于将接收的原始图像数据和/或处理图像数据发送至图像存储单元和图像计算单元。
  9. 根据权利要求8所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于，所述图像采集单元还包括自动对位对焦曝光模块和相机配置模块，
    所述高速接口数据封包模块还用于接收配置参数及测试命令并发送至主控单元；
    所述协议解析模块还用于接收相机数据，并将相机数据按照协议解析出有效的图像数据发送至DDR物理内存；将相机配置参数发送至相机；
    所述图像质量评估与前处理模块还用于根据主控单元控制命令对相机数据进行图像采集质量评估，将质量评估结果发送至主控单元，
    所述主控单元还用于将接收的配置参数、测试命令及质量评估结果发送至自动对位对焦曝光模块；
    所述自动对位对焦曝光模块，用于根据配置参数及质量评估结果实现相机参数设置，并将配置参数及测试命令发送至相机配置模块；
    所述相机配置模块，用于将相机配置参数及测试命令发送至协议解析模块。
  10. 根据权利要求8或9所述的基于CPU+GPU+FPGA架构的自动光学检测系统，其特征在于：所述协议解析模块包括Camera link协议解析模块、Gige Vision协议解析模块和CLHS协议解析模块，所述相接接口包括多个Camera Link接口、多个Gige接口和多个CLHS接口，所述多个Camera Link接口与Camera link协议解析模块连接，所述多个Gige接口与Gige Vision协议解析模块连接，所述多个CLHS接口与CLHS协议解析模块连接。
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