WO2019082273A1

WO2019082273A1 - Determination device, determination system and determination method

Info

Publication number: WO2019082273A1
Application number: PCT/JP2017/038360
Authority: WO
Inventors: 山口　泰生
Original assignee: 三菱電機株式会社
Priority date: 2017-10-24
Filing date: 2017-10-24
Publication date: 2019-05-02
Also published as: JPWO2019082273A1; JP6956797B2

Abstract

According to the present invention, a sensing unit (210) of a determination device (204) receives a plurality of pieces of detection information from an input circuit (202) and changes a plurality of pieces of sensing information, which indicate that the plurality of pieces of detection information are detected, from invalid to valid. When at least one of the plurality of pieces of sensing information is changed from invalid to valid, a determination unit (211) of the determination device (204) determines whether the input circuit (202) is in a normal state by determining whether all the plurality of pieces of sensing information are changed to valid from invalid within a waiting time (Tw).

Description

Judgment apparatus, judgment system and judgment method

The present invention relates to a determination device that determines whether an input circuit for inputting an external signal from an external device is in a normal state, a determination system using the determination device, and a determination method performed by the determination device.

In recent years, in the field of automobiles, in order to improve the safety to the occupants of the vehicle and the people around the vehicle, the fault resistance at the time of use of the devices and parts mounted on the electronic control system for controlling the vehicle is enhanced. Efforts have been made to improve the reliability of electronic control systems.

In Patent Document 1 as a prior art, in an electronic control system of a vehicle, an input circuit for inputting an input signal detects an internal circuit as an input circuit, and an edge detection circuit for detecting that the voltage level of the input signal changes from low level to high level; Disclosed is a method to increase the fault tolerance of the system and the possibility that the input circuit detects the input signal by adopting a dual configuration with a level detection circuit that detects that the voltage level of the input signal is at the high level. doing.

Patent application

However, in the method of Patent Document 1, when any abnormality occurs, such as a voltage erroneously detected as a signal to be output at normal time occurs in one circuit of the internal circuit having a duplex configuration in the input circuit, for example. The electronic control system may malfunction.

An object of the present invention is to solve the above-mentioned problems, and an object thereof is to provide a determination apparatus that determines whether an input circuit for inputting a signal from an external signal is in a normal state.

The present invention is a determination device that determines whether an input circuit that detects an external signal input from an external device by a plurality of internal circuits is in a normal state based on a plurality of pieces of detection information output from the input circuit, The determination device distinguishes and inputs each of the plurality of detection information, and separately indicates that the plurality of detection information corresponding to each of the plurality of detection information indicates that each of the plurality of detection information is detected. When at least one of the plurality of pieces of detection information becomes invalid from being invalidated by the detection unit performing the processing and the processing by the detection unit, the plurality of detection information items corresponding to each of the plurality of detection information within a predetermined time It is determined whether all become invalid or valid, and if all of the plurality of detection information becomes invalid from valid within a predetermined time, it is determined that the input circuit is in a normal state, and a plurality of Detection A determination device and a determining unit and the input circuit is not in a normal state when all of the broadcast is not effective from the disabled.

According to the present invention, the determination device is configured to determine whether the input circuit for inputting the external signal from the external device is in a normal state based on detection information when the external circuit is detected by the input circuit. Therefore, when the input circuit is in an abnormal state, an effect of preventing the electronic control system from malfunctioning can be obtained.

FIG. 1 is a device configuration diagram showing a configuration of devices included in an electronic control system of a vehicle according to a first embodiment of the present invention. It is a block block diagram which shows the functional block of the drive control part which inputs the command signal from a vehicle control part. FIG. 7 is a timing chart showing processing of an edge detection circuit and a level detection circuit when an external signal is input. FIG. 7 is a timing chart showing processing of an edge detection circuit, a level detection circuit, a detection unit, and a determination unit when an external signal is input. FIG. 7 is a timing chart showing processing of the edge detection circuit, the level detection circuit, the detection unit, and the determination unit when the edge detection circuit of the input circuit is in an abnormal state. FIG. 13 is a timing chart showing processing of the edge detection circuit, the level detection circuit, the detection unit, and the determination unit when the level detection circuit of the input circuit is in an abnormal state. FIG. 13 is another timing chart showing processing of the edge detection circuit, the level detection circuit, the detection unit and the determination unit when the edge detection circuit of the input circuit is in an abnormal state. FIG. 17 is another timing chart showing processing of the edge detection circuit, the level detection circuit, the detection unit and the determination unit when the level detection circuit of the input circuit is in an abnormal state. It is a flowchart figure showing processing of a judgment system. It is a block block diagram which shows the functional block of a drive control part at the time of setting the internal circuit of an input circuit as triple construction. FIG. 13 is a timing chart showing processing of an edge detection circuit, a level detection circuit, a detection unit, and a determination unit in a case where the internal circuit of the input circuit is in a triple configuration. It is a block block diagram which shows the functional block of the drive control part as a modification of a determination system. It is a timing chart showing processing in a modification of a judgment system. FIG. 10 is a device configuration diagram showing a configuration of a device included in an electronic control system for an electric drive vehicle according to a second embodiment of the present invention. It is a block block diagram which shows the functional block of the drive control part which inputs the command signal from a vehicle control part. It is a flowchart figure which shows the process which performs a normal operation mode and a test mode in an electronic control system. It is a block block diagram which shows the functional block of the drive control part as another modification of a determination system.

Embodiment 1
FIG. 1 is a device configuration diagram showing a configuration of devices included in an electronic control system 101 of a vehicle 100 according to a first embodiment of the present invention. The vehicle 100 is, for example, a car such as a passenger car, a bus, and a truck, and is a transportation means for transporting a person or a thing.

The electronic control system 101 of the vehicle 100 is an electronic control system 101 for the vehicle 100. The electronic control system 101 may have all the functions installed in the vehicle 100 or may not have all the functions installed in the vehicle 100, and some functions may be provided outside via a network or the like. Control may be performed on the vehicle 100.
In the example of FIG. 1, the electronic control system 101 has all functions installed in the vehicle 100.

As shown in FIG. 1, the vehicle 100 includes an engine 102, a transmission mechanism 103, wheels 104, a generator 106, a battery 105, a brake system 107, a braking mechanism 108, a speed detection unit 109, a drive control unit 110, and a vehicle control unit 111. It consists of
And the electronic control system 101 points out the electrical component which remove | eliminated the wheel 104 from the structure of the vehicle 100. FIG.
Further, in FIG. 1, solid arrows indicate signal paths, and dashed dotted arrows indicate power supply paths.

The engine 102 is an internal combustion engine that generates power by burning a fuel such as gasoline or light oil, for example, and serves as a power source for driving the vehicle 100. The power generated by the engine 102 is transmitted to the wheels 104 as a driving force of the vehicle 100 through the transmission mechanism 103.

The battery 105 is a secondary battery capable of storing, charging and discharging, and serves as a power source of each device of the vehicle 100.

The generator 106 is a power generation device that generates power by using the motive power of the engine 102 via the transmission mechanism 103. By charging the battery 105 with the power generated by the generator 106 while the vehicle 100 is traveling, each device of the vehicle 100 can continue the operation during traveling for a long time using the battery 105 as a power source.

The brake system 107 is a system for braking the vehicle 100. The brake system 107 brakes the vehicle 100 by applying a braking force in a direction in which the rotation of the wheel 104 is suppressed via the braking mechanism 108.

The speed detection unit 109 is a device for detecting the traveling speed of the vehicle 100.

The drive control unit 110 manages the operating states of the engine 102 and the brake system 107, and receives a command signal from the vehicle control unit 111 to control the engine 102 and the brake system 107, thereby driving or braking the vehicle 100. Is a device that controls the running state.

The vehicle control unit 111 acquires information on the operation states of the engine 102 and the brake system 107 managed by the drive control unit 110 and the traveling speed detected by the speed detection unit 109, and responds to the situation while the vehicle 100 is traveling. Is a device that controls the drive control unit 110 to maintain an optimal running state.
Further, the vehicle control unit 111 manages and controls each device of the vehicle 100. For example, when the vehicle control unit 111 manages information on the storage amount of the battery 105 and determines that it is necessary to increase the storage amount of the battery 105, the vehicle control unit 111 transmits the wheel 104 to the drive control unit 110. The engine 102 and the generator 106 are controlled to operate without transmitting power to them.

FIG. 2 is a block diagram showing a functional block of the drive control unit 110 which receives a command signal from the vehicle control unit 111. As shown in FIG. The drive control unit 110 includes a microcomputer 201, an input circuit 202, and a communication circuit 203.

The microcomputer 201 is a microcontroller (Microcontroller) mounted on the in-vehicle apparatus, and for example, the drive control unit 110 controls the engine 102 and the brake system 107 in response to an input of a command signal from the vehicle control unit 111. Execute the process of

The input circuit 202 is a circuit that detects an input of a command signal from the vehicle control unit 111, and outputs detection information indicating that the command signal has been detected to the microcomputer 201.
In the first embodiment, detection information output from the input circuit 202 to the microcomputer 201 is treated as a signal. Further, a device external to the input circuit 202 is defined as an external device.

The communication circuit 203 is a circuit serving as a communication line for the drive control unit 110 to communicate with the vehicle control unit 111. As the communication line, for example, an in-vehicle LAN such as CAN (Controller Area Network) (registered trademark), LIN (Local Interconnect Network), or CXPI (Clock Extension Peripheral Interface) (registered trademark) can be used.

Further, the microcomputer 201 includes a determination device 204, an operation unit 205, a timer 206, a RAM 207, a ROM 208, and an interface circuit 209. The respective devices in the microcomputer 201 can exchange information with each other through the signal transmission path L.

The determination device 204 includes a detection unit 210, a determination unit 211, and a notification unit 212, and determines whether the input circuit 202 is in a normal state based on a signal of detection information input from the input circuit 202.
Terminal P in FIG. 2 is a terminal for inputting a signal of detection information from the input circuit 202 to the microcomputer 201. The microcomputer 201 inputs a signal of the input detection information to the determination device 204 via the terminal P.

The microcomputer 201 may input a signal of detection information to the determination device 204 and to each device in the microcomputer 201 via the terminal P and the signal transmission path L, or the microcomputer 201 via the determination device 204. It may be input to each device within.

The detection unit 210 separately inputs the plurality of pieces of detection information output from the input circuit 202. Then, the detection unit 210 individually makes the logic of the detection information corresponding to the detected detection information and the detection information corresponding to the detection information valid, in order to indicate that the input detection information is detected.

In the first embodiment, the logic of the detection information handled by the detection unit 210 is defined as information represented by two values, such as valid and invalid or ON and OFF.

When determining that at least one of the plurality of pieces of detection information becomes valid from being invalidated by the processing of the detection unit 210, the determination unit 211 determines whether all of the plurality of pieces of detection information are valid within a predetermined time. . Then, when determining that all the detection information is valid within a predetermined time, the determining unit 211 determines that the input circuit 202 is in the normal state. In addition, when determining that all the detection information is not valid within the predetermined time, the determining unit 211 determines that the input circuit 202 is not in the normal state, that is, in the abnormal state.

As a method for the determination unit 211 to confirm the validity of the detection information, when the detection unit 210 validates the detection information, a signal of the detection information is output to the determination unit 211, or the determination unit 211 outputs each signal. It is conceivable to periodically check the detection information.

Details of exchange of information between the detection unit 210 and the determination unit 211 will be described later.

When the notification unit 212 confirms the determination result of the determination unit 211, the notification unit 212 notifies the outside of the determination result. The destination to which the notification unit 212 notifies is, for example, the operation unit 205 that executes a predetermined process corresponding to the input command signal according to the content of the determination result, or communication is possible via the interface circuit 209 It is an external device.

Arithmetic unit 205 executes a program stored in advance in ROM 208 using RAM 207 capable of temporary storage, or predetermined information corresponding to detection information output based on a command signal input circuit 202 receives from vehicle control unit 111. Execute processing

The timer 206 is an apparatus for counting and managing time shared in the microcomputer 201.

The interface circuit 209 is a circuit serving as an interface for connecting the microcomputer 201 to the communication circuit 203.

The input circuit 202 has an edge detection circuit 213 and a level detection circuit 214 as internal circuits in a duplex configuration, branches the input command signal, and simultaneously inputs it to the edge detection circuit 213 and the level detection circuit 214.

The input circuit 202 and the determination device 204 may be disposed in the same device, may be disposed in different adjacent devices, or may be disposed across a plurality of other devices without being adjacent to each other. It may be done.

That is, the configuration of FIG. 2 is an example, and does not depend on the arrangement of the input circuit 202 and the determination device 204 in the electronic control system 101, but the normality of the input circuit 202 based on detection information input from the input circuit 202 by the determination device 204. It can be regarded as a judgment system for judging a state or an abnormal state.

In the first embodiment, a system in which the input circuit 202 and the determination device 204 are combined is defined as a determination system 215. The determination system 215 is shown by a dashed frame in FIG.
In the determination system 215, for example, the determination device 204 can be disposed outside the microcomputer 201 of the drive control unit 110, or the input circuit 202 can be disposed in the microcomputer 201 of the drive control unit 110.
When the determination device 204 is arranged outside the microcomputer 201, the microcomputer 201 can check the determination result of the determination device 204, so that the microcomputer 201 receives a command signal from the vehicle control unit 111 and outputs a predetermined signal. It can be determined whether to execute the process.

The processes of the edge detection circuit 213 and the level detection circuit 214 of the input circuit 202 will be described with reference to FIG.
Here, in the first embodiment, a signal that the input circuit 202 inputs from an external device external to the input circuit 202 is defined as an external signal IN, such as a command signal input from the vehicle control unit 111 described above.

FIG. 3 is a timing chart showing processing of the edge detection circuit 213 and the level detection circuit 214 when the external signal IN is input.

The vertical axis represents the logic of each signal. The logic of the signal is indicated as valid or invalid as well as the logic of the information described above.
In the first embodiment, the logic of such a signal is indicated by a binary value of high level state or low level state of voltage level. That is, the logic of each signal is defined as valid when the voltage level of the signal is high, and defined as invalid when low. Unless otherwise stated, the initial value of the logic of the signal is invalidated.

Also, the horizontal axis represents the passage of time, and time proceeds in the direction of the arrow.

As shown at time T1 in FIG. 3, the edge detection circuit 213 detects that the voltage level of the external signal IN has changed from the low level state to the high level state, as a feature of the input external signal IN. The change at this time is called an edge of the external signal IN.
Then, the edge detection circuit 213 changes the voltage level of the signal from the low level state to the high level state, and outputs an edge detection signal D1. The edge detection signal D1 is detection information indicating that the edge detection circuit 213 has detected an edge of the external signal IN.

Further, as shown at time T2 in FIG. 3, the level detection circuit 214 detects that the voltage level of the external signal IN is in the high level state as a feature of the input external signal IN.
Then, the level detection circuit 214 changes the voltage level of the signal from the low level state to the high level state, and outputs the level detection signal D2. The level detection signal D2 is detection information indicating that the level detection circuit 214 has detected a high level state at the voltage level of the external signal IN.

Here, the edge detection circuit 213 is referred to as a first detection circuit. A feature of the external signal IN detected by the first detection circuit is a first feature. In the above example, the first feature of the external signal IN is that the voltage level of the external signal IN changes from the low level state to the high level state.
Further, the level detection circuit 214 is a second detection circuit. The feature of the external signal IN detected by the second detection circuit is a second feature. In the above-mentioned example, the second feature of the external signal IN is that the voltage level of the external signal IN is in the high level state.
Further, among the plurality of pieces of detection information output from the input circuit 202, the edge detection signal D1 output when the edge detection circuit 213 detects the first feature is set as first detection information. The level detection signal D2 output when the level detection circuit 214 detects the second feature is used as second detection information.

The time for which the edge detection circuit 213 keeps the edge detection signal D1 valid and the time for which the level detection circuit 214 keeps the level detection signal D2 valid, that is, each detection information output from the input circuit 202 is kept valid. The time is appropriately set according to, for example, a specification of a change in voltage level of the input external signal IN, a frequency or timing of inputting the external signal IN, or the like.

Further, in FIG. 3, for convenience of the description, for example, timings that are substantially simultaneous are shown as being shifted, such as time T1 and time T2. The time T1 is set earlier than the time T2, but even if the time T2 is earlier than the time T1, the times T1 and T2 may be simultaneous.

Next, exchange of information between the detection unit 210 and the determination unit 211 in the determination device 204 will be described using FIG.

FIG. 4 is a timing chart showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the external signal IN is input.

The vertical axis represents the logic of each signal and each flag. The logic of each signal is the same as in FIG. The logic of the flag is indicated as valid or invalid as in the logic of the information described above.
In the first embodiment, the logic of such a flag is indicated by a binary value of ON or OFF. That is, the logic of each flag is defined as valid when the flag is ON, and defined as invalid when the flag is OFF. Note that, unless otherwise stated, the initial value of the logic of the flag is invalidated.

The horizontal axis is the same as that in FIG.

The edge detection signal D1, the level detection signal D2, the time T1 and the time T2 in FIG. 4 are the same as those in FIG.

As shown at time T3 in FIG. 4, when the edge detection signal D1 is input, the detection unit 210 detects that the input circuit 202 has detected the edge of the external signal IN. In order to indicate detection at this time, the detection unit 210 sets the edge detection flag F1 from OFF to ON.

Also, as shown at time T4 in FIG. 4, when the level detection signal D2 is input, the detection unit 210 detects that the input circuit 202 has detected the high level state of the external signal IN. In order to indicate detection at this time, the detection unit 210 sets the level detection flag F2 from OFF to ON.

The detection unit 210 handles a plurality of pieces of detection information corresponding to each of a plurality of pieces of detection information to be input. Then, an edge detection flag F1 indicating that the detection unit 210 detects the edge detection signal D1 is set as first detection information, and a level detection flag F2 indicating that the level detection signal D2 is detected is set as second detection information. .

Further, as shown in FIG. 4, when determining that the edge detection flag F1 is turned ON at time T3, the determination unit 211 sets the waiting time Tw and monitors that the waiting time Tw elapses. Here, the waiting time Tw is the above-described predetermined time, and is a time for the determination unit 211 to determine whether all of the plurality of pieces of detection information are valid.

Then, the determination unit 211 confirms that the level detection flag F2 has become ON at time T4 before the waiting time Tw has elapsed. At this time, the determination unit 211 determines that the input circuit 202 is in the normal state because all the flags become valid within the waiting time Tw.

As shown at time T5 in FIG. 4, when it is determined that the input circuit 202 is in the normal state, the determination unit 211 sets the normal determination flag F3 from OFF to ON, and indicates the determination result of the determination process.

In the description so far, the detection unit 210 is set in advance so that all detection information output from the input circuit 202 can be recognized and processed. Further, the determination unit 211 is set in advance so that all detection information handled by the detection unit 210 can be recognized and processed.

Further, as in the times T1 and T2, in FIG. 4, for convenience of the description, for example, timings that are substantially simultaneous are shown being shifted, such as times T3 and T4.
Although time T3 is earlier than time T4, time T3 may be earlier than time T3, or time T3 may be simultaneous with time T4.
That is, the determination unit 211 performs setting and monitoring of the waiting time Tw when it is confirmed that at least one piece of detection information has become valid. Then, the determination unit 211 determines whether all the detection information becomes valid within the waiting time Tw, and determines whether the input circuit 202 is in the normal state.

Information on the logic of each of the edge detection flag F1, the level detection flag F2, and the normality determination flag F3 shown in FIG. 4 may be output as a signal whose voltage level changes to the high level state or the low level state. , And may be written in a predetermined storage area of the RAM 207 as information indicating ON or OFF.

Further, as the timing for resetting the edge detection flag F1, the level detection flag F2 and the normality determination flag F3 from ON to OFF in the determination device 204, for example, as shown in FIG. When the determination unit 211 confirms that the edge detection flag F1 and the level detection flag F2 are ON, the notification by the notification unit 212 is completed, or a combination of these time may be considered.

Next, processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the input circuit 202 is in an abnormal state will be described using the examples of FIGS.

FIG. 5 is a timing chart showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the edge detection circuit 213 of the input circuit 202 is in an abnormal state. The vertical and horizontal axes are the same as in FIG.

An abnormal state of the edge detection circuit 213 refers to, for example, a disconnection at a point where it is detected in the edge detection circuit 213 that the voltage level of the input external signal IN has changed from low level to high level, or an edge detection signal. The voltage level of the terminal that outputs D1 is stuck at a low level, or some abnormality has occurred, and the edge detection signal D1 is not normally output with the input of the external signal IN.

As shown in period E1 of FIG. 5, the edge detection circuit 213 in the abnormal state does not output the edge detection signal D1 despite the fact that the external signal IN is input. Therefore, the detection unit 210 does not set the edge detection flag F1 to ON.

On the other hand, as shown at time T7 in FIG. 5, when the external signal IN is input, the level detection circuit 214 in the normal state detects that the voltage level of the external signal IN is in the high level state, and detects the level. The signal D2 is output. Therefore, the detection unit 210 sets the level detection flag F2 to ON at time T8.

When determining that the level detection flag F2 is turned on at time T8, the determination unit 211 sets a waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the edge detection flag F1 is turned on before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at time T9 when the waiting time Tw has elapsed.

As shown at time T9 in FIG. 5, when it is determined that the input circuit 202 is in the abnormal state, the determination unit 211 sets the abnormality determination flag F4 from OFF to ON, and indicates the determination result of the determination process.

Thus, the determination device 204 indicates that the input circuit 202 is in the normal state by the validity of the normal judgment flag F3 and indicates that the input circuit 202 is in the abnormal state by the validity of the abnormality judgment flag F4. When the external signal IN is input to the input circuit 202 or when an abnormality occurs, the possibility that the electronic control system 101 recognizes the abnormality of the input circuit 202 can be increased more than before.

6 is a timing chart showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the level detection circuit 214 of the input circuit 202 is in an abnormal state. The vertical and horizontal axes are the same as in FIG.

An abnormal state of the level detection circuit 214 refers to, for example, disconnection of a wire at a point where the level of the voltage level of the input external signal IN is detected in the level detection circuit 214 or a voltage at a terminal for outputting the level detection signal D2. The level is stuck at the low level or some abnormality occurs, and the level detection signal D2 is not normally output with the input of the external signal IN.

As shown in period E2 of FIG. 6, the level detection circuit 214 in the abnormal state does not output the level detection signal D2 despite the input of the external signal IN. Therefore, the detection unit 210 does not set the level detection flag F2 to ON.

On the other hand, as shown at time T10 in FIG. 6, when the external signal IN is input, the edge detection circuit 213 in the normal state detects that the voltage level of the external signal IN has changed from low level to high level, An edge detection signal D1 is output. Therefore, the detection unit 210 sets the edge detection flag F1 to ON at time T11.

When determining that the edge detection flag F1 is turned on at time T11, the determination unit 211 sets a waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the level detection flag F2 is turned on before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at time T12 when the waiting time Tw has elapsed, and sets the abnormality determination flag F4 to ON.

FIG. 7 is another timing chart showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the edge detection circuit 213 of the input circuit 202 is in an abnormal state. The vertical and horizontal axes are the same as in FIG.

In the example of FIG. 7, in the edge detection circuit 213, for example, the voltage level of the terminal for outputting the edge detection signal D1 temporarily becomes high due to the phenomenon of oscillation of parts in the circuit and noise superposition on the wiring. This indicates that a certain abnormality has occurred, such as sticking to the signal, and a signal corresponding to the edge detection signal D1 is abnormally output.

As shown in period E3 of FIG. 7, the edge detection circuit 213 in an abnormal state outputs a signal corresponding to the edge detection signal D1 at time T13, even though the external signal IN is not input. Therefore, the detection unit 210 sets the edge detection flag F1 to ON at time T14.

On the other hand, since the level detection circuit 214 in the normal state does not receive the external signal IN, it does not output the level detection signal D2.

When determining that the edge detection flag F1 is turned on at time T14, the determination unit 211 sets a waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the level detection flag F2 is turned on before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at time T15 when the waiting time Tw has elapsed, and sets the abnormality determination flag F4 to ON.

FIG. 8 is another timing chart showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the level detection circuit 214 of the input circuit 202 is in an abnormal state. The vertical and horizontal axes are the same as in FIG.

In the example of FIG. 8, in the level detection circuit 214, for example, the voltage level of the terminal for outputting the level detection signal D2 temporarily becomes high due to the phenomenon of oscillation of parts in the circuit and noise superposition on the wiring. In this state, there is an abnormality such as sticking to the sensor, and a signal corresponding to the level detection signal D2 is output abnormally.

As shown in period E4 of FIG. 8, the level detection circuit 214 in an abnormal state outputs a signal corresponding to the level detection signal D2 at time T16, even though the external signal IN is not input. Therefore, the detection unit 210 sets the level detection flag F2 to ON at time T17.

On the other hand, since the edge detection circuit 213 in the normal state does not receive the external signal IN, it does not output the edge detection signal D1.

When determining that the level detection flag F2 is turned on at time T17, the determination unit 211 sets a waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the edge detection flag F1 is turned on before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at time T18 when the waiting time Tw has elapsed, and sets the abnormality determination flag F4 to ON.

In addition, as a timing which resets the abnormality determination flag F4 from ON to OFF in the determination apparatus 204, the time of the notification in the notification part 212 being completed can be considered, for example.

By the way, in the determination system 215, as described above, the input circuit 202 and the determination device 204 may be disposed across a plurality of other devices as described above, and therefore one of the signals of the detection information output from the other device is the input circuit 202. It is also conceivable to convert the part and output it to the determination device 204. In such a case, it is possible that the signal of the detection information output from the input circuit 202 and the signal of the detection information input by the determination device 204 do not become the same signal. However, the information that needs to be transmitted from the input circuit 202 to the determination device 204 is information indicating whether the internal circuit of the input circuit 202 has detected the external signal IN, and the information on valid or invalid logic is described. It is information. This information is defined as detection information.

The operation of the determination system 215 up to this point will be summarized below.

FIG. 9 is a flowchart showing the process of the determination system 215. In the flowchart of FIG. 9, the process starts when the determination system 215 receives an external signal IN from an external device.

In processing S901, the edge detection circuit 213 and the level detection circuit 214 of the input circuit 202 receive the external signal IN. Then, it progresses to process S902.

In processing S902, the edge detection circuit 213 detects an edge of the external signal IN and outputs detection information. The edge is a feature of the external signal IN in which the voltage level of the signal changes from low level to high level. Further, as a feature of the external signal IN, the level detection circuit 214 detects that the voltage level of the external signal IN is in the high level state, and outputs detection information. Then, it progresses to process S903a.

Processing S 903 a and processing S 903 b indicate loop processing in the determination system 215. In the loop process, when the process proceeds to the process S 903 b, the process returns to the process S 903 a.

In step S904, the detection unit 210 of the determination device 204 determines whether at least one of the plurality of pieces of detection information input from the input circuit 202 has been detected. If at least one piece of detection information is detected, the process proceeds to processing S905. If none of the detection information is detected, the process proceeds to step S 913.

In processing S905, the detection unit 210 makes the detection information corresponding to the detected detection information valid to invalid. Then, it progresses to process S906.

In process S906, the determination unit 211 of the determination apparatus 204 confirms the detection information that has become invalid from valid in process S905. Then, it progresses to process S907.

In processing S907, the determination unit 211 determines whether or not the waiting time Tw is being monitored. If monitoring is in progress, the process proceeds to step S909. If the monitoring is not in progress, the process proceeds to step S908.

In processing S908, the determination unit 211 sets the waiting time Tw and starts monitoring. Thereafter, the process proceeds to step S909.

In processing S909, the determination unit 211 determines whether all the detection information processed by the detection unit 210 has become valid. If all the detection information is valid, the process proceeds to processing S910. If all the detection information is not valid, the process proceeds to processing S914.

In processing S910, the determination unit 211 determines that the input circuit 202 is in the normal state. Then, it progresses to process S911.

In processing S911, the notification unit 212 notifies the determination result of the determination unit 211. Then, it progresses to process S910.

In processing S912, the detection unit 210 resets the detection information to invalid, and the determination unit 211 resets the determination result to invalid. Thereafter, the process ends.

In processing S913, the determination unit 211 determines whether or not the waiting time Tw is being monitored. If monitoring is in progress, the process proceeds to step S914. If the monitoring is not in progress, the process proceeds to processing S 903 b.

In processing S914, the determination unit 211 determines whether or not the waiting time Tw being monitored has elapsed. If the waiting time Tw has elapsed, the process proceeds to step S915. If the waiting time Tw has not elapsed, the process proceeds to step S 903 b.

In processing S915, the determination unit 211 determines that the input circuit 202 is in an abnormal state. Then, it progresses to process S911.

Up to here, an example is described in which the internal circuit of the input circuit 202 is duplicated and each edge individually detects an edge and a high level state which is a feature of the external signal IN and outputs detection information. did. However, the features of the external signal IN detected by the internal circuit of the input circuit 202 are not limited to the edge and high level states. The internal circuit of the input circuit 202 may detect a feature of the external signal IN which is different from the edge and high level state, and output detection information.

Furthermore, the internal circuit of the input circuit 202 may be configured to be three or more multiplexed, and each circuit may individually detect the feature of the external signal IN and output detection information.

FIG. 10 is a block diagram showing functional blocks of the drive control unit 110 in the case where the internal circuit of the input circuit 202 has a triple configuration.
As shown in FIG. 10, the input circuit 202 has an internal circuit in a triple configuration of an edge detection circuit 213, a level detection circuit 214, and a pattern detection circuit 1001. The other configuration is the same as that shown in FIG.

When there are a plurality of types of external signal IN to be input, the pattern detection circuit 1001 detects the type of the external signal IN as a feature of the external signal IN, and outputs detection information corresponding to the type.

FIG. 11 is a timing chart showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the internal circuit of the input circuit 202 has a triple configuration.
As shown in FIG. 11, the input external signals IN1 and IN2 include type information K. As indicated by the external signals IN1 and IN2, the type information K includes a pattern consisting of a low level state and a high level state of voltage levels corresponding to the types of the plurality of external signals IN.

The input circuit 202 detects an edge, a high level state, and a type of the external signal IN, and outputs an edge detection signal D1, a level detection signal D2, and a pattern detection signal D3. The edge detection signal D1, the level detection signal D2, and the pattern detection signal D3 are detection information.

The pattern detection signal D3 corresponds to the pattern of the voltage level in the type information K of the external signal IN, and the contents are different as the pattern detection signals D3a and D3b.

As shown in FIG. 11, the pattern detection circuit 1001 detects the patterns of the external signals IN1 and IN2 different in type from each other, and outputs a pattern detection signal D3a and a pattern detection signal D3b. The pattern detection signal D3a and the pattern detection signal D3b are a pattern detection signal D3.

Then, in the same manner as the processing in FIGS. 4 to 8, the detection unit 210 corresponds to each of the three detection information input from the input circuit 202, that is, the edge detection signal D1, the level detection signal D2, and the pattern detection signal D3. Each of the edge detection flag F1, the level detection flag F2 and the pattern detection flag F5 is changed from OFF to ON. Further, when determining that all the flags become invalid from valid within the waiting time Tw, the determining unit 211 determines that the input circuit 202 is in the normal state.

Here, the pattern detection circuit 1001 is referred to as a third detection circuit. The feature of the external signal IN detected by the pattern detection circuit 1001 is the third feature. Then, among the plurality of pieces of detection information output from the input circuit 202, the pattern detection signal D3 output from the pattern detection circuit 1001 is used as third detection information. Then, detection information indicating that the detection unit 210 has detected the pattern detection signal D3 is set as third detection information.

As described above, by detecting the type of the external signal IN in the input circuit 202, the microcomputer 201 of the drive control unit 110 distinguishes the external signal IN having a plurality of types based on the input pattern detection signal D3, and responds. It becomes possible to execute predetermined processing. That is, the microcomputer 201 of the drive control unit 110 can be executed while discriminating a plurality of predetermined processes.

In addition, an interval time Ti is provided so that the detection device 204 detects and outputs the detection information output from the plurality of external signals IN which are continuously input by the input circuit 202 in a row. think of. That is, the interval time Ti is a time for the detection unit 210 and the determination unit 211 to perform processing based on a plurality of pieces of detection information corresponding to the same external signal IN.

As shown in FIG. 11, the determination unit 211 sets the interval time Ti1 after the determination processing, or sets the interval time Ti2 after the waiting time Tw has elapsed, so that the detection unit 210 and the determination unit 211 are external. It is possible to distinguish a set of detection information output with the input of the signal IN. After the determination process in the determination unit 211 is the time when the normality determination flag F3 or the abnormality determination flag F4 becomes valid.

This has the effect of enabling the microcomputer 201 of the drive control unit 110 to execute a plurality of predetermined processes by inputting a plurality of types of command signals.

In the internal circuit in which the input circuit 202 has a duplex configuration, any two of the first feature, the second feature, and the third feature described above are detected and detection information is output. Also good. For example, the first and third features are detected to output first and third detection information, and the second and third features are detected and second and third detection information and Output third detection information.

Further, a modification of the determination system 215 will be described.
The input circuit 202 inputs an external signal IN in which the voltage level of the signal is maintained at high level or low level according to the control content. The microcomputer 201 determines whether the voltage level of the input external signal IN is high level or low level, and executes predetermined processing corresponding to each voltage level.

FIG. 12 is a block diagram showing functional blocks of the drive control unit 110 as a modification of the determination system 215. As shown in FIG.
As shown in FIG. 12, the input circuit 202 has an internal circuit in a triple configuration of an edge detection circuit 1201, a high level detection circuit 1202 and a low level detection circuit 1203.
Further, as shown in FIG. 12, the determination device 204 includes a detection unit 1204 different from that of FIG. 2.
The other configuration is the same as that shown in FIG.

FIG. 13 is a timing chart showing processing in a modification of the determination system 215.

The edge detection circuit 1201 of the input circuit 202 outputs an edge detection signal D4 upon detecting the change from the low level to the high level and the change from the high level to the low level of the voltage level of the external signal IN.
Further, when detecting that the voltage level of the external signal IN is at the high level, the high level detection circuit 1202 outputs the high level detection signal D5.
The low level detection circuit 1203 outputs a low level detection signal D6 when detecting that the voltage level of the external signal IN is at a low level.

Then, when the edge detection signal D4 is input from the input circuit 202, the detection unit 1204 of the determination device 204 turns the edge detection flag F6 from invalid to valid.
When the detection unit 1204 receives the high level detection signal D5 or the low level detection signal D6 from the input circuit 202, the detection unit 1204 turns the level detection flag F7 from invalid to valid.

Then, the determination unit 211 of the determination device 204 determines whether the edge detection flag F6 and the level detection flag F7 become valid or invalid within the waiting time Tw, as in FIGS. Determine if is in a normal state.

As described above, the detection unit 1204 can also associate one piece of detection information with a plurality of pieces of detection information output from the input circuit 202.

Here, the edge detection circuit 1201 of the input circuit 202 is a fourth detection circuit, the high level detection circuit 1202 is a fifth detection circuit, and the low level detection circuit 1203 is a sixth detection circuit. The edge detection signal D4 output from the edge detection circuit 1201 is used as fourth detection information, the high level detection signal D5 output from the high level detection circuit 1202 is used as fifth detection information, and the low level detection circuit 1203 is output. The low level detection signal D6 is used as sixth detection information. Then, the edge detection flag F6 corresponding to the edge detection signal D4 is set as fourth detection information, and the level detection flag F7 corresponding to the high level detection signal D5 or the low level detection signal D6 is set as fifth detection information.

Furthermore, another modified example of the determination system 215 will be described with reference to FIG.
The input circuit 202 inputs an external signal IN in which the voltage level of the signal is maintained at high level or low level according to the control content, and the microcomputer 201 inputs high level or low level of the voltage level of the input external signal IN. It is the same as that of the above-mentioned modification in that it judges whether it is a level and executes a predetermined process corresponding to each voltage level.

The input circuit 202 has an internal circuit in a quadruple configuration of a high level edge detection circuit 1701, a low level edge detection circuit 1702, a high level voltage detection circuit 1703, and a low level voltage detection circuit 1704.
The other configuration is the same as that shown in FIG.

When the high level edge detection circuit 1701 of the input circuit 202 detects a change from low level to high level of the voltage level of the external signal IN, the high level edge detection circuit 1701 outputs a high level edge detection signal D7.
When the low level edge detection circuit 1702 of the input circuit 202 detects a change from high level to low level of the voltage level of the external signal IN, it outputs a low level edge detection signal D8.
Further, when detecting that the voltage level of the external signal IN is at the high level, the high level voltage detection circuit 1703 outputs the high level voltage detection signal D9.
The low level voltage detection circuit 1704 outputs a low level voltage detection signal D10 when detecting that the voltage level of the external signal IN is at a low level.

Then, when the high level edge detection signal D7 is input from the input circuit 202, the detection unit 1705 of the determination device 204 turns the high level edge detection flag F8 from OFF to ON.
Also, when the low level edge detection signal D8 is input from the input circuit 202, the detection unit 1705 of the determination device 204 turns the low level edge detection flag F9 from OFF to ON.
Further, when the detection unit 1705 receives the high level voltage detection signal D9 from the input circuit 202, the detection unit 1705 turns the high level voltage detection flag F10 from OFF to ON.
When the detection unit 1705 receives the low level voltage detection signal D10 from the input circuit 202, the detection unit 1705 turns the low level voltage detection flag F11 from OFF to ON.

When the determination unit 1706 of the determination device 204 confirms that at least one of the high level edge detection flag F8 and the high level voltage detection flag F10 is turned on, the high level edge detection flag F8 and the high level voltage detection flag F10 are detected. It is determined whether or not both are switched from OFF to ON within the waiting time Tw to determine whether the input circuit 202 is in a normal state.
In addition, when the determination unit 1706 of the determination device 204 confirms that at least one of the low level edge detection flag F9 and the low level voltage detection flag F11 is turned on, the low level edge detection flag F9 and the low level voltage detection flag F11 are detected. It is determined whether or not both are switched from OFF to ON within the waiting time Tw to determine whether the input circuit 202 is in a normal state.

As described above, the determination unit 1706 associates in advance at least two or more of the plurality of pieces of detection information, and determines whether all pieces of detection information associated within the waiting time Tw are valid, to thereby determine the input circuit 202. It is also possible to determine if is normal.

Furthermore, it is also conceivable that any of the internal circuits in the multiplexed configuration of the input circuit 202 detects, for example, a plurality of voltage levels of high level, middle level and low level, as a feature of the external signal IN. At this time, even if the internal circuit that has detected a plurality of voltage levels outputs detection information corresponding to each voltage level, the detection unit 210 corresponds to each detection information in the same manner as described above. The determination unit 211 can determine the normal state of the input circuit 202 by making the detected information from invalid to valid.

That is, in the determination device 204 according to the first embodiment, the detection unit 210 arbitrarily associates the plurality of detection information input from the input circuit 202 with the plurality of detection information based on the setting in advance, and the input detection The detection information corresponding to the information is invalidated to be valid, and the determination unit 211 is configured to distinguish the grouping of the detection information to be monitored in the waiting time Tw. Therefore, the determination unit 211 is flexible according to the specifications of the electronic control system 101 and the input circuit 202. It is possible to execute the determination processing of the normal state of the input circuit 202.

Furthermore, it is also possible to apply the determination system 215 not only to signal input between the drive control unit 110 and the vehicle control unit 111 but also to signal input between other devices.

As described above, according to the first embodiment, in the input circuit 202, the determination device 204 multiplexes in the input circuit 202 whether or not the input circuit 202 receiving the external signal IN from the external device is in a normal state. Since the determination is made based on the detection information output from the internal circuit described above, an effect of preventing the electronic control system 101 from executing a predetermined process can be obtained when the input circuit 202 is in an abnormal state.

That is, it is possible to prevent the electronic control system 101 from malfunctioning due to an abnormality occurring in the input circuit 202.

This means that the electronic control system 101 determines that the input circuit 202 is in a normal state and executes predetermined processing, so that the reliability in the operation of the electronic control system 101 is guaranteed more than ever before.

Further, according to the first embodiment, the input circuit 202 has the internal circuit in a multiplexed configuration, so that the accuracy when the input circuit 202 detects the external signal IN can be improved. As a result, an effect of enhancing the noise resistance of the input circuit 202 can be obtained.

Further, according to the first embodiment, the input circuit 202 is configured to detect a pattern in the type information K of the external signal IN as a feature of the external signal IN, and output detection information corresponding to the detected pattern. Therefore, even if a plurality of types of external signals IN are input to the input circuit 202, the electronic control system 1401 can execute the plurality of predetermined processes corresponding to the plurality of types of external signals IN while discriminating them. .

Further, according to the first embodiment, the determination unit 211 provides the interval time Ti so that the determination device 204 can collectively process the detection information obtained by detecting the same external signal IN in the input circuit 202. Since this is done, even if the input circuit 202 is made to input external signals IN of a plurality of types, it is possible to prevent the determination device 204 from processing the external signals IN of a plurality of types together. As a result, even in the case where the electronic control system 101 handles the plurality of external signals IN successively, it is possible to obtain the effect that each predetermined process corresponding to the plurality of external signals IN can be reliably executed.

Further, according to the first embodiment, the detection unit 1204 of the determination device 204 detects the high level detection signal D5 and the low level detection signal D6 input from the input circuit 202 in correspondence with the level detection flag F7 and detects the detection information. Therefore, even when the external signal IN to be input is a signal that switches and controls the voltage level at both the high level and the low level, the determination unit 211 of the determination device 204 It is possible to perform the determination process of the normal state.

Second Embodiment
In the first embodiment, the determination system 215 always determines whether the input circuit 202 is in the normal state. In the second embodiment, the electronic control system 1401 of the electric drive vehicle 1400 is provided with a normal operation mode and a test mode, and the determination system 1501 makes a determination only in the test mode. The other respects are the same as in the first embodiment.

FIG. 14 is a device configuration diagram showing a configuration of devices included in the electronic control system 1401 for the electric drive vehicle 1400 according to the second embodiment of the present invention. In FIG. 14, the description of the parts in common with the configuration shown in FIG. 1 of the first embodiment will be omitted.

As shown in FIG. 14, electrically driven vehicle 1400 further includes a motor 1402 and a power split mechanism 1403 as compared with vehicle 100 of the first embodiment.
Then, the electronic control system 1401 indicates an electrical component in which the wheel 104 is removed from the configuration of the vehicle 100.

The motor 1402 is a motor such as an AC motor that generates power by using the power supplied from the battery 105 under the control of the drive control unit 1405. The motive power generated by the motor 1402 is transmitted to the wheels 104 as a driving force of the electrically driven vehicle 1400 via the power split mechanism 1403.

The power split mechanism 1403 is a device that includes mechanisms such as a planetary gear and a clutch, and integrates or distributes the power input from the engine 102 and the motor 1402 and outputs it. Power split device 1403 outputs rotational power to wheels 104 only with power from engine 102 based on control from drive control unit 1405, or combines power of engine 102 and motor 1402 to wheels 104. The rotational force can be output or switched.

The electronic control system 1401 of the electric drive vehicle 1400 reduces or stops the output of the engine 102, for example, to suppress the exhaust gas discharged from the electric drive vehicle 1400, and instead raises the output of the motor 1402, It is possible to suppress the generation of exhaust gas caused by the output of the engine 102.

By the way, the vehicle control unit 1404 and the drive control unit 1405 of the electric drive vehicle 1400 perform the switching control of the power of the engine 102 and the motor 1402 described above based on the traveling state of the vehicle and the operation by the passenger's intention. Therefore, the vehicle control unit 1404 and the drive control unit 1405 shown in FIG. 14 of the second embodiment execute more control than the vehicle control unit 111 and the drive control unit 110 of the vehicle 100 according to the first embodiment. As a result, the electronic control system 1401 of the electric drive vehicle 1400 consumes more power from the battery 105.

When the electronic control system 1401 of the electric drive vehicle 1400 is compared with the electronic control system 101 of the first embodiment in FIG. Indicated.

As such, the electronic control system 1401 of the electric drive vehicle 1400 is considered to consume more electric power than the vehicle 100 without motor drive, particularly during traveling. Therefore, it is desirable for the electronic control system 1401 to efficiently use the power supplied from the battery 105 by reducing the processing of the devices constituting the system while securing the reliability of the operation.

Therefore, in the second embodiment, the electronic control system 1401 is provided with a normal operation mode and a test mode. Then, the electronic control system 1401 switches between the normal operation mode and the test mode, and causes the determination device 204 to execute the determination process of the normal state of the input circuit 202 only in the test mode. By doing this, the electronic control system 1401 can reduce the number of processes without constantly performing the process of determining the normal state of the input circuit 202, and can ensure the reliability of the operation.

By the way, the reliability in functional safety of a vehicle is standardized, for example, by defining a mechanism for detecting a failure in the functional safety standard ISO26262.

Therefore, the reliability of the operation of the electronic control system 1401 is set by setting the frequency at which the electronic control system 1401 executes the test mode based on the standard of ASIL (Automotive Safety Integrity Level) according to ISO26262. Is guaranteed.

In the second embodiment, switching between the normal operation mode and the test mode is abbreviated as mode switching. Further, the normal operation mode is defined as a first mode, and the test mode is defined as a second mode.

Further, in the electronic control system 1401, mode switching control is performed by the vehicle control unit 1404 or the drive control unit 1405.

When the vehicle control unit 1404 performs switching control to the test mode, the vehicle control unit 111 instructs the drive control unit 110 to switch to the test mode. In addition, when the drive control unit 110 performs switching control to the test mode, the drive control unit 110 instructs the vehicle control unit 111 to switch to the test mode, and urges the output of a test signal.

FIG. 15 is a block diagram showing a functional block of drive control unit 1405 which receives a command signal from vehicle control unit 1404. Referring to FIG. The determination system 1501 further includes a switching unit 1502. In FIG. 15, the description of the portions common to the functional blocks shown in FIG. 2 of the first embodiment will be omitted.

The switching unit 1502 is provided between the input circuit 202 and the determination device 204. Then, in accordance with the mode switching instruction to the normal operation mode or the test mode, the switching unit 1502 switches whether to input the detection information input from the input circuit 202 to the determination device 204.
The mode switching at this time is performed by the vehicle control unit 1404 or the drive control unit 1405 executing a mode switching instruction.

The switching unit 1502 does not input the plurality of pieces of detection information input from the input circuit 202 to the determination device 204 in the normal operation mode. Further, in the test mode, the switching unit 1502 inputs the plurality of pieces of detection information input from the input circuit 202 to the determination device 204.

Here, similarly to the determination system 215 of the first embodiment, the determination system 1501 performs the determination process of the normal state of the input circuit 202 without depending on the arrangement of each configuration. That is, the switching unit 1502 may be disposed either inside or outside the microcomputer 201, and exchanges information with the drive control unit 1405 or an external device via the signal transmission path L or the communication circuit 203. .

Then, in the normal operation mode, a plurality of pieces of detection information not input to the determination device 204 by the switching unit 1502 can be input to the device inside the microcomputer 201 through the signal transmission path L or the communication circuit 203. The microcomputer 201 can execute predetermined processing based on the detection information.

On the other hand, in the test mode, as in the first embodiment, the switching unit 1502 inputs detection information to the determination device 204, and the microcomputer 201 performs predetermined processing based on the determination result of the determination processing of the determination device 204. It can be done.

That is, since the determination device 204 performs the determination process only in the test mode, the determination device 204 does not receive the detection information and perform the determination process in the normal operation mode. As a result, power consumption of the drive control unit 110 can be suppressed. Furthermore, since the determination device 204 may operate only in the test mode, power consumption can be further suppressed by stopping the determination device 204 in the normal operation mode.

As described above, suppressing the power consumption in the determination system 1501 enables the electronic control system 1401 to use the power stored in the battery 105 more efficiently than the first embodiment.

Next, an operation of causing the electronic control system 1401 to execute the determination system 1501 while switching modes will be described.

FIG. 16 is a flowchart showing the process of executing the normal operation mode and the test mode in the electronic control system 1401.

In FIG. 16, with the activation of the electronic control system 1401, the vehicle control unit 1404 activates the drive control unit 1405 and then instructs the drive control unit 1405 to switch to the test mode. Then, based on the determination result of the determination system 1501, the vehicle control unit 1404 instructs the drive control unit 1405 to switch to the normal operation mode or notifies the outside of an abnormal state.

Here, the process of the determination system 1501 shown in the flowchart of FIG. 9 in the first embodiment is defined as a predefined process S1606.

In processing S1601, the vehicle control unit 1404 activates the drive control unit 1405. Then, it progresses to process S1602.

In process S1602, the vehicle control unit 1404 determines whether the drive control unit 1405 is in the activated state. If the drive control unit 1405 is in the activated state, the process advances to step S1603. If the drive control unit 1405 is not in the activated state, the process advances to step S1611.

In step S1603, the vehicle control unit 1404 instructs the drive control unit 1405 to switch to the test mode. Then, it progresses to process S1604.

In processing S1604, the switching unit 1502 of the drive control unit 1405 and the microcomputer 201 switch to the test mode. When the switching to the test mode is performed, the microcomputer 201 activates the determination device 204 which is in the stopped state. Then, it progresses to process S1605.

In processing S1605, the vehicle control unit 1404 outputs a test signal to the drive control unit 1405. Then, it progresses to process S1606.

In the process S1606, which has already been defined, the determination system 1501 performs the determination process. Thereafter, the process proceeds to step S1607.

In process S1607, the vehicle control unit 1404 confirms the determination result of the determination system 1501, and determines whether the input circuit 202 is in a normal state. If the input circuit 202 is in the normal state, the process proceeds to step S1608. If the input circuit 202 is not in the normal state, the process advances to step S1609.

In step S1608, the vehicle control unit 1404 instructs the drive control unit 1405 to switch to the normal operation mode. Thereafter, the process proceeds to step S1609.

In processing S1609, the switching unit 1502 of the drive control unit 1405 and the microcomputer 201 switch to the normal operation mode. The microcomputer 201 stops the operation of the determination device 204 when the switching to the normal operation mode is performed. Thereafter, the process ends.

In step S1610, the drive control unit 1405 notifies the vehicle control unit 1404 that the input circuit 202 is in an abnormal state. Thereafter, the process ends.

In the process S1611, the vehicle control unit 1404 determines whether or not the start-up time which is the reference required for starting the drive control unit 1405 has elapsed. If the activation time has elapsed, the process proceeds to step S1612. If the activation time has not elapsed, the process proceeds to processing S1602.

In step S1612, the vehicle control unit 1404 notifies the outside that the drive control unit 1405 is in an abnormal state. Thereafter, the process ends.

The execution of the test mode in the electronic control system 1401 is not limited to the start of the system as described above, for example, when the rider of the electrically driven vehicle 1400 operates the shift lever to the parking position or pulls the side brakes. For example, the test mode may be executed at a timing when the electrically driven vehicle 1400 is in a stopped state and can not be expected to be driven immediately.

In addition, the configuration of the determination system 215 of the first embodiment may be applied to the second embodiment or the like, and may be arbitrarily combined in the first and second embodiments.

As described above, according to the second embodiment, the electronic control system 1401 is provided with the normal operation mode and the test mode, and the determination system 1501 determines the normal state of the input circuit 202 in the test mode. Therefore, if it is determined that the input circuit 202 is in the normal state in the test mode, then at least one of the internal circuits of the input circuit 202 detects the external signal IN as in the prior art in the normal operation mode. It is also possible to judge that the distortion is due to the distortion of the external signal IN, not the abnormality of the internal circuit. As a result, it is possible to continue the operation while guaranteeing the reliability of the electronic control system 1401.

This is because the determination system 1501 of the second embodiment executes the test mode according to the standard of ISO 26262, thereby ensuring the reliability of the operation of the electronic control system 1401.

Further, according to the second embodiment, the determination system 1501 includes the switching unit 1502, so that the determination process of the determination system 1501 is executed only in the test mode in response to the input of the external signal IN. Sometimes it is possible not to run it. As a result, since the power consumption of the determination device 204 can be suppressed in the normal operation mode, the electronic control system 1401 can use the power stored in the battery 105 more efficiently than the first embodiment. become able to do.

Reference Signs List 100

vehicle

101, 1401 electronic control system 102 engine 103 transmission mechanism 104 wheel 105 battery 106 generator 107 brake system 108 braking mechanism 109

speed detection unit

110, 1405

drive control unit

111, 1404 vehicle control unit 201 microcomputer 202 input circuit 203 communication circuit 204

Judgment device

215, 1501 Judgment system 1400 Electric drive vehicle 1402 Motor 1403 Power split mechanism

Claims

A determination device that determines whether an input circuit that detects an external signal input from an external device by a plurality of internal circuits is in a normal state based on a plurality of pieces of detection information output from the input circuit,
The determination device is
Each of the plurality of detection information is distinguished and input, and a plurality of detection information corresponding to each of the plurality of detection information indicating that each of the plurality of detection information has been detected is individually made invalid or valid. A detection unit that performs processing;
When at least one of the plurality of pieces of detection information becomes invalid from processing by the detection unit, all of the plurality of pieces of detection information corresponding to each of the plurality of pieces of detection information are invalidated within a predetermined time. It is determined whether or not the input circuit becomes valid, and if all of the plurality of pieces of detection information become invalid to be valid within the predetermined time, it is determined that the input circuit is in a normal state, and the plurality of the plurality of detection information are within the predetermined time. A determination unit that determines that the input circuit is not in the normal state when all of the detection information in the group are not valid from invalidity;
Judgment device equipped with
The determination unit determines an interval for confirming the plurality of pieces of detection information corresponding to the same external signal after the determination process as to whether the input circuit is in the normal state or after the predetermined time has elapsed. Set the time,
The determination apparatus according to claim 1, characterized in that:
A determination device according to claim 1 or 2 and an input circuit,
The determination system used for the electronic control system for vehicles which performs the predetermined | prescribed process corresponding to the said external signal based on the said some detection information output from the said input circuit.
The input circuit is, as the internal circuit,
A first detection circuit that detects a first feature in the external signal input from the external device and outputs first detection information of the plurality of detection information;
And a second detection circuit that detects a second feature in the external signal input from the external device and outputs second detection information of the plurality of detection information,
Have
The detection unit is
When the first detection information is input, the first detection information corresponding to the first detection information is made invalid to be valid,
When the second detection information is input, the second detection information corresponding to the second detection information is made invalid to be valid.
The determination system according to claim 3, characterized in that:
The first detection circuit detects a change from a low level to a high level in the voltage level of the external signal as the first feature,
The second detection circuit detects a high level at a voltage level of the external signal as the second feature.
The determination system according to claim 4, wherein
The input circuit is, as the internal circuit,
A first detection circuit that detects a change from low level to high level in voltage level of the external signal, and outputs first detection information of the plurality of detection information;
A second detection circuit that detects a high level in the voltage level of the external device and outputs second detection information of the plurality of detection information;
And a third detection circuit that detects a pattern consisting of low level and high level in voltage level of the external signal, and outputs third detection information corresponding to the pattern among the plurality of detection information,
Have at least two of
The detection unit is
In the case where the input circuit includes the first detection circuit, when the first detection information is input, the first detection information corresponding to the first detection information among the plurality of detection information is invalidated. Effective from
When the input circuit has the second detection circuit, when the second detection information is input, the second detection information corresponding to the second detection information among the plurality of detection information is invalidated. Effective from
When the input circuit includes the third detection circuit, when the third detection information is input, the third detection information corresponding to the third detection information among the plurality of detection information is invalidated. Valid from,
The determination system according to claim 3, characterized in that:
The input circuit is
A fourth detection circuit that detects a change from low level to high level or a change from high level to low level in voltage level of the external signal, and outputs fourth detection information as the plurality of detection information;
A fifth detection circuit that detects a high level of the voltage level of the external signal and outputs fifth detection information as the plurality of detection information;
And a sixth detection circuit that detects a low level of the voltage level of the external signal and outputs sixth detection information as the plurality of detection information.
Have
The detection unit is
When the fourth detection information is input, the fourth detection information corresponding to the fourth detection information is made invalid to be valid, and when the fifth detection information or the sixth detection information is input, the fifth detection information is input. The fifth detection information corresponding to the first detection information or the sixth detection information from invalid to valid,
The determination system according to claim 3, characterized in that:
The judgment system
And a switching unit configured to distinguish and input each of the plurality of pieces of detection information output from the input circuit.
The switching unit is
When instructed to switch to the first mode from the outside, the plurality of pieces of detection information input from the input circuit are not output to the determination device,
When instructed to switch to the second mode from the outside, the plurality of pieces of detection information input from the input circuit are output to the determination device.
The determination system according to any one of claims 3 to 7, characterized in that.
An input step of inputting each of the plurality of pieces of detection information output from the input circuit according to claim 1;
A detection step of individually detecting the plurality of pieces of detection information input in the input step, and making detection information corresponding to the detected detection information out of the plurality of pieces of detection information invalid or effective;
A determination step of determining whether all of the plurality of pieces of detection information become valid within a predetermined time when at least one of the plurality of pieces of detection information becomes invalid from the plurality of pieces of detection information in the detection step;
A determination step of determining whether the input circuit is in a normal state based on the determination in the determination step;
Determination method having.