JP6956797B2 - Judgment device, judgment system and judgment method - Google Patents

Description

The present invention relates to a determination device for determining whether or not an input circuit for inputting an external signal from an external device is in a normal state, a determination system in which the determination device is used, and a determination method performed by the determination device.

In recent years, in the field of automobiles, in order to improve the safety for passengers of vehicles and people around the vehicles, the fault tolerance of devices and parts mounted on electronic control systems that control vehicles has been improved, thereby improving the fault tolerance. Efforts are being made to improve the reliability of electronic control systems.

As a prior art, in Patent Document 1, in an electronic control system of a vehicle, an input circuit for inputting an input signal is an internal circuit, an edge detection circuit for detecting that the voltage level of the input signal has changed from a low level to a high level, and an edge detection circuit. Disclosure of a method to improve the fault tolerance of the system and the possibility that the input signal detects the input signal by making it a dual configuration with a level detection circuit that detects that the voltage level of the input signal is at a high level. doing.

JP 2016-119016

However, in the method of Patent Document 1, when some abnormality occurs in one of the internal circuits having a duplicated configuration in the input circuit, for example, a voltage that is erroneously detected as a signal output during normal operation is generated. , There is a risk that the electronic control system will malfunction.

The present invention is for solving the above-mentioned problems, and an object of the present invention is to provide a determination device for determining whether or not an input circuit for inputting a signal from an external signal is in a normal state.

The present invention is a determination device for determining whether or not an input circuit that detects an external signal input from an external device by a plurality of internal circuits is in a normal state based on a plurality of detection information output from the input circuit. The determination device distinguishes and inputs each of the plurality of detection information, and individually invalidates and validates the plurality of detection information corresponding to each of the plurality of detection information, indicating that each of the plurality of detection information has been detected. When at least one of the plurality of detection information becomes valid from invalid by the detection unit that performs the processing and the processing by the detection unit, the plurality of detection information corresponding to each of the plurality of detection information is provided within a predetermined time. It is determined whether or not all are invalid to valid, and if all of the plurality of detection information is invalid to valid within a predetermined time, it is determined that the input circuit is in a normal state, and a plurality of detection information are determined to be in a normal state within a predetermined time. It is a determination device including a determination unit that determines that the input circuit is not in a normal state when all of the detection information is invalid to invalid.

According to the present invention, the determination device is configured to determine whether or not the input circuit for inputting an external signal from the external device is in a normal state based on the detection information when the external signal is detected by the input circuit. Therefore, when the input circuit is in an abnormal state, the effect of preventing the electronic control system from malfunctioning can be obtained.

It is a device block diagram which shows the structure of the device included in the electronic control system of a vehicle in Embodiment 1 of this invention. It is a block block diagram which shows the functional block of the drive control part which inputs a command signal from a vehicle control part. It is a timing diagram which shows the processing of an edge detection circuit and a level detection circuit when an external signal is input. It is a timing diagram which shows the process of an edge detection circuit, a level detection circuit, a detection part and a determination part when an external signal is input. It is a timing diagram which shows the process of the edge detection circuit, the level detection circuit, the detection part and the determination part when the edge detection circuit of an input circuit is in an abnormal state. It is a timing diagram which shows the process of the edge detection circuit, the level detection circuit, the detection part and the determination part when the level detection circuit of an input circuit is in an abnormal state. It is another timing diagram which shows the process of the edge detection circuit, the level detection circuit, the detection part and the determination part when the edge detection circuit of an input circuit is in an abnormal state. It is another timing diagram which shows the processing of the edge detection circuit, the level detection circuit, the detection part and the determination part when the level detection circuit of an input circuit is in an abnormal state. It is a flowchart which shows the process of a determination system. It is a block block diagram which shows the functional block of the drive control part when the internal circuit of an input circuit has a triple structure. It is a timing diagram which shows the processing of the edge detection circuit, the level detection circuit, the detection part and the determination part when the internal circuit of an input circuit has a triple structure. It is a block block diagram which shows the functional block of the drive control part as a modification of a determination system. It is a timing diagram which shows the process in the modification of the determination system. It is a device block diagram which shows the structure of the device included in the electronic control system for the electric drive vehicle in Embodiment 2 of this invention. It is a block block diagram which shows the functional block of the drive control part which inputs a command signal from a vehicle control part. It is a flowchart which shows the process which executes the normal operation mode and the test mode in an electronic control system. It is a block block diagram which shows the functional block of the drive control part as another modification of a determination system.

Embodiment 1.
FIG. 1 is a device configuration diagram showing a configuration of a device included in the electronic control system 101 of the vehicle 100 according to the first embodiment of the present invention. The vehicle 100 is, for example, an automobile such as a passenger car, a bus, or a truck, and is a means of transportation for transporting a person or an object.

The electronic control system 101 of the vehicle 100 is an electronic control system 101 for the vehicle 100. In the electronic control system 101, all the functions may be installed in the vehicle 100, or not all the functions are installed in the vehicle 100, and some functions are placed outside and via a network or the like. It may control the vehicle 100.
In the example of FIG. 1, it is assumed that the electronic control system 101 is equipped with all the functions in the vehicle 100.

As shown in FIG. 1, the vehicle 100 includes an engine 102, a transmission mechanism 103, wheels 104, a generator 106, a battery 105, a brake system 107, a braking mechanism 108, a speed detection unit 109, a drive control unit 110, and a vehicle control unit 111. Consists of.
The electronic control system 101 refers to an electrical component excluding the wheels 104 from the configuration of the vehicle 100.
Further, in FIG. 1, the solid line arrow indicates the signal path, and the one-dot broken line arrow indicates the power supply path.

The engine 102 is an internal combustion engine that generates power by burning fuel such as gasoline or light oil, and serves as a power source for driving the vehicle 100. The power generated by the engine 102 is transmitted to the wheels 104 as the driving force of the vehicle 100 via the transmission mechanism 103.

The battery 105 is a secondary battery capable of storing, charging, and discharging, and serves as a power source for each device of the vehicle 100.

The generator 106 is a power generation device that generates power by using the power of the engine 102 via the transmission mechanism 103. By charging the battery 105 with the electric power generated by the generator 106 while the vehicle 100 is running, each device of the vehicle 100 can continue the operation during the running for a long time by using the battery 105 as a power source.

The brake system 107 is a system for braking the vehicle 100. The brake system 107 brakes the vehicle 100 by applying a braking force in a direction that suppresses the rotation of the wheels 104 via the braking mechanism 108.

The speed detection unit 109 is a device for detecting the traveling speed of the vehicle 100.

The drive control unit 110 manages the operating state of the engine 102 and the brake system 107, and drives or brakes the vehicle 100 by inputting a command signal from the vehicle control unit 111 to control the engine 102 and the brake system 107. It is a device that controls the running state.

The vehicle control unit 111 acquires information on the operating states of the engine 102 and the brake system 107 managed by the drive control unit 110 and the traveling speed detected by the speed detecting unit 109, and responds to the situation in which the vehicle 100 is traveling. This is a device that controls the drive control unit 110 so as to maintain an optimum traveling state.
In addition, the vehicle control unit 111 manages and controls each device of the vehicle 100. For example, when the vehicle control unit 111 manages the information on the amount of electricity stored in the battery 105 and determines that it is necessary to increase the amount of electricity stored in the battery 105, the vehicle control unit 111 refers to the wheel 104 with respect to the drive control unit 110. Control is performed so that the engine 102 and the generator 106 are operated without transmitting power to the engine 102.

FIG. 2 is a block configuration diagram showing a functional block of the drive control unit 110 that inputs a command signal from the vehicle control unit 111. The drive control unit 110 includes a microcomputer 201, an input circuit 202, and a communication circuit 203.

The microcomputer 201 is a microcontroller (Microcontroller) mounted on an in-vehicle device. For example, a predetermined device for controlling an engine 102 and a brake system 107 in a drive control unit 110 in response to an input of a command signal from a vehicle control unit 111. Executes the processing of.

The input circuit 202 is a circuit that detects the input of the command signal from the vehicle control unit 111 and outputs the detection information indicating that the command signal has been detected to the microcomputer 201.
In the first embodiment, the detection information output from the input circuit 202 to the microcomputer 201 is treated as a signal. Further, a device outside the input circuit 202 is defined as an external device.

The communication circuit 203 is a circuit that serves as a communication line for the drive control unit 110 to communicate with the vehicle control unit 111. As the communication line, for example, an in-vehicle LAN such as CAN (Control Area Network) (registered trademark), LIN (Local Interconnect Network), or CXPI (Lock Extension Peripheral Interface) (registered trademark) can be used.

Further, the microcomputer 201 includes a determination device 204, a calculation unit 205, a timer 206, a RAM 207, a ROM 208, and an interface circuit 209. It is assumed that each device inside the microcomputer 201 can exchange information with each other through the signal transmission line L.

The determination device 204 has a detection unit 210, a determination unit 211, and a notification unit 212, and determines whether or not the input circuit 202 is in a normal state based on the signal of the detection information input from the input circuit 202.
The terminal P in FIG. 2 is a terminal for inputting a signal of detection information from the input circuit 202 to the microcomputer 201. The microcomputer 201 inputs the input detection information signal to the determination device 204 via the terminal P.

The microcomputer 201 may input the signal of the detection information to the determination device 204 and also input to each device in the microcomputer 201 via the terminal P and the signal transmission line L, or the microcomputer 201 may input the signal of the detection information to each device in the microcomputer 201 via the determination device 204. You may input to each device in.

The detection unit 210 distinguishes and inputs a plurality of detection information output from the input circuit 202. Then, the detection unit 210 individually invalidates and validates the logic of the detected detection information and the corresponding detection information in order to indicate that each of the input detection information has been detected.

In the first embodiment, the logic of the detection information handled by the detection unit 210 is defined as information indicated by two values such as valid and invalid or ON and OFF.

When the determination unit 211 confirms that at least one of the plurality of detection information is valid from invalid by the processing of the detection unit 210, the determination unit 211 determines whether or not all of the plurality of detection information is valid within a predetermined time. .. Then, the determination unit 211 determines that the input circuit 202 is in the normal state when it is determined that all the detection information is valid within a predetermined time. Further, when the determination unit 211 determines that all the detection information is not valid within a predetermined time, it determines that the input circuit 202 is not in the normal state, that is, in the abnormal state.

As a method for the determination unit 211 to confirm the validity of the detection information, when the detection unit 210 enables the detection information, the determination unit 211 outputs the signal of the detection information, or the determination unit 211 outputs the signal of the detection information. It is conceivable to check the detection information periodically.

Details of information exchange between the detection unit 210 and the determination unit 211 will be described later.

When the notification unit 212 confirms the determination result in the determination unit 211, the notification unit 212 notifies the determination result to the outside. The destination to which the notification unit 212 notifies is, for example, the arithmetic unit 205 that executes a predetermined process corresponding to the input command signal, or can communicate via the interface circuit 209, depending on the content of the determination result. It may be an external device.

The calculation unit 205 executes a program stored in advance in the ROM 208 using the RAM 207 capable of temporary storage, or a predetermined value corresponding to the detection information output by the input circuit 202 based on the command signal input from the vehicle control unit 111. Execute processing.

The timer 206 is a device that counts and manages time, which is shared in the microcomputer 201.

The interface circuit 209 is a circuit that serves as an interface for connecting the microcomputer 201 to the communication circuit 203.

The input circuit 202 has an edge detection circuit 213 and a level detection circuit 214 as internal circuits having a dual configuration, and the input command signal is branched and input to the edge detection circuit 213 and the level detection circuit 214 at the same time.

The input circuit 202 and the determination device 204 may be arranged in the same device, may be arranged in different adjacent devices, or may be arranged across a plurality of other devices without being adjacent to each other. May be done.

That is, the configuration of FIG. 2 is an example, and the input circuit 202 is normal based on the detection information input by the determination device 204 from the input circuit 202 without depending on the arrangement of the input circuit 202 and the determination device 204 in the electronic control system 101. It can be regarded as a judgment system for determining a state or an abnormal state.

In the first embodiment, the system in which the input circuit 202 and the determination device 204 are combined is defined as the determination system 215. The determination system 215 is shown by a broken line frame in FIG.
The determination system 215 can, for example, arrange the determination device 204 outside the microcomputer 201 of the drive control unit 110, or arrange the input circuit 202 inside the microcomputer 201 of the drive control unit 110.
When the determination device 204 is arranged outside the microcomputer 201, the microcomputer 201 can confirm the determination result of the determination device 204, so that the microcomputer 201 receives a command signal input from the vehicle control unit 111 and determines a predetermined value. It is possible to determine whether to execute the process.

The processing of the edge detection circuit 213 and the level detection circuit 214 of the input circuit 202 will be described with reference to FIG.
Here, in the first embodiment, a signal input by the input circuit 202 from an external device outside the input circuit 202, such as the command signal input from the vehicle control unit 111 described above, is defined as an external signal IN.

FIG. 3 is a timing diagram showing the processing of the edge detection circuit 213 and the level detection circuit 214 when the external signal IN is input.

The vertical axis represents the logic of each signal. The logic of the signal, like the logic of the information described above, shall be indicated as valid or invalid.
In the first embodiment, the logic of such a signal is shown by two values of a high level state or a low level state of the voltage level. That is, the logic of each signal is defined as valid when the voltage level of the signal is in the high level state and invalid when the voltage level of the signal is in the low level state. Unless otherwise specified, the initial value of the signal logic is invalid.

The horizontal axis represents the passage of time, and time advances in the direction of the arrow.

As shown in the time T1 of FIG. 3, the edge detection circuit 213 detects that the voltage level of the external signal IN has changed from the low level state to the high level state as a feature of the input external signal IN. The change at this time is called the edge of the external signal IN.
Then, the edge detection circuit 213 changes the voltage level of the signal from the low level state to the high level state, and outputs the edge detection signal D1. The edge detection signal D1 is detection information indicating that the edge detection circuit 213 has detected the edge of the external signal IN.

Further, as shown in the time T2 of FIG. 3, the level detection circuit 214 detects that the voltage level of the external signal IN is in a high level state as a feature of the input external signal IN.
Then, the level detection circuit 214 changes the voltage level of the signal from the low level state to the high level state, and outputs the level detection signal D2. The level detection signal D2 is detection information indicating that the level detection circuit 214 has detected a high level state at the voltage level of the external signal IN.

Here, the edge detection circuit 213 is used as the first detection circuit. Then, the feature of the external signal IN detected by the first detection circuit is set as the first feature. In the above example, the first feature of the external signal IN is that the voltage level of the external signal IN changes from the low level state to the high level state.
Further, the level detection circuit 214 is used as a second detection circuit. Then, the feature of the external signal IN detected by the second detection circuit is set as the second feature. In the above example, the second feature of the external signal IN is that the voltage level of the external signal IN is in a high level state.
Further, among the plurality of detection information output by the input circuit 202, the edge detection signal D1 output when the edge detection circuit 213 detects the first feature is used as the first detection information. Then, the level detection signal D2 output when the level detection circuit 214 detects the second feature is used as the second detection information.

The time when the edge detection circuit 213 keeps the edge detection signal D1 valid and the time when the level detection circuit 214 keeps the level detection signal D2 valid, that is, each detection information output by the input circuit 202 is effectively maintained. The time shall be appropriately set according to, for example, the specification of the change in the voltage level of the external signal IN to be input, the frequency or timing of inputting the external signal IN, and the like.

Further, in FIG. 3, for convenience of explanation, the timings that are actually substantially the same, such as time T1 and time T2, are shown at different times. Further, although the time T1 is set to be earlier than the time T2, the time T2 may be earlier than the time T1 or the time T1 and the time T2 may be at the same time.

Next, the exchange of information between the detection unit 210 and the determination unit 211 in the determination device 204 will be described with reference to FIG.

FIG. 4 is a timing diagram showing the processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the external signal IN is input.

The vertical axis represents the logic of each signal and each flag. The logic of each signal is the same as in FIG. The logic of the flag shall be indicated as valid or invalid, as in the logic of information described above.
In the first embodiment, the logic of such a flag is indicated by two values of ON and OFF. That is, the logic of each flag is defined as valid when the flag is ON and invalid when the flag is OFF. Unless otherwise specified, the initial value of the flag logic is invalid.

The horizontal axis is the same as in FIG.

The edge detection signal D1, the level detection signal D2, the time T1 and the time T2 in FIG. 4 are the same as those in FIG.

As shown in the time T3 of FIG. 4, when the edge detection signal D1 is input, the detection unit 210 detects that the input circuit 202 has detected the edge of the external signal IN. In order to indicate the detection at this time, the detection unit 210 sets the edge detection flag F1 from OFF to ON.

Further, as shown in the time T4 of FIG. 4, when the level detection signal D2 is input, the detection unit 210 detects that the input circuit 202 has detected the high level state of the external signal IN. In order to indicate the detection at this time, the detection unit 210 sets the level detection flag F2 from OFF to ON.

The detection unit 210 handles a plurality of detection information corresponding to each of the plurality of input detection information. Then, the edge detection flag F1 indicating that the detection unit 210 has detected the edge detection signal D1 is used as the first detection information, and the level detection flag F2 indicating that the level detection signal D2 has been detected is used as the second detection information. ..

Further, as shown in FIG. 4, when the determination unit 211 confirms that the edge detection flag F1 is turned ON at the time T3, the determination unit 211 sets the waiting time Tw and monitors the elapse of the waiting time Tw. Here, the waiting time Tw is the predetermined time described above, and is the time for the determination unit 211 to determine whether or not all of the plurality of detection information is valid.

Then, the determination unit 211 confirms that the level detection flag F2 is turned on at the time T4 before the waiting time Tw elapses. At this time, the determination unit 211 determines that the input circuit 202 is in the normal state because all the flags are valid within the waiting time Tw.

As shown in the time T5 of FIG. 4, when the determination unit 211 determines that the input circuit 202 is in the normal state, the normal determination flag F3 is set from OFF to ON, and the determination result of the determination process is shown.

In the description so far, it is assumed that the detection unit 210 is preset so that all the detection information output by the input circuit 202 can be recognized and processed. Further, it is assumed that the determination unit 211 is preset so that all the detection information handled by the detection unit 210 can be recognized and processed.

Further, similarly to the time T1 and T2, in FIG. 4, for convenience of explanation, the timings that are actually substantially the same, such as the time T3 and the time T4, are shown at different times.
Further, although the time T3 is set to be earlier than the time T4, the time T4 may be earlier than the time T3, or the time T3 and the time T4 may be at the same time.
That is, the determination unit 211 sets and monitors the waiting time Tw when it is confirmed that at least one detection information is valid. Then, the determination unit 211 determines whether or not all the detection information is valid within the waiting time Tw, and determines whether or not the input circuit 202 is in the normal state.

The logic information of each of the edge detection flag F1, the level detection flag F2, and the normality determination flag F3 shown in FIG. 4 may be output as a signal in which the voltage level changes to a high level state or a low level state. , The information indicating ON or OFF may be written in a predetermined storage area of the RAM 207.

Further, in the determination device 204, the timing for resetting the edge detection flag F1, the level detection flag F2, and the normal determination flag F3 from ON to OFF is, for example, as shown in FIG. , The time when the determination unit 211 confirms that the edge detection flag F1 and the level detection flag F2 are ON, the time when the notification by the notification unit 212 is completed, or a combination of these time points is conceivable.

Next, processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the input circuit 202 is in an abnormal state will be described with reference to the examples of FIGS. 5 to 8.

FIG. 5 is a timing diagram showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the edge detection circuit 213 of the input circuit 202 is in an abnormal state. The vertical axis and the horizontal axis are the same as those in FIG.

The abnormal state of the edge detection circuit 213 means that, for example, in the edge detection circuit 213, the wiring at the position where it is detected that the voltage level of the input external signal IN has changed from the low level to the high level is broken, or the edge detection signal. This refers to a state in which the edge detection signal D1 is not normally output due to the input of the external signal IN due to the voltage level of the terminal that outputs D1 sticking to a low level or some abnormality occurring.

As shown in the period E1 of FIG. 5, the edge detection circuit 213 in the abnormal state does not output the edge detection signal D1 even though the external signal IN is input. Therefore, the detection unit 210 does not set the edge detection flag F1 to ON.

On the other hand, as shown in time T7 of FIG. 5, when the external signal IN is input, the level detection circuit 214 in the normal state detects that the voltage level of the external signal IN is in the high level state and detects the level. The signal D2 is output. Therefore, the detection unit 210 sets the level detection flag F2 to ON at the time T8.

When the determination unit 211 confirms that the level detection flag F2 is turned ON at the time T8, the determination unit 211 sets the waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the edge detection flag F1 is turned on before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at the time T9 when the waiting time Tw has elapsed.

As shown in the time T9 of FIG. 5, when the determination unit 211 determines that the input circuit 202 is in the abnormal state, the abnormality determination flag F4 is set from OFF to ON, and the determination result of the determination process is shown.

In this way, the determination device 204 indicates that the input circuit 202 is in the normal state by enabling the normal determination flag F3, and indicates that the input circuit 202 is in the abnormal state by enabling the abnormality determination flag F4. When the external signal IN is input to the input circuit 202 or when an abnormality occurs, the possibility that the electronic control system 101 knows the abnormality of the input circuit 202 can be increased as compared with the conventional case.

Further, FIG. 6 is a timing diagram showing processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the level detection circuit 214 of the input circuit 202 is in an abnormal state. The vertical axis and the horizontal axis are the same as those in FIG.

The abnormal state of the level detection circuit 214 means that, for example, in the level detection circuit 214, the wiring at the position where the magnitude of the voltage level of the input external signal IN is detected is broken, or the voltage of the terminal that outputs the level detection signal D2. This refers to a state in which the level detection signal D2 is not normally output due to the input of the external signal IN due to the level sticking to the low level or some abnormality occurring.

As shown in the period E2 of FIG. 6, the level detection circuit 214 in the abnormal state does not output the level detection signal D2 even though the external signal IN is input. Therefore, the detection unit 210 does not set the level detection flag F2 to ON.

On the other hand, as shown in the time T10 of FIG. 6, the edge detection circuit 213 in the normal state detects that the voltage level of the external signal IN has changed from the low level to the high level when the external signal IN is input. The edge detection signal D1 is output. Therefore, the detection unit 210 sets the edge detection flag F1 to ON at the time T11.

When the determination unit 211 confirms that the edge detection flag F1 is turned ON at the time T11, the determination unit 211 sets the waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the level detection flag F2 is turned ON before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at the time T12 when the waiting time Tw has elapsed, and sets the abnormality determination flag F4 to ON.

Further, FIG. 7 is another timing diagram showing the processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the edge detection circuit 213 of the input circuit 202 is in an abnormal state. The vertical axis and the horizontal axis are the same as those in FIG.

In the example of FIG. 7, in the edge detection circuit 213, for example, the voltage level of the terminal that outputs the edge detection signal D1 is temporarily high due to the phenomenon of oscillation of components in the circuit and noise superposition on the wiring. Indicates a state in which some abnormality has occurred, such as sticking to the edge detection signal D1, and a signal corresponding to the edge detection signal D1 is abnormally output.

As shown in the period E3 of FIG. 7, the edge detection circuit 213 in the abnormal state outputs a signal corresponding to the edge detection signal D1 at the time T13 even though the external signal IN is not input. Therefore, the detection unit 210 sets the edge detection flag F1 to ON at the time T14.

On the other hand, since the level detection circuit 214 in the normal state does not input the external signal IN, it does not output the level detection signal D2.

When the determination unit 211 confirms that the edge detection flag F1 is turned ON at the time T14, the determination unit 211 sets the waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the level detection flag F2 is turned ON before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at the time T15 when the waiting time Tw has elapsed, and sets the abnormality determination flag F4 to ON.

Further, FIG. 8 is another timing diagram showing the processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the level detection circuit 214 of the input circuit 202 is in an abnormal state. The vertical axis and the horizontal axis are the same as those in FIG.

In the example of FIG. 8, in the level detection circuit 214, for example, the voltage level of the terminal that outputs the level detection signal D2 is temporarily high due to the phenomenon of oscillation of components in the circuit and noise superposition on the wiring. Indicates a state in which a signal corresponding to the level detection signal D2 is abnormally output due to some abnormality such as sticking to.

As shown in the period E4 of FIG. 8, the level detection circuit 214 in the abnormal state outputs a signal corresponding to the level detection signal D2 at the time T16 even though the external signal IN is not input. Therefore, the detection unit 210 sets the level detection flag F2 to ON at the time T17.

On the other hand, since the edge detection circuit 213 in the normal state does not input the external signal IN, it does not output the edge detection signal D1.

When the determination unit 211 confirms that the level detection flag F2 is turned ON at the time T17, the determination unit 211 sets the waiting time Tw and performs monitoring. However, the determination unit 211 does not confirm that the edge detection flag F1 is turned on before the waiting time Tw elapses. As a result, the determination unit 211 determines that the input circuit 202 is in an abnormal state at the time T18 when the waiting time Tw has elapsed, and sets the abnormality determination flag F4 to ON.

As the timing for resetting the abnormality determination flag F4 from ON to OFF in the determination device 204, for example, the time when the notification by the notification unit 212 is completed can be considered.

By the way, in the determination system 215, the input circuit 202 and the determination device 204 may be arranged across a plurality of other devices as described above, so that the other device is one of the detection information signals output from the input circuit 202. It is also conceivable to convert the unit and output it to the determination device 204. In such a case, it is conceivable that the signal of the detection information output by the input circuit 202 and the signal of the detection information input by the determination device 204 may not be the same signal. However, the information that needs to be transmitted from the input circuit 202 to the determination device 204 is information indicating whether or not the internal circuit of the input circuit 202 has detected the external signal IN, and is information about valid or invalid logic. Information. This information is defined as detection information.

The operations of the determination system 215 up to this point will be summarized below.

FIG. 9 is a flowchart showing the processing of the determination system 215. In the flowchart of FIG. 9, the process starts from the point where the determination system 215 inputs the external signal IN from the external device.

In process S901, the edge detection circuit 213 and the level detection circuit 214 of the input circuit 202 input the external signal IN. After that, the process proceeds to process S902.

In the process S902, the edge detection circuit 213 detects the edge of the external signal IN and outputs the detection information. The edge is a feature of the external signal IN in which the voltage level of the signal changes from a low level to a high level. Further, the level detection circuit 214 detects that the voltage level of the external signal IN is in a high level state as a feature of the external signal IN, and outputs the detection information. After that, the process proceeds to process S903a.

Process S903a and process S903b indicate loop processing in the determination system 215. In the loop processing, when the processing proceeds to the processing S903b, the processing is returned to the processing S903a.

In the process S904, it is determined whether or not the detection unit 210 of the determination device 204 has detected at least one of the plurality of detection information input from the input circuit 202. When at least one detection information is detected, the process proceeds to process S905. If no detection information is detected, the process proceeds to process S913.

In the process S905, the detection unit 210 makes the detected detection information and the corresponding detection information valid from invalid. After that, the process proceeds to process S906.

In the process S906, the determination unit 211 of the determination device 204 confirms the detection information that has been changed from invalid to valid in the process S905. After that, the process proceeds to process S907.

In the process S907, the determination unit 211 determines whether or not the waiting time Tw is being monitored. If monitoring is in progress, the process proceeds to process S909. If it is not being monitored, the process proceeds to process S908.

In the process S908, the determination unit 211 sets the waiting time Tw and starts monitoring. After that, the process proceeds to process S909.

In the process S909, the determination unit 211 determines whether or not all the detection information processed by the detection unit 210 is valid. If all the detection information is valid, the process proceeds to process S910. If all the detection information is not valid, the process proceeds to process S914.

In the process S910, the determination unit 211 determines that the input circuit 202 is in the normal state. After that, the process proceeds to process S911.

In process S911, the notification unit 212 notifies the determination result of the determination unit 211. After that, the process proceeds to process S910.

In process S912, the detection unit 210 resets the detection information to invalidity, and the determination unit 211 resets the determination result to invalidity. After that, the process ends.

In the process S913, the determination unit 211 determines whether or not the waiting time Tw is being monitored. If monitoring is in progress, the process proceeds to process S914. If it is not being monitored, the process proceeds to process S903b.

In the process S914, the determination unit 211 determines whether or not the waiting time Tw during monitoring has elapsed. If the waiting time Tw has elapsed, the process proceeds to process S915. If the waiting time Tw has not elapsed, the process proceeds to process S903b.

In process S915, the determination unit 211 determines that the input circuit 202 is in an abnormal state. After that, the process proceeds to process S911.

Up to this point, an example will be described in which the internal circuit of the input circuit 202 is configured as a duplicate, and in each circuit, the edge and the high level state, which are the characteristics of the external signal IN, are individually detected and the detection information is output. bottom. However, the characteristics of the external signal IN detected by the internal circuit of the input circuit 202 are not limited to the edge and high level states. The internal circuit of the input circuit 202 may detect the characteristics of the external signal IN different from the edge and the high level state and output the detection information.

Further, the internal circuit of the input circuit 202 may have a multiplexing configuration of 3 or more, and each circuit may individually detect the characteristics of the external signal IN and output the detection information.

FIG. 10 is a block configuration diagram showing a functional block of the drive control unit 110 when the internal circuit of the input circuit 202 has a triple configuration.
As shown in FIG. 10, the input circuit 202 has an internal circuit having a triple configuration of an edge detection circuit 213, a level detection circuit 214, and a pattern detection circuit 1001. Other configurations are the same as in FIG.

When there are a plurality of types of external signal IN to be input, the pattern detection circuit 1001 detects the type of the external signal IN as a feature of the external signal IN and outputs the detection information corresponding to the type.

Further, FIG. 11 is a timing diagram showing the processing of the edge detection circuit 213, the level detection circuit 214, the detection unit 210, and the determination unit 211 when the internal circuit of the input circuit 202 has a triple configuration.
As shown in FIG. 11, the input external signals IN1 and IN2 include the type information K. As shown in the external signals IN1 and IN2, the type information K includes a pattern consisting of a low level state and a high level state of the voltage level corresponding to a plurality of types of the external signal IN.

The input circuit 202 detects the edge, high level state, and type of the external signal IN, and outputs the edge detection signal D1, the level detection signal D2, and the pattern detection signal D3. The edge detection signal D1, the level detection signal D2, and the pattern detection signal D3 are detection information.

The pattern detection signal D3 corresponds to the voltage level pattern in the type information K of the external signal IN, and has different contents like the pattern detection signals D3a and D3b.

As shown in FIG. 11, the pattern detection circuit 1001 detects the patterns of the external signals IN1 and IN2, which are different types from each other, and outputs the pattern detection signal D3a and the pattern detection signal D3b, respectively. The pattern detection signal D3a and the pattern detection signal D3b are the pattern detection signal D3.

Then, the detection unit 210 corresponds to each of the three detection information input from the input circuit 202, that is, the edge detection signal D1, the level detection signal D2, and the pattern detection signal D3, in the same manner as in the processes of FIGS. Each of the edge detection flag F1, the level detection flag F2, and the pattern detection flag F5 is changed from OFF to ON. Further, the determination unit 211 determines that the input circuit 202 is in the normal state when it determines that all the flags are valid from invalid within the waiting time Tw.

Here, the pattern detection circuit 1001 is referred to as a third detection circuit. The third feature is the feature of the external signal IN detected by the pattern detection circuit 1001. Then, among the plurality of detection information output by the input circuit 202, the pattern detection signal D3 output by the pattern detection circuit 1001 is used as the third detection information. Then, the detection information indicating that the detection unit 210 has detected the pattern detection signal D3 is used as the third detection information.

By detecting the type of the external signal IN in the input circuit 202 in this way, the microcomputer 201 of the drive control unit 110 distinguishes and corresponds to the external signal IN having a plurality of types based on the input pattern detection signal D3. It becomes possible to execute a predetermined process. That is, the microcomputer 201 of the drive control unit 110 can execute while distinguishing a plurality of predetermined processes.

Further, an interval time Ti is provided so that the determination device 204 does not confuse and process the detection information output by detecting the plurality of external signal INs input in succession by the input circuit 202. think of. That is, the interval time Ti is a time for the detection unit 210 and the determination unit 211 to perform processing based on a plurality of detection information corresponding to the same external signal IN.

As shown in FIG. 11, the determination unit 211 sets the interval time Ti1 after the determination process, or sets the interval time Ti2 after the waiting time Tw elapses, so that the detection unit 210 and the determination unit 211 are external. It becomes possible to distinguish a set of detection information output with the input of the signal IN. After the determination process by the determination unit 211 is a time when the normal determination flag F3 or the abnormality determination flag F4 becomes effective.

This also has the effect of enabling the microcomputer 201 of the drive control unit 110 to input a plurality of types of command signals and execute a plurality of predetermined processes.

In the internal circuit having the input circuit 202 in a duplicate configuration, any two of the above-mentioned first feature, second feature, and third feature are detected and the detection information is output. Is also good. For example, the first feature and the third feature are detected and the first detection information and the third detection information are output, or the second feature and the third feature are detected and the second detection information and the second detection information and The third detection information is output.

Further, a modified example of the determination system 215 will be described.
The input circuit 202 inputs an external signal IN in which the voltage level of the signal is maintained at a high level or a low level depending on the control content. The microcomputer 201 determines whether the voltage level of the input external signal IN is a high level or a low level, and executes a predetermined process corresponding to each voltage level.

FIG. 12 is a block configuration diagram showing a functional block of the drive control unit 110 as a modification of the determination system 215.
As shown in FIG. 12, the input circuit 202 has an internal circuit having a triple configuration of an edge detection circuit 1201, a high level detection circuit 1202, and a low level detection circuit 1203.
Further, as shown in FIG. 12, the determination device 204 includes a detection unit 1204 different from that in FIG.
Other configurations are the same as in FIG.

FIG. 13 is a timing diagram showing processing in a modified example of the determination system 215.

The edge detection circuit 1201 of the input circuit 202 outputs the edge detection signal D4 when it detects a change in the voltage level of the external signal IN from a low level to a high level and a change from a high level to a low level.
Further, the high level detection circuit 1202 outputs the high level detection signal D5 when it detects that the voltage level of the external signal IN is at the high level.
Further, the low level detection circuit 1203 outputs the low level detection signal D6 when it detects that the voltage level of the external signal IN is at the low level.

Then, when the edge detection signal D4 is input from the input circuit 202, the detection unit 1204 of the determination device 204 invalidates the edge detection flag F6.
Further, when the high level detection signal D5 or the low level detection signal D6 is input from the input circuit 202, the detection unit 1204 disables the level detection flag F7 from invalidity.

Then, the determination unit 211 of the determination device 204 determines whether the edge detection flag F6 and the level detection flag F7 are valid from invalid within the waiting time Tw in the same manner as in FIGS. Determines if is in a normal state.

In this way, the detection unit 1204 can also associate one detection information with a plurality of detection information output from the input circuit 202.

Here, the edge detection circuit 1201 of the input circuit 202 is a fourth detection circuit, the high level detection circuit 1202 is a fifth detection circuit, and the low level detection circuit 1203 is a sixth detection circuit. Then, the edge detection signal D4 output by the edge detection circuit 1201 is used as the fourth detection information, the high level detection signal D5 output by the high level detection circuit 1202 is used as the fifth detection information, and the low level detection circuit 1203 outputs the information. The low level detection signal D6 is used as the sixth detection information. Then, the edge detection flag F6 corresponding to the edge detection signal D4 is used as the fourth detection information, and the level detection flag F7 corresponding to the high level detection signal D5 or the low level detection signal D6 is used as the fifth detection information.

Further, another modification of the determination system 215 will be described with reference to FIG.
The input circuit 202 inputs an external signal IN whose signal voltage level is maintained at a high level or a low level according to the control content, and the microcomputer 201 inputs whether the voltage level of the input external signal IN is high or low. It is the same as the above-mentioned modification in that it is determined whether it is a level and a predetermined process corresponding to each voltage level is executed.

The input circuit 202 has an internal circuit having a quadruple configuration of a high level edge detection circuit 1701, a low level edge detection circuit 1702, a high level voltage detection circuit 1703, and a low level voltage detection circuit 1704.
Other configurations are the same as in FIG.

When the high-level edge detection circuit 1701 of the input circuit 202 detects a change in the voltage level of the external signal IN from a low level to a high level, it outputs a high-level edge detection signal D7.
Further, the low level edge detection circuit 1702 of the input circuit 202 outputs the low level edge detection signal D8 when it detects a change in the voltage level of the external signal IN from the high level to the low level.
Further, when the high level voltage detection circuit 1703 detects that the voltage level of the external signal IN is at the high level, it outputs the high level voltage detection signal D9.
Further, when the low level voltage detection circuit 1704 detects that the voltage level of the external signal IN is at the low level, the low level voltage detection circuit 1704 outputs the low level voltage detection signal D10.

Then, when the high level edge detection signal D7 is input from the input circuit 202, the detection unit 1705 of the determination device 204 turns the high level edge detection flag F8 from OFF to ON.
Further, when the low level edge detection signal D8 is input from the input circuit 202, the detection unit 1705 of the determination device 204 turns the low level edge detection flag F9 from OFF to ON.
Further, when the high level voltage detection signal D9 is input from the input circuit 202, the detection unit 1705 turns the high level voltage detection flag F10 from OFF to ON.
Further, when the low level voltage detection signal D10 is input from the input circuit 202, the detection unit 1705 turns the low level voltage detection flag F11 from OFF to ON.

Then, when the determination unit 1706 of the determination device 204 confirms that at least one of the high level edge detection flag F8 and the high level voltage detection flag F10 is ON, the high level edge detection flag F8 and the high level voltage detection flag F10 Both of the above determine whether or not the input circuit 202 is in the normal state by determining whether or not the input circuit 202 changes from OFF to ON within the waiting time Tw.
Further, when the determination unit 1706 of the determination device 204 confirms that at least one of the low level edge detection flag F9 and the low level voltage detection flag F11 is ON, the low level edge detection flag F9 and the low level voltage detection flag F11 Both of the above determine whether or not the input circuit 202 is in the normal state by determining whether or not the input circuit 202 changes from OFF to ON within the waiting time Tw.

In this way, the determination unit 1706 associates at least two or more of the plurality of detection information in advance, determines whether or not all the detection information associated within the waiting time Tw is valid, and determines whether the input circuit 202 It is also possible to determine if is normal.

Further, it is conceivable that any of the internal circuits having a multiplexed configuration of the input circuit 202 can detect a plurality of high-level, middle-level, and low-level voltage levels as a feature of the external signal IN. At this time, even when the internal circuit that detects a plurality of voltage levels outputs the detection information corresponding to each voltage level, the detection unit 210 corresponds to each detection information in the same manner as described above. By validating the detected detection information from invalid, the determination unit 211 can determine the normal state of the input circuit 202.

That is, in the determination device 204 of the first embodiment, the detection unit 210 arbitrarily associates the plurality of detection information input from the input circuit 202 with the plurality of detection information based on the settings in advance, and the input detection is performed. Since the detection information corresponding to the information is enabled from invalid and the determination unit 211 is configured to distinguish the group of detection information to be monitored within the waiting time Tw, it is flexible according to the specifications of the electronic control system 101 and the input circuit 202. It is possible to execute the determination process of the normal state of the input circuit 202.

Further, the determination system 215 can be applied not only to the signal input between the drive control unit 110 and the vehicle control unit 111 but also to the signal input between other devices.

As described above, according to the first embodiment, the determination device 204 multiplexizes in the input circuit 202 whether or not the input circuit 202 for inputting the external signal IN from the external device is in the normal state. Since the determination is made based on the detection information output from the internal circuit, the effect of preventing the electronic control system 101 from executing a predetermined process when the input circuit 202 is in an abnormal state can be obtained.

That is, it is possible to prevent the electronic control system 101 from malfunctioning due to an abnormality generated in the input circuit 202.

This means that the electronic control system 101 determines that the input circuit 202 is in the normal state and executes a predetermined process, so that the reliability of the operation of the electronic control system 101 is guaranteed more than before.

Further, according to the first embodiment, since the input circuit 202 has a multiplex configuration of the internal circuit, it is possible to improve the accuracy when the input circuit 202 detects the external signal IN. As a result, the effect of increasing the noise immunity of the input circuit 202 can be obtained.

Further, according to the first embodiment, the input circuit 202 is configured to detect the pattern of the type information K of the external signal IN as a feature of the external signal IN and output the detection information corresponding to the detected pattern. Therefore, even if a plurality of types of external signal INs are input to the input circuit 202, the electronic control system 1401 can execute a plurality of predetermined processes corresponding to the plurality of types of external signal INs while distinguishing them. ..

Further, according to the first embodiment, the determination unit 211 provides an interval time Ti so that the determination device 204 can collectively process the detection information in which the same external signal IN is detected in the input circuit 202. Therefore, even if the input circuit 202 is made to input a plurality of types of external signal INs, it is possible to prevent the determination device 204 from processing the plurality of types of external signal INs together. As a result, even when the electronic control system 101 continuously handles a plurality of external signal INs, it is possible to obtain an effect that each predetermined process corresponding to the plurality of external signal INs can be reliably executed.

Further, according to the first embodiment, the detection unit 1204 of the determination device 204 detects the high level detection signal D5 and the low level detection signal D6 input from the input circuit 202 in association with the level detection flag F7, and detects the detection information. Is configured to output, so even if the input external signal IN is a signal that switches the voltage level between high level and low level and controls it, the determination unit 211 of the determination device 204 is the input circuit 202. It is possible to perform the normal state determination process.

Embodiment 2.
In the first embodiment, the determination system 215 constantly determines whether or not the input circuit 202 is in the normal state. In the second embodiment, the electronic control system 1401 of the electric drive vehicle 1400 is provided with the normal operation mode and the test mode, and the determination system 1501 makes a determination only in the test mode. Other than that, it is the same as that of the first embodiment.

FIG. 14 is a device configuration diagram showing a configuration of a device included in the electronic control system 1401 for the electric drive vehicle 1400 according to the second embodiment of the present invention. In FIG. 14, the description of the parts common to the configuration shown in FIG. 1 of the first embodiment will be omitted.

As shown in FIG. 14, the electrically driven vehicle 1400 further includes a motor 1402 and a power split mechanism 1403 as compared with the vehicle 100 of the first embodiment.
The electronic control system 1401 refers to an electrical component excluding the wheels 104 from the configuration of the vehicle 100.

The motor 1402 is an electric motor such as an AC motor that generates power by using the electric power supplied from the battery 105 based on the control from the drive control unit 1405. The power generated by the motor 1402 is transmitted to the wheels 104 as the driving force of the electric drive vehicle 1400 via the power split mechanism 1403.

The power split mechanism 1403 is a device that includes a mechanism such as a planetary gear and a clutch, and integrates or distributes and outputs the power input from the engine 102 and the motor 1402. The power split mechanism 1403 outputs the rotational force to the wheels 104 only by the power from the engine 102 based on the control from the drive control unit 1405, or the power of the engine 102 and the motor 1402 is used in combination to output the rotational force to the wheels 104. It is possible to output the rotational force or switch to either.

The electronic control system 1401 of the electric drive vehicle 1400 reduces or stops the output of the engine 102 and instead increases the output of the motor 1402 in order to suppress the exhaust gas discharged from the electric drive vehicle 1400, for example. It is possible to suppress the generation of exhaust gas caused by the output of the engine 102.

By the way, the vehicle control unit 1404 and the drive control unit 1405 of the electric drive vehicle 1400 perform the power switching control of the engine 102 and the motor 1402 described above based on the traveling state of the vehicle and the operation by the intention of the occupant. Therefore, the vehicle control unit 1404 and the drive control unit 1405 shown in FIG. 14 of the second embodiment execute more control than the vehicle control unit 111 and the drive control unit 110 of the vehicle 100 of the first embodiment. As a result, the electronic control system 1401 of the electrically driven vehicle 1400 will consume more power from the battery 105.

In FIG. 14, when the electronic control system 1401 of the electric drive vehicle 1400 and the electronic control system 101 of the first embodiment are compared, a supply path in which an increase in the amount of power supplied from the battery 105 is expected is indicated by a two-point broken arrow. Indicated by.

As described above, it is considered that the electronic control system 1401 of the electric drive vehicle 1400 consumes more electric power than the vehicle 100 without the motor drive, especially when traveling. Therefore, it is desirable that the electronic control system 1401 efficiently uses the electric power supplied from the battery 105 by reducing the processing of the devices constituting the system while ensuring the reliability of operation.

Therefore, in the second embodiment, the electronic control system 1401 is provided with a normal operation mode and a test mode. Then, the electronic control system 1401 switches between the normal operation mode and the test mode, and causes the determination device 204 to execute the determination process of the normal state of the input circuit 202 only in the test mode. By doing so, the electronic control system 1401 can reduce the processing without constantly performing the normal state determination processing of the input circuit 202, and can secure the reliability of the operation.

By the way, the reliability of the functional safety of a vehicle has been standardized, for example, by defining a mechanism for detecting a failure in the functional safety standard ISO26262.

Therefore, the reliability of the operation of the electronic control system 1401 is set by setting the frequency with which the electronic control system 1401 executes the test mode based on the standard of ASIL (Automotive Safety Intelligence Level) in ISO26262. Is guaranteed.

In the second embodiment, switching between the normal operation mode and the test mode is abbreviated as mode switching. Further, the normal operation mode is defined as the first mode, and the test mode is defined as the second mode.

Further, in the electronic control system 1401, the mode switching control is performed by the vehicle control unit 1404 or the drive control unit 1405.

When the vehicle control unit 1404 controls the switching to the test mode, the vehicle control unit 111 instructs the drive control unit 110 to switch to the test mode. Further, when the drive control unit 110 controls the switching to the test mode, the drive control unit 110 instructs the vehicle control unit 111 to switch to the test mode and prompts the output of the test signal.

FIG. 15 is a block configuration diagram showing a functional block of the drive control unit 1405 for inputting a command signal from the vehicle control unit 1404. The determination system 1501 further includes a switching unit 1502. In FIG. 15, the description of the portion common to the functional block shown in FIG. 2 of the first embodiment will be omitted.

The switching unit 1502 is provided between the input circuit 202 and the determination device 204. Then, the switching unit 1502 switches whether or not to input the detection information input from the input circuit 202 to the determination device 204 according to the instruction of mode switching to the normal operation mode or the test mode.
The mode switching at this time is performed by the vehicle control unit 1404 or the drive control unit 1405 executing a mode switching instruction.

The switching unit 1502 does not input the plurality of detection information input from the input circuit 202 to the determination device 204 in the normal operation mode. Further, in the test mode, the switching unit 1502 inputs a plurality of detection information input from the input circuit 202 to the determination device 204.

Here, similarly to the determination system 215 of the first embodiment, the determination system 1501 performs the determination process of the normal state of the input circuit 202 without depending on the arrangement of each configuration. That is, the switching unit 1502 may be arranged either inside or outside the microcomputer 201, and exchanges information with the drive control unit 1405 or the external device via the signal transmission line L or the communication circuit 203. ..

Then, in the normal operation mode, a plurality of detection information that the switching unit 1502 did not input to the determination device 204 can be input to the device inside the microcomputer 201 via the signal transmission line L or the communication circuit 203. , Microcomputer 201 can execute a predetermined process based on the detection information.

On the other hand, in the test mode, the switching unit 1502 inputs the detection information to the determination device 204, and the microcomputer 201 performs a predetermined process based on the determination result of the determination process of the determination device 204 in the same manner as in the first embodiment. Can be executed.

That is, since the determination device 204 performs the determination process only in the test mode, the determination device 204 does not input the detection information and perform the determination process in the normal operation mode. As a result, the power consumption of the drive control unit 110 can be suppressed. Further, since the determination device 204 only needs to operate in the test mode, it is possible to further reduce the power consumption by stopping the determination device 204 in the normal operation mode.

As described above, suppressing the power consumption in the determination system 1501 enables the electronic control system 1401 to use the power stored in the battery 105 more efficiently than in the first embodiment.

Next, an operation in which the electronic control system 1401 executes the determination system 1501 while switching modes will be described.

FIG. 16 is a flowchart showing a process of executing the normal operation mode and the test mode in the electronic control system 1401.

In FIG. 16, the vehicle control unit 1404 activates the drive control unit 1405 with the activation of the electronic control system 1401, and then instructs the drive control unit 1405 to switch to the test mode. Then, the vehicle control unit 1404 instructs the drive control unit 1405 to switch to the normal operation mode or notifies the outside of the abnormal state based on the determination result of the determination system 1501.

Here, the process of the determination system 1501 shown in the flowchart of FIG. 9 in the first embodiment is defined as the defined process S1606.

In process S1601, the vehicle control unit 1404 activates the drive control unit 1405. After that, the process proceeds to process S1602.

In the process S1602, the vehicle control unit 1404 determines whether or not the drive control unit 1405 is in the activated state. If the drive control unit 1405 is in the activated state, the process proceeds to process S1603. If the drive control unit 1405 is not in the activated state, the process proceeds to process S1611.

In the process S1603, the vehicle control unit 1404 instructs the drive control unit 1405 to switch to the test mode. After that, the process proceeds to process S1604.

In the process S1604, the switching unit 1502 of the drive control unit 1405 and the microcomputer 201 switch to the test mode. When switching to the test mode is performed, the microcomputer 201 activates the determination device 204 in the stopped state. After that, the process proceeds to process S1605.

In process S1605, the vehicle control unit 1404 outputs a test signal to the drive control unit 1405. After that, the process proceeds to process S1606.

In the defined process S1606, the determination system 1501 performs the determination process. After that, the process proceeds to process S1607.

In the process S1607, the vehicle control unit 1404 confirms the determination result of the determination system 1501 and determines whether or not the input circuit 202 is in the normal state. If the input circuit 202 is in the normal state, the process proceeds to process S1608. If the input circuit 202 is not in the normal state, the process proceeds to process S1609.

In the process S1608, the vehicle control unit 1404 instructs the drive control unit 1405 to switch to the normal operation mode. After that, the process proceeds to process S1609.

In the process S1609, the switching unit 1502 of the drive control unit 1405 and the microcomputer 201 switch to the normal operation mode. The microcomputer 201 stops the operation of the determination device 204 when the mode is switched to the normal operation mode. After that, the process ends.

In the process S1610, the drive control unit 1405 notifies the vehicle control unit 1404 that the input circuit 202 is in an abnormal state. After that, the process ends.

In the process S1611, the vehicle control unit 1404 determines whether or not the start-up time, which is the reference required for starting the drive control unit 1405, has elapsed. If the startup time has elapsed, the process proceeds to process S1612. If the startup time has not elapsed, the process proceeds to process S1602.

In the process S1612, the vehicle control unit 1404 notifies the outside that the drive control unit 1405 is in an abnormal state. After that, the process ends.

The execution of the test mode in the electronic control system 1401 is not limited to the time when the system is started as described above, for example, when the passenger of the electric drive vehicle 1400 operates the shift lever to the parking position or pulls the side brake. The test mode may be executed at a timing such as when the electric drive vehicle 1400 is in a stopped state and is not expected to be driven immediately.

Further, the configuration of the determination system 215 of the first embodiment may be arbitrarily combined in the first and second embodiments, such as applying the configuration of the determination system 215 to the second embodiment.

As described above, according to the second embodiment, the electronic control system 1401 is provided with the normal operation mode and the test mode, and the determination system 1501 is configured to determine the normal state of the input circuit 202 in the test mode. Therefore, if it is determined that the input circuit 202 is in the normal state in the test mode, it means that in the normal operation mode, at least one of the internal circuits of the input circuit 202 detects the external signal IN as in the prior art. However, it can be determined that it is not due to an abnormality in the internal circuit but due to distortion of the external signal IN. As a result, it is possible to continue the operation while guaranteeing the reliability of the electronic control system 1401.

This is because the determination system 1501 of the second embodiment executes the test mode according to the standard in ISO 26262, so that the reliability of the operation of the electronic control system 1401 is guaranteed.

Further, according to the second embodiment, since the determination system 1501 is provided with the switching unit 1502, the determination process of the determination system 1501 is executed only in the test mode in accordance with the input of the external signal IN, and the determination process is executed only in the test mode. Sometimes it is possible to prevent it from running. As a result, since the power consumption in the determination device 204 can be suppressed in the normal operation mode, the electronic control system 1401 can utilize the power stored in the battery 105 more efficiently than in the first embodiment. become able to do.

100 Vehicle 101, 1401 Electronic control system 102 Engine 103 Transmission mechanism 104 Wheel 105 Battery 106 Generator 107 Brake system 108 Braking mechanism 109 Speed detection unit 110, 1405 Drive control unit 111, 1404 Vehicle control unit 201 Microcomputer 202 Input circuit 203 Communication circuit 204 Judgment device 215, 1501 Judgment system 1400 Electric drive vehicle 1402 Motor 1403 Power split mechanism

Claims (11)

A plurality of detection information output from the input circuit indicates whether or not the input circuit for detecting the single external signal by the plurality of internal circuits when a single external signal is input from the external device is in a normal state. It is a judgment device that judges based on
Each of the plurality of internal circuits detects different features in the single external signal.
The input circuit outputs the plurality of detection information corresponding to the different features, and outputs the plurality of detection information.
The determination device is
Each of the plurality of detection information is input separately, and a plurality of detection information corresponding to each of the plurality of detection information indicating that each of the plurality of detection information has been detected is individually invalidated to valid. A detector that performs processing and
When at least one of the plurality of detection information becomes valid from invalid by the processing in the detection unit, all of the plurality of detection information corresponding to each of the plurality of detection information is invalid within a predetermined time. It is determined whether or not the input circuit is valid, and when all of the plurality of detection information becomes valid from invalid within the predetermined time, it is determined that the input circuit is in a normal state, and the plurality of detection information are determined within the predetermined time. A determination unit that determines that the input circuit is not in a normal state when all of the detection information of
Judgment device equipped with. A plurality of detection information output from the input circuit indicates whether or not the input circuit for detecting the single external signal by the plurality of internal circuits when a single external signal is input from the external device is in a normal state. It is a judgment device that judges based on
Each of the plurality of internal circuits detects different features in the single external signal.
The input circuit outputs the plurality of detection information corresponding to the different features, and outputs the plurality of detection information.
The determination device is
A detection unit that separately inputs each of the plurality of detection information and inputs a plurality of detection information corresponding to each of the plurality of detection information, indicating that each of the plurality of detection information has been detected.
The input circuit is in a normal state based on whether or not the other plurality of detection information is input within a predetermined time after at least one of the plurality of detection information is input in the detection unit. A judgment unit that determines whether or not
Judgment device equipped with. The determination unit confirms the plurality of detection information corresponding to the same single external signal after the determination process of whether or not the input circuit is in the normal state or after the lapse of the predetermined time. Set the interval time for,
The determination device according to claim 1 or 2 , wherein the determination device is characterized by the above. The determination device and the input circuit according to any one of claims 1 to 3 are provided.
A determination system used in an electronic control system for a vehicle that executes a predetermined process corresponding to the single external signal based on the plurality of detection information output from the input circuit. The input circuit is used as the internal circuit.
A first detection circuit that detects a first feature in the single external signal input from the external device and outputs the first detection information among the plurality of detection information.
A second detection circuit that detects the second feature in the single external signal input from the external device and outputs the second detection information among the plurality of detection information.
Have,
The detection unit
When the first detection information is input, the first detection information corresponding to the first detection information is changed from invalid to valid.
When the second detection information is input, the second detection information corresponding to the second detection information is changed from invalid to valid.
The determination system according to claim 4 , wherein the determination system is characterized in that. The first detection circuit detects a change from a low level to a high level at the voltage level of the single external signal as the first feature.
The second detection circuit detects a high level at the voltage level of the single external signal as the second feature.
The determination system according to claim 5 , wherein the determination system is characterized in that. The input circuit is used as the internal circuit.
A first detection circuit that detects a change from a low level to a high level in the voltage level of the single external signal and outputs the first detection information among the plurality of detection information.
A second detection circuit that detects a high level at the voltage level of the external device and outputs the second detection information among the plurality of detection information.
A third detection that detects a pattern consisting of a low level and a high level at the voltage level of the single external signal, and outputs a third detection information corresponding to the pattern among the plurality of detection information. circuit,
Have at least two of them
The detection unit
When the input circuit has the first detection circuit and the first detection information is input, the first detection information corresponding to the first detection information among the plurality of detection information is invalidated. Valid from
When the input circuit has the second detection circuit and the second detection information is input, the second detection information corresponding to the second detection information among the plurality of detection information is invalidated. Valid from
When the input circuit has the third detection circuit and the third detection information is input, the third detection information corresponding to the third detection information among the plurality of detection information is invalidated. Valid from,
The determination system according to claim 4 , wherein the determination system is characterized in that. The input circuit
A fourth detection circuit that detects a change from low level to high level or a change from high level to low level at the voltage level of the single external signal and outputs a fourth detection information as a plurality of detection information.
A fifth detection circuit that detects a high level at the voltage level of the single external signal and outputs the fifth detection information as the plurality of detection information.
A sixth detection circuit that detects the low level of the single external signal at the voltage level and outputs the sixth detection information as the plurality of detection information.
Have,
The detection unit
When the fourth detection information is input, the fourth detection information corresponding to the fourth detection information is invalidated and enabled, and when the fifth detection information or the sixth detection information is input, the fifth detection information is input. The detection information of the above or the fifth detection information corresponding to the sixth detection information is changed from invalid to valid.
The determination system according to claim 4 , wherein the determination system is characterized in that. The judgment system is
Further, a switching unit for separately inputting each of the plurality of detection information output by the input circuit is provided.
The switching unit is
When the switch to the first mode is instructed from the outside, the plurality of detection information input from the input circuit is not output to the determination device.
When instructed to switch to the second mode from the outside, the plurality of detection information input from the input circuit is output to the determination device.
The determination system according to any one of claims 4 to 8 , wherein the determination system is characterized in that. An input step of inputting each of the plurality of detection information output from the input circuit according to claim 1.
A detection step of individually detecting the plurality of detection information input in the input step and validating the detected detection information and the corresponding detection information from the plurality of detection information from invalidity.
When at least one of the plurality of detection information becomes valid from invalid in the detection step, a determination step of determining whether or not all of the plurality of detection information becomes valid within a predetermined time, and a determination step.
A determination step of determining whether or not the input circuit is in a normal state based on the determination in the determination step,
Judgment method having. An input step of inputting each of the plurality of detection information output from the input circuit according to claim 1.
A detection step in which each of the plurality of detection information is input separately, and a plurality of detection information corresponding to each of the plurality of detection information is input, indicating that each of the plurality of detection information has been detected.
In the detection step, the input circuit is in a normal state based on whether or not the other plurality of detection information is input within a predetermined time after at least one of the plurality of detection information is input. Judgment process to determine whether or not
Judgment method having.

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