WO2019082235A1 - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Semiconductor device and manufacturing method for semiconductor device

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Publication number
WO2019082235A1
WO2019082235A1 PCT/JP2017/038146 JP2017038146W WO2019082235A1 WO 2019082235 A1 WO2019082235 A1 WO 2019082235A1 JP 2017038146 W JP2017038146 W JP 2017038146W WO 2019082235 A1 WO2019082235 A1 WO 2019082235A1
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WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor device
manufacturing
gettering layer
resist
Prior art date
Application number
PCT/JP2017/038146
Other languages
French (fr)
Japanese (ja)
Inventor
平治 小林
隆俊 増田
Original Assignee
ウルトラメモリ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウルトラメモリ株式会社 filed Critical ウルトラメモリ株式会社
Priority to PCT/JP2017/038146 priority Critical patent/WO2019082235A1/en
Priority to JP2019549685A priority patent/JPWO2019082235A1/en
Priority to CN201780096095.3A priority patent/CN111247621A/en
Publication of WO2019082235A1 publication Critical patent/WO2019082235A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
  • a layer called a gettering layer is formed in the vicinity of the back surface of the silicon substrate (the surface opposite to the surface on which the semiconductor element is formed).
  • the gettering layer can capture heavy metal elements.
  • the gettering layer can suppress the entry of contaminants into the silicon substrate.
  • a gettering layer is formed on the back surface of the silicon substrate. Specifically, a gettering layer is formed on the back surface of the silicon substrate by implanting an impurity such as argon ions. Also in the method of manufacturing a semiconductor device disclosed in Non-Patent Document 1, a gettering layer is formed by implanting argon ions into a silicon substrate. Thus, since impurities such as copper can be captured by the gettering layer, contamination of the silicon substrate with contaminants can be suppressed.
  • the silicon substrate is thinned further (for example, 20 ⁇ m or less), it is conceivable that ions implanted into the silicon substrate may reach the surface of the silicon substrate. Ions reaching the surface of the silicon substrate are considered to affect the semiconductor element, which is not preferable. Therefore, even when the silicon substrate is thinned, it is preferable that the gettering layer be formed.
  • An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a gettering layer even if the substrate is further thinned, and a semiconductor device having a gettering layer formed thereon.
  • the present invention is a method of manufacturing a semiconductor device in which a plurality of substrates are stacked, which includes the step of stacking a second substrate on a first substrate, and the surface of the second substrate, A step of polishing the surface opposite to the surface on which the device layer is formed, and irradiating cluster ions containing a constituent element contributing to gettering toward the surface of the polished second substrate to form cluster ions And a step of forming a gettering layer containing the constituent elements of
  • the surface on which the device layer is to be formed is relative to the first substrate. It is preferable to be disposed opposite to each other.
  • the surface of the second substrate opposite to the surface on which the device layer is formed is the second surface. It is preferable to be disposed opposite to one substrate.
  • the gettering layer In the step of forming the gettering layer, it is preferable that the gettering layer be formed in a partial region of the surface of the second substrate.
  • a position at which the resist overlaps with the element region formed in the second substrate and whose distance to the gettering layer is equal to or less than a predetermined value Preferably, it is formed in
  • the resist is formed in the second substrate, and in the boundary exposed to the polished surface of the second substrate, at the boundary where the polarity changes. Preferably, they are formed at overlapping positions.
  • the resist is preferably formed to be thicker than a thickness of the gettering layer.
  • the cluster ions be irradiated at positions surrounding the metal-filled vias.
  • the present invention is a semiconductor device in which a plurality of substrates are stacked, comprising: a first substrate; and a second substrate superimposed on the first substrate, at least the second
  • the present invention relates to a semiconductor device provided with a gettering layer containing constituent elements of cluster ions, the gettering layer being formed on the polished surface side of the second substrate.
  • the present invention it is possible to provide a method of manufacturing a semiconductor device capable of forming a gettering layer, and a semiconductor device having a gettering layer formed thereon, even when the substrate is further thinned.
  • FIG. 7 is a schematic side view of the semiconductor device when stacking two substrates in the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a side view of the semiconductor device after one of the substrates is polished in the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 7 is a side view of the semiconductor device when cluster ions are irradiated to the semiconductor device in the method of manufacturing the semiconductor device of the first embodiment;
  • FIG. 4 is a partial enlarged cross-sectional view of the semiconductor device shown in FIG. 3;
  • FIG. 7 is a side view of the semiconductor device when the substrates are further superposed in the method of manufacturing the semiconductor device of the first embodiment.
  • FIG. 7 is a side view of the semiconductor device when a further substrate is stacked in the method of manufacturing the semiconductor device of the first embodiment.
  • FIG. 13 is a side view of the semiconductor device after polishing a further substrate in the method of manufacturing the semiconductor device of the first embodiment. In the semiconductor device of a 1st embodiment, it is a side view of the semiconductor device at the time of irradiating a cluster ion to the further substrate.
  • FIG. 6 is a partially enlarged cross-sectional view of a part of a substrate of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 18 is a partial enlarged cross-sectional view of a semiconductor device in which a resist layer is formed when cluster ions are irradiated in the method of manufacturing a semiconductor device of the second embodiment.
  • FIG. 13 is a partially enlarged step view showing the semiconductor substrate when two substrates are superimposed on each other in the method for manufacturing a semiconductor device of the second embodiment.
  • FIG. 10 is a partially enlarged cross-sectional view of a portion of a substrate of a semiconductor device according to a third embodiment of the present invention;
  • FIG. 19 is a partially enlarged step surface view of the semiconductor device when cluster ions are irradiated in the method of manufacturing a semiconductor device according to the third embodiment.
  • FIG. 16 is a partially enlarged step view of a semiconductor device in which a gettering layer is formed around a via in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor device is formed by stacking a plurality of substrates.
  • the semiconductor device is, for example, a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • a gettering layer is formed on each of the substrates to capture contaminants such as heavy metals.
  • the gettering layer is formed along the surface direction of the substrate.
  • the gettering layer captures contaminants such as heavy metals. Thereby, the gettering layer suppresses the contamination inside the substrate by the contaminant.
  • the semiconductor device 1 is formed, for example, by laminating a plurality of substrates 10 as shown in FIG.
  • Each of the substrates 10 comprises a substrate body 20 and a device layer 30.
  • the substrate body 20 is, for example, a silicon substrate.
  • the substrate body 20 has a gettering layer 40 (see FIG. 4) on one surface side in the thickness direction.
  • the substrate 10 (hereinafter referred to as the first substrate 10a) disposed at the lowermost position (the lower side of the sheet of FIG. 1) may be any of the plurality of substrates 10 in the following description.
  • the substrate body 20a) is formed thicker.
  • the substrate main body 20b of the other substrate 10 (hereinafter referred to as a second substrate 10b) is formed thinner. That is, in the present embodiment, the second substrate 10b having the thinner substrate body 20b is disposed so as to overlap on one first substrate 10a having the thicker (thickest) substrate body 20a. As shown in FIG.
  • a plurality of regions having different polarities are formed in the substrate body 20.
  • “a” is attached to the reference numeral of the configuration of the first substrate 10 a
  • “b” is attached to the reference numeral of the configuration of the second substrate 10 b.
  • neither “a” nor “b” is attached, it indicates that any substrate 10 may be provided.
  • the gettering layer 40 is a so-called strained layer (crystal defect layer).
  • the gettering layer 40 of the second substrate 10b contains a constituent element (for example, carbon or hydrogen atom) of cluster ions, and is formed by irradiation (implantation) of cluster ions to the substrate body 20b.
  • the gettering layer 40b is formed with a predetermined thickness from the surface on one side in the thickness direction of the substrate body 20b. In the present embodiment, the gettering layer 40 b is formed, for example, to a thickness of 100 nm or less.
  • the device layer 30 is, for example, a layer including the transistors 31a and 31b, the insulating layers 32a and 32b, and the like.
  • the device layer 30 is disposed on the other side in the thickness direction of the substrate body 20.
  • the device layer 30a is disposed on the side of the first substrate 10a having the thicker substrate body 20a, which faces upward (in the plane of FIG. 1) of the substrate body 20a.
  • the device layer 30b is disposed on the side of the second substrate 10b having the thinner substrate body 20b, which faces the lower side of the substrate body 20b (downward in the drawing of FIG. 1).
  • the device layer 30 electrically connects between the adjacent substrates 10.
  • a method of manufacturing the semiconductor device 1 will be described.
  • (d) forming a gettering layer a constituent element (for example, carbon or hydrogen) contributing to gettering toward the surface of the polished second substrate 10b and containing the constituent elements of cluster ions.
  • the step of stacking is performed. As shown in FIG. 1, the first substrate 10a and the second substrate 10b are disposed in a state in which the surfaces (other surfaces) on which the device layers 30a and 30b are formed face each other. Then, the first substrate 10a and the second substrate 10b are overlapped and bonded on the surface of the device layers 30a and 30b.
  • the second substrate 10 b is polished on the other side (the side opposite to the side on which the device layer 30 b is formed). That is, the substrate main body 20b of the second substrate 10b is polished on the other surface side. Thereby, the substrate body 20b of the second substrate 10b is polished on the surface opposite to the surface on which the device layer 30b is formed.
  • the substrate body 20b of the second substrate 10b is polished to a thickness of, for example, 5 to 20 ⁇ m.
  • the step of forming gettering layer 40b is performed. Specifically, as shown in FIG. 3, the gettering layer 40b is formed with a predetermined thickness (for example, 100 nm or less) from one surface of the substrate body 20b of the second substrate 10b. In the present embodiment, the gettering layer 40 b is formed by irradiating cluster ions on one surface side of the substrate body 20 b of the second substrate 10 b. The formation of the gettering layer 40b by irradiation of cluster ions will be described in detail later.
  • substrate 10c is aligned on the 2nd board
  • the third substrate 10c is aligned in a state where the device layer 30 is opposed to one surface of the substrate body 20b of the second substrate 10b.
  • the third substrate 10c is bonded to the second substrate 10b. Then, as shown in FIG. 7, one surface of the substrate body 20c of the third substrate 10c is polished.
  • a gettering layer 40c is formed. Specifically, the gettering layer 40c is formed by irradiating cluster ions (for example, carbon or hydrogen) on one surface side of the substrate main body 20c of the third substrate 10c.
  • cluster ions for example, carbon or hydrogen
  • a cluster ion is, for example, a collection of atoms or molecules including carbon and hydrogen molecules.
  • the energy instantaneously reaches a high temperature of about 1350 to 1400.degree.
  • the cluster ions melt the substrate body 20b by becoming high temperature. Thereafter, the substrate body 20b is rapidly cooled. Thereby, carbon and hydrogen molecules contained in the irradiated cluster ions are dissolved in the vicinity of the surface of one surface of the substrate body 20b.
  • the gettering layer 40b means a layer in which the constituent element of the ion to be irradiated is solid-solved in the lattice position or substitution position of the crystal on the surface of the substrate body 20b.
  • SIMS Secondary Ion Mass Spectrometry, secondary ion mass spectrometry
  • the following effects can be obtained.
  • the step of stacking the second substrate 10b on the first substrate 10a and the surface of the second substrate 10b on which the device layer 30b is formed A step of polishing the opposite surface and irradiation of cluster ions containing a constituent element contributing to gettering toward the surface of the polished second substrate 10b, the gettering layer 40b containing a constituent element of cluster ions And b.
  • the ion implantation region (depth) can be limited to the side opposite to the second substrate 10b. Therefore, it is possible to manufacture the semiconductor device 1 with high reliability by suppressing the ions from reaching the surface of the second substrate 10b on which the device layer 30 is formed.
  • the surface on which the device layer 30b is formed is the surface on which the first substrate 10a is formed. It was made to be arranged oppositely. Thereby, the first substrate 10a and the second substrate 10b can be electrically connected.
  • the semiconductor device 1 includes the first substrate 10 a and the second substrate 10 b stacked on the first substrate 10 a, and at least the second substrate 10 b is a getter containing a constituent element of cluster ions.
  • a ringing layer 40b is provided, and the gettering layer 40b is formed on the polished surface side of the second substrate 10b. As a result, even when the second substrate 10b is thinner, the gettering layer 40b can be formed.
  • the semiconductor device 1 according to the second embodiment differs from the first embodiment in that the gettering layer 40b is formed in a partial region of the surface of the second substrate 10b.
  • the semiconductor device 1 according to the second embodiment is characterized in that the surface opposite to the surface on which the device layer 30b of the second substrate 10b is formed is disposed so as to face the first substrate 10a. It differs from the embodiment.
  • the first substrate 10a is polished in the same manner as the second substrate 10b, and has a gettering layer 40a using cluster ions (see FIG. 11). That is, in the second embodiment, the first substrate 10a and the second substrate 10b are formed in the same configuration.
  • the substrate body 20b of the second substrate 10b has a plurality of regions 50b of different polarities along the surface on which the device layer 30b is formed. Further, the substrate body 20b of the second substrate 10b has another region 60b of different polarity at a deeper position than the plurality of regions 50b of different polarities (the whole of the plurality of regions is referred to as an element region 70).
  • the second substrate 10b is formed thinner than the first embodiment.
  • the substrate body 20b of the second substrate 10b is formed with a thickness of, for example, about 5 ⁇ m.
  • the plurality of regions 50b having different polarities are, for example, regions where the region 51b of the N-well and the region 52b of the P-well are disposed adjacent to each other.
  • the plurality of regions 50b of different polarities are formed with a predetermined thickness from the other surface (opposite surface) of the substrate body 20b of the second substrate 10b.
  • the other regions 60b having different polarities are disposed overlapping the plurality of regions 50b having different polarities, across parts of the plurality of regions 50b having different polarities.
  • the other regions 60b different in polarity are disposed, for example, overlapping the region 51b of the N-well and a part of the region 52b of the P-well.
  • Another region 60b of different polarity is formed with a predetermined thickness. That is, the other regions 60b having different polarities are formed closer to one surface of the substrate body 20b (the surface on which the gettering layer 40b is formed) than the plurality of regions 50b having different polarities.
  • one surface of the second substrate 10b is polished. Specifically, one surface of the substrate body 20b of the second substrate 10b (surface opposite to the surface on which the device layer 30b is formed) is polished. Next, the gettering layer 40b is formed.
  • the step of forming the gettering layer 40b includes the steps of forming a resist 80b on the surface of the second substrate 10b, irradiating the surface of the second substrate 10b and the resist 80b with cluster ions, and removing the resist 80b.
  • a resist 80b is formed on one surface side (polished surface side) of the second substrate 10b.
  • the distance between the resist 80b and the gettering layer 40b in the element regions 70b (the plurality of regions 50b of different polarities and the other regions 60b of different polarities) formed in the second substrate 10b is equal to or less than a predetermined value. It is formed in the position which overlaps with element field 70b.
  • the resist 80 b is formed at a position overlapping with the other region 60 b of different polarity.
  • the gettering layer 40b of a predetermined depth is formed from one surface side of the substrate body 20b of the second substrate 10b. Specifically, the gettering layer 40b is formed at the position of the surface area of the second substrate 10b where the resist 80b is not formed on one surface of the substrate body 20b. On the other hand, the gettering layer 40b is not formed at the position of the surface area where the resist 80b is formed in one surface of the substrate body 20b of the second substrate 10b. That is, the gettering layer 40 b is not formed at a position overlapping with the other region 60 b of different polarity.
  • the step of removing the resist 80b is performed. Thereby, the resist 80b is removed from one surface of the substrate body 20b of the second substrate 10b.
  • the first substrate 10a is also formed in the same manner as the second substrate 10b.
  • the step of laminating the first substrate 10a on the second substrate 10b is performed.
  • the first substrate 10a has the same configuration as the second substrate 10b.
  • the second substrate 10b is bonded in a state in which the first substrate 10a and one surface of the second substrate 10b face each other. That is, the gettering layer of the second substrate 10b is joined in a state of facing the gettering layer 40b of the first substrate 10a.
  • the surface of the second substrate 10b opposite to the surface on which the device layer 30b is formed is the first surface. It was arranged to face the substrate 10a. Thereby, the versatility of the semiconductor device 1 can be enhanced.
  • the gettering layer 40b is formed in a partial region of the surface of the second substrate 10b.
  • the gettering layer 40b can be formed at a position according to the purpose, so that the versatility of the semiconductor device 1 can be further enhanced.
  • the step of forming the gettering layer 40b includes the steps of: forming a resist 80b on the surface of the second substrate 10b; irradiating the surface of the second substrate 10b and the resist 80b with cluster ions; Removing 80b. Thereby, the region which constitutes gettering layer 40b can be determined appropriately.
  • the resist 80b is formed thicker than the thickness for forming the gettering layer 40b. Thus, formation of the gettering layer 40b on the second substrate 10b through the resist 80b can be suppressed.
  • FIG. 12 and 13 a semiconductor device 1 and a method of manufacturing the semiconductor device 1 according to a third embodiment of the present invention will be described with reference to FIGS. 12 and 13.
  • FIG. 12 and 13 the same components will be assigned the same reference numerals, and the description thereof will be omitted or simplified.
  • the semiconductor device 1 according to the third embodiment differs from the second embodiment in that the substrate 10 is formed thinner.
  • the semiconductor device 1 according to the third embodiment is different from that of the second embodiment in that the plurality of regions 50b having different polarities are also exposed to the other surface of the substrate body 20b.
  • the semiconductor device 1 according to the third embodiment is different from the first and second embodiments in that the gettering layers 40b are formed in the plurality of regions 50b having different polarities.
  • the first substrate 10a in the third embodiment is formed in the same configuration as the second substrate 10b.
  • the substrate body 20b of the second substrate 10b has a thickness of, for example, 2 to 5 ⁇ m.
  • the substrate main body 20b of the second substrate 10b is constituted by a plurality of regions 50b of different polarities.
  • the gettering layer 40 b is formed independently in each of the plurality of regions 50 b with different polarities. In other words, the gettering layer 40b is not disposed at the boundary B where the polarities of the plurality of regions 50b of different polarities change.
  • the gettering layer is formed with a predetermined thickness on one side of the substrate body 20b.
  • the step of polishing the second substrate 10b is performed. Thereby, the substrate body 20b of the second substrate 10b is polished to a thickness of 2 to 5 ⁇ m. Next, the step of forming gettering layer 40b is performed.
  • the resist 80b is formed in the second substrate 10b and exposed on the polished surface of the second substrate 10b. In the region where the polarity changes. Next, a step of irradiating cluster ions on the surface of the second substrate 10b and the resist 80b is performed.
  • the gettering layer 40b is formed on one surface of the substrate body 20b of the second substrate 10b.
  • the gettering layer 40b is not formed at a position where the resist 80b is formed on one surface of the substrate body 20b of the second substrate 10b. That is, the gettering layer 40 b is not formed at the boundary B where the polarity changes.
  • gettering layers are formed independently in each of the plurality of regions 50b of which the polarity changes.
  • the resist 80b is removed.
  • the first substrate 10a is also formed in the same manner as the second substrate 10b. Then, in the step of stacking the plurality of substrates 10, the second substrate 10b and the first substrate 10a are stacked as in the first embodiment or the second embodiment.
  • the resist 80b is formed in the second substrate 10b, and overlaps the boundary B where the polarity changes in the area exposed on the polished surface of the second substrate 10b. Formed in position. As a result, it is possible to suppress the occurrence of a leak between the plurality of regions 50b of which the polarity changes.
  • the semiconductor device 1 according to the fourth embodiment and a method of manufacturing the semiconductor device 1 will be described with reference to FIG.
  • the same components will be assigned the same reference numerals, and the description thereof will be omitted or simplified.
  • the semiconductor device 1 according to the fourth embodiment is different from the first to third embodiments in that the second substrate 10b has a via 90b filled with metal as shown in FIG.
  • the semiconductor device 1 according to the fourth embodiment is different from the first to third embodiments in that the gettering layer 40b is formed at a position surrounding the via 90b. Accordingly, in the method of manufacturing the semiconductor device 1 according to the fourth embodiment, in the step of irradiating cluster ions, cluster ions are irradiated at positions surrounding the via 90 b filled with the metal M.
  • the third embodiment is different from the third embodiment.
  • the first substrate 10a has the same configuration as the second substrate 10b.
  • the via 90 b is formed to penetrate the device layer 30 b and the substrate body 20 b in the thickness direction.
  • the via 90b is formed to penetrate the region 52b of the P-well.
  • the via 90 b is formed so as to gradually expand in diameter in the thickness direction from the substrate body 20 b toward the device layer 30 b.
  • the via 90 b is filled with a metal M such as copper, for example. That is, the via 90b is disposed at the position where the wiring is formed.
  • the gettering layer 40 b is formed at a position surrounding the via 90 b. Specifically, the gettering layer 40b is formed at a position surrounding the via 90b on one surface of the substrate body 20b of the second substrate 10b.
  • the step of polishing is the same as that of the third embodiment.
  • a resist 80b is formed which overlaps the area other than the position surrounding the via 90b on one surface of the substrate body 20b of the second substrate 10b.
  • the cluster ions are irradiated on one surface of the substrate body 20b of the second substrate 10b and the resist 80b.
  • the gettering layer 40b is formed at a position surrounding the via 90b on one surface of the substrate body 20b of the second substrate 10b.
  • the resist 80b is removed.
  • the first substrate 10a is also formed in the same manner as the second substrate 10b.
  • the process of laminating the second substrate 10 b and the first substrate 10 a is the same as that of the second embodiment or the third embodiment.
  • the cluster ions are irradiated to a position surrounding the via 90 b filled with the metal M.
  • the metal M filled in the via 90 b can be prevented from invading the substrate body 20 b, and the reliability of the semiconductor device 1 can be improved.
  • cluster ions in the above embodiment includes carbon and hydrogen atoms, it is not limited thereto. That is, cluster ions can include various other atoms or molecules that can form the gettering layer 40b.
  • the region 52b of the P-well among the plurality of regions 50b of different polarities in the third embodiment may be irradiated with B10H14, B18H22 or the like as cluster ions. In this case, a resist 80b is formed to cover the region 51b.
  • the first substrate 10a, the second substrate 10b, and the third substrate 10c are stacked.
  • four or more substrates 10 may be stacked.
  • the first substrate 10a may be a substrate formed only of the substrate body 20a on which the device layer 30a is not formed, or may be a support substrate formed of, for example, a glass material or the like. In this case, the first substrate may be removed after multiple substrates are stacked thereon.
  • substrate 10 further on the surface which irradiated cluster ion you may laminate
  • the first substrate 10a may be the same as the first embodiment, and the substrates 10 other than the first substrate 10a may have the same structure as the second substrate 10b. .
  • the uppermost substrate for example, the third substrate 10c on the top of the drawing of FIG. 7 may be polished only by polishing one surface of the substrate body 20. Good.
  • the intrinsic gettering layer may be formed on the first surface side of the substrate body 20a of the first substrate 10a.
  • the first substrate 10a has the same configuration as the second substrate 10b, but the first substrate 10a is the same as the first embodiment, and the second The substrate 10 b and the third substrate 10 c may have the same configuration.

Abstract

The purpose of the present invention is to provide: a semiconductor manufacturing method with which it is possible to form a gettering layer even in a thinned substrate; and a semiconductor device having the gettering layer formed therein. Disclosed is a manufacturing method for a semiconductor device 1 in which a plurality of substrates are laminated, the manufacturing method comprising: a step for laminating a second substrate with respect to a first substrate; a step for polishing one of the surfaces of the second substrate that is opposite to the other surface where a device layer is formed; and a step for irradiating the polished surface of the second substrate with a beam of cluster ions containing a constituent element contributory to gettering so as to form a gettering layer containing the constituent element of the cluster ions.

Description

半導体装置及び半導体装置の製造方法Semiconductor device and method of manufacturing semiconductor device
　本発明は、半導体装置及び半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
　従来より、重金属等の汚染物質が半導体装置のシリコン基板中に侵入することで、半導体装置の半導体素子に影響が出ることが知られている。そこで、シリコン基板の裏面（半導体素子が形成される面とは反対の面）近傍に、ゲッタリング層と呼ばれる層を形成することが行われている。ゲッタリング層は、重金属元素を捕獲することができる。これにより、ゲッタリング層は、シリコン基板中への汚染物質の侵入を抑制することができる。 Heretofore, it has been known that contamination of a silicon substrate of a semiconductor device with a contaminant such as heavy metal affects the semiconductor element of the semiconductor device. Therefore, a layer called a gettering layer is formed in the vicinity of the back surface of the silicon substrate (the surface opposite to the surface on which the semiconductor element is formed). The gettering layer can capture heavy metal elements. Thus, the gettering layer can suppress the entry of contaminants into the silicon substrate.
　近年では、半導体装置の小型化がすすめられており、これに伴ってシリコン基板の薄型化も実現されている。そこで、薄型化されたシリコン基板であってもゲッタリング層を形成可能な半導体装置の製造方法が提案されている（例えば、特許文献１及び非特許文献１参照）。 In recent years, miniaturization of semiconductor devices has been promoted, and along with this, thinning of silicon substrates has also been realized. Therefore, a method of manufacturing a semiconductor device capable of forming a gettering layer even with a thinned silicon substrate has been proposed (see, for example, Patent Document 1 and Non-Patent Document 1).
特開２００５－３１７８０５号公報JP 2005-317805 A
　特許文献１に開示された半導体装置の製造方法では、シリコン基板の表面に半導体素子を形成した後に、シリコン基板の裏面にゲッタリング層が形成される。具体的には、シリコン基板の裏面に、アルゴンイオン等の不純物を打ち込むことでゲッタリング層が形成される。また、非特許文献１に開示された半導体装置の製造方法においても、アルゴンイオンをシリコン基板に打ち込むことで、ゲッタリング層が形成される。これにより、銅等の不純物をゲッタリング層で捕獲できるので、シリコン基板が汚染物質で汚染されることを抑制できる。 In the method of manufacturing a semiconductor device disclosed in Patent Document 1, after forming a semiconductor element on the surface of a silicon substrate, a gettering layer is formed on the back surface of the silicon substrate. Specifically, a gettering layer is formed on the back surface of the silicon substrate by implanting an impurity such as argon ions. Also in the method of manufacturing a semiconductor device disclosed in Non-Patent Document 1, a gettering layer is formed by implanting argon ions into a silicon substrate. Thus, since impurities such as copper can be captured by the gettering layer, contamination of the silicon substrate with contaminants can be suppressed.
　一方、シリコン基板がより薄型化される場合（例えば、２０μｍ以下）、シリコン基板に打ち込まれるイオンがシリコン基板の表面に達してしまうことが考えられる。シリコン基板の表面に達したイオンは、半導体素子に影響を与えることが考えられ好ましくない。そこで、シリコン基板がより薄型化された場合であっても、ゲッタリング層が形成されるのが好適である。 On the other hand, when the silicon substrate is thinned further (for example, 20 μm or less), it is conceivable that ions implanted into the silicon substrate may reach the surface of the silicon substrate. Ions reaching the surface of the silicon substrate are considered to affect the semiconductor element, which is not preferable. Therefore, even when the silicon substrate is thinned, it is preferable that the gettering layer be formed.
　本発明は、基板がより薄型化された場合であっても、ゲッタリング層を形成可能な半導体装置の製造方法、及びゲッタリング層が形成された半導体装置を提供することを目的とする。 An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a gettering layer even if the substrate is further thinned, and a semiconductor device having a gettering layer formed thereon.
　（ｉ）本発明は、複数の基板が積層された半導体装置の製造方法であって、第１の基板に対して第２の基板を積層する工程と、前記第２の基板の面のうち、デバイス層が形成される面とは逆の面を研磨する工程と、研磨された前記第２の基板の面に向けて、ゲッタリングに寄与する構成元素を含むクラスターイオンを照射して、クラスターイオンの構成元素を含むゲッタリング層を構成する工程と、を備える半導体装置の製造方法に関する。 (I) The present invention is a method of manufacturing a semiconductor device in which a plurality of substrates are stacked, which includes the step of stacking a second substrate on a first substrate, and the surface of the second substrate, A step of polishing the surface opposite to the surface on which the device layer is formed, and irradiating cluster ions containing a constituent element contributing to gettering toward the surface of the polished second substrate to form cluster ions And a step of forming a gettering layer containing the constituent elements of
　（ｉｉ）また、前記第１の基板に対して前記第２の基板を積層する工程において、前記第２の基板の面のうち、デバイス層が形成される面が、前記第１の基板に対して対向配置されることが好ましい。 (Ii) In the step of laminating the second substrate on the first substrate, of the surfaces of the second substrate, the surface on which the device layer is to be formed is relative to the first substrate. It is preferable to be disposed opposite to each other.
　（ｉｉｉ）また、前記第１の基板に対して前記第２の基板を積層する工程において、前記第２の基板の面のうち、デバイス層が形成される面とは逆の面が、前記第１の基板に対して対向配置されることが好ましい。 (Iii) In the step of laminating the second substrate on the first substrate, the surface of the second substrate opposite to the surface on which the device layer is formed is the second surface. It is preferable to be disposed opposite to one substrate.
　（ｉｖ）また、前記ゲッタリング層を構成する工程において、前記第２の基板の面のうち一部の領域に前記ゲッタリング層が構成されることが好ましい。 (Iv) In the step of forming the gettering layer, it is preferable that the gettering layer be formed in a partial region of the surface of the second substrate.
　（ｖ）また、前記ゲッタリング層を構成する工程は、前記第２の基板の面上にレジストを形成する工程と、前記第２の基板の面と前記レジストにクラスターイオンを照射する工程と、前記レジストを除去する工程と、を備えることが好ましい。 (V) In the step of forming the gettering layer, a step of forming a resist on the surface of the second substrate, a step of irradiating the surface of the second substrate and the resist with cluster ions, And removing the resist.
　（ｖｉ）また、前記レジストを形成する工程において、前記レジストは、前記第２の基板内に形成される素子領域のうち、前記ゲッタリング層との距離が所定値以下となる素子領域に重なる位置に形成されることが好ましい。 (Vi) In the step of forming the resist, a position at which the resist overlaps with the element region formed in the second substrate and whose distance to the gettering layer is equal to or less than a predetermined value Preferably, it is formed in
　（ｖｉｉ）また、前記レジストを形成する工程において、前記レジストは、前記第２の基板内に形成され、前記第２の基板の研磨される面に露出する領域のうち、極性が変化する境界に重なる位置に形成されることが好ましい。 (Vii) In the step of forming the resist, the resist is formed in the second substrate, and in the boundary exposed to the polished surface of the second substrate, at the boundary where the polarity changes. Preferably, they are formed at overlapping positions.
　（ｖｉｉｉ）また、前記レジストを形成する工程において、前記レジストは、前記ゲッタリング層を形成する厚さよりも厚く形成されることが好ましい。 (Viii) Further, in the step of forming the resist, the resist is preferably formed to be thicker than a thickness of the gettering layer.
　（ｉｘ）また、クラスターイオンを照射する工程において、クラスターイオンは、金属が充填されるビアを囲繞する位置に照射されることが好ましい。 (Ix) Also, in the step of irradiating cluster ions, it is preferable that the cluster ions be irradiated at positions surrounding the metal-filled vias.
　（ｘ）また、第１の基板に対して第２の基板を積層する工程において、上記（ｉｉ）～（ｖｉｉｉ）のいずれかに記載された前記第２の基板の複数が前記第１の基板に積層されることが好ましい。 (X) In the step of laminating the second substrate on the first substrate, a plurality of the second substrates described in any of the above (ii) to (viii) are the first substrate. It is preferable to be laminated.
　（ｘｉ）また、本発明は、複数の基板が積層された半導体装置であって、第１の基板と、前記第１の基板に重ね合わされる第２の基板と、を備え、少なくとも前記第２の基板は、クラスターイオンの構成元素を含むゲッタリング層を備え、前記ゲッタリング層は、前記第２の基板の研磨された面側に形成される半導体装置に関する。 (Xi) Further, the present invention is a semiconductor device in which a plurality of substrates are stacked, comprising: a first substrate; and a second substrate superimposed on the first substrate, at least the second The present invention relates to a semiconductor device provided with a gettering layer containing constituent elements of cluster ions, the gettering layer being formed on the polished surface side of the second substrate.
　本発明によれば、基板がより薄型化された場合であっても、ゲッタリング層を形成可能な半導体装置の製造方法、及びゲッタリング層が形成された半導体装置を提供することができる。 According to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of forming a gettering layer, and a semiconductor device having a gettering layer formed thereon, even when the substrate is further thinned.
本発明の第１実施形態に係る半導体装置の製造方法において、２つの基板を重ね合わせる際の半導体装置の概略側面図である。FIG. 7 is a schematic side view of the semiconductor device when stacking two substrates in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. 第１実施形態の半導体装置の製造方法において、一方の基板が研磨された後の半導体装置の側面図である。FIG. 7 is a side view of the semiconductor device after one of the substrates is polished in the method for manufacturing the semiconductor device of the first embodiment. 第１の実施形態の半導体装置の製造方法において、半導体装置にクラスターイオンが照射される際の半導体装置の側面図である。FIG. 7 is a side view of the semiconductor device when cluster ions are irradiated to the semiconductor device in the method of manufacturing the semiconductor device of the first embodiment; 図３に示す半導体装置の部分拡大断面図である。FIG. 4 is a partial enlarged cross-sectional view of the semiconductor device shown in FIG. 3; 第１実施形態の半導体装置の製造方法において、さらに基板を重ね合わせる際の半導体装置の側面図である。FIG. 7 is a side view of the semiconductor device when the substrates are further superposed in the method of manufacturing the semiconductor device of the first embodiment. 第１実施形態の半導体装置の製造方法において、さらなる基板を重ね合わせた際の半導体装置の側面図である。FIG. 7 is a side view of the semiconductor device when a further substrate is stacked in the method of manufacturing the semiconductor device of the first embodiment. 第１実施形態の半導体装置の製造方法において、さらなる基板を研磨した後の半導体装置の側面図である。FIG. 13 is a side view of the semiconductor device after polishing a further substrate in the method of manufacturing the semiconductor device of the first embodiment. 第１の実施形態の半導体装置において、さらなる基板にクラスターイオンを照射する際の半導体装置の側面図である。In the semiconductor device of a 1st embodiment, it is a side view of the semiconductor device at the time of irradiating a cluster ion to the further substrate. 本発明の第２の実施形態に係る半導体装置の基板の一部を拡大した部分拡大断面図である。FIG. 6 is a partially enlarged cross-sectional view of a part of a substrate of a semiconductor device according to a second embodiment of the present invention. 第２の実施形態の半導体装置の製造方法において、クラスターイオンが照射される際のレジスト層が形成された半導体装置の部分拡大断面面図である。FIG. 18 is a partial enlarged cross-sectional view of a semiconductor device in which a resist layer is formed when cluster ions are irradiated in the method of manufacturing a semiconductor device of the second embodiment. 第２の実施形態の半導体装置の製造方法において、２つの基板が重ね合わされた際の半導体基板を示す部分拡大段面図である。FIG. 13 is a partially enlarged step view showing the semiconductor substrate when two substrates are superimposed on each other in the method for manufacturing a semiconductor device of the second embodiment. 本発明の第３の実施形態に係る半導体装置の基板の一部を拡大した部分拡大断面図である。FIG. 10 is a partially enlarged cross-sectional view of a portion of a substrate of a semiconductor device according to a third embodiment of the present invention; 第３の実施形態に係る半導体装置の製造方法において、クラスターイオンが照射される際の半導体装置の部分拡大段面図である。FIG. 19 is a partially enlarged step surface view of the semiconductor device when cluster ions are irradiated in the method of manufacturing a semiconductor device according to the third embodiment. 本発明の第４の実施形態に係る半導体装置の製造方法において、ビアの周囲にゲッタリング層が形成された半導体装置の部分拡大段面図である。FIG. 16 is a partially enlarged step view of a semiconductor device in which a gettering layer is formed around a via in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.
　以下、本発明の各実施形態に係る半導体装置及び半導体装置の製造方法の各実施形態について、図面を参照して説明する。
　まず、各実施形態に係る半導体装置の概要について説明する。
　半導体装置は、複数の基板を積層して形成される。半導体装置は、例えば、ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）である。 Hereinafter, each embodiment of a semiconductor device and a method of manufacturing the semiconductor device according to each embodiment of the present invention will be described with reference to the drawings.
First, an outline of the semiconductor device according to each embodiment will be described.
The semiconductor device is formed by stacking a plurality of substrates. The semiconductor device is, for example, a dynamic random access memory (DRAM).
　基板のそれぞれには、重金属等の汚染物質を捕獲するためのゲッタリング層が形成される。ゲッタリング層は、基板の板面方向に沿って形成される。ゲッタリング層は、重金属等の汚染物質を捕獲する。これにより、ゲッタリング層は、汚染物質による基板内部の汚染を抑制する。 A gettering layer is formed on each of the substrates to capture contaminants such as heavy metals. The gettering layer is formed along the surface direction of the substrate. The gettering layer captures contaminants such as heavy metals. Thereby, the gettering layer suppresses the contamination inside the substrate by the contaminant.
［第１実施形態］
　次に、本発明の第１実施形態に係る半導体装置１及び半導体装置１の製造方法について、図１～図８を参照して説明する。
　半導体装置１は、例えば、図１に示すように、複数の基板１０を積層して形成される。
　基板１０のそれぞれは、基板本体２０と、デバイス層３０と、を備える。 First Embodiment
Next, the semiconductor device 1 and the method of manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 8.
The semiconductor device 1 is formed, for example, by laminating a plurality of substrates 10 as shown in FIG.
Each of the substrates 10 comprises a substrate body 20 and a device layer 30.
　基板本体２０は、例えば、シリコン基板である。基板本体２０は、厚さ方向の一方の面側にゲッタリング層４０（図４参照）を有する。本実施形態において、最下方（図１の紙面下方）に配置される基板１０（以下、第１の基板１０ａという。以下、基板１０と記載する場合、複数の基板１０のいずれであってもよいことを示す。）の基板本体２０ａは、より厚く形成される。そして、他の基板１０（以下、第２の基板１０ｂという）の基板本体２０ｂは、より薄く形成される。即ち、本実施形態において、より薄い基板本体２０ｂを有する第２の基板１０ｂは、より厚い（最も厚い）基板本体２０ａを有する１つの第１の基板１０ａ上に重ねて配置される。基板本体２０には、図４に示すように、極性の異なる複数の領域が形成される。
　以下の説明において、第１の基板１０ａが備える構成の符号には「ａ」を付し、第２の基板１０ｂが備える構成の符号には、「ｂ」を付して説明する。一方で、「ａ」及び「ｂ」のいずれも付されない場合には、いずれの基板１０が備えていてもよいことを示す。 The substrate body 20 is, for example, a silicon substrate. The substrate body 20 has a gettering layer 40 (see FIG. 4) on one surface side in the thickness direction. In the present embodiment, the substrate 10 (hereinafter referred to as the first substrate 10a) disposed at the lowermost position (the lower side of the sheet of FIG. 1) may be any of the plurality of substrates 10 in the following description. The substrate body 20a) is formed thicker. The substrate main body 20b of the other substrate 10 (hereinafter referred to as a second substrate 10b) is formed thinner. That is, in the present embodiment, the second substrate 10b having the thinner substrate body 20b is disposed so as to overlap on one first substrate 10a having the thicker (thickest) substrate body 20a. As shown in FIG. 4, a plurality of regions having different polarities are formed in the substrate body 20.
In the following description, “a” is attached to the reference numeral of the configuration of the first substrate 10 a, and “b” is attached to the reference numeral of the configuration of the second substrate 10 b. On the other hand, when neither “a” nor “b” is attached, it indicates that any substrate 10 may be provided.
　ゲッタリング層４０は、いわゆる歪層（結晶欠陥層）である。特に、第２の基板１０ｂのゲッタリング層４０は、クラスターイオンの構成元素（例えば、カーボンや水素原子）を含み、クラスターイオンの基板本体２０ｂへの照射（注入）により形成される。ゲッタリング層４０ｂは、基板本体２０ｂの厚さ方向一方側の面から所定の厚さで形成される。本実施形態において、ゲッタリング層４０ｂは、例えば、１００ｎｍ以下の厚さで形成される。 The gettering layer 40 is a so-called strained layer (crystal defect layer). In particular, the gettering layer 40 of the second substrate 10b contains a constituent element (for example, carbon or hydrogen atom) of cluster ions, and is formed by irradiation (implantation) of cluster ions to the substrate body 20b. The gettering layer 40b is formed with a predetermined thickness from the surface on one side in the thickness direction of the substrate body 20b. In the present embodiment, the gettering layer 40 b is formed, for example, to a thickness of 100 nm or less.
　デバイス層３０は、例えば、トランジスタ３１ａ，３１ｂ及び絶縁層３２ａ，３２ｂ等を有する層である。デバイス層３０は、基板本体２０の厚さ方向の他方の面側に配置される。本実施形態において、デバイス層３０ａは、より厚い基板本体２０ａを有する第１の基板１０ａにおいて、基板本体２０ａの上方（図１の紙面上方）を向く面側に配置される。また、デバイス層３０ｂは、より薄い基板本体２０ｂを有する第２の基板１０ｂにおいて、基板本体２０ｂの下方（図１の紙面下方）を向く面側に配置される。デバイス層３０は、隣接する基板１０との間を電気的に接続する。 The device layer 30 is, for example, a layer including the transistors 31a and 31b, the insulating layers 32a and 32b, and the like. The device layer 30 is disposed on the other side in the thickness direction of the substrate body 20. In the present embodiment, the device layer 30a is disposed on the side of the first substrate 10a having the thicker substrate body 20a, which faces upward (in the plane of FIG. 1) of the substrate body 20a. The device layer 30b is disposed on the side of the second substrate 10b having the thinner substrate body 20b, which faces the lower side of the substrate body 20b (downward in the drawing of FIG. 1). The device layer 30 electrically connects between the adjacent substrates 10.
　次に、本実施形態に係る半導体装置１の製造方法を説明する。
　半導体装置１の製造方法は、第１の基板１０ａに対して第２の基板１０ｂを積層する工程と、第２の基板１０ｂの面のうち、デバイス層３０ｂが形成される面とは逆の面を研磨する工程と、研磨された第２の基板１０ｂの面に向けて、ゲッタリングに寄与する構成元素（例えば、カーボンや水素）を含むクラスターイオンを照射して、クラスターイオンの構成元素を含むゲッタリング層を構成する工程と、を備える。 Next, a method of manufacturing the semiconductor device 1 according to the present embodiment will be described.
In the method of manufacturing the semiconductor device 1, a step of stacking the second substrate 10 b on the first substrate 10 a and a surface of the second substrate 10 b opposite to the surface on which the device layer 30 b is formed. And ionizing cluster ions containing a constituent element (for example, carbon or hydrogen) contributing to gettering toward the surface of the polished second substrate 10b and containing the constituent elements of cluster ions. And (d) forming a gettering layer.
　まず、積層する工程が実施される。第１の基板１０ａ及び第２の基板１０ｂは、図１に示すように、デバイス層３０ａ，３０ｂの形成される面（他方の面）を対向させた状態で配置される。そして、第１の基板１０ａ及び第２の基板１０ｂは、デバイス層３０ａ，３０ｂの表面で重ね合わされて接合される。 First, the step of stacking is performed. As shown in FIG. 1, the first substrate 10a and the second substrate 10b are disposed in a state in which the surfaces (other surfaces) on which the device layers 30a and 30b are formed face each other. Then, the first substrate 10a and the second substrate 10b are overlapped and bonded on the surface of the device layers 30a and 30b.
　次いで、研磨する工程が実施される。図２に示すように、第２の基板１０ｂは、面の他方側（デバイス層３０ｂが形成される面とは逆の面側）を研磨される。即ち、第２の基板１０ｂの基板本体２０ｂは、他方の面側を研磨される。これにより、第２の基板１０ｂの基板本体２０ｂは、デバイス層３０ｂが形成される面とは逆の面を研磨される。第２の基板１０ｂの基板本体２０ｂは、例えば、５～２０μｍの薄さまで研磨される。 Then, a polishing step is performed. As shown in FIG. 2, the second substrate 10 b is polished on the other side (the side opposite to the side on which the device layer 30 b is formed). That is, the substrate main body 20b of the second substrate 10b is polished on the other surface side. Thereby, the substrate body 20b of the second substrate 10b is polished on the surface opposite to the surface on which the device layer 30b is formed. The substrate body 20b of the second substrate 10b is polished to a thickness of, for example, 5 to 20 μm.
　次いで、ゲッタリング層４０ｂを構成する工程が実施される。具体的には、図３に示すように、ゲッタリング層４０ｂは、第２の基板１０ｂの基板本体２０ｂの一方面から、所定の厚さ（例えば、１００ｎｍ以下）で形成される。本実施形態において、ゲッタリング層４０ｂは、第２の基板１０ｂの基板本体２０ｂの一方の面側へクラスターイオンを照射することで形成される。クラスターイオンの照射によるゲッタリング層４０ｂの形成については後に詳述する。 Next, the step of forming gettering layer 40b is performed. Specifically, as shown in FIG. 3, the gettering layer 40b is formed with a predetermined thickness (for example, 100 nm or less) from one surface of the substrate body 20b of the second substrate 10b. In the present embodiment, the gettering layer 40 b is formed by irradiating cluster ions on one surface side of the substrate body 20 b of the second substrate 10 b. The formation of the gettering layer 40b by irradiation of cluster ions will be described in detail later.
　さらに基板１０を積層する場合、図５に示すように、第３の基板１０ｃが、第２の基板１０ｂ上に位置合わせされる。このとき、第３の基板１０ｃは、デバイス層３０を第２の基板１０ｂの基板本体２０ｂの一方の面に対向させた状態で位置合わせされる。 Furthermore, when laminating | stacking the board | substrate 10, as shown in FIG. 5, the 3rd board | substrate 10c is aligned on the 2nd board | substrate 10b. At this time, the third substrate 10c is aligned in a state where the device layer 30 is opposed to one surface of the substrate body 20b of the second substrate 10b.
　次いで、図６に示すように、第３の基板１０ｃが、第２の基板１０ｂに接合される。そして、図７に示すように、第３の基板１０ｃの基板本体２０ｃの一方の面が研磨される。 Next, as shown in FIG. 6, the third substrate 10c is bonded to the second substrate 10b. Then, as shown in FIG. 7, one surface of the substrate body 20c of the third substrate 10c is polished.
　次いで、図８に示すように、ゲッタリング層４０ｃが形成される。具体的には、ゲッタリング層４０ｃは、第３の基板１０ｃの基板本体２０ｃの一方の面側へクラスターイオン（例えば、カーボンや水素）を照射することで形成される。 Next, as shown in FIG. 8, a gettering layer 40c is formed. Specifically, the gettering layer 40c is formed by irradiating cluster ions (for example, carbon or hydrogen) on one surface side of the substrate main body 20c of the third substrate 10c.
　クラスターイオンの照射によるゲッタリング層４０ｂの形成について、詳述する。
　クラスターイオンは、例えば、カーボンや水素分子を含む原子又は分子の集まった塊である。クラスターイオンは、基板本体２０ｂの一方の面側に照射（注入）されると、そのエネルギーで瞬間的に１３５０～１４００℃程度の高温状態となる。クラスターイオンは、高温となることで、基板本体２０ｂを融解する。その後、基板本体２０ｂは、急速に冷却される。これにより、照射されたクラスターイオンに含まれるカーボンや水素分子は、基板本体２０ｂの一方の面の表面近傍に固溶する。即ち、ゲッタリング層４０ｂとは、照射するイオンの構成元素が基板本体２０ｂ表面の結晶の格子間位置又は置換位置に固溶した層を意味する。ゲッタリング層４０ｂは、ＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ、二次イオン質量分析）において、基板本体２０ｂの深さ方向（厚さ方向）における構成元素の濃度分布を測定した際に、バックグラウンドより多く検出される範囲として特定される。 The formation of the gettering layer 40b by irradiation of cluster ions will be described in detail.
A cluster ion is, for example, a collection of atoms or molecules including carbon and hydrogen molecules. When cluster ions are irradiated (injected) on one surface side of the substrate body 20b, the energy instantaneously reaches a high temperature of about 1350 to 1400.degree. The cluster ions melt the substrate body 20b by becoming high temperature. Thereafter, the substrate body 20b is rapidly cooled. Thereby, carbon and hydrogen molecules contained in the irradiated cluster ions are dissolved in the vicinity of the surface of one surface of the substrate body 20b. That is, the gettering layer 40b means a layer in which the constituent element of the ion to be irradiated is solid-solved in the lattice position or substitution position of the crystal on the surface of the substrate body 20b. When the concentration distribution of constituent elements in the depth direction (thickness direction) of the substrate main body 20b is measured in SIMS (Secondary Ion Mass Spectrometry, secondary ion mass spectrometry), the gettering layer 40b is detected more than the background. Identified as the
　以上の第１実施形態に係る半導体装置１の製造方法及び半導体装置１によれば、以下の効果を奏する。
（１）半導体装置１の製造方法は、第１の基板１０ａに対して第２の基板１０ｂを積層する工程と、第２の基板１０ｂの面のうち、デバイス層３０ｂが形成される面とは逆の面を研磨する工程と、研磨された第２の基板１０ｂの面に向けて、ゲッタリングに寄与する構成元素を含むクラスターイオンを照射して、クラスターイオンの構成元素を含むゲッタリング層４０ｂを構成する工程と、を備える。これにより、イオンの注入領域（深さ）を第２の基板１０ｂの逆の面側に限定することができる。したがって、第２の基板１０ｂのデバイス層３０が形成される面までイオンが到達してしまうことを抑制して、信頼度の高い半導体装置１を製造することができる。 According to the method of manufacturing the semiconductor device 1 and the semiconductor device 1 of the first embodiment described above, the following effects can be obtained.
(1) In the method of manufacturing the semiconductor device 1, the step of stacking the second substrate 10b on the first substrate 10a and the surface of the second substrate 10b on which the device layer 30b is formed A step of polishing the opposite surface and irradiation of cluster ions containing a constituent element contributing to gettering toward the surface of the polished second substrate 10b, the gettering layer 40b containing a constituent element of cluster ions And b. Thus, the ion implantation region (depth) can be limited to the side opposite to the second substrate 10b. Therefore, it is possible to manufacture the semiconductor device 1 with high reliability by suppressing the ions from reaching the surface of the second substrate 10b on which the device layer 30 is formed.
（２）第１の基板１０ａに対して第２の基板１０ｂを積層する工程において、第２の基板１０ｂの面のうち、デバイス層３０ｂが形成される面が、第１の基板１０ａに対して対向配置されるようにした。これにより、第１の基板１０ａ及び第２の基板１０ｂを電気的に接続することができる。 (2) In the step of stacking the second substrate 10b on the first substrate 10a, of the surfaces of the second substrate 10b, the surface on which the device layer 30b is formed is the surface on which the first substrate 10a is formed. It was made to be arranged oppositely. Thereby, the first substrate 10a and the second substrate 10b can be electrically connected.
（３）半導体装置１は、第１の基板１０ａと、第１の基板１０ａに重ね合わされる第２の基板１０ｂと、を備え、少なくとも第２の基板１０ｂは、クラスターイオンの構成元素を含むゲッタリング層４０ｂを備え、ゲッタリング層４０ｂは、第２の基板１０ｂの研磨された面側に形成される。これにより、第２の基板１０ｂがより薄い場合であってもゲッタリング層４０ｂを構成できる。 (3) The semiconductor device 1 includes the first substrate 10 a and the second substrate 10 b stacked on the first substrate 10 a, and at least the second substrate 10 b is a getter containing a constituent element of cluster ions. A ringing layer 40b is provided, and the gettering layer 40b is formed on the polished surface side of the second substrate 10b. As a result, even when the second substrate 10b is thinner, the gettering layer 40b can be formed.
［第２実施形態］
　次に、本発明の第２実施形態に係る半導体装置１の製造方法及び半導体装置１について、図９～図１１を参照して説明する。第２実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。
　第２実施形態に係る半導体装置１は、ゲッタリング層４０ｂが第２の基板１０ｂの面のうち一部の領域に構成される点で、第１実施形態と異なる。また、第２実施形態に係る半導体装置１は、第２の基板１０ｂのデバイス層３０ｂの形成される面とは逆の面が、第１の基板１０ａに対して対向配置される点で第１実施形態と異なる。なお、第２実施形態では、第１の基板１０ａは、第２の基板１０ｂと同様に研磨されるとともに、クラスターイオンを用いたゲッタリング層４０ａを有する（図１１参照）。即ち、第２実施形態では、第１の基板１０ａ及び第２の基板１０ｂが同じ構成で形成される。 Second Embodiment
Next, a method of manufacturing the semiconductor device 1 and the semiconductor device 1 according to the second embodiment of the present invention will be described with reference to FIGS. 9 to 11. In the description of the second embodiment, the same components will be assigned the same reference numerals, and the description thereof will be omitted or simplified.
The semiconductor device 1 according to the second embodiment differs from the first embodiment in that the gettering layer 40b is formed in a partial region of the surface of the second substrate 10b. The semiconductor device 1 according to the second embodiment is characterized in that the surface opposite to the surface on which the device layer 30b of the second substrate 10b is formed is disposed so as to face the first substrate 10a. It differs from the embodiment. In the second embodiment, the first substrate 10a is polished in the same manner as the second substrate 10b, and has a gettering layer 40a using cluster ions (see FIG. 11). That is, in the second embodiment, the first substrate 10a and the second substrate 10b are formed in the same configuration.
　第２の基板１０ｂの基板本体２０ｂは、デバイス層３０ｂの形成される面に沿って、極性の異なる複数の領域５０ｂを有する。また、第２の基板１０ｂの基板本体２０ｂは、極性の異なる複数の領域５０ｂよりも深い位置に極性の異なる他の領域６０ｂを有する（複数の領域の全体を素子領域７０という）。第２の基板１０ｂは、第１の実施形態よりもより薄く形成される。第２の基板１０ｂの基板本体２０ｂは、例えば、５μｍ程度の薄さで形成される。 The substrate body 20b of the second substrate 10b has a plurality of regions 50b of different polarities along the surface on which the device layer 30b is formed. Further, the substrate body 20b of the second substrate 10b has another region 60b of different polarity at a deeper position than the plurality of regions 50b of different polarities (the whole of the plurality of regions is referred to as an element region 70). The second substrate 10b is formed thinner than the first embodiment. The substrate body 20b of the second substrate 10b is formed with a thickness of, for example, about 5 μm.
　極性の異なる複数の領域５０ｂは、例えば、Ｎ－ｗｅｌｌの領域５１ｂとＰ－ｗｅｌｌの領域５２ｂとが隣接配置される領域である。極性の異なる複数の領域５０ｂは、第２の基板１０ｂの基板本体２０ｂの他方の面（逆側の面）から所定の厚さで形成される。 The plurality of regions 50b having different polarities are, for example, regions where the region 51b of the N-well and the region 52b of the P-well are disposed adjacent to each other. The plurality of regions 50b of different polarities are formed with a predetermined thickness from the other surface (opposite surface) of the substrate body 20b of the second substrate 10b.
　極性の異なる他の領域６０ｂは、極性の異なる複数の領域５０ｂの一部に跨って、極性の異なる複数の領域５０ｂに重ねて配置される。極性の異なる他の領域６０ｂは、例えば、Ｎ－ｗｅｌｌの領域５１ｂとＰ－ｗｅｌｌの領域５２ｂの一部に跨って重ねて配置される。極性の異なる他の領域６０ｂは、所定の厚さで形成される。即ち、極性の異なる他の領域６０ｂは、極性の異なる複数の領域５０ｂよりも基板本体２０ｂの一方の面側（ゲッタリング層４０ｂが形成される面側）に近い位置に形成される。 The other regions 60b having different polarities are disposed overlapping the plurality of regions 50b having different polarities, across parts of the plurality of regions 50b having different polarities. The other regions 60b different in polarity are disposed, for example, overlapping the region 51b of the N-well and a part of the region 52b of the P-well. Another region 60b of different polarity is formed with a predetermined thickness. That is, the other regions 60b having different polarities are formed closer to one surface of the substrate body 20b (the surface on which the gettering layer 40b is formed) than the plurality of regions 50b having different polarities.
　次に、第２実施形態に係る半導体装置１の製造方法について説明する。 Next, a method of manufacturing the semiconductor device 1 according to the second embodiment will be described.
　まず、第２の基板１０ｂの一方の面が研磨される。具体的には、第２の基板１０ｂの基板本体２０ｂの一方の面（デバイス層３０ｂが形成される面とは逆の面）が、研磨される。次いで、ゲッタリング層４０ｂが構成される。 First, one surface of the second substrate 10b is polished. Specifically, one surface of the substrate body 20b of the second substrate 10b (surface opposite to the surface on which the device layer 30b is formed) is polished. Next, the gettering layer 40b is formed.
　ゲッタリング層４０ｂを形成する工程は、第２の基板１０ｂの面上にレジスト８０ｂを形成する工程と、第２の基板１０ｂの面とレジスト８０ｂにクラスターイオンを照射する工程と、レジスト８０ｂを除去する工程と、を備える。 The step of forming the gettering layer 40b includes the steps of forming a resist 80b on the surface of the second substrate 10b, irradiating the surface of the second substrate 10b and the resist 80b with cluster ions, and removing the resist 80b. And
　まず、第２の基板１０ｂの面上にレジスト８０ｂを形成する工程が実施される。図１０に示すように、第２の基板１０ｂの一方の面側（研磨された面側）にレジスト８０ｂが形成される。レジスト８０ｂは、第２の基板１０ｂ内に形成される素子領域７０ｂ（極性の異なる複数の領域５０ｂ及び極性の異なる他の領域６０ｂ）のうち、ゲッタリング層４０ｂとの距離が所定値以下となる素子領域７０ｂに重なる位置に形成される。本実施形態において、レジスト８０ｂは、極性の異なる他の領域６０ｂと重なる位置に形成される。 First, the step of forming a resist 80b on the surface of the second substrate 10b is performed. As shown in FIG. 10, a resist 80b is formed on one surface side (polished surface side) of the second substrate 10b. The distance between the resist 80b and the gettering layer 40b in the element regions 70b (the plurality of regions 50b of different polarities and the other regions 60b of different polarities) formed in the second substrate 10b is equal to or less than a predetermined value. It is formed in the position which overlaps with element field 70b. In the present embodiment, the resist 80 b is formed at a position overlapping with the other region 60 b of different polarity.
　次いで、第２の基板１０ｂの面とレジスト８０ｂにクラスターイオンを照射する工程が実施される。これにより、第２の基板１０ｂの基板本体２０ｂの一方の面側から所定の深さのゲッタリング層４０ｂが形成される。具体的には、第２の基板１０ｂの基板本体２０ｂの一方の面のうち、レジスト８０ｂの形成されていない面領域の位置にゲッタリング層４０ｂが形成される。一方、第２の基板１０ｂの基板本体２０ｂの一方の面のうち、レジスト８０ｂの形成されている面領域の位置にはゲッタリング層４０ｂが形成されない。即ち、極性の異なる他の領域６０ｂと重なる位置には、ゲッタリング層４０ｂが形成されない。 Then, a step of irradiating cluster ion to the surface of the second substrate 10b and the resist 80b is performed. Thereby, the gettering layer 40b of a predetermined depth is formed from one surface side of the substrate body 20b of the second substrate 10b. Specifically, the gettering layer 40b is formed at the position of the surface area of the second substrate 10b where the resist 80b is not formed on one surface of the substrate body 20b. On the other hand, the gettering layer 40b is not formed at the position of the surface area where the resist 80b is formed in one surface of the substrate body 20b of the second substrate 10b. That is, the gettering layer 40 b is not formed at a position overlapping with the other region 60 b of different polarity.
　次いで、レジスト８０ｂを除去する工程が実施される。これにより、第２の基板１０ｂの基板本体２０ｂの一方の面上から、レジスト８０ｂが除去される。また、第１の基板１０ａも第２の基板１０ｂと同様に形成される。 Next, the step of removing the resist 80b is performed. Thereby, the resist 80b is removed from one surface of the substrate body 20b of the second substrate 10b. The first substrate 10a is also formed in the same manner as the second substrate 10b.
　次いで、図１１に示すように、第２の基板１０ｂに対して第１の基板１０ａを積層する工程が実施される。本実施形態において、第１の基板１０ａは、第２の基板１０ｂと同様の構成を有する。第２の基板１０ｂは、第１の基板１０ａと一方の面同士を対向させた状態で接合される。即ち、第２の基板１０ｂのゲッタリング層は、第１の基板１０ａのゲッタリング層４０ｂと対向した状態で接合される。 Next, as shown in FIG. 11, the step of laminating the first substrate 10a on the second substrate 10b is performed. In the present embodiment, the first substrate 10a has the same configuration as the second substrate 10b. The second substrate 10b is bonded in a state in which the first substrate 10a and one surface of the second substrate 10b face each other. That is, the gettering layer of the second substrate 10b is joined in a state of facing the gettering layer 40b of the first substrate 10a.
　以上の第２実施形態に係る半導体装置１の製造方法及び半導体装置１によれば、以下の効果を奏する。 According to the method of manufacturing the semiconductor device 1 and the semiconductor device 1 according to the second embodiment described above, the following effects can be obtained.
（４）第１の基板１０ａに対して第２の基板１０ｂを積層する工程において、第２の基板１０ｂの面のうち、デバイス層３０ｂが形成される面とは逆の面が、第１の基板１０ａに対して対向配置されるようにした。これにより、半導体装置１の汎用性を高めることができる。 (4) In the step of stacking the second substrate 10b on the first substrate 10a, the surface of the second substrate 10b opposite to the surface on which the device layer 30b is formed is the first surface. It was arranged to face the substrate 10a. Thereby, the versatility of the semiconductor device 1 can be enhanced.
（５）ゲッタリング層４０ｂを構成する工程において、第２の基板１０ｂの面のうち一部の領域にゲッタリング層４０ｂが構成される。これにより、目的に合わせた位置にゲッタリング層４０ｂを構成することができるので、半導体装置１の汎用性をより高めることができる。 (5) In the step of forming the gettering layer 40b, the gettering layer 40b is formed in a partial region of the surface of the second substrate 10b. As a result, the gettering layer 40b can be formed at a position according to the purpose, so that the versatility of the semiconductor device 1 can be further enhanced.
（６）ゲッタリング層４０ｂを構成する工程は、第２の基板１０ｂの面上にレジスト８０ｂを形成する工程と、第２の基板１０ｂの面とレジスト８０ｂにクラスターイオンを照射する工程と、レジスト８０ｂを除去する工程と、を備える。これにより、ゲッタリング層４０ｂを構成する領域を適宜決定することができる。 (6) The step of forming the gettering layer 40b includes the steps of: forming a resist 80b on the surface of the second substrate 10b; irradiating the surface of the second substrate 10b and the resist 80b with cluster ions; Removing 80b. Thereby, the region which constitutes gettering layer 40b can be determined appropriately.
（７）レジスト８０ｂを形成する工程において、レジスト８０ｂは、第２の基板１０ｂ内に形成される素子領域７０ｂのうち、ゲッタリング層４０ｂとの距離が所定値以下となる素子領域７０ｂに重なる位置に形成される。これにより、ゲッタリング層４０ｂと、素子領域７０ｂとの間に所定以上の距離を開けることができるので、ゲッタリング層４０ｂと素子領域７０ｂとの間にリークが発生することを抑制できる。 (7) In the step of forming the resist 80b, the position where the resist 80b overlaps the element region 70b where the distance to the gettering layer 40b is equal to or less than a predetermined value in the element region 70b formed in the second substrate 10b. Is formed. Accordingly, since a predetermined distance or more can be provided between the gettering layer 40b and the element region 70b, generation of a leak between the gettering layer 40b and the element region 70b can be suppressed.
（８）レジスト８０ｂを形成する工程において、レジスト８０ｂは、ゲッタリング層４０ｂを形成する厚さよりも厚く形成される。これにより、レジスト８０ｂを通過して第２の基板１０ｂ上にゲッタリング層４０ｂが形成されることを抑制できる。 (8) In the step of forming the resist 80b, the resist 80b is formed thicker than the thickness for forming the gettering layer 40b. Thus, formation of the gettering layer 40b on the second substrate 10b through the resist 80b can be suppressed.
［第３実施形態］
　次に、本発明の第３実施形態に係る半導体装置１及び半導体装置１の製造方法について、図１２及び図１３を参照して説明する。第３実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。
　第３実施形態に係る半導体装置１は、基板１０がさらに薄く形成される点で第２実施形態と異なる。これにより、第３実施形態に係る半導体装置１は、極性の異なる複数の領域５０ｂが基板本体２０ｂの他の面にも露出する点で第２実施形態と異なる。また、第３実施形態に係る半導体装置１は、極性の異なる複数の領域５０ｂにゲッタリング層４０ｂが形成される点で第１実施形態及び第２実施形態と異なる。第３の実施形態における第１の基板１０ａは、第２の基板１０ｂと同様の構成で形成される。 Third Embodiment
Next, a semiconductor device 1 and a method of manufacturing the semiconductor device 1 according to a third embodiment of the present invention will be described with reference to FIGS. 12 and 13. FIG. In the description of the third embodiment, the same components will be assigned the same reference numerals, and the description thereof will be omitted or simplified.
The semiconductor device 1 according to the third embodiment differs from the second embodiment in that the substrate 10 is formed thinner. Thus, the semiconductor device 1 according to the third embodiment is different from that of the second embodiment in that the plurality of regions 50b having different polarities are also exposed to the other surface of the substrate body 20b. The semiconductor device 1 according to the third embodiment is different from the first and second embodiments in that the gettering layers 40b are formed in the plurality of regions 50b having different polarities. The first substrate 10a in the third embodiment is formed in the same configuration as the second substrate 10b.
　第２の基板１０ｂの基板本体２０ｂは、例えば、２～５μｍの厚さである。第２の基板１０ｂの基板本体２０ｂは、例えば、図１２に示すように、極性の異なる複数の領域５０ｂによって構成される。 The substrate body 20b of the second substrate 10b has a thickness of, for example, 2 to 5 μm. For example, as shown in FIG. 12, the substrate main body 20b of the second substrate 10b is constituted by a plurality of regions 50b of different polarities.
　ゲッタリング層４０ｂは、極性の異なる複数の領域５０ｂのそれぞれに独立して形成される。換言すると、ゲッタリング層４０ｂは、極性の異なる複数の領域５０ｂのそれぞれの極性の変化する境界Ｂには配置されない。ゲッタリング層は、基板本体２０ｂの一方の面側に所定の厚さで形成される。 The gettering layer 40 b is formed independently in each of the plurality of regions 50 b with different polarities. In other words, the gettering layer 40b is not disposed at the boundary B where the polarities of the plurality of regions 50b of different polarities change. The gettering layer is formed with a predetermined thickness on one side of the substrate body 20b.
　次に、第３実施形態に係る半導体装置１の製造方法について説明する。
　まず、第２の基板１０ｂを研磨する工程が実施される。これにより第２の基板１０ｂの基板本体２０ｂは、２～５μｍの厚さに研磨される。次いで、ゲッタリング層４０ｂを構成する工程が実施される。 Next, a method of manufacturing the semiconductor device 1 according to the third embodiment will be described.
First, the step of polishing the second substrate 10b is performed. Thereby, the substrate body 20b of the second substrate 10b is polished to a thickness of 2 to 5 μm. Next, the step of forming gettering layer 40b is performed.
　第２の基板１０ｂの面上にレジスト８０ｂを構成する工程において、図１３に示すように、レジスト８０ｂは、第２の基板１０ｂ内に形成され、第２の基板１０ｂの研磨される面に露出する領域のうち、極性が変化する境界Ｂに重なる位置に形成される。次いで、第２の基板１０ｂの面とレジスト８０ｂとにクラスターイオンを照射する工程が実施される。 In the step of forming the resist 80b on the surface of the second substrate 10b, as shown in FIG. 13, the resist 80b is formed in the second substrate 10b and exposed on the polished surface of the second substrate 10b. In the region where the polarity changes. Next, a step of irradiating cluster ions on the surface of the second substrate 10b and the resist 80b is performed.
　クラスターイオンを照射する工程において、第２の基板１０ｂの基板本体２０ｂの一方の面に、ゲッタリング層４０ｂが形成される。ここで、第２の基板１０ｂの基板本体２０ｂの一方の面のうち、レジスト８０ｂが形成された位置にはゲッタリング層４０ｂが形成されない。即ち、極性が変化する境界Ｂには、ゲッタリング層４０ｂが形成されない。これにより、極性が変化する複数の領域５０ｂのそれぞれに独立してゲッタリング層が形成される。 In the step of irradiating cluster ions, the gettering layer 40b is formed on one surface of the substrate body 20b of the second substrate 10b. Here, the gettering layer 40b is not formed at a position where the resist 80b is formed on one surface of the substrate body 20b of the second substrate 10b. That is, the gettering layer 40 b is not formed at the boundary B where the polarity changes. Thus, gettering layers are formed independently in each of the plurality of regions 50b of which the polarity changes.
　次いで、レジスト８０ｂを除去する工程において、レジスト８０ｂが除去される。また、第１の基板１０ａも第２の基板１０ｂと同様に形成される。そして、複数の基板１０を積層する工程において、第１実施形態又は第２実施形態と同様に、第２の基板１０ｂと第１の基板１０ａとが積層される。 Next, in the step of removing the resist 80b, the resist 80b is removed. The first substrate 10a is also formed in the same manner as the second substrate 10b. Then, in the step of stacking the plurality of substrates 10, the second substrate 10b and the first substrate 10a are stacked as in the first embodiment or the second embodiment.
　以上の第３実施形態に係る半導体装置１の製造方法及び半導体装置１によれば、上記（８）の効果に加え、以下の効果を奏する。 According to the method of manufacturing the semiconductor device 1 and the semiconductor device 1 of the third embodiment described above, the following effects can be obtained in addition to the effect of (8).
　（９）レジスト８０ｂを形成する工程において、レジスト８０ｂは、第２の基板１０ｂ内に形成され、第２の基板１０ｂの研磨される面に露出する領域のうち、極性が変化する境界Ｂに重なる位置に形成される。これにより、極性が変化する複数の領域５０ｂ間にリークが発生することを抑制できる。 (9) In the step of forming the resist 80b, the resist 80b is formed in the second substrate 10b, and overlaps the boundary B where the polarity changes in the area exposed on the polished surface of the second substrate 10b. Formed in position. As a result, it is possible to suppress the occurrence of a leak between the plurality of regions 50b of which the polarity changes.
［第４実施形態］
　次に、第４実施形態に係る半導体装置１及び半導体装置１の製造方法について、図１４を参照して説明する。第４実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。 Fourth Embodiment
Next, the semiconductor device 1 according to the fourth embodiment and a method of manufacturing the semiconductor device 1 will be described with reference to FIG. In the description of the fourth embodiment, the same components will be assigned the same reference numerals, and the description thereof will be omitted or simplified.
　第４実施形態に係る半導体装置１は、図１４に示すように、第２の基板１０ｂが、金属の充填されるビア９０ｂを有する点で第１～第３実施形態と異なる。また、第４実施形態に係る半導体装置１は、ビア９０ｂを囲繞する位置にゲッタリング層４０ｂが形成される点で第１～第３実施形態と異なる。これに伴い、第４実施形態に係る半導体装置１の製造方法は、クラスターイオンを照射する工程において、クラスターイオンが、金属Ｍの充填されるビア９０ｂを囲繞する位置に照射される点で第１～第３実施形態と異なる。なお、第４実施形態において、第１の基板１０ａは、第２の基板１０ｂと同じ構成を有する。 The semiconductor device 1 according to the fourth embodiment is different from the first to third embodiments in that the second substrate 10b has a via 90b filled with metal as shown in FIG. The semiconductor device 1 according to the fourth embodiment is different from the first to third embodiments in that the gettering layer 40b is formed at a position surrounding the via 90b. Accordingly, in the method of manufacturing the semiconductor device 1 according to the fourth embodiment, in the step of irradiating cluster ions, cluster ions are irradiated at positions surrounding the via 90 b filled with the metal M. The third embodiment is different from the third embodiment. In the fourth embodiment, the first substrate 10a has the same configuration as the second substrate 10b.
　ビア９０ｂは、デバイス層３０ｂ及び基板本体２０ｂを厚さ方向に貫通して形成される。本実施形態において、ビア９０ｂは、Ｐ－ｗｅｌｌの領域５２ｂを貫通して形成される。また、ビア９０ｂは、基板本体２０ｂからデバイス層３０ｂに向かう厚さ方向において、徐々に拡径して形成される。ビア９０ｂは、例えば、銅等の金属Ｍが充填される。即ち、ビア９０ｂは、配線が形成される位置に配置される。 The via 90 b is formed to penetrate the device layer 30 b and the substrate body 20 b in the thickness direction. In the present embodiment, the via 90b is formed to penetrate the region 52b of the P-well. Also, the via 90 b is formed so as to gradually expand in diameter in the thickness direction from the substrate body 20 b toward the device layer 30 b. The via 90 b is filled with a metal M such as copper, for example. That is, the via 90b is disposed at the position where the wiring is formed.
　ゲッタリング層４０ｂは、ビア９０ｂを囲繞する位置に形成される。具体的には、ゲッタリング層４０ｂは、第２の基板１０ｂの基板本体２０ｂの一方の面のうち、ビア９０ｂを囲繞する位置に形成される。 The gettering layer 40 b is formed at a position surrounding the via 90 b. Specifically, the gettering layer 40b is formed at a position surrounding the via 90b on one surface of the substrate body 20b of the second substrate 10b.
　次に、本実施形態に係る半導体装置１の製造方法について説明する。 Next, a method of manufacturing the semiconductor device 1 according to the present embodiment will be described.
　研磨する工程は、第３実施形態と同様である。次いで、レジスト８０ｂを形成する工程において、第２の基板１０ｂの基板本体２０ｂの一方の面のうち、ビア９０ｂを囲繞する位置以外の領域に重なるレジスト８０ｂが形成される。次いで、クラスターイオンを照射する工程において、第２の基板１０ｂの基板本体２０ｂの一方の面と、レジスト８０ｂとにクラスターイオンが照射される。これにより、第２の基板１０ｂの基板本体２０ｂの一方の面のうち、ビア９０ｂを囲繞する位置にゲッタリング層４０ｂが構成される。 The step of polishing is the same as that of the third embodiment. Next, in the step of forming the resist 80b, a resist 80b is formed which overlaps the area other than the position surrounding the via 90b on one surface of the substrate body 20b of the second substrate 10b. Next, in the step of irradiating cluster ions, the cluster ions are irradiated on one surface of the substrate body 20b of the second substrate 10b and the resist 80b. Thus, the gettering layer 40b is formed at a position surrounding the via 90b on one surface of the substrate body 20b of the second substrate 10b.
　次いで、レジスト８０ｂを除去する工程において、レジスト８０ｂが除去される。また、第１の基板１０ａも第２の基板１０ｂと同様に形成される。第２の基板１０ｂと第１の基板１０ａを積層する工程は、第２実施形態や第３実施形態と同様である。 Next, in the step of removing the resist 80b, the resist 80b is removed. The first substrate 10a is also formed in the same manner as the second substrate 10b. The process of laminating the second substrate 10 b and the first substrate 10 a is the same as that of the second embodiment or the third embodiment.
　以上の第４実施形態に係る半導体装置１の製造方法及び半導体装置１によれば、上記（９）の効果に加え、以下の効果を奏する。 According to the method of manufacturing the semiconductor device 1 and the semiconductor device 1 of the fourth embodiment described above, the following effects can be obtained in addition to the effect of (9).
　（１０）クラスターイオンを照射する工程において、クラスターイオンは、金属Ｍが充填されるビア９０ｂを囲繞する位置に照射される。これにより、ビア９０ｂに充填される金属Ｍが基板本体２０ｂに侵入することを抑制でき、半導体装置１の信頼性を向上できる。 (10) In the step of irradiating cluster ions, the cluster ions are irradiated to a position surrounding the via 90 b filled with the metal M. Thereby, the metal M filled in the via 90 b can be prevented from invading the substrate body 20 b, and the reliability of the semiconductor device 1 can be improved.
　以上、本発明の半導体装置及び半導体装置の製造方法の好ましい各実施形態につき説明したが、本発明は、上述の実施形態に制限されるものではなく、適宜変更が可能である。 Although the preferred embodiments of the semiconductor device and the semiconductor device manufacturing method of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be modified as appropriate.
　例えば、上記実施形態におけるクラスターイオンについて、カーボン及び水素原子を含むとしたが、これに制限されない。即ち、クラスターイオンは、ゲッタリング層４０ｂを形成可能な他の種々の原子や分子を含むことができる。例えば、第３実施形態において極性の異なる複数の領域５０ｂのうちＰ－ｗｅｌｌの領域５２ｂに対しては、クラスターイオンとしてＢ１０Ｈ１４、Ｂ１８Ｈ２２等を照射しても良い。この場合、領域５１ｂを覆うようにレジスト８０ｂを形成しておく。 For example, although the cluster ion in the above embodiment includes carbon and hydrogen atoms, it is not limited thereto. That is, cluster ions can include various other atoms or molecules that can form the gettering layer 40b. For example, the region 52b of the P-well among the plurality of regions 50b of different polarities in the third embodiment may be irradiated with B10H14, B18H22 or the like as cluster ions. In this case, a resist 80b is formed to cover the region 51b.
　また、上記実施形態において、第１の基板１０ａ、第２の基板１０ｂ、及び第３の基板１０ｃを積層する形態について説明したが、４つ以上の基板１０が積層されるようにしてもよい。また、第１の基板１０ａはデバイス層３０ａが形成されない基板本体２０ａのみからなる基板でも良く、あるいは例えばガラス材等からなる支持基板でも良い。この場合、第１の基板はその上に複数の基板が積層された後に取り除かれてもよい。また、クラスターイオンを照射した面にさらに基板１０を積層する場合に、クラスターイオンを照射した面をさらに研磨してから積層してもよい。また、第２～第４実施形態において、第１の基板１０ａを第１の実施形態と同様とした上で、第１の基板１０ａ以外の基板１０を第２の基板１０ｂと同じ構造としてもよい。また、３つ以上の基板１０を積層する場合、最も上方に位置する基板（例えば、図７の紙面最上方の第３の基板１０ｃ）は、基板本体２０の一方の面が研磨されるのみでもよい。 In the above embodiment, the first substrate 10a, the second substrate 10b, and the third substrate 10c are stacked. However, four or more substrates 10 may be stacked. The first substrate 10a may be a substrate formed only of the substrate body 20a on which the device layer 30a is not formed, or may be a support substrate formed of, for example, a glass material or the like. In this case, the first substrate may be removed after multiple substrates are stacked thereon. Moreover, when laminating | stacking the board | substrate 10 further on the surface which irradiated cluster ion, you may laminate | stack, after grind | polishing the surface which irradiated cluster ion further. In the second to fourth embodiments, the first substrate 10a may be the same as the first embodiment, and the substrates 10 other than the first substrate 10a may have the same structure as the second substrate 10b. . When three or more substrates 10 are stacked, the uppermost substrate (for example, the third substrate 10c on the top of the drawing of FIG. 7) may be polished only by polishing one surface of the substrate body 20. Good.
　また、上記実施形態において、第１の基板１０ａは、基板本体２０ａの一方の面側にイントリンシックゲッタリング層が形成されてもよい。 In the above embodiment, the intrinsic gettering layer may be formed on the first surface side of the substrate body 20a of the first substrate 10a.
　また、上記第２～第４実施形態において、第１の基板１０ａを第２の基板１０ｂと同じ構成であるとしたが、第１の基板１０ａを第１の実施形態と同様とし、第２の基板１０ｂ及び第３の基板１０ｃを同様の構成としてもよい。 In the second to fourth embodiments, the first substrate 10a has the same configuration as the second substrate 10b, but the first substrate 10a is the same as the first embodiment, and the second The substrate 10 b and the third substrate 10 c may have the same configuration.
　１　半導体装置
　１０ａ　第1の基板
　１０ｂ　第２の基板
　２０，２０ａ，２０ｂ　基板本体
　３０，３０ａ，３０ｂ　デバイス層
　４０，４０ａ，４０ｂ　ゲッタリング層
　７０ｂ　素子領域
　８０ｂ　レジスト
　９０ｂ　ビア
　Ｂ　境界 Reference Signs List 1 semiconductor device 10a first substrate 10b second substrate 20, 20a, 20b substrate body 30, 30a, 30b device layer 40, 40a, 40b gettering layer 70b element region 80b resist 90b via B boundary

Claims (11)

  1. 　複数の基板が積層された半導体装置の製造方法であって、
    　第１の基板に対して第２の基板を積層する工程と、
    　前記第２の基板の面のうち、デバイス層が形成される面とは逆の面を研磨する工程と、
    　研磨された前記第２の基板の面に向けて、ゲッタリングに寄与する構成元素を含むクラスターイオンを照射して、クラスターイオンの構成元素を含むゲッタリング層を構成する工程と、
    を備える半導体装置の製造方法。     A method of manufacturing a semiconductor device in which a plurality of substrates are stacked,
    Laminating a second substrate to the first substrate;
    Polishing the surface of the second substrate opposite to the surface on which the device layer is formed;
    Irradiating a cluster ion containing a constituent element contributing to gettering toward the surface of the second substrate thus polished to form a gettering layer containing a constituent element of cluster ion;
    And a method of manufacturing a semiconductor device.
  2. 　前記第１の基板に対して前記第２の基板を積層する工程において、前記第２の基板の面のうち、デバイス層が形成される面が、前記第１の基板に対して対向配置される請求項１に記載の半導体装置の製造方法。 In the step of laminating the second substrate on the first substrate, the surface of the second substrate on which the device layer is formed is disposed to face the first substrate. A method of manufacturing a semiconductor device according to claim 1.
  3. 　前記第１の基板に対して前記第２の基板を積層する工程において、前記第２の基板の面のうち、デバイス層が形成される面とは逆の面が、前記第１の基板に対して対向配置される請求項１又は２に記載の半導体装置の製造方法。 In the step of laminating the second substrate to the first substrate, of the surfaces of the second substrate, the surface opposite to the surface on which the device layer is formed is the surface of the first substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is disposed to face each other.
  4. 　前記ゲッタリング層を構成する工程において、前記第２の基板の面のうち一部の領域に前記ゲッタリング層が構成される請求項１～３のいずれかに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein in the step of forming the gettering layer, the gettering layer is formed in a partial region of the surface of the second substrate.
  5. 　前記ゲッタリング層を構成する工程は、
    　前記第２の基板の面上にレジストを形成する工程と、
    　前記第２の基板の面と前記レジストにクラスターイオンを照射する工程と、
    　前記レジストを除去する工程と、
    を備える請求項４に記載の半導体装置の製造方法。     In the step of forming the gettering layer,
    Forming a resist on the surface of the second substrate;
    Irradiating the surface of the second substrate and the resist with cluster ions;
    Removing the resist;
    A method of manufacturing a semiconductor device according to claim 4, comprising:
  6. 　前記レジストを形成する工程において、前記レジストは、前記第２の基板内に形成される素子領域のうち、前記ゲッタリング層との距離が所定値以下となる素子領域に重なる位置に形成される請求項５に記載の半導体装置の製造方法。 In the step of forming the resist, the resist is formed at a position overlapping an element region in which a distance to the gettering layer is equal to or less than a predetermined value among the element regions formed in the second substrate. 6. A method of manufacturing a semiconductor device according to item 5.
  7. 　前記レジストを形成する工程において、前記レジストは、前記第２の基板内に形成され、前記第２の基板の研磨される面に露出する領域のうち、極性が変化する境界に重なる位置に形成される請求項５に記載の半導体装置の製造方法。 In the step of forming the resist, the resist is formed in the second substrate, and is formed at a position overlapping the boundary where the polarity changes among regions exposed on the polished surface of the second substrate. A method of manufacturing a semiconductor device according to claim 5.
  8. 　前記レジストを形成する工程において、前記レジストは、前記ゲッタリング層を形成する厚さよりも厚く形成される請求項５～７のいずれかに記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein in the step of forming the resist, the resist is formed to be thicker than a thickness of the gettering layer.
  9. 　クラスターイオンを照射する工程において、クラスターイオンは、金属が充填されるビアを囲繞する位置に照射される請求項５～８のいずれかに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 5 to 8, wherein in the step of irradiating cluster ions, the cluster ions are irradiated to a position surrounding the via filled with metal.
  10. 　第１の基板に対して第２の基板を積層する工程において、請求項２～８のいずれかに記載された前記第２の基板の複数が前記第１の基板に積層される半導体装置の製造方法。 9. A semiconductor device in which a plurality of the second substrates according to any one of claims 2 to 8 are stacked on the first substrate in the step of stacking the second substrate on the first substrate. Method.
  11. 　複数の基板が積層された半導体装置であって、
    　第１の基板と、
    　前記第１の基板に重ね合わされる第２の基板と、
    を備え、
    　少なくとも前記第２の基板は、クラスターイオンの構成元素を含むゲッタリング層を備え、
    　前記ゲッタリング層は、前記第２の基板の研磨された面側に形成される半導体装置。     A semiconductor device in which a plurality of substrates are stacked,
    A first substrate,
    A second substrate superimposed on the first substrate;
    Equipped with
    At least the second substrate includes a gettering layer containing a constituent element of cluster ions,
    The semiconductor device, wherein the gettering layer is formed on the polished surface side of the second substrate.
PCT/JP2017/038146 2017-10-23 2017-10-23 Semiconductor device and manufacturing method for semiconductor device WO2019082235A1 (en)

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