WO2019080124A1 - 多通道无源互调数字抵消电路 - Google Patents

多通道无源互调数字抵消电路

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Publication number
WO2019080124A1
WO2019080124A1 PCT/CN2017/108128 CN2017108128W WO2019080124A1 WO 2019080124 A1 WO2019080124 A1 WO 2019080124A1 CN 2017108128 W CN2017108128 W CN 2017108128W WO 2019080124 A1 WO2019080124 A1 WO 2019080124A1
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WO
WIPO (PCT)
Prior art keywords
filter
output port
input port
channel
circuit
Prior art date
Application number
PCT/CN2017/108128
Other languages
English (en)
French (fr)
Inventor
王昊
陈莹莹
罗宇平
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201780095095.1A priority Critical patent/CN111108694B/zh
Priority to PCT/CN2017/108128 priority patent/WO2019080124A1/zh
Priority to EP17929753.6A priority patent/EP3687074B1/en
Publication of WO2019080124A1 publication Critical patent/WO2019080124A1/zh
Priority to US16/857,815 priority patent/US10911084B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/50—Circuits using different frequencies for the two directions of communication
    • H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
    • H04B1/525—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements
    • H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/01—Equalisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08—Access point devices
    • H04W88/085—Access point devices with remote components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of passive intermodulation cancellation, and in particular to a multi-channel passive intermodulation digital cancellation circuit
  • the antenna feeder system will generate passive intermodulation due to bad parts, loose screws, vibration, etc.
  • Passive Inter Modulation (PIM) interference signal when the frequency of the PIM interference signal falls within the receiving frequency band, it will overlap or expand the spectrum of the receiving signal, which seriously affects the receiving sensitivity of the base station system, and thus affects the uplink throughput rate of the network.
  • PIM Passive Inter Modulation
  • the PIM canceller is capable of nonlinearly modeling and canceling PIM interference signals falling into the receive band on the digital domain.
  • PIM interference signals for multi-transmit and receive RF systems with channel combiners, such as bridges and V-network structures, cannot be offset.
  • the embodiment of the invention discloses a multi-channel passive intermodulation digital cancellation circuit, which can solve the PIM interference signal of the multi-transmitting and receiving radio system in the form of a bridge including a bridge and a V network structure, which cannot be cancelled. problem.
  • an embodiment of the present invention provides a multi-channel PIM digital cancellation circuit, including:
  • a first frequency shift rate module a second frequency shift rate module, a first conversion circuit, a second conversion circuit, a duplexer, a second transmit duplexer, a channel combiner, a third conversion circuit, and cascade filtering a circuit, a PIM canceller, a feedback circuit, and a first adder;
  • An input port of the first frequency shift rate module is a first input port of the multi-channel PIM digital cancellation circuit, and an output port of the first frequency shift rate module is coupled to an input port of the first conversion circuit Connected, an output port of the first conversion circuit is connected to a first input port of the duplexer, and a first output port of the duplexer is connected to a first input/output port of the channel combiner ;
  • An input port of the second frequency-shifting rate module is used as a second input port of the multi-channel PIM digital cancellation circuit, and an output port of the second frequency-shifting rate module is connected to an input port of the second conversion circuit Connected, an output port of the second conversion circuit is connected to an input port of the second transmitting duplexer, an output port of the second transmitting duplexer and a second input/output port of the channel combiner Connected
  • the first input port of the cascaded filtering module is connected to the output port of the first frequency-shifting rate module, and the output of the second input port of the cascaded filtering module and the output of the second frequency-shifting rate module a port is connected, a first output port and a second output port of the cascade filtering module are both connected to an input port of the PIM canceller, an output port of the PIM canceller and the first adder The first input port is connected;
  • a first input/output port of the channel combiner is connected to a second input port of the duplexer, and a second output port of the duplexer is connected to an input port of the third conversion circuit,
  • An output port of the third conversion circuit is coupled to a second input port of the first adder, and an output port of the first adder is an output port of the multi-channel PIM digital cancellation circuit.
  • the cascaded filtering circuit includes:
  • First channel filter second channel filter, first equalization filter, second equalization filter, first linear filter, second linear filter, third linear filter, fourth linear filter, second Adder and third adder;
  • the input port of the first channel filter and the input port of the second channel filter are respectively a first input port and a second input port of the cascade filter circuit, and an output port of the first channel filter Connected to an input port of the first equalization filter, an output port of the second channel filter is connected to an input port of the second equalization filter;
  • An output port of the first equalization filter is connected to an input port of the first linear filter and an input port of the second linear filter, and an output port of the second equalization filter and the third An input port of the linear filter is connected to an input port of the fourth linear filter;
  • An output port of the first linear filter and an output port of the third linear filter are respectively connected to a first input port and a second input port of the second adder, the second linear filter
  • An output port and an output port of the fourth linear filter are respectively connected to the first input port and the second input port of the third adder;
  • An output port of the second adder and an output port of the third adder are a first output port and a second output port of the cascade filter circuit, respectively.
  • the first conversion circuit includes:
  • a first digital domain downlink a first digital to analog converter, and a first analog domain downlink
  • An input port of the first digital domain downlink is an input port of the first conversion circuit, and an output port of the first digital domain downlink is connected to an input port of the first digital-to-analog converter, An output port of the first digital-to-analog converter is connected to an input port of the first analog domain downlink, and an output port of the first analog domain downlink is an output port of the first conversion circuit.
  • the second conversion circuit includes:
  • An input port of the second digital domain downlink is an input port of the second conversion circuit, and an output port of the second digital domain downlink is connected to an input port of the second digital-to-analog converter, An output port of the second digital-to-analog converter is connected to an input port of the second analog domain downlink, and an output port of the second analog domain downlink is an output port of the second conversion circuit.
  • the duplexer comprises:
  • An input port of the first transceiver duplexer is a first input port of the duplexer, and an output port of the first transmit duplexer is a first output port of the duplexer;
  • the input port of the receiving duplexer is a second input port of the duplexer, and the output port of the receiving duplexer is a second output port of the duplexer.
  • the third conversion circuit comprises:
  • An input port of the analog domain uplink is an input port of the third conversion circuit, and an output port of the analog domain uplink is connected to an input port of a first analog to digital converter, the first modulus
  • the output port of the converter is the output port of the third conversion circuit.
  • the feedback circuit comprises:
  • a combiner a second analog to digital converter, a digital domain feedback link, and a third memory
  • An input port of the combiner is an input port of the feedback circuit, and an output port of the combiner is connected to an input port of the second analog to digital converter;
  • An output port of the second analog to digital converter is coupled to an input port of the digital domain feedback link, and an output port of the digital domain feedback link is coupled to an input port of the third memory.
  • the multi-channel PIM digital cancellation circuit further includes a first data data collection node U0, a second data collection node U1, and a third data collection node S0;
  • the first data collection node U0 is located at an output port of the first frequency shift rate module, and the second data collection node U1 is located at an output port of the second frequency shift rate module, the third The data collection node S0 is located at the output port of the second digital domain downlink.
  • the multi-channel PIM digital cancellation circuit further includes a first coupling node P0 and a second coupling node P1;
  • the first coupling node P0 is connected to an output port of the first transmitting duplexer
  • the second coupling node P1 is connected to an output port of the second transmitting duplexer.
  • the multi-channel PIM digital cancellation circuit further includes a first memory and a second memory;
  • An input port of the first memory is coupled to an output port of the first frequency shift rate module, and an input port of the second memory is coupled to an output port of the second frequency shift rate module.
  • the multi-channel PIM digital cancellation circuit further includes a processor, the processor including a first processor, a second processor, and a third processor;
  • An output port of the first processor, an output port of the second memory, and an output port of the third memory are both connected to an input port of the first processor, and an output port of the first processor and the first An input port of a coefficient register of a channel filter is connected to an input port of a coefficient register of the second channel filter;
  • An output port of the second processor is coupled to an input port of a coefficient register of the first equalization filter and an input port of a coefficient register of the second equalization filter;
  • An output port of the third processor and an input port of a coefficient register of the first linear filter, an input port of a coefficient register of the second linear filter, and an input of a coefficient register of the third linear filter The port is coupled to an input port of a coefficient register of the fourth linear filter.
  • the first processor is configured to store data collected from the first data collection node U0 into the first memory
  • the first processor is further configured to store data collected from the second data collection node U1 into the second memory;
  • the first processor is further configured to store data collected from the third data collection node S0 into the third memory.
  • the first processor is further configured to:
  • the filter coefficients of the first channel filter and the filter coefficients of the second channel filter are respectively downloaded to a coefficient register of the first channel filter and a coefficient register of the second channel filter.
  • the second processing is further used to:
  • the filter coefficients of the first equalization filter and the filter coefficients of the second equalization filter are respectively downloaded to a coefficient register of the first equalization filter and a coefficient register of the second equalization filter.
  • the third processor is further configured to:
  • the delay difference of the channel filter in the cascaded filter circuit after the downlink signal, the digital-to-analog converter and the analog domain downlink of the transmitted signal is generated. , phase difference and other channel response inconsistency compensation; the equalization filter in the cascade filter circuit is used to simulate the group delay unevenness of the duplexer in the multi-channel PIM digital cancellation circuit; the linear filtering of the cascade filter.
  • the S-parameters of the channel combiner in the multi-channel PIM digital cancellation circuit are fitted, and the combined process of the channel combiner is accurately fitted in the digital domain, so that the multi-channel PIM digital cancellation circuit can be offset in the inclusion.
  • the channel combiner transmits and receives signals of PIM interference signals of the radio frequency system.
  • FIG. 1 is a schematic structural diagram of a multi-channel PIM digital cancellation circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a cascade filtering circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic partial structural diagram of a multi-channel PIM digital cancellation circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another multi-channel PIM digital cancellation circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another cascading filter circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of another multi-channel PIM digital cancellation circuit according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a multi-channel digital PIM cancellation circuit according to an embodiment of the present invention.
  • the multi-channel PIM digital cancellation circuit includes:
  • the first frequency shift rate module 101, the first memory 102, the first conversion circuit 103, the duplexer 104, the channel combiner 105, the second frequency shift rate module 106, the second memory 107, and the second conversion circuit 108 The second transmit duplexer 109, the cascade filter circuit 110, the PIM canceller 111, the third conversion circuit 112, the feedback circuit 113, and the first adder 114.
  • the input port of the first frequency-shifting rate module 101 is the first input port of the multi-channel PIM digital cancellation circuit, the output port of the first frequency-shifting rate module 101 and the input port of the first conversion circuit 103.
  • the output port of the first conversion circuit 103 is connected to the first input port of the duplexer 104, and the first output port of the duplexer 104 is connected to the first input and output port of the channel combiner 105. connection.
  • the first conversion circuit 103 includes a first digital domain downlink 1031, a first digital to analog converter 1032, and a first analog domain downlink 1033.
  • An input port of the first digital domain downlink 1031 is an input port of the first conversion circuit 103, and an output port of the first digital domain downlink 1031 is connected to an input port of the first digital-to-analog converter 1032.
  • An output port of the first digital-to-analog converter 1032 is connected to an input port of the first analog domain downlink 1033, and an output port of the first analog domain downlink 1033 is an output port of the first conversion circuit.
  • the duplexer 104 described above includes a first transmit duplexer 1041 and a receive duplexer 1042.
  • the input port 1041 of the first transmitting duplexer is a first input port of the duplexer 104
  • the output port of the first transmitting duplexer 1041 is a first output port of the duplexer 104
  • the receiving duplex The input port and the output port of the device 1042 are the second input port and the second output port of the duplexer 104, respectively.
  • the output port of the first transmitting duplexer 1041 and the input port of the receiving duplexer 1042 are connected to the common nail head of the duplexer 104. From the outside, the duplexer 104 has an input and output port. The input and output port is connected to the first input and output port of the channel combiner 105.
  • the output port of the first conversion circuit is connected to the first input port of the duplexer 104, specifically the output port of the first conversion circuit and the input port of the first transmit duplexer 1041 of the duplexer 104.
  • the first output port of the duplexer 104 is connected to the first input and output port of the channel combiner 105, specifically the output port of the first transmit duplexer 1041 of the duplexer 104 and the channel.
  • the first input and output ports of the combiner 105 are connected.
  • the input port of the second frequency shift rate module 106 is the second input port of the multi-channel PIM digital cancellation circuit, the output port of the second frequency shift rate module 106 and the input port of the second conversion circuit 108. Connected, the output port of the second conversion circuit 108 is connected to the input port of the second transmitting duplexer 109, and the output port of the second transmitting duplexer 109 and the second input and output of the channel combiner 105 are connected. The ports are connected.
  • the second conversion circuit 108 includes a second digital domain downlink 1081 and a second digital to analog converter 1082. And a second analog domain downlink 1083.
  • the input port of the second digital domain downlink 1081 is an input port of the second conversion circuit 108, and the output port of the second digital domain downlink 1081 is connected to an input port of the second digital-to-analog converter 1082.
  • An output port of the second digital-to-analog converter 1082 is connected to an input port of the second analog domain downlink 1083, and an output port of the second analog domain downlink 1083 is an output port of the second conversion circuit 108.
  • the multi-channel PIM digital cancellation circuit further includes a first data collection node U0 and a second data collection node U1.
  • the first data collection node U0 is connected to the output port of the first frequency shift rate module 101
  • the second data collection node U1 is connected to the output port of the second frequency shift rate module 106.
  • the first input port of the cascade filter circuit 110 is connected to the first data collection node U0
  • the second input port of the cascade filter circuit 110 is connected to the second data collection node U1.
  • the first input port of the cascade filter circuit 110 is connected to the output port of the first frequency shift rate module 101
  • the second input port of the cascade filter circuit 110 is connected to the output port of the second frequency shift rate module 106. connection.
  • the first output port and the second output port of the cascade filter circuit 110 are both connected to the input port of the PIM canceller 111, and the output port of the PIM canceller 111 is connected to the first input port of the first adder 114. connection.
  • the input port of the first memory 102 is connected to the first data collection node U0, and the input port of the second memory 107 is connected to the first data collection node U1.
  • the input port of the first memory 102 is connected to the output port of the first frequency shift rate module 101, and the input port of the second memory 107 is connected to the output port of the second frequency shift rate module 106. connection.
  • the first input/output port of the channel combiner 105 is connected to the second input port of the duplexer 104 (ie, the input port of the receiving duplexer 1042), and the second output port of the duplexer 104 (ie, The output port of the receiving duplexer 1042 is connected to the input port of the third converting circuit 112, and the output port of the third converting circuit 112 is connected to the second input port of the first adder 114, the first The output port of adder 114 is the output port of the multi-channel PIM digital cancellation circuit described above.
  • the third conversion circuit 112 described above includes a first analog to digital converter 1121 and an analog domain uplink 1122.
  • the input port of the analog domain uplink is an input port of the third converter circuit, and the output port of the analog domain uplink is connected to an input port of the first analog-to-digital converter, the first analog-to-digital converter
  • the output port is the output port of the above third conversion circuit.
  • the multi-channel PIM digital cancellation circuit further includes a first coupling node P0 and a second coupling node P1.
  • the first coupling node P0 is located between the first output port of the duplexer 104 (ie, the output port of the first transmitting duplexer 1041) and the first input/output port of the channel combiner 105
  • the second The coupling node P1 is located between the second transmitting duplexer 109 and the second input/output port of the channel combiner 105.
  • the first coupling node P0 and the second coupling node P1 are both connected to an input port of the feedback circuit 113.
  • the feedback circuit 113 includes a combiner 1131, a second analog to digital converter 1132, a digital domain feedback link 1133, and a third memory 1134.
  • An input port of the combiner 1131 is an input port of the feedback circuit 114, an output port of the combiner 1131 is connected to an input port of the second analog-to-digital converter 1132, and the second analog-to-digital converter 1132 is configured as described above.
  • An input port of the digital domain feedback link 1133 is connected, and an output port of the digital domain feedback link 1133 is connected to an input port of the third memory 1134.
  • the first transmission signal Ch0 is input to the multi-channel PIM digital cancellation circuit through the input port of the first frequency shift rate module 101 described above.
  • the first frequency-shifting rate module 101 transmits the first transmission signal obtained after the processing to the first conversion circuit 103 after sequentially performing frequency shifting, variable rate, and clipping processing on the first transmission signal Ch0.
  • a digital domain downlink 1031 wherein the first digital domain downlink 1031 performs digital predistortion, quadrature modulation compensation (QMC) processing, etc. on the first transmission signal, and performs a second process after processing.
  • the transmission signal is transmitted to the first digital-to-analog converter 1032, and the first digital-to-analog converter 1032 converts the second transmission signal from the digital domain to the analog domain.
  • the first digital-to-analog converter 1032 performs the above-mentioned
  • the second transmission signal is converted from the digital signal to the analog signal to obtain a third transmission signal, and the third transmission signal is transmitted to the first analog domain downlink 1033.
  • the first analog domain downlink 1033 performs power amplifier processing and the like on the third transmission signal to obtain a fourth transmission signal, and transmits the fourth transmission signal to the first transmitting duplexer 104, the first transmitting duplexer
  • the device 1041 transmits the fourth transmission signal to the channel combiner 105.
  • the second transmission signal Ch1 is input to the multi-channel PIM digital cancellation circuit through the input port of the second frequency shift rate module 106.
  • the second frequency shift rate module 106 transmits the fifth transmission signal obtained after the processing to the second conversion signal 108 after the frequency shifting, the variable rate, and the clipping processing are sequentially performed on the second transmission signal Ch1.
  • a second digital domain downlink 1081 wherein the second digital domain downlink 1081 performs digital predistortion, quadrature modulation compensation (QMC), and the like on the sixth transmission signal, and processes the sixth obtained after processing.
  • the transmission signal is transmitted to the second digital-to-analog converter 1082, and the first digital-to-analog converter 1082 converts the sixth transmission signal from the digital domain to the analog domain.
  • the second digital-to-analog converter 1082 The sixth transmission signal is converted from the digital signal to the analog signal to obtain a seventh transmission signal, and the seventh transmission signal is transmitted to the second analog domain downlink 1083.
  • the second analog domain downlink 1083 performs power amplifier processing and the like on the seventh transmission signal to obtain an eighth transmission signal, and transmits the eighth transmission signal to the second transmitting duplexer 109, the first transmitting duplexer
  • the transmitter 109 transmits the eighth transmission signal described above to the channel coupler 105 described above.
  • QMC processing specifically compensates for phase offset, amplitude offset, and local oscillator leakage during the Analog Quadrature Modulation (AQM) process. This function is specifically implemented by the QMC module.
  • the channel combiner 105 combines the fourth transmission signal and the eighth transmission signal together and sends them to the antenna port for transmission.
  • the signals collected by the first coupling node P0 and the second coupling node P1 are the fourth transmission signal and the eighth transmission signal, respectively.
  • the combiner 1131 After the fourth transmission signal and the eighth transmission signal are transmitted to an input port of the feedback circuit 113 (ie, an input port of the combiner 1131), the combiner 1131 performs the fourth transmission signal and the eighth transmission signal.
  • the second analog-to-digital converter 1132 converts the first processed signal from the analog domain to the digital domain, that is, converts the first processed signal from an analog signal to a digital signal to obtain a second processed signal, and the second digital domain downlink After performing frequency shifting and variable rate processing on the second processed signal, a third processed signal is obtained, and the third processed signal is stored in the third memory 1134.
  • the cascade filter circuit 110 After the first input port and the second input port of the cascade filter circuit 110 respectively input the first transmit signal and the fifth transmit signal, the cascade filter circuit 110 is configured according to the first transmit signal and the second transmit signal. The first output port and the second port respectively output the first filtered signal and the second filtered signal. After the input port of the PIM canceller 111 inputs the first filtered signal and the second filtered signal, the PIM canceller 111 is configured according to the first filtered signal. The second and second filtered signals generate a PIM cancellation signal and are output from its output port.
  • the multi-channel PIM digital cancellation circuit further includes a processor.
  • the processor After the first frequency-shifting rate module 101 outputs the first transmission signal, the processor stores the first transmission signal in the first memory 102, that is, the data storage collected by the processor from the first data collection node U0. Go to the first memory 102 described above.
  • the processor stores the fifth sending information in the second memory 107, that is, the processor collects from the second data collecting node U1. The arrived data is stored in the second memory 107 described above.
  • first memory 102, the second memory 107, and the third memory 1134 may be a random access memory (RAM).
  • RAM random access memory
  • the first memory 102, the second memory 107, and the third memory 1134 described above are different RAMs.
  • the antenna of the channel combiner 105 transmits the first received signal to the receiving duplexer 1042, and the receiving duplexer 1042 transmits the first received signal to the analog
  • the domain uplink 1122 is configured to perform low noise, filtering, and the like on the first received signal to obtain a second received signal.
  • the first analog-to-digital converter 1032 converts the second received information from the analog domain to the digital domain, that is, converts the second received signal from an analog signal to a digital signal to obtain a third received signal.
  • the third received signal may be regarded as the first transmit signal Ch0 plus the PIM interference signal, and the PIM cancellation signal is a PIM interference signal simulated by the multi-channel PIM digital cancellation circuit.
  • the third received signal is subtracted from the PIM cancellation signal to obtain the corrected signal, that is, the first transmission signal Ch0.
  • FIG. 2 is a schematic structural diagram of a cascaded filter circuit according to an embodiment of the present invention.
  • the circuit 110 includes: a first channel filter 1101, a second channel filter 1102, a first equalization filter 1103, a second equalization filter 1104, a first linear filter 1105, and a second linear filter.
  • the input port of the first channel filter 1101 and the input port of the second channel filter 1102 are respectively a first input port and a second input port of the cascade filter circuit 110, and an input port of the first channel filter 1101.
  • the input port of the second channel filter 1102 is connected to the input port of the second equalization filter 1104.
  • An input port of the first linear filter 1105 and an input port of the second linear filter 1106 are connected to an output port of the first equalization filter 1103, and an input port of the third linear filter 1107 and the fourth
  • the input ports of the linear filter 1108 are each connected to the output port of the second equalization filter 1104 described above.
  • the output port of the first linear filter 1105 and the output port of the third linear filter 1107 are respectively connected to the first input port and the second input port of the second adder 1109, and the second linear filter 1106
  • the output port and the output port of the fourth linear filter 1108 are connected to the first input port and the second input port of the third adder 1110, respectively.
  • the output port of the second adder 1109 and the output port of the third adder 1110 are respectively a first output port and a second output port of the cascade filter circuit 110.
  • the first channel filter 1101 After the first processing signal U0 is input to the first channel filter 1101, the first channel filter 1101 outputs a third filtered signal F1; after the second processed signal U1 is input to the second channel filter 1102, the second pass The filter 1102 outputs a fourth filtered signal F2. among them, And FIR_CH0 and FIR_CH1 are the filter coefficients of the first channel filter 1101 and the filter coefficients of the second channel filter 1102, respectively.
  • the third filtered signal F1 is input to the first equalization filter 1103
  • the fourth filtered signal F2 is input to the second equalization filter 1104, the second pass The filter 1104 outputs a fourth filtered signal F4.
  • DUP_EQ1 and DUP_EQ2 are the filter coefficients of the first equalization filter 1103 and the filter coefficients of the second equalization filter 1104, respectively.
  • the fifth filtered signal F3 is input to the first linear filter 1105 and the second linear filter 1106, the first linear filter 1105 and the second linear filter 1106 respectively output the seventh filtered signal F5 and the eighth filtered signal.
  • HB_FIR1, HB_FIR2, HB_FIR3, and HB_FIR4 are the filter coefficients of the first linear filter 1105, the filter coefficients of the second linear filter 1106, the filter coefficients of the third linear filter 1107, and the filtering of the fourth linear filter 1108, respectively. coefficient.
  • the seventh filter signal F5 and the ninth filter signal F7 are respectively input to the second adder 1109 through the first input port and the second input port of the second adder 1109, the second adder 1109 outputs the first filter signal.
  • TX0; the eighth filter signal F6 and the tenth filter signal F8 are respectively input to the third adder 1110 through the first input port and the second input port of the third adder 1110, and the third adder 1110 outputs the above Two filtered signals TX1.
  • first channel filter 1101 and the second channel filter 1102 compensate channel response such as delay difference and phase difference generated by the first transmission signal Ch0 and the second transmission signal Ch1 through different channels.
  • the inconsistency is such that the first filtered signal and the second filtered signal input by the PIM canceller 111 are consistent with the characteristics of the first fourth transmit signal and the eighth transmit signal input by the channel combiner, respectively.
  • the first equalization filter 1103 and the second equalization filter 1104 are used to simulate the group delay unevenness characteristic of the above-described transmitting duplexer.
  • the above four sets of linear filters are used to simulate the combined relationship and process of the above-described multi-channel combiner 105.
  • the multi-channel PIM digital cancellation circuit further includes a processor 115.
  • the processor 115 includes a first processor 1151, a second processor 1152, and a third processor 1153.
  • the output port of the first memory 102, the output port of the second memory 107, and the output port of the third memory 1134 are both connected to the input port of the first processor 1151, and the coefficient register 1101 of the first channel filter is The input port and the input port of the coefficient register 1102 of the second channel filter are both connected to the output port of the first processor 1151.
  • the input port of the coefficient register 1103 of the first equalization filter and the input port of the coefficient register 1104 of the second equalization filter are both connected to the output port of the second processor 1152, and the coefficient register of the first linear filter.
  • An input port of 1105, an input port of the coefficient register 1106 of the second linear filter, an input port of the coefficient register 1107 of the third linear filter, and an input port of the coefficient register 1108 of the fourth linear filter are both the same as the above.
  • the output ports of the three processors 1153 are connected.
  • the first processor 1151 acquires the first transmission signal from the first memory 102, acquires the fifth transmission signal from the second memory 107, and acquires the third processing signal from the third memory 1134.
  • the first processor 1151 performs LS linear interpolation fitting according to the first transmit signal, the fifth transmit signal, and the third processed signal to obtain the filter coefficient FIR_CH0 of the first channel filter 1101 and the second channel filter 1102. Filter coefficient FIR_CH1.
  • the first processor 1151 downloads FIR_CH0 and FIR_CH1 into the coefficient register 1101 of the first channel filter and the coefficient register 1102 of the second channel filter, respectively.
  • the second processor 1152 pairs the duplexer 104 (including the first transmit duplexer 1041 and the receive dual)
  • the processor 1042 performs a transmit signal and a receive signal test to obtain two sets of group delay parameters or S parameters of the duplexer 104.
  • the second processor 1152 converts the S parameter of the duplexer into a group delay parameter.
  • the second processor 1152 performs LS linear interpolation fitting according to the two groups of group delay parameters to obtain the filter coefficient DUP_EQ1 of the first equalization filter and the filter coefficient DUP_EQ2 of the second equalization filter.
  • the second processor 1152 downloads DUP_EQ1 and DUP_EQ2 to the coefficient register 1103 of the first equalization filter and the coefficient register 1104 of the second equalization filter, respectively.
  • the third processor 1153 tests the channel combiner to obtain the S parameter of the channel combiner. Then, the third processor 1153 obtains frequency response information of signals from P0 to H0, P0 to H1, P1 to H0, P1 to H1 according to the S parameter (refer to FIG. 1 herein).
  • the third processor 1153 uses four sets of linear filters (including a first linear filter 1105, a second linear filter 1106, a third linear filter 1107, and a fourth linear filter 1108) to linearize the above four paths respectively. Interpolation fitting yields the filter coefficients of four sets of linear filters: HB_FIR1, HB_FIR2, HB_FIR3, and HB_FIR4.
  • the third processor downloads the four filter coefficients HB_FIR1, HB_FIR2, HB_FIR3, and HB_FIR4 to the coefficient register 1105 of the first linear filter, the coefficient register 1106 of the second linear filter, and the coefficient register of the third linear filter, respectively. 1107 and the coefficient register 1108 of the fourth linear filter.
  • first processor 1151, the second processor 1152, and the third processor 1153 may all be DSP chips, and the foregoing first processor 1151, second processor 1152, and third processor 1153 may be The same DSP chip can also be different DSP chips.
  • channel combiner in the multi-channel PIM digital cancellation circuit described above in FIGS. 1-3 is a bridge.
  • the delay difference of the channel filter in the cascaded filter circuit after the downlink signal, the digital-to-analog converter and the analog domain downlink of the transmitted signal is generated. , phase difference and other channel response inconsistency compensation; the equalization filter in the cascade filter circuit is used to simulate the group delay unevenness of the duplexer in the multi-channel PIM digital cancellation circuit; the linear filtering of the cascade filter.
  • the S-parameters of the channel combiner in the multi-channel PIM digital cancellation circuit are fitted, and the combined process of the channel combiner is accurately fitted in the digital domain, so that the multi-channel PIM digital cancellation circuit can be offset in the inclusion.
  • the channel combiner transmits and receives signals of PIM interference signals of the radio frequency system.
  • FIG. 4 is a schematic structural diagram of a multi-channel PIM digital cancellation circuit according to an embodiment of the present invention. As shown in FIG. 4, the above circuit includes:
  • the first frequency shift rate module 401, the first memory 402, the first conversion circuit 403, the duplexer 404, the channel combiner 405, the second frequency shift rate module 406, the second memory 407, and the second conversion circuit 408 The second transmit duplexer 409, the cascade filter circuit 410, the PIM canceller 411, the third conversion circuit 412, the feedback circuit 413, and the first adder 414.
  • the first input and output port of the channel combiner 410 and the first output port of the duplexer 404 ie, the output port of the first transmit duplexer 4041) and the second input port (ie, the input of the receive duplexer 4042)
  • the port is connected, and the second input/output port of the channel combiner 410 is connected to the output port of the second transmitting duplexer 409.
  • the channel combiner further includes N antennas, and the first input and output ports and the second input and output ports of the channel combiner are connected to the N antennas.
  • the signal output by the first transmitting duplexer is transmitted through the N antennas of the channel combiner, and the signal output by the second transmitting duplexer is also transmitted through the N antennas of the channel combiner.
  • FIG. 5 is a schematic structural diagram of a cascaded filter circuit according to an embodiment of the present invention.
  • the cascade filter circuit includes: a first channel filter, a second channel filter, a first equalization filter, a second equalization filter, N linear filters, and N/2 adders.
  • the N linear filters are, in order, a linear filter 1, a linear filter 2, a linear filter 3, a linear filter 4, a linear filter 5, a linear filter 6, a linear filter N-1, and a linear filter N. And are numbered 1, 2, 3, 4, 5, 6, ... N-1 and N, respectively.
  • the above N/2 adders are, in order, adder 1, adder 2, adder 3, adder N/2, and are numbered 1, 2, 3, ..., N/2, respectively. Wherein, the above N is an even number greater than 2.
  • the input port of the first channel filter and the input port of the second channel filter are respectively a first input port and a second input port of the cascade filter circuit.
  • the output port of the first channel filter is connected to the input port of the first equalization filter, and the output port of the second channel filter is connected to the input port of the second equalization filter.
  • An output port of the first equalization filter is connected to an input port of an odd-numbered line filter among the N linear filters, and an output port of the second equalization filter and the N linear filters are numbered even The input ports of the linear filter are connected.
  • An output port of each of the above two linear filters (including an output port of the linear filter i and an output port of the linear filter j) is connected to the first input port and the second input port of the adder m .
  • the relationship between the number i of the linear filter i and the number j of the linear filter j satisfies the relationship that the difference between j and i is 1 and j is greater than 2 and less than or equal to an even number of N/2, i is greater than 0 and An odd number less than N/2.
  • the output ports of the above N/2 adders are the output ports of the cascade filter circuit described above.
  • the first channel filter After the first processing signal U0 is input to the first channel filter, the first channel filter outputs a first filtered signal F1; after the second processed signal U1 is input to the second channel filter, the second pass filter outputs The second filtered signal F2. among them, And FIR_CH0 and FIR_CH1 are the filter coefficients of the first channel filter and the filter coefficients of the second channel filter, respectively.
  • the first equalization filter After the first filtered signal F1 is input to the first equalization filter, the first equalization filter outputs a third filtered signal F3; after the second filtered signal F2 is input to the second equalization filter, the second filtered filter outputs The fourth filtered signal F4. among them, And DUP_EQ1 and DUP_EQ2 are the filter coefficients of the first equalization filter and the filter coefficients of the second equalization filter, respectively.
  • the third filtered signal F3 passes through the linear filter having an odd number among the N linear filters, and the linear filters numbered odd in the N linear filters respectively output the first linear filtered signals S1, S3, and S5. ...S(N-1).
  • the fourth filtered signal F4 passes through the linear filter numbered as an even number among the N linear filters, and the linear filters numbered evenly among the N linear filters respectively output the first linear filtered signals S2, S4, S6... ...SN.
  • the above And HB_FIR1, HB_FIR3, HB_FIR5, ..., HB_FIR(N-1) are respectively linear filters of odd numbers in the above N linear filters
  • HB_FIR2, HB_FIR4, HB_FIR6, ... HB_FIRN are respectively numbered in the above N linear filters. Odd linear filter.
  • N/2 second linear filtered signals TX1 are obtained.
  • TX1 S1+S2
  • TX2 S3+S4
  • the multi-channel PIM digital cancellation circuit further includes a processor, and the processor includes a first processor, a second processor, and a third processor.
  • the output port of the first memory, the output port of the second memory, and the output port of the third memory are both connected to an input port of the first processor, an input port of a coefficient register of the first channel filter, and the foregoing
  • the input ports of the coefficient registers of the second channel filter are all connected to the output ports of the first processor described above.
  • the input port of the coefficient register of the first equalization filter and the input port of the coefficient register of the second equalization filter are both connected to the output port of the second processor, and the input port of the coefficient register of the N sets of linear filters Both are connected to the output port of the third processor described above.
  • the first processor acquires the first transmission signal from the first memory, acquires the fifth transmission signal from the second memory, and acquires the third processing signal from the third memory.
  • the first processor performs LS linear interpolation fitting according to the first transmit signal, the fifth transmit signal, and the third processed signal to obtain the filter coefficient FIR_CH0 of the first channel filter and the filter coefficient of the second channel filter. FIR_CH1.
  • the first processor downloads FIR_CH0 and FIR_CH1 to the coefficient register of the first channel filter and the coefficient register of the second channel filter, respectively.
  • the second processor transmits a signal to the duplexer (including the first transmit duplexer and the receive duplexer) And receiving a signal test to obtain two sets of group delay parameters or S parameters of the duplexer.
  • the second processor converts the S parameter of the duplexer into a group delay parameter.
  • the second processor performs LS linear interpolation fitting according to the two groups of group delay parameters to obtain the filter coefficient DUP_EQ1 of the first equalization filter and the filter coefficient DUP_EQ2 of the second equalization filter.
  • the second processor 1152 acquires DUP_EQ1 and DUP_EQ2
  • the second processor downloads DUP_EQ1 and DUP_EQ2 to the coefficient register and the first equalization filter respectively.
  • the equalization filter is in the coefficient register.
  • the third processor adopts N sets of linear filters to perform linear interpolation fitting on the N-path responses respectively, and obtains filter coefficients of N sets of linear filters: HB_FIR1, HB_FIR2, HB_FIR3, ... HB_FIRN.
  • the third processor downloads the N filter coefficients into the coefficient registers of the N sets of linear filters, respectively.
  • the first channel filter and the second channel filter compensate for the inconsistency of the channel response such as the delay difference and the phase difference generated by the first transmission signal Ch0 and the second transmission signal Ch1 after passing through different channels.
  • the first filter signal and the second filter signal input by the PIM canceller are respectively consistent with the characteristics of the first fourth transmit signal and the eighth transmit signal input by the channel combiner.
  • the first equalization filter and the second equalization filter are used to simulate a group delay unevenness characteristic of the transmitting duplexer.
  • the above-mentioned N sets of linear filters are used to simulate the combined relationship and process of the combiner of the above V network structure.
  • the disclosed apparatus may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical or otherwise.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

Abstract

本发明公开了一种多通道PIM数字抵消电路，包括：第一移频变速率模块、第二移频变速率模块、第一转换电路、第二转换电路、双工器、第二发射双工器、通道合路器、第三转换电路、级联滤波电路、PIM抵消器、反馈电路和第一加法器。其中，级联滤波电路对发射信号通过数字域下行链路、数模转换器和模拟域下行链路后产生的时延差、相位差等通道响应进行补偿；级联滤波电路模拟多通道PIM数字抵消电路中的双工器的群时延不平坦特性；级联滤波器拟合多通道PIM数字抵消电路中的通道合路器的S参数，对通道合路器的合路过程在数字域进行精确拟合，最终使本发明产生能够抵消在包含通道合路器多发射、接收中射频系统的PIM干扰信号的信号。

Description

多通道无源互调数字抵消电路 技术领域
本申请涉及无源互调抵消领域，特别涉及一种多通道无源互调数字抵消电路
背景技术
在频分双工(Frequency Division Duplexing，FDD)制式多载波基站通信系统中，在多载波、大发射带宽场景下，天馈系统会因为坏件、螺钉松动、震动等原因产生无源互调(Passive Inter Modulation，PIM)干扰信号，当PIM干扰信号的频点落在接收频段内，会对接收信号频谱重合或扩展，严重影响基站系统接收灵敏度，进而影响网络上行吞吐率。
基于上述问题，在现有技术中，提出了一种PIM抵消器。该PIM抵消器能够对落入接收频段的PIM干扰信号在数字域上进行非线性建模并抵消。但是对含有通道合路器，如电桥、V网络结构等多发射、接收中射频系统的PIM干扰信号是无法抵消的。
发明内容
本发明实施例公开了一种多通道无源互调数字抵消电路，可解决对含有电桥、V网络结构等形式的合路器的多发射、接收中射频系统的PIM干扰信号是无法抵消的问题。
第一方面，本发明实施例提供了一种多通道PIM数字抵消电路，包括：
第一移频变速率模块、第二移频变速率模块、第一转换电路、第二转换电路、双工器、第二发射双工器、通道合路器、第三转换电路、级联滤波电路、PIM抵消器、反馈电路和第一加法器；
所述第一移频变速率模块的输入端口作为所述多通道PIM数字抵消电路的第一输入端口，所述第一移频变速率模块的输出端口与所述第一转换电路的输入端口相连接，所述第一转换电路的输出端口与所述双工器的第一输入端口相连接，所述双工器的第一输出端口与所述通道合路器的第一输入输出端口相连接；
所述第二移频变速率模块的输入端口作为所述多通道PIM数字抵消电路的第二输入端口，所述第二移频变速率模块的输出端口与所述第二转换电路的输入端口相连接，所述第二转换电路的输出端口与所述第二发射双工器的输入端口相连接，所述第二发射双工器的输出端口与所述通道合路器的第二输入输出端口相连接；
所述级联滤波模块的第一输入端口与所述第一移频变速率模块的输出端口相连接，所述级联滤波模块的第二输入端口与所述第二移频变速率模块的输出端口相连接，所述级联滤波模块的第一输出端口和所述第二输出端口均与所述PIM抵消器的输入端口相连接，所述PIM抵消器的输出端口与所述第一加法器的第一输入端口相连接；
所述通道合路器的第一输入输出端口与所述双工器的第二输入端口相连接，所述双工器的第二输出端口与所述第三转换电路的输入端口相连接，所述第三转换电路的输出端口与所述第一加法器的第二输入端口相连接，所述第一加法器的输出端口为所述多通道PIM数字抵消电路的输出端口。
在一种可行的实施例中，所述级联滤波电路包括：
第一通道滤波器、第二通道滤波器、第一均衡滤波器、第二均衡滤波器、第一线性滤波器、第二线性滤波器、第三线性滤波器、第四线性滤波器、第二加法器和第三加法器；
所述第一通道滤波器的输入端口和所述第二通道滤波器的输入端口分别为所述级联滤波电路的第一输入端口和第二输入端口，所述第一通道滤波器的输出端口与所述第一均衡滤波器的输入端口相连接，所述第二通道滤波器的输出端口与所述第二均衡滤波器的输入端口相连接；
所述第一均衡滤波器的输出端口与所述第一线性滤波器的输入端口和所述第二线性滤波器的输入端口相连接，所述第二均衡滤波器的输出端口与所述第三线性滤波器的输入端口和所述第四线性滤波器的输入端口相连接；
所述第一线性滤波器的输出端口与所述第三线性滤波器的输出端口分别与所述第二加法器的第一输入端口和第二输入端口相连接，所述第二线性滤波器的输出端口与所述第四线性滤波器的输出端口分别与所述第三加法器的第一输入端口和第二输入端口相连接；
所述第二加法器的输出端口和所述第三加法器的输出端口分别为所述级联滤波电路的第一输出端口和第二输出端口。
在一种可行的实施例中，所述第一转换电路包括：
第一数字域下行链路、第一数模转换器和第一模拟域下行链路；
所述第一数字域下行链路的输入端口为所述第一转换电路的输入端口，所述第一数字域下行链路的输出端口与所述第一数模转换器的输入端口相连接，所述第一数模转换器的输出端口与所述第一模拟域下行链路的输入端口相连接，所述第一模拟域下行链路的输出端口为所述第一转换电路的输出端口。
在一种可行的实施例中，所述第二转换电路包括：
第二数字域下行链路、第二数模转换器和第二模拟域下行链路；
所述第二数字域下行链路的输入端口为所述第二转换电路的输入端口，所述第二数字域下行链路的输出端口与所述第二数模转换器的输入端口相连接，所述第二数模转换器的输出端口与所述第二模拟域下行链路的输入端口相连接，所述第二模拟域下行链路的输出端口为所述第二转换电路的输出端口。
在一种可行的实施例中，所述双工器包括：
第一发射双工器和接收双工器；
所述第一发射双工器的输入端口为所述双工器的第一输入端口，所述第一发射双工器的输出端口为所述双工器的第一输出端口；
所述接收双工器的输入端口为所述双工器的第二输入端口，所述接收双工器的输出端口为所述双工器的第二输出端口。
在一种可行的实施例中，第三转换电路包括：
第一模数转换电路和模拟域上行链路；
所述模拟域上行链路的输入端口为所述第三转换电路的输入端口，所述模拟域上行链路的输出端口与第一模数转换器的输入端口相连接，所述第一模数转换器的输出端口为所述第三转换电路的输出端口。
在一种可行的实施例中，所述反馈电路包括：
合路器、第二模数转换器、数字域反馈链路和第三存储器；
所述合路器的输入端口为所述反馈电路的输入端口，所述合路器的输出端口与所述第二模数转换器的输入端口相连接；
所述第二模数转换器的输出端口与所述数字域反馈链路的输入端口相连接，所述数字域反馈链路的输出端口与所述第三存储器的输入端口相连接。
在一种可行的实施例中，所述多通道PIM数字抵消电路还包括第一数据数据采集节点U0、第二数据采集节点U1和第三数据采集节点S0；
所述第一数据采集节点U0位于所述第一移频变速率模块的输出端口处，所述第二数据采集节点U1位于所述第二移频变速率模块的输出端口处，所述第三数据采集节点S0位于所述第二数字域下行链路的输出端口处。
在一种可行的实施例中，所述多通道PIM数字抵消电路还包括第一耦合节点P0和第二耦合节点P1；
所述第一耦合节点P0与所述第一发射双工器的输出端口相连接，所述第二耦合节点P1与所述第二发射双工器的输出端口相连接。
在一种可行的实施例中，所述多通道PIM数字抵消电路还包括第一存储器和第二存储器；
所述第一存储器的输入端口与所述第一移频变速率模块的输出端口相连接，所述第二存储器的输入端口与所述第二移频变速率模块的输出端口相连接。
在一种可行的实施例中，所述多通道PIM数字抵消电路还包括处理器，所述处理器包括第一处理器、第二处理器和第三处理器；
所述第一处理器的输出端口、第二存储器的输出端口和第三存储器的输出端口均与所述第一处理器的输入端口相连接，所述第一处理器的输出端口与所述第一通道滤波器的系数寄存器的输入端口和所述第二通道滤波器的系数寄存器的输入端口相连接；
所述第二处理器的输出端口与所述第一均衡滤波器的系数寄存器的输入端口和所述第二均衡滤波器的系数寄存器的输入端口相连接；
所述第三处理器的输出端口与所述第一线性滤波器的系数寄存器的输入端口、所述第二线性滤波器的系数寄存器的输入端口、所述第三线性滤波器的系数寄存器的输入端口和所述第四线性滤波器的系数寄存器的输入端口相连接。
在一种可行的实施例中，所述第一处理器，用于将从所述第一数据采集节点U0采集的数据存储到所述第一存储器中；
所述第一处理器，还用于将从所述第二数据采集节点U1采集的数据存储到所述第二存储器中；
所述第一处理器，还用于将从所述第三数据采集节点S0采集的数据存储到所述第三存储器中。
在一种可行的实施例中，所述第一处理器还用于：
从所述第一存储器中获取从所述第一数据采集节点U0采集的数据，从所述第二存储器中获取从所述第二数据采集节点U1采集的数据，从所述第三存储器中获取从所述第三数据采集节点S0采集的数据；
对所述从所述第一数据采集节点U0采集的数据、所述从所述第二数据采集节点U1采集的数据和所述从所述第三数据采集节点S0采集的数据进行线性插值拟合，以得到所述第一通道滤波器的滤波系数和所述第二通道滤波器的滤波系数；
将所述第一通道滤波器的滤波系数和所述第二通道滤波器的滤波系数分别下载到所述第一通道滤波器的系数寄存器和所述第二通道滤波器的系数寄存器中。
在一种可行的实施例中，所述第二处理器还用于：
获取所述双工器的S参数；
对所述双工器的S参数进行线性插值拟合，以得到所述第一均衡滤波器的滤波系数和所述第二均衡滤波器的滤波系数；
将所述第一均衡滤波器的滤波系数和所述第二均衡滤波器的滤波系数分别下载到所述第一均衡滤波器的系数寄存器和所述第二均衡滤波器的系数寄存器中。
在一种可行的实施例中，所述第三处理器还用于：
获取所述通道合路器的S参数；
对所述通道合路器的S参数进行线性插值拟合，以得到所述第一线性滤波器的滤波系数、所述第二线性滤波器的滤波系数、所述第三线性滤波器的滤波系数和所述第四线性滤波器的滤波系数；
将所述第一线性滤波器的滤波系数、所述第二线性滤波器的滤波系数、所述第三线性滤波器的滤波系数和所述第四线性滤波器的滤波系数分别下载到所述第一线性滤波器的系数寄存器、所述第二线性滤波器的系数寄存器、所述第三线性滤波器的系数寄存器和所述第四线性滤波器的系数寄存器中。
可以看出，在本发明实施例的方案中，级联滤波电路中的通道滤波器对发射信号的在通过数字域下行链路、数模转换器和模拟域下行链路后产生的时延差、相位差等通道响应不一致性进行补偿；上述级联滤波电路中的均衡滤波器用来模拟多通道PIM数字抵消电路中的双工器的群时延不平坦特性；上述级联滤波器的线性滤波器拟合多通道PIM数字抵消电路中的通道合路器的S参数，对通道合路器的合路过程在数字域进行精确拟合，最终以使多通道PIM数字抵消电路产生能够抵消在包含通道合路器多发射、接收中射频系统的PIM干扰信号的信号。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种多通道PIM数字抵消电路的结构示意图；
图2为本发明实施例提供的一种级联滤波电路的结构示意图；
图3为本发明实施例提供的一种多通道PIM数字抵消电路的局部结构示意图；
图4为本发明实施例提供的另一种多通道PIM数字抵消电路的结构示意图；
图5为本发明实施例提供的另一种级联滤波电路的结构示意图；
图6为本发明实施例提供的另一种多通道PIM数字抵消电路的局部结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
参见图1，图1为本发明实施例提供的一种多通道数字PIM抵消电路的结构示意图。如图1所示，该多通道PIM数字抵消电路包括：。
第一移频变速率模块101、第一存储器102、第一转换电路103、双工器104、通道合路器105、第二移频变速率模块106、第二存储器107、第二转换电路108、第二发射双工器109、级联滤波电路110、PIM抵消器111、第三转换电路112、反馈电路113和第一加法器114。
其中，上述第一移频变速率模块101的输入端口为上述多通道PIM数字抵消电路的第一输入端口，上述第一移频变速率模块101的输出端口与上述第一转换电路103的输入端口相连接，上述第一转换电路103的输出端口与上述双工器104中第一输入端口相连接，该双工器104的第一输出端口与上述通道合路器105的第一输入输出端口相连接。
具体地，上述第一转换电路103包括第一数字域下行链路1031、第一数模转换器1032和第一模拟域下行链路1033。上述第一数字域下行链路1031的输入端口为上述第一转换电路103的输入端口，上述第一数字域下行链路1031的输出端口与上述第一数模转换器1032的输入端口相连接，该第一数模转换器1032的输出端口与上述第一模拟域下行链路1033的输入端口相连接，该第一模拟域下行链路1033的输出端口为上述第一转换电路的输出端口。
具体地，上述双工器104包括第一发射双工器1041和接收双工器1042。该第一发射双工器的输入端口1041为上述双工器104的第一输入端口，上述第一发射双工器1041的输出端口为上述双工器104的第一输出端口，上述接收双工器1042的输入端口和输出端口分别为上述双工器104的第二输入端口和第二输出端口。
需要说明的是，对于上述第一发射双工器1041的输出端口与上述接收双工器1042的输入端口均连接在上述双工器104的共钉头上。从外部来看，上述双工器104有一个输入输出端口。该输入输出端口与上述通道合路器105的第一输入输出端口相连接。
上述第一转换电路的输出端口与上述双工器104的第一输入端口相连接具体为上述第一转换电路的输出端口与上述双工器104中的第一发射双工器1041的输入端口的相连接，该双工器104的第一输出端口与上述通道合路器105的第一输入输出端口相连接具体为该双工器104中的第一发射双工器1041的输出端口与上述通道合路器105的第一输入输出端口相连接。
其中，上述第二移频变速率模块106的输入端口为上述多通道PIM数字抵消电路的第二输入端口，上述第二移频变速率模块106的输出端口与上述第二转换电路108的输入端口相连接，上述第二转换电路108的输出端口与上述第二发射双工器109的输入端口相连接，该第二发射双工器109的输出端口与上述通道合路器105的第二输入输出端口相连接。
具体地，上述第二转换电路108包括第二数字域下行链路1081、第二数模转换器1082 和第二模拟域下行链路1083。上述第二数字域下行链路1081的输入端口为上述第二转换电路108的输入端口，上述第二数字域下行链路1081的输出端口与上述第二数模转换器1082的输入端口相连接，该第二数模转换器1082的输出端口与上述第二模拟域下行链路1083的输入端口相连接，该第二模拟域下行链路1083的输出端口为上述第二转换电路108的输出端口。
其中，上述多通道PIM数字抵消电路还包括第一数据采集节点U0和第二数据采集节点U1。该第一数据采集节点U0与上述第一移频变速率模块101的输出端口相连接，上述第二数据采集节点U1与上述第二移频变速率模块106的输出端口相连接。上述级联滤波电路110的第一输入端口与上述第一数据采集节点U0相连接，该级联滤波电路110的第二输入端口与上述第二数据采集节点U1相连接，换句话说，上述级联滤波电路110的第一输入端口与上述第一移频变速率模块101的输出端口相连接，该级联滤波电路110的第二输入端口与上述第二移频变速率模块106的输出端口相连接。上述级联滤波电路110的第一输出端口与第二输出端口均与上述PIM抵消器111的输入端口相连接，上述PIM抵消器111的输出端口与上述第一加法器114的第一输入端口相连接。
进一步地，上述第一存储器102的输入端口与上述第一数据采集节点U0相连接，上述第二存储器107的输入端口与上述第一数据采集节点U1连接。换句话说，上述第一存储器102的输入端口与上述第一移频变速率模块101的输出端口相连接，上述第二存储器107的输入端口与上述第二移频变速率模块106的输出端口相连接。
上述通道合路器105的第一输入输出端口与上述双工器104的第二输入端口(即上述接收双工器1042的输入端口)相连接，上述双工器104的第二输出端口(即上述接收双工器1042的输出端口)与上述第三转换电路112的输入端口相连接，该第三转换电路112的输出端口与上述第一加法器114的第二输入端口相连接，该第一加法器114的输出端口为上述多通道PIM数字抵消电路的输出端口。
具体地，上述第三转换电路112包括第一模数转换器1121和模拟域上行链路1122。上述模拟域上行链路的输入端口为上述第三转换器电路的输入端口，该模拟域上行链路的输出端口与上述第一模数转换器的输入端口相连接，该第一模数转换器的输出端口为上述第三转换电路的输出端口。
其中，上述多通道PIM数字抵消电路还包括第一耦合节点P0和第二耦合节点P1。该第一耦合节点P0位于上述双工器104的第一输出端口(即上述第一发射双工器1041的输出端口)与上述通道合路器105的第一输入输出端口之间，上述第二耦合节点P1位于上述第二发射双工器109与上述通道合路器105的第二输入输出端口之间。上述第一耦合节点P0和上述第二耦合节点P1均与上述反馈电路113的输入端口相连接。
具体地，上述反馈电路113包括合路器1131、第二模数转换器1132、数字域反馈链路1133和第三存储器1134。上述合路器1131的输入端口为上述反馈电路114的输入端口，上述合路器1131的输出端口与上述第二模数转换器1132的输入端口相连接，上述第二模数转换器1132与上述数字域反馈链路1133的输入端口相连接，该数字域反馈链路1133的输出端口与上述第三存储器1134的输入端口相连接。
具体地，上述多通道PIM数字抵消电路的工作过程如下：
发送方向：第一发射信号Ch0通过上述第一移频变速率模块101的输入端口输入上述多通道PIM数字抵消电路。上述第一移频变速率模块101对上述第一发射信号Ch0分别先后进行移频、变速率和消波处理后，将处理后得到的第一发送信号传输至上述第一转换电路103中的第一数字域下行链路1031，该第一数字域下行链路1031对上述第一发送信号进行数字预失真、正交调制补偿(Quadrature Modulation Compensation，QMC)等处理，并将处理后得到的第二发送信号传输至上述第一数模转换器1032，上述第一数模转换器1032将上述第二发送信号从数字域转换到模拟域，换句话说，上述第一数模转换器1032将上述第二发送信号从数字信号转换为模拟信号，得到第三发送信号，并将该第三发送信号传输至上述第一模拟域下行链路1033。该第一模拟域下行链路1033对上述第三发送信号进行功放等处理，得到第四发送信号，并将该第四发送信号传输至上述第一发射双工器104，该第一发射双工器1041将上述第四发送信号传输至上述通道合路器105。
同理，第二发射信号Ch1通过上述第二移频变速率模块106的输入端口输入上述多通道PIM数字抵消电路。上述第二移频变速率模块106对上述第二发射信号Ch1分别先后进行移频、变速率和消波处理后，将处理后得到的第五发送信号传输至上述第二转换电路108中的第二数字域下行链路1081，该第二数字域下行链路1081对上述第六发送信号进行数字预失真、正交调制补偿(Quadrature Modulation Compensation，QMC)等处理，并将处理后得到的第六发送信号传输至上述第二数模转换器1082，上述第一数模转换器1082将上述第六发送信号从数字域转换到模拟域，换句话说，上述第二数模转换器1082将上述第六发送信号从数字信号转换为模拟信号，得到第七发送信号，并将该第七发送信号传输至上述第二模拟域下行链路1083。该第二模拟域下行链路1083对上述第七发送信号进行功放等处理，得到第八发送信号，并将该第八发送信号传输至上述第二发射双工器109，该第一发射双工器109将上述第八发送信号传输至上述通道耦合器105。
需要说明的是，上述QMC处理具体是对模拟正交调制(Analog Quadrature Modulation，AQM)过程中的相偏、幅偏以及本振泄露进行补偿。该功能具体由QMC模块实现。
上述通道合路器105将上述第四发送信号和上述第八发送信号组合到一起，并送入天线口发射出去。
在上述第一耦合节点P0和上述第二耦合节点P1采集的信号分别为第四发送信号和第八发送信号。上述第四发送信号和上述第八发送信号传输至上述反馈电路113的输入端口(即上述合路器1131的输入端口)后，该合路器1131将上述第四发送信号和第八发送信号进行叠加得到第一处理信号，即该第一处理信号＝第四发送信号+第八发送信号。上述第二模数转换器1132将上述第一处理信号从模拟域转换到数字域，即将该第一处理信号从模拟信号转换为数字信号，得到第二处理信号，上述第二数字域下行链路对该第二处理信号进行移频和变速率处理后，得到第三处理信号，并将该第三处理信号存储至上述第三存储器1134中。
上述级联滤波电路110的第一输入端口和第二输入端口分别输入上述第一发送信号和上述第五发送信号后，上述级联滤波电路110根据上述第一发送信号和第二发送信号从其第一输出端口和第二端口分别输出第一滤波信号和第二滤波信号。上述PIM抵消器111的输入端口输入上述第一滤波信号和第二滤波信号后，该PIM抵消器111根据该第一滤波信 号和第二滤波信号生成PIM抵消信号，并从其输出端口输出。
其中，上述多通道PIM数字抵消电路还包括处理器。上述第一移频变速率模块101输出第一发送信号后，上述处理器将该第一发送信号存储到上述第一存储器102中，即上述处理器从上述第一数据采集节点U0采集的数据存储到上述第一存储器102中。同理，上述第二移频变速率模块106输出第五发送信号后，上述处理器将该第五发送信息存储到上述第二存储器107中，即上述处理器从上述第二数据采集节点U1采集到的数据存储到上述第二存储器107中。
需要说明的是，上述第一存储器102、第二存储器107和第三存储器1134可为随机存取存储器(Random Access Memory，RAM)。上述第一存储器102、第二存储器107和第三存储器1134为不同的RAM。
接收方向：上述通道合路器105的天线接收到第一接收信号后，将该第一接收信号传输至上述接收双工器1042，该接收双工器1042将上述第一接收信号传输至上述模拟域上行链路1122，该模拟域上行链路对上述第一接收信号进行低噪放、滤波等处理，得到第二接收信号。上述第一模数转换器1032将该第二接收信息从模拟域转换到数字域即将上述第二接收信号从模拟信号转换为数字信号，得到第三接收信号。
上述第一加法器114将上述第三接收信号与上述PIM抵消器111产生的PIM抵消信号进行相减，得到校正后的信号，即校正后的信号＝第三接收信号-PIM抵消信号。
需要说明的是，上述第三接收信号可以看成上述第一发射信号Ch0加上PIM干扰信号，上述PIM抵消信号为上述多通道PIM数字抵消电路模拟出来的PIM干扰信号。上述第三接收信号减去上述PIM抵消信号可得到上述校正后的信号即上述第一发射信号Ch0。
下面具体介绍上述级联滤波电路的电路架构和工作原理。
参见图2，图2为本发明实施例提供的一种级联滤波电路的结构示意图。如图2所示，该电路110包括：第一通道滤波器1101、第二通道滤波器1102、第一均衡滤波器1103、第二均衡滤波器1104、第一线性滤波器1105、第二线性滤波器1106、第三线性滤波器1107、第四线性滤波器1108、第二加法器1109和第三加法器1110。
上述第一通道滤波器1101的输入端口和上述第二通道滤波器1102的输入端口分别为上述级联滤波电路110的第一输入端口和第二输端口，上述第一通道滤波器1101的输入端口与上述第一均衡滤波器1103的输入端口相连接，上述第二通道滤波器1102的输入端口与上述第二均衡滤波器1104的输入端口相连接。上述第一线性滤波器1105的输入端口和上述第二线性滤波器1106的输入端口均与上述第一均衡滤波器1103的输出端口相连接，上述第三线性滤波器1107的输入端口和上述第四线性滤波器1108的输入端口均与上述第二均衡滤波器1104的输出端口相连接。上述第一线性滤波器1105的输出端口和上述第三线性滤波器1107的输出端口分别与上述第二加法器1109的第一输入端口和第二输入端口相连接，上述第二线性滤波器1106的输出端口和上述第四线性滤波器1108的输出端口分别与上述第三加法器1110的第一输入端口和第二输入端口相连接。上述第二加法器1109的输出端口和上述第三加法器1110的输出端口分别为上述级联滤波电路110的第一输出端口和第二输出端口。
上述第一处理信号U0输入上述第一通道滤波器1101后，该第一通道滤波器1101输出 第三滤波信号F1；上述第二处理信号U1输入上述第二通道滤波器1102后，该第二通过滤波器1102输出第四滤波信号F2。其中，
Figure PCTCN2017108128-appb-000001
且FIR_CH0和FIR_CH1分别为上述第一通道滤波器1101的滤波系数和上述第二通道滤波器1102的滤波系数。上述第三滤波信号F1输入上述第一均衡滤波器1103后，该第一均衡滤波器1103输出第五滤波信号F3；上述第四滤波信号F2输入上述第二均衡滤波器1104后，该第二通过滤波器1104输出第四滤波信号F4。其中，
Figure PCTCN2017108128-appb-000002
且DUP_EQ1和DUP_EQ2分别为上述第一均衡滤波器1103的滤波系数和上述第二均衡滤波器1104的滤波系数。上述第五滤波信号F3输入上述第一线性滤波器1105和上述第二线性滤波器1106后，该第一线性滤波器1105和第二线性滤波器1106分别输出第七滤波信号F5和第八滤波信号F6；上述第六滤波信号F4输入上述第三线性滤波器1107和上述第四线性滤波器1108后，该第三线性滤波器1107和第四线性滤波器1108分别输出第九滤波信号F7和第十滤波信号F8。其中，
Figure PCTCN2017108128-appb-000003
Figure PCTCN2017108128-appb-000004
且该HB_FIR1、HB_FIR2、HB_FIR3和HB_FIR4分别为上述第一线性滤波器1105的滤波系数、第二线性滤波器1106的滤波系数、第三线性滤波器1107的滤波系数和第四线性滤波器1108的滤波系数。上述第七滤波信号F5和第九滤波信号F7分别通过上述第二加法器1109的第一输入端口和第二输入端口输入上述第二加法器1109后，该第二加法器1109输出第一滤波信号TX0；上述第八滤波信号F6和第十滤波信号F8分别通过上述第三加法器1110的第一输入端口和第二输入端口输入上述第三加法器1110后，该第三加法器1110输出上述第二滤波信号TX1。其中，TX0＝F5+F7，TX1＝F6+F8。
需要指出的是，上述
Figure PCTCN2017108128-appb-000005
为卷积运算符。
需要说明的是，上述第一通道滤波器1101和上述第二通道滤波器1102补偿上述第一发射信号Ch0和上述第二发射信号Ch1在经过不同的通道产生的时延差、相位差等通道响应的不一致性，以使PIM抵消器111输入的第一滤波信号和第二滤波信号分别与通道合路器输入的第一第四发送信号和第八发送信号的特性保持一致。上述第一均衡滤波器1103和上述第二均衡滤波器1104用来模拟上述发射双工器的群时延不平坦特性。上述四组线性滤波器用来模拟上述多通道合路器105的合路关系和过程。
下面具体介绍上述处理器与上述多通道PIM数字抵消电路其他部分的连接关系和处理器的工作过程。
如图3所示，上述多通道PIM数字抵消电路还包括处理器115，该处理器115包括第一处理器1151，第二处理器1152和第三处理器1153。
上述第一存储器102的输出端口、上述第二存储器107的输出端口和上述第三存储器1134的输出端口均与上述第一处理器1151的输入端口相连接，上述第一通道滤波器的系数寄存器1101的输入端口和上述第二通道滤波器的系数寄存器1102的输入端口均与上述第一处理器1151的输出端口相连接。上述第一均衡滤波器的系数寄存器1103的输入端口和上述第二均衡滤波器的系数寄存器1104的输入端口均与上述第二处理器1152的输出端口相连接，上述第一线性滤波器的系数寄存器1105的输入端口、上述第二线性滤波器的系数寄存器1106的输入端口、上述第三线性滤波器的系数寄存器1107的输入端口和上述第四线性滤波器的系数寄存器1108的输入端口均与上述第三处理器1153的输出端口相连接。
上述第一处理器1151从上述第一存储器102中获取上述第一发送信号，从上述第二存储器107中获取上述第五发送信号，从上述第三存储器1134中获取上述第三处理信号。上述第一处理器1151根据上述第一发送信号、第五发送信号和第三处理信号进行LS线性插值拟合，以获取上述第一通道滤波器1101的滤波系数FIR_CH0和上述第二通道滤波器1102的滤波系数FIR_CH1。上述第一处理器获1151取FIR_CH0和FIR_CH1后，该第一处理器1151将FIR_CH0和FIR_CH1分别下载到上述第一通道滤波器的系数寄存器1101和第二通道滤波器的系数寄存器1102中。
上述级联滤波电路110中的第一均衡滤波器1103和第二均衡滤波器1104在进行工作之前，上述第二处理器1152对上述双工器104(包括第一发射双工器1041和接收双工器1042)进行发射信号和接收信号测试，以得到两组群时延参数或者该双工器104的S参数。当得到的数据为双工器S参数时，上述第二处理器1152将上述双工器的S参数转换为群时延参数。上述第二处理器1152根据上述两组群时延参数进行LS线性插值拟合，以得到上述第一均衡滤波器的滤波系数DUP_EQ1和上述第二均衡滤波器的滤波系数DUP_EQ2。上述第二处理器获1152获取DUP_EQ1和DUP_EQ2后，该第二处理器1152将DUP_EQ1和DUP_EQ2分别下载到上述第一均衡滤波器的系数寄存器1103和第二均衡滤波器的系数寄存器1104中。
上述第三处理器1153在上述通道合路器105工作之前，该第三处理器1153对该通道合路器进行测试，以得到该通道合路器的S参数。然后上述第三处理器1153根据该S参数得到信号从P0到H0、P0到H1、P1到H0、P1到H1的频率响应信息(此处参见图1所示)。上述第三处理器1153采用四组线性滤波器(包括第一线性滤波器1105、第二线性滤波器1106、第三线性滤波器1107和第四线性滤波器1108)分别对上面四路响应进行线性插值拟合，得到四组线性滤波器的滤波系数：HB_FIR1、HB_FIR2、HB_FIR3和HB_FIR4。上述第三处理器将该HB_FIR1、HB_FIR2、HB_FIR3和HB_FIR4这四个滤波系数分别下载到第一线性滤波器的系数寄存器1105、第二线性滤波器的系数寄存器1106、第三线性滤波器的系数寄存器1107和第四线性滤波器的系数寄存器1108中。
需要说明的是，上述第一处理器1151、第二处理器1152和第三处理器1153可均为DSP芯片，且上述第一处理器1151、第二处理器1152和第三处理器1153可为同一块DSP芯片，也可为不同的DSP芯片。
需要指出的是，上述图1-图3所述的多通道PIM数字抵消电路中的通道合路器为电桥。
可以看出，在本发明实施例的方案中，级联滤波电路中的通道滤波器对发射信号的在通过数字域下行链路、数模转换器和模拟域下行链路后产生的时延差、相位差等通道响应不一致性进行补偿；上述级联滤波电路中的均衡滤波器用来模拟多通道PIM数字抵消电路中的双工器的群时延不平坦特性；上述级联滤波器的线性滤波器拟合多通道PIM数字抵消电路中的通道合路器的S参数，对通道合路器的合路过程在数字域进行精确拟合，最终以使多通道PIM数字抵消电路产生能够抵消在包含通道合路器多发射、接收中射频系统的PIM干扰信号的信号。
在一种可行的实施例中，当上述多通道PIM数字抵消电路中的通道合路器为V网络结 构的合路器时，如图4所示。图4为本发明实施例提供的一种多通道PIM数字抵消电路的结构示意图。如图4所示，上述电路包括：
第一移频变速率模块401、第一存储器402、第一转换电路403、双工器404、通道合路器405、第二移频变速率模块406、第二存储器407、第二转换电路408、第二发射双工器409、级联滤波电路410、PIM抵消器411、第三转换电路412、反馈电路413和第一加法器414。
需要说明的是，上述多通道PIM数字抵消电路中除了通道合路器405和级联滤波电路410之外，其他电路或者模块的连接关系及功能的相关描述可参见上述图1所示实施例的相关描述，在此不再赘述。
上述通道合路器410的第一输入输出端口与上述双工器404的第一输出端口(即第一发射双工器4041的输出端口)和第二输入端口(即接收双工器4042的输入端口)相连接，该通道合路器410的第二输入输出端口与上述第二发射双工器409的输出端口相连接。该通道合路器还包括N个天线，上述通道合路器的第输入输出一端口和第二输入输出端口均与该N个天线相连接。
上述第一发射双工器输出的信号通过该通道合路器的N个天线发射出去，且上述第二发射双工器输出的信号也是通过上述通道合路器的N个天线发射出去。
下面介绍上述级联滤波电路的结构和工作原理。
参见图5，图5为本发明实施例提供的一种级联滤波电路的结构示意图。如图5所示，该级联滤波电路包括：第一通道滤波器、第二通道滤波器、第一均衡滤波器、第二均衡滤波器、N个线性滤波器和N/2个加法器。该N个线性滤波器依次为线性滤波器1、线性滤波器2、线性滤波器3、线性滤波器4、线性滤波器5、线性滤波器6……线性滤波器N-1和线性滤波器N，并且分别编号为1、2、3、4、5、6……N-1和N。上述N/2个加法器依次为加法器1、加法器2、加法器3……加法器N/2，并且分别编号为1、2、3……N/2。其中，上述N为大于2的偶数。
上述第一通道滤波器的输入端口和上述第二通道滤波器的输入端口分别为上述级联滤波电路的第一输入端口和第二输入端口。上述第一通道滤波器的输出端口与上述第一均衡滤波器的输入端口相连接，上述第二通道滤波器的输出端口与上述第二均衡滤波器的输入端口相连接。上述第一均衡滤波器的输出端口与上述N个线性滤波器中编号为奇数的线路滤波器的输入端口相连接，上述第二均衡滤波器的输出端口与上述N个线性滤波器中编号为偶数的线性滤波器的输入端口相连接。
上述N个线性滤波器中每两个线性滤波器的输出端口(包括线性滤波器i的输出端口和线性滤波器j的输出端口)与加法器m的第一输入端口和第二输入端口相连接。其中，上述线性滤波器i的编号i和上述线性滤波器j的编号j满足的关系为：j与i之差为1且j大于2且小于或者等于N/2的偶数，i为大于0且小于N/2的奇数。上述加法器m的编号m＝j/2。上述N/2个加法器的输出端口为上述级联滤波电路的输出端口。
上述第一处理信号U0输入上述第一通道滤波器后，该第一通道滤波器输出第一滤波信号F1；上述第二处理信号U1输入上述第二通道滤波器后，该第二通过滤波器输出第二滤波信号F2。其中，
Figure PCTCN2017108128-appb-000006
且FIR_CH0和FIR_CH1分 别为上述第一通道滤波器的滤波系数和上述第二通道滤波器的滤波系数。上述第一滤波信号F1输入上述第一均衡滤波器后，该第一均衡滤波器输出第三滤波信号F3；上述第二滤波信号F2输入上述第二均衡滤波器后，该第二通过滤波器输出第四滤波信号F4。其中，
Figure PCTCN2017108128-appb-000007
且DUP_EQ1和DUP_EQ2分别为上述第一均衡滤波器的滤波系数和上述第二均衡滤波器的滤波系数。
上述第三滤波信号F3通过上述N个线性滤波器中的编号为奇数的线性滤波器后，该N个线性滤波器中编号为奇数的线性滤波器分别输出第一线性滤波信号S1、S3、S5……S(N-1)。上述第四滤波信号F4通过上述N个线性滤波器中编号为偶数的线性滤波器后，该N个线性滤波器中编号为偶数的线性滤波器分别输出第一线性滤波信号S2、S4、S6……SN。其中，上述
Figure PCTCN2017108128-appb-000008
Figure PCTCN2017108128-appb-000009
Figure PCTCN2017108128-appb-000010
且HB_FIR1、HB_FIR3、HB_FIR5……HB_FIR(N-1)分别为上述N个线性滤波器中编号为奇数的线性滤波器，HB_FIR2、HB_FIR4、HB_FIR6……HB_FIRN分别为上述N个线性滤波器中编号为奇数的线性滤波器。
上述第一线性滤波信号S1、S2、S3、S4、S5、S6……S(N-1)和SN输入到上述N/2个加法器后，得到N/2个第二线性滤波信号TX1、TX2、TX3……TX(N/2)。其中，TX1＝S1+S2、TX2＝S3+S4、TX3＝S5+S6……TX(N/2)＝S(N-1)+SN。
如图6所示，上述多通道PIM数字抵消电路还包括处理器，该处理器包括第一处理器，第二处理器和第三处理器。
上述第一存储器的输出端口、上述第二存储器的输出端口和上述第三存储器的输出端口均与上述第一处理器的输入端口相连接，上述第一通道滤波器的系数寄存器的输入端口和上述第二通道滤波器的系数寄存器的输入端口均与上述第一处理器的输出端口相连接。上述第一均衡滤波器的系数寄存器的输入端口和上述第二均衡滤波器的系数寄存器的输入端口均与上述第二处理器的输出端口相连接，上述N组线性滤波器的系数寄存器的输入端口均与上述第三处理器的输出端口相连接。
上述第一处理器从上述第一存储器中获取上述第一发送信号，从上述第二存储器中获取上述第五发送信号，从上述第三存储器中获取上述第三处理信号。上述第一处理器根据上述第一发送信号、第五发送信号和第三处理信号进行LS线性插值拟合，以获取上述第一通道滤波器的滤波系数FIR_CH0和上述第二通道滤波器的滤波系数FIR_CH1。上述第一处理器获取FIR_CH0和FIR_CH1后，该第一处理器将FIR_CH0和FIR_CH1分别下载到上述第一通道滤波器的系数寄存器和第二通道滤波器的系数寄存器中。
上述级联滤波电路中的第一均衡滤波器和第二均衡滤波器在进行工作之前，上述第二处理器对上述双工器(包括第一发射双工器和接收双工器)进行发射信号和接收信号测试，以得到两组群时延参数或者该双工器的S参数。当得到的数据为双工器S参数时，上述第二处理器将上述双工器的S参数转换为群时延参数。上述第二处理器根据上述两组群时延参数进行LS线性插值拟合，以得到上述第一均衡滤波器的滤波系数DUP_EQ1和上述第二均衡滤波器的滤波系数DUP_EQ2。上述第二处理器1152获取DUP_EQ1和DUP_EQ2后，该第二处理器将DUP_EQ1和DUP_EQ2分别下载到上述第一均衡滤波器的系数寄存器和第 二均衡滤波器的系数寄存器中。
上述第三处理器在上述V网络结构的合路器工作之前，该第三处理器对该通道合路器进行测试，以得到该V网络结构的合路器的S参数。然后上述第三处理器根据该S参数得到信号从P0到H0、P0到H1、P0到H2……P0到H(M-1)、P1到H0、P1到H1、P1到H2……P1到H(M-1)的频率响应信息(此处参见图4所示),M＝N/2。上述第三处理器采用N组线性滤波器分别对上面N路响应进行线性插值拟合，得到N组线性滤波器的滤波系数：HB_FIR1、HB_FIR2、HB_FIR3……HB_FIRN。上述第三处理器将该N个滤波系数分别下载到N组线性滤波器的系数寄存器中。
需要说明的是，上述第一通道滤波器和上述第二通道滤波器补偿上述第一发射信号Ch0和上述第二发射信号Ch1在经过不同的通道产生的时延差、相位差等通道响应的不一致性，以使PIM抵消器输入的第一滤波信号和第二滤波信号分别与通道合路器输入的第一第四发送信号和第八发送信号的特性保持一致。上述第一均衡滤波器和上述第二均衡滤波器用来模拟上述发射双工器的群时延不平坦特性。上述N组线性滤波器用来模拟上述V网络结构的合路器的合路关系和过程。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上对本发明实施例进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上上述，本说明书内容不应理解为对本发明的限制。

Claims (15)

  1. 一种多通道无源互调PIM数字抵消电路，其特征在于，包括：
    第一移频变速率模块、第二移频变速率模块、第一转换电路、第二转换电路、双工器、第二发射双工器、通道合路器、第三转换电路、级联滤波电路、PIM抵消器、反馈电路和第一加法器；
    所述第一移频变速率模块的输入端口作为所述多通道PIM数字抵消电路的第一输入端口，所述第一移频变速率模块的输出端口与所述第一转换电路的输入端口相连接，所述第一转换电路的输出端口与所述双工器的第一输入端口相连接，所述双工器的第一输出端口与所述通道合路器的第一输入输出端口相连接；
    所述第二移频变速率模块的输入端口作为所述多通道PIM数字抵消电路的第二输入端口，所述第二移频变速率模块的输出端口与所述第二转换电路的输入端口相连接，所述第二转换电路的输出端口与所述第二发射双工器的输入端口相连接，所述第二发射双工器的输出端口与所述通道合路器的第二输入输出端口相连接；
    所述级联滤波模块的第一输入端口与所述第一移频变速率模块的输出端口相连接，所述级联滤波模块的第二输入端口与所述第二移频变速率模块的输出端口相连接，所述级联滤波模块的第一输出端口和所述第二输出端口均与所述PIM抵消器输入端口相连接，所述PIM抵消器的输出端口与所述第一加法器的第一输入端口相连接；
    所述通道合路器的第一输入输出端口与所述双工器的第二输入端口相连接，所述双工器的第二输出端口与所述第三转换电路的输入端口相连接，所述第三转换电路的输出端口与所述第一加法器的第二输入端口相连接，所述第一加法器的输出端口为所述多通道PIM数字抵消电路的输出端口。
  2. 根据权利要求1所述的电路，其特征在于，所述级联滤波电路包括：
    第一通道滤波器、第二通道滤波器、第一均衡滤波器、第二均衡滤波器、第一线性滤波器、第二线性滤波器、第三线性滤波器、第四线性滤波器、第二加法器和第三加法器；
    所述第一通道滤波器的输入端口和所述第二通道滤波器的输入端口分别为所述级联滤波电路的第一输入端口和第二输入端口，所述第一通道滤波器的输出端口与所述第一均衡滤波器的输入端口相连接，所述第二通道滤波器的输出端口与所述第二均衡滤波器的输入端口相连接；
    所述第一均衡滤波器的输出端口与所述第一线性滤波器的输入端口和所述第二线性滤波器的输入端口相连接，所述第二均衡滤波器的输出端口与所述第三线性滤波器的输入端口和所述第四线性滤波器的输入端口相连接；
    所述第一线性滤波器的输出端口与所述第三线性滤波器的输出端口分别与所述第二加法器的第一输入端口和第二输入端口相连接，所述第二线性滤波器的输出端口与所述第四线性滤波器的输出端口分别与所述第三加法器的第一输入端口和第二输入端口相连接；
    所述第二加法器的输出端口和所述第三加法器的输出端口分别为所述级联滤波电路的第一输出端口和第二输出端口。
  3. 根据权利要求1或2所述的电路，其特征在于，所述第一转换电路包括：
    第一数字域下行链路、第一数模转换器和第一模拟域下行链路；
    所述第一数字域下行链路的输入端口为所述第一转换电路的输入端口，所述第一数字域下行链路的输出端口与所述第一数模转换器的输入端口相连接，所述第一数模转换器的输出端口与所述第一模拟域下行链路的输入端口相连接，所述第一模拟域下行链路的输出端口为所述第一转换电路的输出端口。
  4. 根据权利要求1或3所述的电路，其特征在于，所述第二转换电路包括：
    第二数字域下行链路、第二数模转换器和第二模拟域下行链路；
    所述第二数字域下行链路的输入端口为所述第二转换电路的输入端口，所述第二数字域下行链路的输出端口与所述第二数模转换器的输入端口相连接，所述第二数模转换器的输出端口与所述第二模拟域下行链路的输入端口相连接，所述第二模拟域下行链路的输出端口为所述第二转换电路的输出端口。
  5. 根据权利要求1或4所述的电路，其特征在于，所述双工器包括：
    第一发射双工器和接收双工器；
    所述第一发射双工器的输入端口为所述双工器的第一输入端口，所述第一发射双工器的输出端口为所述双工器的第一输出端口；
    所述接收双工器的输入端口为所述双工器的第二输入端口，所述接收双工器的输出端口为所述双工器的第二输出端口。
  6. 根据权利要求1或5所述的电路，其特征在于，第三转换电路包括：
    第一模数转换电路和模拟域上行链路；
    所述模拟域上行链路的输入端口为所述第三转换电路的输入端口，所述模拟域上行链路的输出端口与第一模数转换器的输入端口相连接，所述第一模数转换器的输出端口为所述第三转换电路的输出端口。
  7. 根据权利要求1或6所述的电路，其特征在于，所述反馈电路包括：
    合路器、第二模数转换器、数字域反馈链路和第三存储器；
    所述合路器的输入端口为所述反馈电路的输入端口，所述合路器的输出端口与所述第二模数转换器的输入端口相连接；
    所述第二模数转换器的输出端口与所述数字域反馈链路的输入端口相连接，所述数字域反馈链路的输出端口与所述第三存储器的输入端口相连接。
  8. 根据权利要求6所述的电路，其特征在于，所述多通道PIM数字抵消电路还包括第一数据数据采集节点U0、第二数据采集节点U1和第三数据采集节点S0；
    所述第一数据采集节点U0位于所述第一移频变速率模块的输出端口处，所述第二数据采集节点U1位于所述第二移频变速率模块的输出端口处，所述第三数据采集节点S0位于所述第二数字域下行链路的输出端口处。
  9. 根据权利要求5所述的电路，其特征在于，所述多通道PIM数字抵消电路还包括第一耦合节点P0和第二耦合节点P1；
    所述第一耦合节点P0与所述第一发射双工器的输出端口相连接，所述第二耦合节点P1与所述第二发射双工器的输出端口相连接。
  10. 根据权利要求1-9任一项所述的电路，其特征在于，所述多通道PIM数字抵消电 路还包括第一存储器和第二存储器；
    所述第一存储器的输入端口与所述第一移频变速率模块的输出端口相连接，所述第二存储器的输入端口与所述第二移频变速率模块的输出端口相连接。
  11. 根据权利要求10所述的电路，其特征在于，所述多通道PIM数字抵消电路还包括处理器，所述处理器包括第一处理器、第二处理器和第三处理器；
    所述第一处理器的输出端口、第二存储器的输出端口和第三存储器的输出端口均与所述第一处理器的输入端口相连接，所述第一处理器的输出端口与所述第一通道滤波器的系数寄存器的输入端口和所述第二通道滤波器的系数寄存器的输入端口相连接；
    所述第二处理器的输出端口与所述第一均衡滤波器的系数寄存器的输入端口和所述第二均衡滤波器的系数寄存器的输入端口相连接；
    所述第三处理器的输出端口与所述第一线性滤波器的系数寄存器的输入端口、所述第二线性滤波器的系数寄存器的输入端口、所述第三线性滤波器的系数寄存器的输入端口和所述第四线性滤波器的系数寄存器的输入端口相连接。
  12. 根据权利要求11所述的电路，其特征在于，
    所述第一处理器，用于将从所述第一数据采集节点U0采集的数据存储到所述第一存储器中；
    所述第一处理器，还用于将从所述第二数据采集节点U1采集的数据存储到所述第二存储器中；
    所述第一处理器，还用于将从所述第三数据采集节点S0采集的数据存储到所述第三存储器中。
  13. 根据权利要求12所述电路，其特征在于，所述第一处理器还用于：
    从所述第一存储器中获取从所述第一数据采集节点U0采集的数据，从所述第二存储器中获取从所述第二数据采集节点U1采集的数据，从所述第三存储器中获取从所述第三数据采集节点S0采集的数据；
    对所述从所述第一数据采集节点U0采集的数据、所述从所述第二数据采集节点U1采集的数据和所述从所述第三数据采集节点S0采集的数据进行线性插值拟合，以得到所述第一通道滤波器的滤波系数和所述第二通道滤波器的滤波系数；
    将所述第一通道滤波器的滤波系数和所述第二通道滤波器的滤波系数分别下载到所述第一通道滤波器的系数寄存器和所述第二通道滤波器的系数寄存器中。
  14. 根据权利要求12所述的电路，其特征在于，所述第二处理器还用于：
    获取所述双工器的S参数；
    对所述双工器的S参数进行线性插值拟合，以得到所述第一均衡滤波器的滤波系数和所述第二均衡滤波器的滤波系数；
    将所述第一均衡滤波器的滤波系数和所述第二均衡滤波器的滤波系数分别下载到所述第一均衡滤波器的系数寄存器和所述第二均衡滤波器的系数寄存器中。
  15. 根据权利要求12所述电路，其特征在于，所述第三处理器还用于：
    获取所述通道合路器的S参数；
    对所述通道合路器的S参数进行线性插值拟合，以得到所述第一线性滤波器的滤波系 数、所述第二线性滤波器的滤波系数、所述第三线性滤波器的滤波系数和所述第四线性滤波器的滤波系数；
    将所述第一线性滤波器的滤波系数、所述第二线性滤波器的滤波系数、所述第三线性滤波器的滤波系数和所述第四线性滤波器的滤波系数分别下载到所述第一线性滤波器的系数寄存器、所述第二线性滤波器的系数寄存器、所述第三线性滤波器的系数寄存器和所述第四线性滤波器的系数寄存器中。
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