WO2019076121A1 - 显示装置、像素电路及其驱动方法和驱动装置 - Google Patents

显示装置、像素电路及其驱动方法和驱动装置 Download PDF

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Publication number
WO2019076121A1
WO2019076121A1 PCT/CN2018/100784 CN2018100784W WO2019076121A1 WO 2019076121 A1 WO2019076121 A1 WO 2019076121A1 CN 2018100784 W CN2018100784 W CN 2018100784W WO 2019076121 A1 WO2019076121 A1 WO 2019076121A1
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Prior art keywords
data signal
pixel circuit
frame
pixel
row
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PCT/CN2018/100784
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English (en)
French (fr)
Inventor
李琨
张大宇
詹一飞
凌小涵
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US16/331,649 priority Critical patent/US11393420B2/en
Publication of WO2019076121A1 publication Critical patent/WO2019076121A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a driving method of a pixel circuit, a driving device of a pixel circuit, a pixel circuit, and a display device.
  • the voltage of the source driving signal is symmetrically distributed with respect to the common electrode voltage Vcom, but in fact, the center voltage of the driving signal tends to be offset from Vcom, so Will cause the positive and negative pixel voltage to be asymmetrical.
  • driving methods such as point flip, column flip, row flip, 2H1V flip, 1H2V flip and Z flip.
  • the specific driving method can be determined according to the display quality, power consumption, driving voltage magnitude, and accompanying adverse factors of each driving method.
  • the present disclosure aims to solve at least one of the technical problems in the related art to some extent.
  • a driving method of a pixel circuit comprising the steps of: outputting a gate signal and a data signal in a first preset manner to a frame sequence formed by consecutive X frames of a picture display; a pixel circuit that outputs a gate signal and a data signal to the pixel circuit in a second preset manner during a frame sequence formed by consecutive Y frames adjacent to a sequence of frames of consecutive X frames displayed on the screen, wherein the The first preset mode is different from the second preset mode, and X and Y are positive integers not lower than 2.
  • the outputting the gate signal and the data signal to the pixel circuit in a first preset manner includes grouping all the rows of the pixel circuit in a plurality of rows of pixel units, and The gate signals are output in an out-of-order manner in each group to the pixel cells of all rows in the group.
  • the outputting the gate signal and the data signal to the pixel circuit in a second preset manner includes sequentially outputting a gate signal to pixel units of all rows of the pixel circuit.
  • the gate signal and the data signal are outputted in the first preset manner during the Nth frame and the N+1th frame of the screen display.
  • a pixel circuit wherein N is a positive integer; during the N+2th frame and the N+3th frame of the picture display, the gate signal and the data signal are output to the pixel circuit in the second preset manner .
  • the outputting the gate signal and the data signal to the pixel circuit in the first preset manner includes: performing, on a row of every three rows of pixel units, all rows of the pixel circuit Grouping, and in each group, outputting gate signals to the pixel unit in the order of the first row, the third row, and the second row
  • the outputting the gate signal and the data signal to the pixel circuit in the second preset manner includes sequentially outputting the gate signal to the pixel unit in an order from the first row to the last row. in.
  • a corresponding data signal is also outputted to each of the pixel units of the row.
  • the polarity of the data signal of the Nth frame and the (N+1)th frame is opposite, and the pole of the data signal of the N+2th frame and the (N+3th frame) The opposite is true.
  • the data signal of the Nth frame has a negative polarity
  • the data signal of the (N+1)th frame has a positive polarity
  • the data signal of the N+2th frame has a negative polarity
  • the data signal of the N+3th frame has a positive polarity
  • a driving apparatus for a pixel circuit comprising: a first driver configured to output a gate signal in a first preset manner during a frame sequence formed by consecutive X frames of a picture display And a data signal to the pixel circuit; the second driver configured to output the gate signal in a second preset manner during a frame sequence of consecutive Y frames adjacent to the frame sequence formed by the consecutive X frames displayed on the screen And a data signal to the pixel circuit, wherein the first preset manner is different from the second preset manner, and X and Y are positive integers not lower than 2.
  • the first driver in response to the first driver outputting a gate signal and a data signal to the pixel circuit in a first preset manner, is configured by grouping a plurality of rows of pixel units All rows of the pixel circuit are grouped, and the gate signals are output in an out-of-order manner to pixel cells of all rows in the group in each group.
  • the second driver in response to the second driver outputting a gate signal and a data signal to the pixel circuit in a second preset manner, sequentially outputs a gate signal to all of the pixel circuits The pixel unit of the line.
  • the first driver is configured to output in the first preset manner during the Nth frame and the N+1th frame of the screen display under the condition that X and Y are 2. a gate signal and a data signal to the pixel circuit, wherein N is a positive integer; and the second driver is configured to be during the N+2th frame and the N+3th frame of the picture display
  • the second preset mode outputs a gate signal and a data signal to the pixel circuit.
  • the first driver in response to the first driver outputting a gate signal and a data signal to the pixel circuit in the first preset manner, the first driver is grouped by three rows of pixel units. All the rows of the pixel circuit are grouped, and gate signals are output to the pixel cells in the order of the first row, the third row, and the second row in each group.
  • the any one of the drivers in a case where any one of the first driver and the second driver outputs the gate signal to a row of pixel units, the any one of the drivers further outputs corresponding data.
  • the signal is in each pixel unit of the row.
  • the polarity of the data signal of the Nth frame and the (N+1)th frame is opposite, and the pole of the data signal of the N+2th frame and the (N+3th frame) The opposite is true.
  • the data signal of the Nth frame in a case where the data signal of the Nth frame is negative polarity, the data signal of the (N+1)th frame has a positive polarity, and the data signal of the N+2th frame has a negative polarity.
  • the data signal of the N+3th frame has a positive polarity.
  • a pixel circuit comprising any of the above-described driving devices.
  • a display device comprising the above-described pixel circuit.
  • a computing device comprising: a processor; a memory having computer executable instructions that, when executed by the processor, perform as claimed in claims 1-8 The driving method according to any one of the preceding claims.
  • FIG. 1 is a flow chart of a method of driving a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit in the related art
  • FIG. 3 is a schematic diagram showing the generation of horizontal stripes when the pixel circuit is driven by the Z flip driving method
  • FIG. 4 is a schematic diagram of pixel voltage per frame when a screen is displayed, according to an embodiment of the present disclosure
  • FIG. 5 is a schematic block diagram of a driving device of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic block diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure.
  • a driving method of a pixel circuit, a driving device of a pixel circuit, a pixel circuit, and a display device will be described below with reference to the accompanying drawings.
  • FIG. 1 is a flowchart of a driving method of a pixel circuit, according to an embodiment of the present disclosure. As shown in FIG. 1, the driving method of the pixel circuit may include the following steps:
  • Step S1 During the frame sequence formed by consecutive X frames displayed on the screen, the gate signal and the data signal are output to the pixel circuit in a first preset manner.
  • Step S2 outputting a gate signal and a data signal to the pixel circuit in a second preset manner during a frame sequence formed by consecutive Y frames adjacent to the frame sequence formed by the consecutive X frames, wherein the first preset is The mode is different from the second preset mode, and X and Y are positive integers not lower than 2.
  • R ij represents a red pixel unit
  • G ij represents a green pixel unit
  • B ij represents a blue pixel unit
  • Gi represents a gate signal input end of the i-th row of pixel units
  • Sj represents a pixel unit of the j-th column.
  • Data signal input where i and j are positive integers.
  • the gate signal is sequentially output to the gate signal input terminals G1, G2, ... G6 during each frame of the screen display, and the gate signal is outputted.
  • the data signal is output to the data signal input terminals S1, S2, ..., S7, thereby realizing the display of the picture.
  • this driving method causes a horizontal streak phenomenon under certain screens.
  • FIG. 3 is a schematic diagram showing the generation of horizontal stripes when the pixel circuit is driven by the Z flip driving method.
  • the gray scale voltage of the eighth gray scale is set to 0
  • the gray scale voltage of the gray level of the 134th gray scale is set to H (positive polarity)
  • the gray scale voltage of the gray level of the 156th gray scale is set. It is determined as L (negative polarity), then when the voltage at the input end of the data signal is from 0 ⁇ H or from 0 ⁇ L, the pixel charging may be insufficient due to the sudden change of the voltage at the input end of the data signal and the delay of the data signal.
  • the charging condition is: the red pixel unit (R) is basically not bright, the even-numbered row of green pixel units (G) is insufficiently charged, and the odd-numbered row of blue pixel units (B) is undercharged; when the display screen R165+G134+B8 is displayed, The charging condition is: the blue pixel unit is basically not bright, the even-numbered row of red pixel units is undercharged, and the odd-numbered row of green pixel units is undercharged.
  • the brightness of the green pixel unit is the highest and the human eye is sensitive to green, when the difference between the lines is different, the color mixture perceived by the human eye is greatly affected by the insufficient charging of the green pixel, so that the difference between the lines and the light can be seen macroscopically.
  • the bad phenomenon ie, horizontal stripes, which affects the display quality of the picture.
  • the pixel circuit is driven by a first preset manner (for example, a conventional Z flip driving method) during a frame sequence composed of consecutive X frames displayed on the screen, and the continuous X is displayed on the screen.
  • a first preset manner for example, a conventional Z flip driving method
  • a sequence of frames consisting of consecutive consecutive Y frames of frames constitutes a second preset manner (for example, a driving method different from the conventional Z flip) to drive the pixel circuits such that the charging time of the pixel circuits is spatially ( That is, the pixel units of different rows are balanced, thereby effectively improving the problem of light-dark difference (ie, horizontal stripes) between lines, and thus effectively improving the display quality of the screen.
  • the first preset mode adopted during the frame sequence formed by consecutive X frames of the screen is used during the frame sequence composed of consecutive Y frames adjacent to the frame sequence formed by the consecutive X frames.
  • the second preset mode can be interchanged.
  • a driving method different from the conventional Z flip is employed, and a frame sequence composed of consecutive Y frames adjacent to a frame sequence composed of consecutive X frames is used during the frame sequence of the screen display.
  • the conventional Z flip drive mode is employed during a frame sequence composed of consecutive Y frames adjacent to a frame sequence composed of consecutive X frames.
  • the pixel circuit shown in FIG. 2 is still taken as an example.
  • the first row, the second row, the third row, and the fourth row of pixel units may be divided into one group, and the fifth row and the sixth row are The seventh and eighth rows of pixel units are divided into a group, and so on.
  • the gate signals are output to the rows of pixel cells in an out-of-order manner. For example, the gate signal is first outputted to the gate signal input terminal G1 of the first row of pixel units, then the gate signal is outputted to the gate signal input terminal G3 of the third row of pixel units, and the gate signal is output to the second row of pixels.
  • the gate signal input terminal G2 of the unit finally outputs the gate signal to the gate signal input terminal G4 of the fourth row of pixel units.
  • the gate signal is first outputted to the gate signal input terminal G5 of the fifth row of pixel units, and then the gate signal is outputted to the gate signal input terminal G7 of the seventh row of pixel units, and so on, until all the grids The input of the pole signal is completed.
  • other rows of gate signals may be input in other orders, which are not specifically limited herein.
  • the gate signal is output to the pixel unit in a sequential manner.
  • the gate signal is first outputted to the gate signal input terminal G1 of the first row of pixel units, then the gate signal is outputted to the gate signal input terminal G2 of the second row of pixel units, and the gate signal is output to the third row of pixels.
  • the gate signal input terminal G3 of the cell next, sequentially outputs the gate signal to the fourth row of pixel cells, the fifth row of pixel cells, the sixth row of pixel cells, ... until the input of all row gate signals is completed.
  • the first preset manner described above is adopted during adjacent frames of the screen display, and the second preset manner described above is adopted during subsequent frames.
  • the charging time of the pixel circuit can be balanced in space, thereby effectively improving the problem of bright and dark differences between rows (ie, horizontal stripes), effectively improving the display quality of the image, and the method is simple and easy, and the reliability is high.
  • the gate signal and the data signal are output to the pixel circuit in a first preset manner during the Nth frame and the N+1th frame of the screen display, wherein N is a positive integer; during the N+2th frame and the N+3th frame of the screen display, the gate signal and the data signal are output to the pixel circuit in a second preset manner.
  • the pixel circuit can be driven by using a first preset manner (for example, a conventional Z flip driving method) during the Nth frame and the N+1th frame displayed on the screen.
  • the pixel circuit is driven by a second preset mode (for example, a driving method different from the conventional Z flip) during the N+2th frame and the N+3th frame of the screen display.
  • This can make the charging time of the pixel circuit balance in space, thereby effectively improving the problem of light-dark difference (ie, horizontal stripes) between lines, and effectively improving the display quality of the picture.
  • outputting the gate signal and the data signal to the pixel circuit in a first preset manner includes grouping all the rows of the pixel circuit in groups of three rows of pixel units, and in each group The gate signals are output to the pixel units of the corresponding rows in the order of the first row, the third row, and the second row. Further, when the gate signal is outputted to the pixel unit, a corresponding data signal is also outputted to each of the pixel units of the row.
  • the pixel circuit shown in FIG. 2 is still taken as an example. As shown in FIG. 2, the first row, the second row, and the third row of pixel units may be divided into one group, and the fourth row, the fifth row, and the sixth row of pixel units are divided into one group, and so on. Then, in each group, the gate signals are output in a preset order.
  • the gate signal is first outputted to the gate signal input terminal G1 of the first row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7.
  • the data signal ie, the pixel voltage
  • the gate signal is outputted to the gate signal input terminal G3 of the third row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7, and the data signals of the third row of pixel units (ie, The pixel voltage) is written.
  • the gate signal is outputted to the gate signal input terminal G2 of the second row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7, and the data signals of the second row of pixel units (ie, The pixel voltage) is written.
  • the gate signals are sequentially outputted to the gate signal input ends of the fourth row pixel unit, the sixth row pixel unit, and the fifth row pixel unit, and when the gate signal is output to the gate signal input end of the row of pixel units, A corresponding data signal is output to the data signal input of each pixel unit of the row to write a corresponding data signal (ie, a pixel voltage) into the corresponding pixel unit.
  • the N+1th frame displayed on the screen is the same as the driving method during the Nth frame, and will not be described here.
  • the gate signal is first outputted to the gate signal input terminal G2 of the second row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ... S7, at this time, the data signal (ie, the pixel voltage) of the pixel unit of the second row is written. Then, the gate signal is outputted to the gate signal input terminal G1 of the first row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7, and the data signals of the first row of pixel units (ie, The pixel voltage) is written.
  • the gate signal is outputted to the gate signal input terminal G3 of the third row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7, and the data signals of the third row of pixel units (ie, The pixel voltage) is written.
  • the gate signals are sequentially outputted to the fifth row pixel unit, the fourth row pixel unit, and the sixth row pixel unit, and when the gate signal is output to the gate signal input end of the row of pixel units, the corresponding data signal is output to The data signal input of each pixel unit of the row is used to write a corresponding data signal (ie, a pixel voltage) into the corresponding pixel unit.
  • the N+1th frame displayed on the screen is the same as the driving method during the Nth frame, and will not be described here.
  • the gate signal may be output to the pixel unit of the corresponding row in the order of the third row, the first row, the second row, and then the fourth row, the sixth row, and the fifth row. And outputting the gate signal to the gate signal input end of the row of pixel units, and outputting the corresponding data signal to the data signal input end of each pixel unit of the row, which will not be described in detail herein.
  • outputting the gate signal and the data signal to the pixel circuit in a second preset manner includes sequentially outputting the gate signal to the pixel unit of the corresponding row in order from the first row to the last row. Further, when the gate signal is outputted to the pixel unit of one row, the corresponding data signal is also outputted to each pixel unit of the row.
  • the pixel circuit shown in FIG. 2 is still taken as an example.
  • the gate signal is first outputted to the gate signal input terminal G1 of the first row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, . .S7, at this time, the data signal (ie, the pixel voltage) of the pixel unit of the first row is written.
  • the gate signal is outputted to the gate signal input terminal G2 of the second row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7, and the data signals of the second row of pixel units (ie, The pixel voltage) is written.
  • the gate signal is outputted to the gate signal input terminal G3 of the third row of pixel units, and the data signal is outputted to the data signal input terminals S1, S2, ..., S7, and the data signals of the third row of pixel units (ie, The pixel voltage) is written.
  • the gate signals are sequentially outputted to the fourth row of pixel cells, the fifth row of pixel cells, and the sixth row of pixel cells, and when the gate signals are outputted to one row of pixel cells, corresponding data signals are output to each of the rows In the pixel unit, the data signal (ie, the pixel voltage) is written into the corresponding pixel unit.
  • the N+3 frame displayed on the screen is the same as the N+2 frame, and will not be described here.
  • the second preset mode may be a conventional Z flip drive mode.
  • the first preset mode will adopt a drive mode different from the Z flip.
  • the two frame pixel voltages are written in the same way (for example, a forward Z flip drive mode can be used), and the next two frames of pixel voltages are written in a different manner than the first two frames (for example, Reverse Z flip drive mode), so alternate.
  • the polarity of the data signal of the Nth frame and the (N+1)th frame is opposite to the polarity of the data signal of the N+2th frame and the N+3th frame.
  • the data signal of the Nth frame is negative polarity
  • the data signal of the (N+1)th frame is positive polarity
  • the data signal of the N+2th frame is negative polarity
  • the data signal of the N+3th frame is positive polarity.
  • the pixel circuit can be charged in the first preset manner during the Nth frame of the screen display, and the polarity of the charging voltage (ie, the data signal, that is, the pixel voltage) can be negative.
  • the pixel circuit is also charged in the first preset mode during the N+1th frame of the screen display, except that the polarity of the charging voltage is positive.
  • the pixel circuit is charged in the second preset mode during the N+2th frame of the screen display, and the polarity of the charging voltage is negative polarity.
  • the pixel circuit is also charged by the second preset mode, except that the polarity of the charging voltage of the frame is positive, and sequentially alternates.
  • the two pixel voltages are written in the same manner, but the written pixel voltages have opposite polarities.
  • the next two frames of pixel voltage are written in the same way, but different from the writing mode of the first two frames, and the polarities of the pixel voltages of the two frames are opposite, thus alternate.
  • This can balance the charging time of the pixel circuit in space, effectively improve the difference between the brightness and darkness of the line (ie, horizontal stripes), effectively improve the display quality of the picture, and the method is simple and easy, and the reliability is high.
  • the driving process is the same as the driving process when X and Y are 2, but the number of consecutive frames corresponding to the same driving mode is different, and specific reference may be made to X and Y being 2
  • the driving process is not detailed here.
  • FIG. 5 is a schematic block diagram of a driving device of a pixel circuit in accordance with one embodiment of the present disclosure.
  • the driving device 10 of the pixel circuit may include a first driver 11 and a second driver 12.
  • the second driver 12 in a case where the second driver 12 outputs the gate signal and the data signal to the pixel circuit in a second preset manner, the second driver 12 sequentially outputs the gate signal to all rows of the pixel circuit. In the pixel unit.
  • the first driver 11 is configured to output the gate in a first preset manner during the Nth frame and the N+1th frame of the screen display.
  • Signal and data signals to the pixel circuit wherein N is a positive integer; and the second driver 12 is configured to output the gate signal in a second predetermined manner during the N+2th frame and the N+3th frame of the picture display And data signals to the pixel circuit.
  • the first driver 11 in a case where the first driver 11 outputs the gate signal and the data signal to the pixel circuit in a first preset manner, the first driver 11 performs a pair of pixel circuits for each of the three rows of pixel units. All the rows are grouped, and in each group, the gate signals are output to the pixel units of the corresponding rows in the order of the first row, the third row, and the second row.
  • the second driver 12 in a case where the second driver 12 outputs the gate signal and the data signal to the pixel circuit in the second preset manner, the second driver 12 sequentially outputs the gates in the order from the first row to the last row.
  • the pole signal is in the pixel unit of the corresponding row.
  • the polarity of the data signal of the Nth frame and the (N+1)th frame is opposite to the polarity of the data signal of the N+2th frame and the N+3th frame.
  • the data signal of the Nth frame is negative polarity
  • the data signal of the (N+1)th frame is positive polarity
  • the data signal of the N+2th frame is negative polarity
  • the data signal of the N+3th frame is positive.
  • FIG. 6 is a schematic block diagram of a pixel circuit in accordance with an embodiment of the present disclosure. As shown in FIG. 6, the pixel circuit 100 of the embodiment of the present disclosure includes the above-described driving device 10.
  • the charging time of the pixel circuit can be balanced in space by the driving device, thereby effectively improving the difference between the bright and dark between the lines, that is, the horizontal stripes, and effectively improving the display quality of the picture. And the reliability is high.
  • FIG. 7 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure. As shown in FIG. 7, the display device 1000 of the embodiment of the present disclosure includes the pixel circuit 100 described above.
  • the display device can effectively improve the difference in brightness and darkness between lines, that is, the horizontal stripes, by the above-described pixel circuit, thereby effectively improving the display quality of the screen and having high reliability.
  • FIG. 8 illustrates an example computing device 800 that can implement the various techniques described herein.
  • Computing device 800 can be, for example, a server, a device associated with a client (eg, a client device), a system on a chip, and/or any other suitable computing device or computing system.
  • the example computing device 800 as illustrated includes a processing system 801 communicatively coupled to each other, one or more computer readable media 802, and one or more I/O interfaces 803. Although not shown, computing device 800 may further include a system bus or other data and command transmission system that couples various components to each other.
  • Processing system 801 represents functionality for performing one or more operations using hardware. Accordingly, processing system 801 is illustrated as including hardware elements 804 that can be configured as processors, functional blocks, and the like.
  • the processor can be comprised of a semiconductor and/or a transistor (eg, an electronic integrated circuit (IC)).
  • the processor-executable instructions can be electronically executable instructions.
  • One or more input/output interfaces 803 represent functionality for allowing a user to input commands and information to computing device 800 using various input devices and also to allow various output devices to present information to users and/or other components or devices.
  • input devices include a keyboard, a cursor control device (eg, a mouse), a microphone (eg, for voice input), a scanner, touch functionality (eg, a capacitive or other sensor configured to detect a physical touch), a camera (For example, it may use non-visible wavelengths that are visible or such as infrared frequencies to detect movements that are not touch-related such as gestures, etc.).
  • Examples of output devices include display devices (eg, monitors or projectors), speakers, printers, network cards, tactile response devices, and the like.
  • modules include routines, programs, objects, components, components, data structures, and the like that perform particular tasks or implement particular abstract data types.
  • module means software, firmware, hardware, or a combination thereof.
  • the features of the techniques described herein are platform-independent, which means that the techniques can be implemented on a variety of computing platforms having multiple processors.
  • Software, hardware or program modules and other program modules may be implemented as one or more instructions and/or logic embodied on some form of computer readable storage medium and/or by one or more hardware elements 804.
  • Computing device 800 can be configured to implement specific instructions and/or functionality corresponding to software and/or hardware modules.
  • computing device 800 can take a variety of different configurations, such as computers, mobile devices, and televisions.
  • the techniques described herein may be supported by these various configurations of computing device 800 and are not limited to the specific examples of the techniques described herein.
  • This functionality may also be implemented in whole or in part by using a distributed system, such as being implemented on a "cloud.”
  • a person skilled in the art can understand that the drawings are only schematic diagrams of alternative embodiments, and the modules or processes in the drawings are not necessarily required to implement the disclosure.
  • modules in the apparatus described in the embodiments may be distributed in the manner described in the embodiments, or may be distributed in a manner different from that described in the embodiment.
  • the modules of the above embodiments may be combined into one module, or may be further split into multiple sub-modules.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed”, and the like, are to be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated or defined otherwise. Or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, which can be the internal connection of two elements or the interaction of two elements, unless There are also clear limits.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

一种显示装置（1000）、像素电路（100）及其驱动方法和驱动装置（10），驱动方法包括：在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至像素电路（100）；在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至像素电路（100），其中，第一预设方式与第二预设方式不同，X、Y为不低于2的正整数；可以使像素电路（100）的充电时间在空间上达到平衡，从而提高了画面的显示品质。

Description

显示装置、像素电路及其驱动方法和驱动装置
相关申请
本申请要求申请日为2017年10月18日、申请号为CN201710972270.2的中国专利申请的优先权，该优先权申请的整体内容通过引用的方式被合并于此。
技术领域
本公开涉及显示技术的领域，特别涉及一种像素电路的驱动方法、一种像素电路的驱动装置、一种像素电路以及一种显示装置。
背景技术
通常，在理想的TFT-LCD的驱动模型中，源极驱动信号的电压以公共电极电压Vcom为基准呈对称分布，然而事实上，该驱动信号的中心电压往往与Vcom存在一定的偏移，所以将导致正负像素电压不对称。
为了解决正负像素电压不对称带来的问题，目前提出了许多驱动方式，例如点翻转、列翻转、行翻转、2H1V翻转、1H2V翻转以及Z翻转等。具体选择哪种驱动方式可根据每种驱动方式的显示品质、功耗、驱动电压大小以及伴随的不良因素等被决定。
Z翻转是目前最常用的一种翻转方式，其借助于内部像素结构使得列翻转达到点翻转的效果，但是Z翻转存在一个严重的弊端，就是在画面显示时可能出现横纹。
发明内容
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。
根据本公开第一方面，提出了一种像素电路的驱动方法，包括以下步骤：在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至所述像素电路；在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至所述像素电路，其中，所述第一预设方式与所述第二预设方式不同，X、Y为不低于2的正整数。
根据本公开的一个实施例，所述以第一预设方式输出栅极信号和数据信号至所述像素电路包括：以多行像素单元为一组将所述像素电路的所有行进行分组，并且在每一组中以乱序的方式输出栅极信号至该组中的所有行的像素单元中。
根据本公开的一个实施例，所述以第二预设方式输出栅极信号和数据信号至所述像素电路，包括：顺序地输出栅极信号至像素电路的所有行的像素单元。
根据本公开的一个实施例，在X和Y为2的条件下，在画面显示的第N帧和第N+1帧期间，以所述第一预设方式输出栅极信号和数据信号至所述像素电路，其中，N为正整数；在所述画面显示的第N+2帧和第N+3帧期间，以所述第二预设方式输出栅极信号和数据信号至所述像素电路。
根据本公开的一个实施例，所述以所述第一预设方式输出栅极信号和数据信号至所述像素电路包括：按照每三行像素单元为一组对所述像素电路的所有行进行分组，并且在每一组中，按照第一行、第三行、第二行的顺序输出栅极信号至像素单元中
根据本公开的一个实施例，所述以所述第二预设方式输出栅极信号和数据信号至所述像素电路包括：按照从第一行至最后一行的顺序依次输出栅极信号至像素单元中。
根据本公开的一个实施例，在输出所述栅极信号至所述像素单元中时，还输出相应的数据信号至该行的每一个像素单元中。
根据本公开的一个实施例，所述第N帧与所述第N+1帧的数据信号的极性相反，并且所述第N+2帧与所述第N+3帧的数据信号的极性相反。
根据本公开的一个实施例，在所述第N帧的数据信号具有负极性的情况下，所述第N+1帧的数据信号具有正极性，所述第N+2帧的数据信号具有负极性，以及所述第N+3帧的数据信号具有正极性。
根据本公开的第二方面，提出了一种像素电路的驱动装置，包括：第一驱动器，被配置成在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至所述像素电路；第二驱动器，被配置成在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至所述像素 电路，其中，所述第一预设方式与所述第二预设方式不同，X、Y为不低于2的正整数。
根据本公开的一个实施例，响应于所述第一驱动器以第一预设方式输出栅极信号和数据信号至所述像素电路，所述第一驱动器以多行像素单元为一组将所述像素电路的所有行进行分组，并且在每一组中以乱序的方式输出栅极信号至该组中的所有行的像素单元。
根据本公开的一个实施例，响应于所述第二驱动器以第二预设方式输出栅极信号和数据信号至所述像素电路，所述第二驱动器顺序地输出栅极信号至像素电路的所有行的像素单元。
根据本公开的一个实施例，在X和Y为2的条件下，所述第一驱动器被配置成在画面显示的第N帧和第N+1帧期间，以所述第一预设方式输出栅极信号和数据信号至所述像素电路，其中，N为正整数；以及所述第二驱动器被配置成在所述画面显示的第N+2帧和第N+3帧期间，以所述第二预设方式输出栅极信号和数据信号至所述像素电路。
根据本公开的一个实施例，响应于所述第一驱动器以所述第一预设方式输出栅极信号和数据信号至所述像素电路，所述第一驱动器按照每三行像素单元为一组对所述像素电路的所有行进行分组，并且在每一组中按照第一行、第三行和第二行的顺序输出栅极信号至像素单元中。
根据本公开的一个实施例，响应于所述第二驱动器以所述第二预设方式输出栅极信号和数据信号至所述像素电路，所述第二驱动器按照从第一行至最后一行的顺序依次输出栅极信号至像素单元中。
根据本公开的一个实施例，在所述第一驱动器和所述第二驱动器中的任意一个驱动器输出所述栅极信号至一行像素单元中的情况下，所述任意一个驱动器还输出相应的数据信号至该行的每一个像素单元中。
根据本公开的一个实施例，所述第N帧与所述第N+1帧的数据信号的极性相反，并且所述第N+2帧与所述第N+3帧的数据信号的极性相反。
根据本公开的一个实施例，在所述第N帧的数据信号为负极性的情况下，所述第N+1帧的数据信号具有正极性，所述第N+2帧的数据信号具有负极性，所述第N+3帧的数据信号具有正极性。
根据本公开的第三方面，提出了一种像素电路，其包括上述的任一驱动装置。
根据本公开的第四方面，提出了一种显示装置，其包括上述的像素电路。
根据本公开的第五方面，提出了一种计算设备，包括：处理器；存储器，其存储器有计算机可执行指令，当所述计算机可执行指令被处理器执行时，执行如权利要求1-8中任一项所述的驱动方法。
附图说明
图1是根据本公开的实施例的一种像素电路的驱动方法的流程图；
图2是相关技术中像素电路的结构示意图；
图3是采用Z翻转驱动方式驱动像素电路时产生横纹的示意原理图；
图4是根据本公开的一个实施例的画面显示时每帧像素电压的示意图；
图5是根据本公开的一个实施例的像素电路的驱动装置的示意框图；
图6是根据本公开的实施例的像素电路的示意框图；
图7是根据本公开的实施例的显示装置的示意框图。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中相同或类似的标号自始至终表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下面参照附图来描述根据本公开的实施例提出的像素电路的驱动方法、像素电路的驱动装置、像素电路以及显示装置。
图1是根据本公开的实施例的一种像素电路的驱动方法的流程图。如图1所示，该像素电路的驱动方法可包括以下步骤：
步骤S1：在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至像素电路。
步骤S2：在画面显示的与连续X帧构成的帧序列相邻的连续Y帧 构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至像素电路，其中，第一预设方式与第二预设方式不同，X、Y为不低于2的正整数。
以图2所示的像素电路为例。如图2所示，R i-j表示红色像素单元、G i-j表示绿色像素单元、B i-j表示蓝色像素单元，Gi表示第i行像素单元的栅极信号输入端，Sj表示第j列像素单元的数据信号输入端，其中，i和j为正整数。当采用常规的Z翻转驱动方式对像素电路进行驱动时，在画面显示的每一帧期间，依次输出栅极信号至栅极信号输入端G1、G2、...G6，并在输出栅极信号的同时，数据信号被输出至数据信号输入端S1、S2、...S7，从而实现画面的显示。然而，该驱动方式在某些特定画面下会导致横纹现象的出现。
图3示出了采用Z翻转驱动方式驱动像素电路时产生横纹的示意原理图。参考图3，假设将第8级灰阶的灰阶电压设定为0，将第134级灰阶的灰阶电压设定为H(正极性)，将第156级灰阶的灰阶电压设定为L(负极性)，那么当数据信号输入端的电压由0→H或由0→L时，由于数据信号输入端的电压突变并且存在数据信号延时的问题，可能引发像素充电不足。例如，在采用Z翻转驱动方式时，当显示画面R8+G134+B165(即，第8级灰阶的红色像素、第134级灰阶的绿色像素以及第156级灰阶的蓝色像素)时，其充电情况为：红色像素单元(R)基本不亮，偶数行绿色像素单元(G)充电不足，奇数行蓝色像素单元(B)充电不足；当显示画面R165+G134+B8时，其充电情况为：蓝色像素单元基本不亮，偶数行红色像素单元充电不足，奇数行绿色像素单元充电不足。由于绿色像素单元的亮度最高，并且人眼对绿色比较敏感，因此当行间充电有差异时，人眼感觉到的混色受绿色像素充电不足影响较大，从而宏观上可看到行间亮暗差异的不良现象(即横纹)，从而影响画面的显示品质。
通过上述分析可以看出，导致行间亮暗差异(即横纹)的主要原因在于：像素充电不足。在本公开的实施例中，通过在画面显示的连续X帧构成的帧序列期间采用第一预设方式(例如，常规的Z翻转驱动方式)来驱动像素电路，以及在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间采用第二预设方式(例如，不同于常规的Z翻转的驱动方式)来驱动像素电路，使得像素电路的充电 时间在空间上(即，不同行的像素单元间)达到平衡，从而有效改善行间亮暗差异(即横纹)的问题，并且因此有效提高画面的显示品质。
可以理解的是，在画面显示的连续X帧构成的帧序列期间采用的第一预设方式与在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间采用的第二预设方式可以进行互换。例如，在画面显示的连续X帧构成的帧序列期间采用不同于常规的Z翻转的驱动方式，而在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间采用常规的Z翻转驱动方式。
进一步地，在本公开的一个实施例中，以第一预设方式输出栅极信号和数据信号至像素电路包括：以多行像素单元为一组对像素电路的所有行进行分组，并且在每一组中，以乱序的方式输出栅极信号至该组中的所有行的像素单元中；以第二预设方式输出栅极信号和数据信号至像素电路，包括：以顺序输出栅极信号至像素电路的所有行的像素单元。
仍以图2所示的像素电路为例。当以第一预设方式输出栅极信号和数据信号至像素电路时，可将第一行、第二行、第三行和第四行像素单元划分为一组，将第五行、第六行、第七行和第八行像素单元划分为一组，依次类推。在每一组中，以乱序的方式输出栅极信号至各行像素单元中。例如，先输出栅极信号至第一行像素单元的栅极信号输入端G1，然后输出栅极信号至第三行像素单元的栅极信号输入端G3，再输出栅极信号至第二行像素单元的栅极信号输入端G2，最后输出栅极信号至第四行像素单元的栅极信号输入端G4。接下来，先输出栅极信号至第五行像素单元的栅极信号输入端G5，然后输出栅极信号至第七行像素单元的栅极信号输入端G7，...依次类推，直至所有行栅极信号的输入被完成。当然，也可以采用其它顺序来输入所有行栅极信号，这里对其并不做具体限定。
在以第二预设方式输出栅极信号和数据信号至像素电路的情况下，以顺序的方式输出栅极信号至所述像素单元中。例如，先输出栅极信号至第一行像素单元的栅极信号输入端G1，然后输出栅极信号至第二行像素单元的栅极信号输入端G2，再输出栅极信号至第三行像素单元的栅极信号输入端G3，接下来，依次输出栅极信号至第四行像素单元、第五行像素单元、第六行像素单元...，直至所有行栅极信号的 输入被完成。
因此，在画面显示的相邻几帧期间采用上述的第一预设方式，并在随后的几帧期间采用上述的第二预设方式。以这种方式，可以使得像素电路的充电时间在空间上达到平衡，从而有效改善行间亮暗差异(即横纹)的问题，有效提高了画面的显示品质，而且方法简单易行，可靠性高。
为使本领域技术人员能够更加清楚的了解本公开，下面结合本公开的具体示例来做进一步说明。
根据本公开的一个实施例，当X和Y为2时，在画面显示的第N帧和第N+1帧期间，以第一预设方式输出栅极信号和数据信号至像素电路，其中，N为正整数；在画面显示的第N+2帧和第N+3帧期间，以第二预设方式输出栅极信号和数据信号至像素电路。
也就是说，当X和Y为2时，可通过在画面显示的第N帧和第N+1帧期间采用第一预设方式(例如，常规的Z翻转驱动方式)来驱动像素电路，而在画面显示的第N+2帧和第N+3帧期间采用第二预设方式(例如，不同于常规的Z翻转的驱动方式)来驱动像素电路。这可以使像素电路的充电时间在空间上达到平衡，从而有效改善行间亮暗差异(即横纹)的问题，有效提高画面的显示品质。
在本公开的一个实施例中，以第一预设方式输出栅极信号和数据信号至像素电路包括：以每三行像素单元为一组对像素电路的所有行进行分组，并且在每一组中，按照第一行、第三行、第二行的顺序输出栅极信号至相应行的像素单元中。进一步地，在输出栅极信号至像素单元中时，还输出相应的数据信号至该行的每一个像素单元中。
仍以图2所示的像素电路为例。如图2所示，可将第一行、第二行和第三行像素单元划分为一组，将第四行、第五行和第六行像素单元划分为一组，依次类推。然后，在每一组中，按照预设顺序输出栅极信号。
作为一个具体示例，在画面显示的第N帧期间，先输出栅极信号至第一行像素单元的栅极信号输入端G1，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第一行像素单元的数据信号(即像素电压)被写入。然后，输出栅极信号至第三行像素单元的栅极信号输入端G3，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第三 行像素单元的数据信号(即像素电压)被写入。然后，输出栅极信号至第二行像素单元的栅极信号输入端G2，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第二行像素单元的数据信号(即像素电压)被写入。接下来，依次输出栅极信号至第四行像素单元、第六行像素单元和第五行像素单元的栅极信号输入端，并在输出栅极信号至一行像素单元的栅极信号输入端时，输出相应的数据信号至该行的每一个像素单元的数据信号输入端中，以将相应的数据信号(即像素电压)写入相应像素单元中。画面显示的第N+1帧与第N帧期间的驱动方式相同，这里就不再赘述。
作为另一个具体示例，在画面显示的第N帧期间，先输出栅极信号至第二行像素单元的栅极信号输入端G2，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第二行像素单元的数据信号(即像素电压)被写入。然后，输出栅极信号至第一行像素单元的栅极信号输入端G1，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第一行像素单元的数据信号(即像素电压)被写入。然后，输出栅极信号至第三行像素单元的栅极信号输入端G3，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第三行像素单元的数据信号(即像素电压)被写入。接下来，依次输出栅极信号至第五行像素单元、第四行像素单元和第六行像素单元，并在输出栅极信号至一行像素单元的栅极信号输入端时，输出相应的数据信号至该行的每一个像素单元的数据信号输入端中，以将相应的数据信号(即像素电压)写入相应像素单元中。画面显示的第N+1帧与第N帧期间的驱动方式相同，这里就不再赘述。
在本公开的其它实施例中，也可以按照先第三行再第一行再第二行，然后再第四行再第六行再第五行的顺序输出栅极信号至相应行的像素单元中，并在输出栅极信号至一行像素单元的栅极信号输入端时，输出相应的数据信号至该行的每一个像素单元的数据信号输入端中，具体这里就不再详述。
根据本公开的一个实施例，以第二预设方式输出栅极信号和数据信号至像素电路，包括：按照从第一行至最后一行的顺序依次输出栅极信号至相应行的像素单元中。进一步，在输出栅极信号至一行的像素单元中时，还输出相应的数据信号至该行的每一个像素单元中。
仍以图2所示的像素电路为例。如图2所示，在画面显示的第N+2帧，先输出栅极信号至第一行像素单元的栅极信号输入端G1，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第一行像素单元的数据信号(即像素电压)被写入。然后，输出栅极信号至第二行像素单元的栅极信号输入端G2，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第二行像素单元的数据信号(即像素电压)被写入。然后，输出栅极信号至第三行像素单元的栅极信号输入端G3，同时输出数据信号至数据信号输入端S1、S2、...S7，此时第三行像素单元的数据信号(即像素电压)被写入。接下来，依次输出栅极信号至第四行像素单元、第五行像素单元和第六行像素单元，并在输出栅极信号至一行像素单元中时，输出相应的数据信号至该行的每一个像素单元中，以将数据信号(即像素电压)写入相应像素单元中。画面显示的第N+3帧与第N+2帧的驱动方式相同，这里就不再赘述。
也就是说，第二预设方式可以为采用常规的Z翻转驱动方式，当然在第二预设方式为Z翻转驱动方式时，第一预设方式将采用不同于Z翻转的驱动方式。简单来说，两帧像素电压被写入的方式相同(例如，可以采用正向的Z翻转驱动方式)，接下来的两帧像素电压被写入的方式不同于前两帧(例如，可以采用反向的Z翻转驱动方式)，如此交替下去。这使得像素电路的充电时间在空间上达到平衡，从而有效改善Z翻转驱动方式带来的行间亮暗差异(即横纹)的问题，有效提高了画面的显示品质，而且方法简单易行，可靠性高。
根据本公开的一个实施例，第N帧与第N+1帧的数据信号的极性相反，第N+2帧与第N+3帧的数据信号的极性相反。
进一步地，当第N帧的数据信号为负极性时，第N+1帧的数据信号为正极性，第N+2帧的数据信号为负极性，第N+3帧的数据信号为正极性。
如图4所示，在画面显示的第N帧期间可以采用第一预设方式对像素电路进行充电，充电电压(即数据信号，也即像素电压)的极性可以为负极性。在画面显示的第N+1帧期间也采用第一预设方式对像素电路进行充电，只是充电电压的极性为正极性。接下来，在画面显示的第N+2帧期间采用第二预设方式对像素电路进行充电，充电电压的极性为负极性。在画面显示的第N+3帧期间，也采用第二预设方式 对像素电路进行充电，只是该帧的充电电压的极性为正极性，依次交替下去。
也就是说，两帧像素电压被写入的方式相同，但写入的像素电压的极性相反。接下来的两帧像素电压被写入的方式也相同，但不同于前两帧的写入方式，并且这两帧像素电压的极性也是相反的，如此交替下去。这能够使像素电路的充电时间在空间上达到平衡，有效改善行间亮暗差异(即横纹)的问题，有效提高了画面的显示品质，而且方法简单易行，可靠性高。
另外，当X、Y为大于2的整数时，其驱动过程与X、Y为2时的驱动过程相同，只是相同驱动方式所对应的连续帧数不同，具体可参考X、Y为2时的驱动过程，这里就不再详述。
综上，根据本公开的实施例的像素电路的驱动方法，通过在画面显示的相邻几帧期间采用相同的驱动方式，并在随后的几帧期间采用另外的相同驱动方式，使得像素电路的充电时间在空间上达到平衡，从而有效改善行间亮暗差异(即横纹)的问题，有效提高了画面的显示品质，而且该驱动方法简单易行，可靠性高。
图5是根据本公开的一个实施例的像素电路的驱动装置的示意框图。如图5所示，该像素电路的驱动装置10可包括第一驱动器11和第二驱动器12。
第一驱动器11被配置成在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至像素电路；第二驱动器12被配置成在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至像素电路，其中，第一预设方式与第二预设方式不同，X、Y为不低于2的正整数。
根据本公开的一个实施例，在第一驱动器11以第一预设方式输出栅极信号和数据信号至像素电路的情况下，第一驱动器11以多行像素单元为一组对像素电路的所有行进行分组，并且在每一组中，以乱序的方式输出栅极信号至该组中的所有行的像素单元中。
根据本公开的一个实施例，在第二驱动器12以第二预设方式输出栅极信号和数据信号至像素电路的情况下，第二驱动器12顺序地输出栅极信号至像素电路的所有行的像素单元中。
在本公开的一个实施例中，在X和Y为2的条件下，第一驱动器11被配置成在画面显示的第N帧和第N+1帧期间，以第一预设方式输出栅极信号和数据信号至像素电路，其中，N为正整数；以及第二驱动器12被配置成在画面显示的第N+2帧和第N+3帧期间，以第二预设方式输出栅极信号和数据信号至像素电路。
根据本公开的一个实施例，在第一驱动器11以第一预设方式输出栅极信号和数据信号至像素电路的情况下，第一驱动器11按照每三行像素单元为一组对像素电路的所有行进行分组，并且在每一组中，按照第一行、第三行、第二行的顺序输出栅极信号至相应行的像素单元中。
根据本公开的一个实施例，在第二驱动器12以第二预设方式输出栅极信号和数据信号至像素电路的情况下，第二驱动器12按照从第一行至最后一行的顺序依次输出栅极信号至相应行的像素单元中。
进一步地，在第一驱动器11或第二驱动器12输出栅极信号至一行像素单元中时，其还输出相应的数据信号至该行的每一个像素单元中。
根据本公开的一个实施例，第N帧与第N+1帧的数据信号的极性相反，第N+2帧与第N+3帧的数据信号的极性相反。
进一步地，当第N帧的数据信号为负极性时，第N+1帧的数据信号为正极性，第N+2帧的数据信号为负极性，并且第N+3帧的数据信号为正极性。
需要说明的是，本公开的实施例的像素电路的驱动装置中未披露的细节可以参照本公开的实施例的像素电路的驱动方法中所披露的细节，这里不再赘述。
在根据本公开的实施例的像素电路的驱动装置中，通过第一驱动器在画面显示的相邻几帧期间采用相同的驱动方式，并通过第二驱动器在随后的几帧期间采用另外的同一驱动方式，使得像素电路的充电时间在空间上达到平衡，从而有效改善行间亮暗差异(即横纹)的问题，有效提高了画面的显示品质。而且所述驱动装置的驱动方式简单易行，可靠性高。
图6是根据本公开的实施例的像素电路的示意框图。如图6所示，本公开的实施例的像素电路100包括上述的驱动装置10。
本公开的实施例的像素电路，通过上述的驱动装置，能够使得像素电路的充电时间在空间上达到平衡，从而有效改善行间亮暗差异即横纹的问题，有效提高了画面的显示品质，而且可靠性高。
图7是根据本公开的实施例的显示装置的示意框图。如图7所示，本公开的实施例的显示装置1000包括上述的像素电路100。
本公开的实施例的显示装置，通过上述的像素电路，能够有效改善行间亮暗差异即横纹的问题，从而有效提高画面的显示品质，而且可靠性高。
图8图示了可以实施本文中描述的各种技术的示例计算设备800。计算设备800例如可以是服务器、与客户端相关联的设备(例如，客户端设备)、片上系统和/或任何其它合适的计算设备或者计算系统。
如所图示的示例计算设备800包括通信地耦接到彼此的处理系统801、一个或多个计算机可读介质802和一个或多个I/O接口803。尽管未示出，但计算设备800可以进一步包括将各种构件耦接到彼此的系统总线或者其它的数据和命令传输系统。
处理系统801表示用于使用硬件执行一个或多个操作的功能性。相应地，处理系统801被图示为包括硬件元件804，其可以被配置为处理器、功能块等。例如，处理器可以由半导体和/或晶体管(例如，电子集成电路(IC))组成。在这样的上下文中，处理器可执行指令可以是电子可执行的指令。
计算机可读介质802被图示为包括存储器/存储装置805。存储器/存储装置805可以包括易失性介质(诸如是随机存取存储器(RAM))和/或非易失性介质(诸如是只读存储器(ROM)、闪存、光盘、磁盘等)。存储器/存储装置805可以包括固定介质(例如，RAM、ROM、固定硬盘驱动器等)以及可移除介质(例如，闪存、可移除硬盘驱动器、光盘等)。
一个或多个输入/输出接口803表示用于允许用户使用各种输入设备向计算设备800输入命令和信息以及还允许使用各种输出设备向用户和/或其它构件或者设备呈现信息的功能性。输入设备的示例包括键盘、光标控制设备(例如，鼠标)、麦克风(例如，用于语音输入)、扫描仪、触摸功能性(例如，被配置为检测物理触摸的电容式或其它传感器)、照相机(例如，其可以使用可见的或者诸如是红外频率这 样的非可见的波长来检测诸如是手势的不涉及触摸的移动)等。输出设备的示例包括显示设备(例如，监视器或者投影仪)、扬声器、打印机、网卡、触觉响应设备等。
在本文中可能在软件、硬件元件或者程序模块的一般上下文中描述了各种技术。一般地，这样的模块包括执行特定的任务或者实施特定的抽象数据类型的例程、程序、对象、元件、构件、数据结构等。一般地，如本文中使用的术语“模块”、“功能性”和“构件”表示软件、固件、硬件或者其组合。本文中描述的技术的特征是平台无关的，这意味着可以在具有多种处理器的多种计算平台上实施所述技术。
软件、硬件或者程序模块和其它程序模块可以作为被体现在某种形式的计算机可读存储介质上的一个或多个指令和/或逻辑和/或通过一个或多个硬件元件804被实施。计算设备800可以被配置为实施与软件和/或硬件模块相对应的特定的指令和/或功能。
在各种实施方案中，计算设备800可以采取多种不同的配置，诸如计算机、移动装置和电视机等。本文中描述的技术可以被计算设备800的这些各种配置支持，并且不限于本文中描述的技术的具体的示例。该功能性也可以全部或者部分地通过使用分布式系统被实施，诸如在“云”上被实施。本领域技术人员可以理解附图只是可选实施例的示意图，附图中的模块或流程并不一定是实施本公开所必须的。
本领域技术人员可以理解实施例中描述的装置中的模块可以按照实施例描述的方式被分布，也可以以不同于本实施例描述方式被分布。上述实施例的模块可以合并为一个模块，也可以进一步拆分成多个子模块。
需要理解的是，在本公开的描述中，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为 指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体的连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介的间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (19)

  1. 一种像素电路的驱动方法，包括：
    在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至所述像素电路；
    在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至所述像素电路，其中，所述第一预设方式与所述第二预设方式不同，X、Y为不低于2的正整数。
  2. 如权利要求1所述的驱动方法，其中，所述以第一预设方式输出栅极信号和数据信号至所述像素电路包括：以多行像素单元为一组将所述像素电路的所有行进行分组，并且在每一组中以乱序的方式输出栅极信号至该组中的所有行的像素单元中。
  3. 如权利要求1所述的驱动方法，其中，所述以第二预设方式输出栅极信号和数据信号至所述像素电路，包括：顺序地输出栅极信号至像素电路的所有行的像素单元。
  4. 如权利要求1所述的驱动方法，其中，在X和Y为2的条件下，
    在画面显示的第N帧和第N+1帧期间，以所述第一预设方式输出栅极信号和数据信号至所述像素电路，其中，N为正整数；
    在所述画面显示的第N+2帧和第N+3帧期间，以所述第二预设方式输出栅极信号和数据信号至所述像素电路。
  5. 如权利要求4所述的驱动方法，其中，
    所述以所述第一预设方式输出栅极信号和数据信号至所述像素电路包括：按照每三行像素单元为一组对所述像素电路的所有行进行分组，并且在每一组中，按照第一行、第三行、第二行的顺序输出栅极信号至像素单元中；
    所述以所述第二预设方式输出栅极信号和数据信号至所述像素电路包括：按照从第一行至最后一行的顺序依次输出栅极信号至像素单元中。
  6. 如权利要求5所述的驱动方法，其中，在输出所述栅极信号至一行像素单元中时，还输出相应的数据信号至该行的每一个像素单元中。
  7. 如权利要求6所述的驱动方法，其中，所述第N帧与所述第N+1帧的数据信号的极性相反，并且所述第N+2帧与所述第N+3帧的数据信号的极性相反。
  8. 如权利要求7所述的驱动方法，其中，在所述第N帧的数据信号具有负极性的情况下，所述第N+1帧的数据信号具有正极性，所述第N+2帧的数据信号具有负极性，以及所述第N+3帧的数据信号具有正极性。
  9. 一种像素电路的驱动装置，包括：
    第一驱动器，被配置成在画面显示的连续X帧构成的帧序列期间，以第一预设方式输出栅极信号和数据信号至所述像素电路；
    第二驱动器，被配置成在画面显示的与连续X帧构成的帧序列相邻的连续Y帧构成的帧序列期间，以第二预设方式输出栅极信号和数据信号至所述像素电路，其中，所述第一预设方式与所述第二预设方式不同，X、Y为不低于2的正整数。
  10. 如权利要求9所述的驱动装置，其中，响应于所述第一驱动器以第一预设方式输出栅极信号和数据信号至所述像素电路，所述第一驱动器以多行像素单元为一组将所述像素电路的所有行进行分组，并且在每一组中以乱序的方式输出栅极信号至该组中的所有行的像素单元。
  11. 如权利要求9所述的驱动装置，其中，响应于所述第二驱动器以第二预设方式输出栅极信号和数据信号至所述像素电路时，所述第二驱动器顺序地输出栅极信号至像素电路的所有行的像素单元。
  12. 如权利要求9所述的驱动装置，其中，在X和Y为2的条件下，
    所述第一驱动器被配置成在画面显示的第N帧和第N+1帧期间，以所述第一预设方式输出栅极信号和数据信号至所述像素电路，其中，N为正整数；以及
    所述第二驱动器被配置成在所述画面显示的第N+2帧和第N+3帧期间，以所述第二预设方式输出栅极信号和数据信号至所述像素电路。
  13. 如权利要求12所述的驱动装置，其中，
    响应于所述第一驱动器以所述第一预设方式输出栅极信号和数据信号至所述像素电路，所述第一驱动器按照每三行像素单元为一组对 所述像素电路的所有行进行分组，并且在每一组中按照第一行、第三行和第二行的顺序输出栅极信号至像素单元中；
    响应于所述第二驱动器以所述第二预设方式输出栅极信号和数据信号至所述像素电路时，所述第二驱动器按照从第一行至最后一行的顺序依次输出栅极信号至像素单元中。
  14. 如权利要求13所述的驱动装置，其中，在所述第一驱动器和所述第二驱动器中的任意一个驱动器输出所述栅极信号至一行像素单元中的情况下，所述任意一个驱动器还输出相应的数据信号至该行的每一个像素单元中。
  15. 如权利要求14所述的驱动装置，其中，所述第N帧与所述第N+1帧的数据信号的极性相反，并且所述第N+2帧与所述第N+3帧的数据信号的极性相反。
  16. 如权利要求15所述的驱动装置，其中，在所述第N帧的数据信号为负极性的情况下，所述第N+1帧的数据信号具有正极性，所述第N+2帧的数据信号具有负极性，所述第N+3帧的数据信号具有正极性。
  17. 一种像素电路，包括如权利要求9-16中任一项所述的驱动装置。
  18. 一种显示装置，包括如权利要求17所述的像素电路。
  19. 一种计算设备，包括：
    处理器；
    存储器，其存储器有计算机可执行指令，当所述计算机可执行指令被处理器执行时，执行如权利要求1-8中任一项所述的驱动方法。
PCT/CN2018/100784 2017-10-18 2018-08-16 显示装置、像素电路及其驱动方法和驱动装置 WO2019076121A1 (zh)

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