WO2019075887A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

Info

Publication number
WO2019075887A1
WO2019075887A1 PCT/CN2017/116355 CN2017116355W WO2019075887A1 WO 2019075887 A1 WO2019075887 A1 WO 2019075887A1 CN 2017116355 W CN2017116355 W CN 2017116355W WO 2019075887 A1 WO2019075887 A1 WO 2019075887A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
array substrate
alignment
substrate
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/116355
Other languages
English (en)
French (fr)
Inventor
谢克成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2019075887A1 publication Critical patent/WO2019075887A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes

Definitions

  • the invention relates to a liquid crystal display panel technology, in particular to an array substrate and a display panel.
  • TFT-LCD Thin Film Transistor, Liquid Crystal Display, Liquid Crystal Display
  • CF substrate color filter substrate
  • the liquid crystal and the sealant are dropped on the array substrate or the color filter substrate, and the array substrate and the color filter substrate of the liquid crystal and the sealant are dropped, and cured by the sealant.
  • the accuracy of the group and the degree of shrinkage of the surface of the two substrate films may cause slight deviation between the upper and lower substrates (the upper substrate may be a color film substrate or a general one).
  • the cover plate and the lower substrate are array substrates), so that light leakage is poor.
  • the current solution is to control the accuracy of the group and control the shrinkage of the layers of the upper and lower substrates. This method sacrifices the monitoring production time of each site during the operation and cannot completely solve the light leakage problem.
  • the present invention provides an array substrate and a display panel to solve the problem of light leakage caused by the offset of the upper and lower substrates.
  • the invention provides an array substrate comprising a thin film transistor, a common electrode, a pixel electrode and an alignment electrode, the alignment electrode being disposed at a position corresponding to a black matrix, wherein the alignment electrode is used for liquid crystal located at a position of a black matrix
  • the molecules provide a directional voltage that aligns the liquid crystal molecules at that location.
  • the alignment electrode is made of an indium tin oxide material.
  • the alignment electrode includes a first electrode and a second electrode, and the second electrode is distributed at least on one side of the first electrode and connected to the first electrode.
  • the second electrode is circular or polygonal.
  • the alignment electrode is connected to the common electrode, the scan line of the array substrate or the data line of the array substrate.
  • the alignment electrode is disposed on the same layer as the pixel electrode.
  • the present invention also provides a display panel comprising an upper substrate and a lower substrate, the lower substrate adopting the array substrate, and the upper substrate comprises a black matrix.
  • the alignment electrode is defined in a line width of the black matrix.
  • the array substrate is a COA array substrate.
  • the present invention provides an alignment electrode on the array substrate corresponding to the position of the black matrix, and provides a directional voltage to the liquid crystal molecules through the alignment electrode, so that the liquid crystal molecules located at the black matrix position can be aligned.
  • the present invention provides an alignment electrode on the array substrate corresponding to the position of the black matrix, and provides a directional voltage to the liquid crystal molecules through the alignment electrode, so that the liquid crystal molecules located at the black matrix position can be aligned.
  • FIG. 1 is a schematic structural view of an array substrate of the present invention
  • Figure 2 is a projection view showing the positional relationship between the alignment electrode of the present invention and the black matrix
  • FIG. 3 is a schematic structural view of still another array substrate of the present invention.
  • FIG. 4 is a schematic view of a display panel of the present invention.
  • the array substrate of the present invention comprises a substrate 10 , a thin film transistor 1 disposed on the substrate 10 , a common electrode 2 , a pixel electrode 3 , and a alignment electrode 4 , and the alignment electrode 4 is disposed corresponding to the position of the black matrix.
  • the alignment electrode 4 is used to supply a directional voltage to the liquid crystal molecules located at the position of the black matrix, so that the liquid crystal molecules at the position are aligned.
  • the alignment electrode 4 and the pixel electrode 3 are disposed on the same layer.
  • the alignment electrode 4 is defined in the line width of the black matrix 5, that is, the width of the maximum pattern of the alignment electrode 4 is smaller than the line of the black matrix 5. width.
  • the alignment electrode 4 is made of an indium tin oxide (ITO) material.
  • the alignment electrode 4 includes a first electrode 41 and a second electrode 42.
  • the second electrode 42 is distributed at least on one side of the first electrode 41 and connected to the first electrode 41; specifically, the second The electrodes 42 are distributed on both sides of the first electrode 41 such that a plurality of branches are formed on both sides of the first electrode 41.
  • the shape of the second electrode 42 can be set according to actual conditions, for example, a circle or a polygon.
  • the second electrode 42 has a rectangular strip shape.
  • the edge of the first electrode 41 is formed into a zigzag structure.
  • the alignment electrode 4 is connected to the common electrode 2, the scan line of the array substrate (not shown) or the data line of the array substrate (not shown), but the invention is not limited thereto, and the alignment electrode may be specifically 4, a voltage for aligning is input, specifically, the first electrode 41 is connected to the common electrode 2, the scan line of the array substrate or the data line of the array substrate, and since the scan line and the data line are conventional components of the array substrate, Further, it is only necessary to ensure that the alignment electrode 4 is connected to the common electrode 2, the scan line of the array substrate (not shown) or the data line of the array substrate (not shown); As shown, the alignment electrode 4 is connected to the common electrode 2.
  • the method for fabricating the alignment electrode 4 can be realized by a conventional method for producing an ITO film layer. After the patterning, the alignment electrode 4 is formed, which is not specifically limited.
  • the thin film transistor 1 of the array substrate of the present invention includes a buffer layer 11, a polysilicon layer 12, a gate insulating layer 13, a gate electrode 15, an interlayer insulating layer 14, a source electrode 16, a drain electrode 17,
  • a light shielding layer (LS) 19 may also be provided at 12 places.
  • the substrate 10 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • the buffer layer 11 is disposed on the substrate 10.
  • the polysilicon layer 12 is disposed on the buffer layer 11.
  • the polysilicon layer 12 includes an undoped layer 121, a heavily doped layer 122 disposed on both sides of the undoped layer 121, and a lightly doped layer 123 disposed between the heavily doped layer 122 and the undoped layer 121.
  • the lightly doped layer 123 is an N-type lightly doped layer
  • the heavily doped layer 122 is an N-type heavily doped layer.
  • the invention is not limited thereto, for example, the lightly doped layer 123 may also be a P-type lightly doped layer.
  • the hetero-doped layer 122 may also be a P-type heavily doped layer.
  • the gate insulating layer 13 is disposed on the polysilicon layer 12 and the buffer layer 11.
  • the gate electrode 15 is disposed on the gate insulating layer 13, and the gate electrode 15 is disposed on the polysilicon layer 12.
  • the interlayer insulating layer 14 is provided on the gate electrode 15 and the gate insulating layer 13.
  • Via holes are respectively provided in the interlayer insulating layer 14 at the positions of the heavily doped layer 122 to expose the heavily doped layer 122, respectively.
  • the source 16 and the drain 17 are disposed on the interlayer insulating layer 14.
  • the source 16 and the drain 17 are in contact with the heavily doped layer 122 via holes, respectively.
  • the flat layer 18 is disposed on the interlayer insulating layer 14, the source 16 and the drain 17.
  • a via hole is provided on the flat layer 18 at the drain electrode 17 to expose the drain electrode 17.
  • the common electrode 2 is disposed on the flat layer 18, and the insulating layer 19 is disposed on the common electrode and the flat layer 18.
  • the insulating layer 19 is provided with a via hole at the drain electrode 17, and the via hole and the via hole on the flat layer 18. Connected to expose the drain 17.
  • the pixel electrode 3 and the alignment electrode 4 are provided on the insulating layer 19, and the pixel electrode 3 is in contact with the drain electrode 17 via the via hole of the insulating layer 19 and the via hole of the flat layer 18.
  • the present invention can also employ a COA array substrate in the prior art, but the invention is not limited thereto.
  • the COA array substrate includes a substrate 300, a gate 301 sequentially formed on the substrate 300, a gate insulating layer 302, an active layer 303, a source 304, a drain 305, and a first passivation layer 306.
  • the gate 301 is disposed on a surface of the substrate 300;
  • a gate insulating layer 302 is formed on the gate 301 to cover the gate 301 and the substrate 300;
  • the active layer 303 is formed on the gate insulating layer 302;
  • the source 304 and the drain 305 are formed on the active layer 303 and the source of the active layer 303 Zone and drain zone contact;
  • the first passivation layer 306 is formed on the source 304 and the drain 305, covering the source 304, the drain 305 and the gate insulating layer 302.
  • the first passivation layer 306 is provided with a via hole at the drain 305. Exposing drain 305
  • the color resist layer 307 includes color blocking blocks separated from each other;
  • the flat layer 308 is formed on the color resist layer 307, and a via hole is disposed on the flat layer 308 at the drain to expose the drain 305, and the via hole communicates with the via hole of the first passivation layer 306;
  • the common electrode 2 is formed on the flat layer 308;
  • a second passivation layer 309 is overlying the planarization layer 308 and the common electrode 2, and a via is provided at the second passivation layer 309 at the via of the planarization layer to expose the drain 305, the via and the first passivation Layer vias, flat layers via vias;
  • the pixel electrode 10 is disposed on the second passivation layer 309 and is in contact with the drain 305 via the second passivation layer via, the flat via, the first passivation via, and the like;
  • the alignment electrode 4 is provided on the second passivation layer 309.
  • the present invention also discloses a display panel including an upper substrate 100 and a lower substrate 200.
  • the lower substrate 200 adopts the foregoing array substrate, and the upper substrate 100 includes a black matrix 5, wherein the The alignment electrode 4 is defined in the line width of the black matrix 5, that is, the maximum width of the pattern of the alignment electrode 4 is smaller than the line width of the black matrix 5.
  • the upper substrate 100 is an existing color film substrate.
  • the color film substrate includes a glass substrate 101, a color resistance 103, and a setting.
  • a liquid crystal 400 is disposed between the upper substrate 100 and the lower substrate 200.
  • the lower substrate is located at the BM (black matrix) position, and the alignment electrode is disposed; during the photo-alignment process, the alignment electrode is provided with a directional voltage for the liquid crystal molecules, and the liquid crystal molecules at the position are aligned (FIG. 4).
  • the alignment electrode can be connected to the common electrode, the fixed alignment voltage is provided through the common electrode, or can be connected to the data line or the scan line, and the fixed alignment voltage is provided by the data line or the scan line. According to this method, even if the BM of the upper substrate is shifted after the group, the liquid crystal molecules at the position coincide with the arrangement of the liquid crystal molecules in the pixel, and light leakage does not occur. The yield of the product and the efficiency in the production process are greatly improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Liquid Crystal (AREA)

Abstract

提供了一种阵列基板，包括薄膜晶体管（1）、公共电极（2）、像素电极（3）以及配向电极（4），配向电极（4）设于与黑色矩阵（5）位置相对应处，配向电极（4）用于为位于黑色矩阵（5）位置处的液晶分子提供定向电压，使该位置处的液晶分子进行定向排列。还提供了一种显示面板，包括上基板（100）和下基板（200），下基板（200）采用阵列基板，上基板（100）包括黑色矩阵（5）。与现有技术相比，通过在阵列基板上与黑色矩阵（5）位置相对应处设置配向电极（4），通过配向电极（4）为液晶分子提供定向的电压，从而使得位于黑色矩阵（5）位置上的液晶分子能够进行定向排列，从而解决漏光的问题，进一步提升产品的良率和生产效率。

Description

阵列基板及显示面板 技术领域
本发明涉及一种液晶显示面板技术，特别是一种阵列基板及显示面板。
背景技术
TFT-LCD(Thin Film Transistor，薄膜晶体管，Liquid Crystal Display,液晶显示器)的制作非常复杂，需要经过阵列基板(TFT基板)制作，彩膜基板(CF基板)制作，在阵列基板和彩膜基板上分别涂布PI(配向膜)，完成PI涂布后，在阵列基板或彩膜基板上滴下液晶和框胶，并将滴下液晶和框胶的阵列基板和彩膜基板对组，经过框胶固化后完成制作。在将阵列基板和彩膜基板对组过程中，因对组精度和两个基板膜面收缩程度不同，容易导致上下基板间发生细微偏移(这里的上基板可以为彩膜基板也可以是一般的盖板，下基板为阵列基板)，从而发生漏光不良。目前的解决方法是管控对组精度和管控上下基板各层膜的收缩。该方法在作业过程中会牺牲掉各站点的监控生产时间，并且不能彻底解决漏光问题。
发明内容
为克服现有技术的不足，本发明提供一种阵列基板及显示面板，解决因上下基板偏移导致的漏光问题。
本发明提供了一种阵列基板，包括薄膜晶体管、公共电极、像素电极以及配向电极，所述配向电极设于与黑色矩阵位置相对应处，所述配向电极用于为位于黑色矩阵位置处的液晶分子提供定向电压，使该位置处的液晶分子进行定向排列。
进一步地，所述配向电极采用氧化铟锡材料制成。
进一步地，所述配向电极包括第一电极以及第二电极，所述第二电极至少分布在第一电极的其中一侧且与第一电极相连。
进一步地，所述第二电极为圆形或多边形。
进一步地，所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
进一步地，所述配向电极与像素电极设置在同一层上。
本发明还提供了一种显示面板，包括上基板和下基板，所述下基板采用所述的阵列基板，所述上基板包括黑色矩阵。
进一步地，所述配向电极限定于黑色矩阵的线宽之中。
进一步地，所述阵列基板为COA阵列基板。
本发明与现有技术相比，通过在阵列基板上与黑色矩阵位置相对应处设置配向电极，通过配向电极为液晶分子提供定向的电压，从而使得位于黑色矩阵位置上的液晶分子能够进行定向排列，从而解决漏光的问题，进一步提升产品的良率和生产效率。
附图说明
图1是本发明阵列基板的结构示意图；
图2是本发明配向电极与黑色矩阵的位置关系投影图；
图3是本发明的又一种阵列基板的结构示意图；
图4是本发明显示面板的示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
如图1所示，本发明的阵列基板包括基板10、设于基板10上的薄膜晶体管1、公共电极2、像素电极3以及配向电极4，所述配向电极4设于与黑色矩阵位置相对应处(从图中看，其与薄膜晶体管1的位置也相对)，所述配向电极4用于为位于黑色矩阵位置处的液晶分子提供定向电压，使该位置处的液晶分子进行定向排列，所述配向电极4与像素电极3设置在同一层上，具体地，所述配向电极4限定于黑色矩阵5的线宽之中，也就是说配向电极4的最大图形的宽度小于黑色矩阵5的线宽。
所述配向电极4采用氧化铟锡(ITO)材料制成。
如图2所示，配向电极4包括第一电极41以及第二电极42，所述第二电极42至少分布在第一电极41的其中一侧且与第一电极41相连；具体地，第二电极42分布在第一电极41的两侧，使第一电极41的两侧形成多个分支。这里值得注意的是，对配向电极4进行图案化时，第二电极42的形状可根据实际情况进行设置，例如为圆形或多边形，如图2所示，第二电极42为矩形条状，使第一电极41的边缘形成锯齿状结构。
所述配向电极4与公共电极2、阵列基板的扫描线(图中未示出)或阵列基板的数据线(图中未示出)相连，但本发明不限于此，还可以专门对配向电极4输入一用于配向的电压，具体地，第一电极41与公共电极2、阵列基板的扫描线或阵列基板的数据线连接，由于扫描线和数据线为阵列基板的常规部件，在此不再赘述，仅需保证配向电极4与公共电极2、阵列基板的扫描线(图中未示出)或阵列基板的数据线(图中未示出)的其中之一相连即可；如图2所示，配向电极4与公共电极2相连。
本发明中，配向电极4的制作方法可采用现有的ITO膜层的制作方法实现，通过图案化后，形成配向电极4，在此不做具体限定。
作为本发明的一个实施例，本发明的阵列基板中薄膜晶体管1包括缓冲层11、多晶硅层12、栅极绝缘层13、栅极15、层间绝缘层14、源极16、漏极17、平坦层18，但本发明的薄膜晶体管的结构并不限于此，其还可以是非晶硅薄膜晶体管、金属氧化物薄膜晶体管等其他类型的薄膜晶体管；在基板10与缓冲层11之间位于多晶硅层12处还可设有遮光层(LS)19。
具体而言，在本实施例中，基板10可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
缓冲层11设置于基板10上。
多晶硅层12设置于缓冲层11上。多晶硅层12包括未掺杂层121、分别设置于未掺杂层121两侧的重掺杂层122及设置于重掺杂层122和未掺杂层121之间的轻掺杂层123。这里，轻掺杂层123为N型轻掺杂层，重掺杂层122为N型重掺杂层，单本发明并不限制于此，例如轻掺杂层123也可以为P型轻掺杂层，重掺杂层122也可以为P型重掺杂层。
栅极绝缘层13设置于多晶硅层12和缓冲层11上。
栅极15设置于栅极绝缘层13上，并且栅极15位于多晶硅层12上。
层间绝缘层14设置于栅极15和栅极绝缘层13上。
层间绝缘层14中位于重掺杂层122位置处分别设有过孔，以分别将重掺杂层122暴露。
源极16和漏极17设置于层间绝缘层14上。源极16以及漏极17分别经过孔与重掺杂层122接触。
平坦层18设置于层间绝缘层14、源极16和漏极17上。平坦层18上位于漏极17处设有过孔，以将漏极17暴露。
公共电极2设于平坦层18上，在公共电极以及平坦层18上设有绝缘层19，绝缘层19上位于漏极17处设有过孔，该过孔与位于平坦层18上的过孔连通，以暴露漏极17。
像素电极3以及配向电极4设于绝缘层19上，像素电极3经绝缘层19过孔以及平坦层18过孔与漏极17接触。
当然，本发明除采用上述阵列基板的结构外，还可以采用现有技术中的COA阵列基板，但本发明不限于此。
如图3所示，COA阵列基板包括基板300以及依次形成于基板300上的栅极301、栅极绝缘层302、有源层303、源极304、漏极305、第一钝化层306、色阻层307、平坦层308、公共电极2、第二钝化层309、像素电极3；配向电极4设于第二钝化层309上，与像素电极3设置在同一层。
具体地，栅极301设置于基板300的表面上；
栅极绝缘层302形成于栅极301上，覆盖栅极301以及基板300上；
有源层303形成于栅极绝缘层302上；
所述源极304以及漏极305形成于有源层303上，且与有源层303的源极 区以及漏极区接触；
第一钝化层306形成于源极304以及漏极305上，覆盖源极304、漏极305以及栅极绝缘层302上；第一钝化层306位于漏极305处设置有过孔，以将漏极305暴露
所述色阻层307包括彼此分开的色阻块；
平坦层308形成与色阻层307上，在平坦层308上位于漏极处设置有过孔，以将漏极305暴露，该过孔与第一钝化层306的过孔连通；
公共电极2形成于平坦层308上；
第二钝化层309覆盖在平坦层308以及公共电极2上，在第二钝化层309位于平坦层过孔处设有过孔，以将漏极305暴露，该过孔与第一钝化层过孔、平坦层过孔连通；
所述像素电极10设于第二钝化层309上，并经第二钝化层过孔、平坦层过孔、第一钝化层过孔等与漏极305接触；
配向电极4设于第二钝化层309上。
如图4所示，本发明还公开了一种显示面板，包括上基板100和下基板200，所述下基板200采用前述的阵列基板，所述上基板100包括黑色矩阵5，其中，所述配向电极4限定于黑色矩阵5的线宽之中，也就是说配向电极4的图形最大的宽度小于黑色矩阵5的线宽。
所述阵列基板的具体结构在前述已经详细的阐述，在此不再对应用于显示面板中的阵列基板作详细的赘述。
此处需要注意的是，当阵列基板采用一般的薄膜晶体管阵列基板时，上基板100为现有的彩膜基板，如图1所示，该彩膜基板包括玻璃基板101、色阻103、设置在色阻间的黑色矩阵5以及ITO膜层102；而当阵列基板采用COA阵列基板时，如图4所示，上基板100的结构如下：包括玻璃基板101，在玻璃基板101与下基板200相对的一侧表面上设置黑色矩阵5，在玻璃基板101以及黑色矩阵5上设置一层ITO膜层102。
在上基板100和下基板200之间设置有液晶400。
本发明在下基板位于BM(黑色矩阵)位置上，设置配向电极；在光配向过程中通过该配向电极为液晶分子提供定向的电压，将该位置的液晶分子进行定向排列(图4)。该配向电极可以连接到公共电极上，通过公共电极提供固定配向电压，也可以连接到数据线或扫描线上，由数据线或扫描线提供固定的配向电压。通过该方法，即使上基板的BM对组后发生偏移，因该位置的液晶分子与像素内的液晶分子的排列一致，不会发生漏光现象。对产品的良率和生产过程中的效率有很大的提升。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (20)

  1. 一种阵列基板，其中：包括薄膜晶体管、公共电极、像素电极以及配向电极，所述配向电极设于与黑色矩阵位置相对应处，所述配向电极用于为位于黑色矩阵位置处的液晶分子提供定向电压，使该位置处的液晶分子进行定向排列。
  2. 根据权利要求1所述的阵列基板，其中：所述配向电极采用氧化铟锡材料制成。
  3. 根据权利要求1所述的阵列基板，其中：所述配向电极包括第一电极以及第二电极，所述第二电极至少分布在第一电极的其中一侧且与第一电极相连。
  4. 根据权利要求3所述的阵列基板，其中：所述第二电极为圆形或多边形。
  5. 根据权利要求1所述的阵列基板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  6. 根据权利要求2所述的阵列基板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  7. 根据权利要求3所述的阵列基板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  8. 根据权利要求4所述的阵列基板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  9. 根据权利要求1所述的阵列基板，其中：所述配向电极与像素电极设置在同一层上。
  10. 一种显示面板，包括上基板和下基板，其中：所述下基板采用阵列基板，所述上基板包括黑色矩阵，所述阵列基板包括薄膜晶体管、公共电极、像素电极以及配向电极，所述配向电极设于与黑色矩阵位置相对应处，所述配向电极用于为位于黑色矩阵位置处的液晶分子提供定向电压，使该位置处的液晶 分子进行定向排列。
  11. 根据权利要求10所述的显示面板，其中：所述配向电极采用氧化铟锡材料制成。
  12. 根据权利要求10所述的显示面板，其中：所述配向电极包括第一电极以及第二电极，所述第二电极至少分布在第一电极的其中一侧且与第一电极相连。
  13. 根据权利要求12所述的显示面板，其中：所述第二电极为圆形或多边形。
  14. 根据权利要求10所述的显示面板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  15. 根据权利要求11所述的显示面板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  16. 根据权利要求12所述的显示面板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  17. 根据权利要求13所述的显示面板，其中：所述配向电极与公共电极、阵列基板的扫描线或阵列基板的数据线相连。
  18. 根据权利要求10所述的显示面板，其中：所述配向电极与像素电极设置在同一层上。
  19. 根据权利要求10所述的显示面板，其中：所述配向电极限定于黑色矩阵的线宽之中。
  20. 根据权利要求10所述的显示面板，其中：所述阵列基板为COA阵列基板。
PCT/CN2017/116355 2017-10-19 2017-12-15 阵列基板及显示面板 Ceased WO2019075887A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710980466.6A CN107728391A (zh) 2017-10-19 2017-10-19 阵列基板及显示面板
CN201710980466.6 2017-10-19

Publications (1)

Publication Number Publication Date
WO2019075887A1 true WO2019075887A1 (zh) 2019-04-25

Family

ID=61212208

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/116355 Ceased WO2019075887A1 (zh) 2017-10-19 2017-12-15 阵列基板及显示面板

Country Status (2)

Country Link
CN (1) CN107728391A (zh)
WO (1) WO2019075887A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108873517B (zh) * 2018-06-25 2023-10-20 厦门天马微电子有限公司 一种阵列基板、显示面板以及显示装置
CN112068377A (zh) * 2020-09-28 2020-12-11 成都中电熊猫显示科技有限公司 阵列基板以及液晶面板
CN117192841A (zh) * 2023-08-30 2023-12-08 长沙惠科光电有限公司 显示面板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11202338A (ja) * 1998-01-19 1999-07-30 Hitachi Ltd 液晶表示装置
CN101109883A (zh) * 2007-08-21 2008-01-23 友达光电股份有限公司 像素结构、其制作方法及多域垂直配向型液晶显示装置
CN101354503A (zh) * 2008-09-24 2009-01-28 友达光电股份有限公司 液晶显示面板及其像素结构
CN101634785A (zh) * 2008-07-22 2010-01-27 胜华科技股份有限公司 液晶显示面板与应用其的液晶显示装置
JP2014182236A (ja) * 2013-03-19 2014-09-29 Japan Display Inc 液晶表示装置及びその製造方法
CN106773330A (zh) * 2016-11-25 2017-05-31 深圳市华星光电技术有限公司 液晶面板及其液晶配向方法、液晶显示器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101169562B (zh) * 2006-10-23 2011-04-06 奇美电子股份有限公司 多域垂直配向式液晶显示面板
KR100796126B1 (ko) * 2007-02-07 2008-01-21 삼성에스디아이 주식회사 액정표시장치 및 그 제조방법
CN104898330A (zh) * 2015-05-12 2015-09-09 南京中电熊猫液晶显示科技有限公司 一种tft阵列基板、液晶显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11202338A (ja) * 1998-01-19 1999-07-30 Hitachi Ltd 液晶表示装置
CN101109883A (zh) * 2007-08-21 2008-01-23 友达光电股份有限公司 像素结构、其制作方法及多域垂直配向型液晶显示装置
CN101634785A (zh) * 2008-07-22 2010-01-27 胜华科技股份有限公司 液晶显示面板与应用其的液晶显示装置
CN101354503A (zh) * 2008-09-24 2009-01-28 友达光电股份有限公司 液晶显示面板及其像素结构
JP2014182236A (ja) * 2013-03-19 2014-09-29 Japan Display Inc 液晶表示装置及びその製造方法
CN106773330A (zh) * 2016-11-25 2017-05-31 深圳市华星光电技术有限公司 液晶面板及其液晶配向方法、液晶显示器

Also Published As

Publication number Publication date
CN107728391A (zh) 2018-02-23

Similar Documents

Publication Publication Date Title
KR101905757B1 (ko) 에프에프에스 방식 액정표시장치용 어레이기판 및 그 제조방법
US8754415B2 (en) High light transmittance in-plane switching liquid crystal display device and method for manufacturing the same
US10268082B2 (en) Display panel and method of manufacturing the same, and display device
KR100928494B1 (ko) 액정표시장치 및 그 제조방법
US9046714B2 (en) Thin film transistor substrate and method for fabricating the same
US8134654B2 (en) Liquid crystal display and method for manufacturing the same
WO2013139192A1 (zh) 触摸液晶显示装置、液晶显示面板及上部基板
US9595549B2 (en) Display device comprising a plurality of microcavities and an encapsulation layer that seals the plurality of microcavities and method of manufacturing the same
US11158717B1 (en) Method for manufacturing thin-film transistor (TFT) substrate and TFT substrate
KR101973753B1 (ko) 금속 산화물 반도체를 포함하는 박막 트랜지스터 기판 및 그 제조 방법
WO2018032670A1 (zh) Tft基板的制作方法
US8665413B2 (en) Thin film transistor array panel, liquid crystal display, and manufacturing method thereof
WO2014131238A1 (zh) 阵列基板及其制作方法、显示面板及其制作方法
US10168570B2 (en) Display apparatus
WO2019100430A1 (zh) 一种tft阵列基板、制作方法以及液晶显示面板
US9735181B2 (en) Array substrate and method of manufacturing the same, display panel, and display device
WO2019075887A1 (zh) 阵列基板及显示面板
KR102244437B1 (ko) 액정 표시장치 및 그 제조방법
JP3741372B2 (ja) 液晶表示器の自己位置合わせ画素電極の製造方法
KR20030026088A (ko) 기판 흡착용 진공 척 구조
US8035104B2 (en) Thin film transistor display panel and manufacturing method thereof
WO2018152868A1 (zh) 阵列基板及液晶显示面板
US9780127B2 (en) Liquid crystral display and manufacturing method thereof
CN102778793A (zh) 一种液晶显示装置、阵列基板及其制造方法
US11887990B2 (en) Method for manufacturing array substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17928954

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17928954

Country of ref document: EP

Kind code of ref document: A1