WO2019062656A1 - 数据传输 - Google Patents

数据传输 Download PDF

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Publication number
WO2019062656A1
WO2019062656A1 PCT/CN2018/106875 CN2018106875W WO2019062656A1 WO 2019062656 A1 WO2019062656 A1 WO 2019062656A1 CN 2018106875 W CN2018106875 W CN 2018106875W WO 2019062656 A1 WO2019062656 A1 WO 2019062656A1
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WO
WIPO (PCT)
Prior art keywords
data
logical channel
window
interface board
rate
Prior art date
Application number
PCT/CN2018/106875
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English (en)
French (fr)
Inventor
郭道荣
Original Assignee
新华三技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新华三技术有限公司 filed Critical 新华三技术有限公司
Priority to JP2020517587A priority Critical patent/JP6978596B2/ja
Priority to EP18863120.4A priority patent/EP3675439B1/en
Priority to US16/648,212 priority patent/US11252111B2/en
Publication of WO2019062656A1 publication Critical patent/WO2019062656A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/27—Evaluation or update of window size, e.g. using information derived from acknowledged [ACK] packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes

Definitions

  • Network devices usually include a main control board and an interface board.
  • the main control board can be connected to the interface board through a high-speed interface;
  • the network device when the network device is configured to be distributed, the network device further includes a line card, and similarly, the line card can pass through the high-speed interface and the interface board. connection.
  • the high speed interface here is, for example, an Ethernet interface capable of achieving a GE level transmission rate.
  • the CPU Central Processing Unit
  • the main control board does not become a performance bottleneck.
  • the interface board is connected to other devices through non-Ethernet interfaces (such as E1 interface, T1 interface, asynchronous serial interface, synchronous serial interface, AM (Analog Modem) interface, etc.).
  • the transmission rate of the non-Ethernet interface is slower, such as 100M.
  • the transfer rate of the level Therefore, the rate at which the main control board or line card sends data to the interface board does not match the rate at which the interface board sends data to other devices. After the interface board receives a large amount of data through the Ethernet interface, only a small amount of data is sent through the non-Ethernet interface, which may result in packet loss.
  • FIG. 1 is a flow chart of a data transmission method in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a network device in an implementation manner of the present application.
  • 3A and 3B are schematic diagrams of a basic information table in an embodiment of the present application.
  • 3C-3F are schematic diagrams of window management in an embodiment of the present application.
  • 4A and 4B are schematic diagrams of message formats in an embodiment of the present application.
  • Fig. 5 is a structural diagram of a data transmission device in an embodiment of the present application.
  • FIG. 6 is a hardware structural diagram of a network device in an embodiment of the present application.
  • first, second, third, etc. may be used to describe various information in the embodiments of the present application, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information without departing from the scope of the present application.
  • second information may also be referred to as the first information.
  • word “if” may be interpreted to mean “at time” or "when” or "in response to determination.”
  • the embodiment of the present application provides a data transmission method, which can be applied to a network device.
  • the main control board and the interface board in the network device are connected through a high-speed interface as an example.
  • the case where the line card and the interface board are connected through the high-speed interface is similar, and details are not described herein again.
  • the number of the main control boards included in the network device may be one or more, and the number of the interface boards may be one or more.
  • the main control board can be connected to the interface board through the Ethernet interface, PCIE (Peripheral Component Interconnect Express), SPI4 (Serial Peripheral Interface), and the interface board can pass the E1 interface.
  • the T1 interface, the asynchronous serial interface, the synchronous serial interface, and the AM interface are connected to other devices. Under normal circumstances, the data transmission rate between the main control board and the interface board is greater than the data transmission rate between the interface board and other devices.
  • FIG. 1 it is a schematic flowchart of a data transmission method proposed in the embodiment of the present application.
  • the data transmission method is applicable to a network device including a main control board and an interface board.
  • Step 101 Determine an interface board and a logical channel corresponding to the first data to be sent. If the logical channel has the capability of transmitting the first data, adding header information to the first data, obtaining the second data, and storing the second data in a buffer corresponding to the logical channel.
  • the header information may include, but is not limited to, an interface board identifier of the interface board and a logical channel identifier of the logical channel.
  • the logical channel has the capability of transmitting the first data. If yes, the header information is added to the first data to obtain the second data; if not, the first data is not sent, but the first data is stored in the memory, and the logical channel has the first data to be sent. When the capability is, the first data is read from the memory, and the header information is added to the first data to obtain the second data.
  • the following manner may be adopted: obtaining a remaining resource size of the logical channel; if the remaining resource size is greater than or equal to the length of the first data, determining the logical channel Having the ability to transmit the first data; if the remaining resource size is less than the length of the first data, determining that the logical channel does not have the capability to send the first data.
  • the remaining resource size of the logical channel may also be updated to a difference between the current remaining resource size and the length of the first data.
  • the process of adding the header information to the first data to obtain the second data may include, but is not limited to, determining the unique identifier corresponding to the interface board (hereinafter referred to as the interface board identifier). And determine the unique identifier of the logical channel (hereinafter also referred to as logical channel identifier). Then, header information is added for the first data, and the header information may include, but is not limited to, the interface board identifier and the logical channel identifier.
  • the first data to which the header information is added may be referred to as the second data.
  • each logical channel may have a buffer; however, multiple logical channels may also correspond to the same buffer. Therefore, after the second data is obtained, the second data can be stored in a buffer corresponding to the logical channel.
  • Step 102 Read the second data from the buffer, obtain the interface board identifier and the logical channel identifier from the header information of the second data, remove the header information of the second data, obtain the first data, and obtain the first data.
  • a data is sent to the corresponding interface board of the interface board identifier.
  • the remaining resource size of the logical channel corresponding to the buffer may be updated to the sum of the current remaining resource size and the length of the first data.
  • the buffer of the logical channel can also be implemented using a windowing mechanism.
  • the logical channel may correspond to a send window having a length equal to the size of the buffer corresponding to the logical channel.
  • the parameters of the sending window may include, but are not limited to, a window starting position, a window ending position, and a window occupying position; a length between the window starting position and the window ending position is a length of the sending window; the window occupying position The length between the end position of the window and the remaining resource size of the logical channel.
  • the above process of “renewing the remaining resource size of the logical channel to the difference between the current remaining resource size and the length of the first data” may include: moving the window occupied position to a specified length in a direction of the window end position. .
  • the foregoing “update the remaining resource size of the logical channel corresponding to the buffer to the sum of the current remaining resource size and the length of the first data” may include, but is not limited to, the window occupying position to the beginning of the window.
  • the direction moves by a specified length; or, the start position of the window is moved to a specified length in a direction in which the window is occupied, and the end position of the window is moved to a specified length in a moving direction of the start position of the window.
  • the specified length may be the length of the first data.
  • the location of the second data in the buffer may also be obtained, and the sending window is determined according to the location of the second data in the buffer.
  • the start position of the window; then, the end position of the window of the send window can also be moved according to the moving length of the start position of the window.
  • the interface board identifier and the logical channel identifier may be obtained from the header information of the second data, and the header of the second data is removed. Information to get the first data.
  • the process of sending the first data to the interface board corresponding to the interface board identifier may include: acquiring a first rate used by the interface board to send the first data by using the logical channel, according to the first The rate determines a second rate used when the first data is sent to the interface board; and sends the first data to the interface board corresponding to the interface board identifier based on the second rate. Wherein the second rate is less than the first rate.
  • the process of determining the second rate used when the first data is sent to the interface board according to the first rate may include, but is not limited to, determining the forwarding manner of the interface board according to the feature data, and The first data is processed in a forwarding manner to obtain third data to be transmitted at the first rate; and a rate at which the first data is processed is determined as the second rate.
  • the method may further include the following steps: querying the pre-configured basic information table to obtain the feature type identifier corresponding to the logical channel identifier, and then Obtaining feature data corresponding to the feature type identifier.
  • the basic information table is used to record the correspondence between the logical channel identifier and the feature type identifier.
  • multiple logical channels can share the processing capability of the same main control board, and data can be stored in a buffer corresponding to each logical channel, and can be sent in a buffer through a logical channel.
  • the data can solve the problem that the rate of the main control board and the interface board does not match, avoid the packet loss problem of the interface board, and meet the QOS (Quality Of Service) requirements.
  • the networking diagram of the application scenario is shown in FIG. 2, and the main control board 210, the interface board 231, and the interface board 232 are taken as an example for description. However, the number of interface boards can also be more.
  • the first speed limiting device 212 is a newly added unit in the main control board 210, and the second speed limiting device 220 is also a newly added unit.
  • the second speed limiting device 220 can be deployed in the main control board, and each of the main control boards 210 is deployed with a second speed limiting device 220.
  • the second speed limiting device 220 can also be disposed in the interface boards 231 and 232.
  • the interface boards 231, 232 are deployed with a second speed limiting device 220.
  • the second speed limiting device 220 can be deployed separately instead of being deployed in the main control board 210 or the interface boards 231, 232.
  • the second speed limit device 220 will be described as an example.
  • the first rate limiting device 212 is a newly added unit in the main control board 210, and may be a hardware device. This type is not limited. If the second speed limiting device 220 is a newly added unit in the main control board 210 or the interface boards 231, 232, the second speed limiting device 220 may be a hardware device, and if the second speed limiting device 220 is separately deployed, the second The speed limiting device 220 can be a separate single board, and no limitation is imposed on this type.
  • the main control board 210 can be connected to the second speed limiting device 220 through an Ethernet interface, a PCIE, an SPI4, etc., and the second speed limiting device 220 can be connected to the interface board 231/interface board 232 through an Ethernet interface, a PCIE, an SPI4, or the like.
  • the main control board 210 and the second speed limiting device 220 are connected by an Ethernet interface, and the Ethernet controller 213 is used to implement an Ethernet interface connection.
  • the interface board 231/interface board 232 can be connected to other devices through an E1 interface, a T1 interface, an asynchronous serial interface, a synchronous serial interface, and an AM interface.
  • connection manner between the main control board 210 and the second speed limiting device 220 can be the same as the connection manner between the second speed limiting device 220 and the interface board 231 / interface board 232.
  • the maximum data transmission rate of the main control board 210 and the second speed limiting device 220 is the same as the maximum data transmission rate of the second speed limiting device 220 and the interface board 231 / interface board 232, which are larger than the interface board 231 / interface board 232. Maximum data transfer rate with other devices.
  • a processor 211 for example, a central processing unit (CPU)
  • CPU central processing unit
  • the first speed limiting device 212 can be controlled by a bus and Ethernet.
  • the device 213 is connected.
  • the main control board 210 can also create a logical channel, which is a data transmission channel.
  • a logical channel which is a data transmission channel.
  • the logical channel can be a data transmission channel "processor 211 ⁇ first speed limit device 212 ⁇ Ethernet controller 213 ⁇ second speed limit device 220 ⁇
  • the interface board 231 / the interface on the interface board 232, that is, the logical channel will pass through the above devices.
  • the outbound interface of the logical channel can be an E1 interface, a T1 interface, an asynchronous serial interface, a synchronous serial interface, or an AM interface.
  • the outbound interface of the logical channel may be a logical interface or a physical interface.
  • Different logical channels can occupy different physical interfaces. Different logical channels can share the same physical interface.
  • One logical channel can also occupy multiple physical interfaces.
  • logical channel 241 occupies physical interface 1 and physical interface 2
  • logical channel 242 occupies physical interface 3
  • logical channel 243 and logical channel 244 share physical interface 4. That is, the data transmission rate of the logical channel 241 is the sum of the data transmission rates of the physical interface 1 and the physical interface 2, the data transmission rate of the logical channel 242 is the data transmission rate of the physical interface 3, and the data transmission of the logical channel 243 and the logical channel 244. The sum of the rates is the data transmission rate of the physical interface 4.
  • the main control board 210 can also allocate a buffer for each logical channel and establish a correspondence between the logical channel and the buffer.
  • the logical channel 241 corresponds to the buffer 251
  • the logical channel 242 corresponds to the buffer 252
  • the logical channel 243 corresponds to the buffer 253
  • the logical channel 244 corresponds to the buffer 254.
  • the data that needs to be sent through the logical channel 241 is first buffered into the buffer 251, then the data is read from the buffer 251, and finally the data is sent through the logical channel 241.
  • Data that needs to be sent through the logical channel 242 is first buffered to buffer 252, then data is read from buffer 252, and the data is ultimately sent through the logical channel 242. And so on.
  • the main control board 210 can create multiple logical channels as needed, and the number of the logical channels is not limited.
  • the logical channel can be for "processor 211 ⁇ first speed limiting device 212 ⁇ Ethernet control a logical channel of the 213 ⁇ the second speed limiting device 220 ⁇ the outbound interface on the interface board 231/interface board 232” is not limited thereto, as long as the logical channel can correspond to one outgoing interface (located on the interface board), and
  • the process of sending data through a logical channel is the process of sending data through the outbound interface.
  • the main control board 210 can allocate a buffer for the logical channel and configure a send window for the logical channel.
  • the size of the buffer is related to the data transmission rate of the interface corresponding to the logical channel, and the length of the transmission window is the same as the buffer size corresponding to the logical channel. For example, when the data transmission rate of the outbound interface is 56 Kbits/s, the size of the buffer and the length of the transmission window are both 56K.
  • the first rate limiting device 212 may include a basic information table of each logical channel, and the basic information of the logical channel may include, but is not limited to, an interface board identifier, a logical channel identifier, an interface type, window position information, and the like. Each logical channel corresponds to a basic information table.
  • the content of the basic information table can be seen in FIG. 3A or FIG. 3B.
  • FIG. 3A is an example of a basic information table at an initial moment
  • FIG. 3B is an example of a basic information table at a certain moment. .
  • the interface board identifies the ID of the downlink port connected to the interface board on the main control board, which is the downlink port number of the main control board.
  • the downlink port number is uniformly numbered in the system. According to the downlink port number, the main control board can know which downlink port sends data to the interface board.
  • the logical channel identifies the ChID as the unique identifier of the logical channel.
  • the logical channel identifier can be formed by splicing the slot number (SlotID), port number (PortID), and subchannel number (SubChanID) of the interface board.
  • the slot number is up to 4 digits and can support 16 slots.
  • the port number is 6 digits in the middle and can support 64 ports.
  • the subchannel number is the last 12 digits and supports up to 4096 subchannels.
  • the logical channel identifier into which the slot number, the port number, and the sub-channel number are spliced is only an example, and no limitation is imposed on this.
  • the interface type is the type of the interface corresponding to the logical channel, such as POS, CE1, CPOS, AsySer (asynchronous serial interface), E1 interface, T1 interface, and AM interface.
  • the window location information may include the length of the send window WinSize, the left edge of the window, LeftEdge, the right edge of the window, the EdgeEdge, and the edge of the currently transmitted data, TxEdge.
  • the left edge of the window, LeftEdge can also be called the window start position.
  • the right edge of the window, RightEdge can also be called the end of the window.
  • the length of the send window WinSize can be, for example, 128K bytes (ie 0x20000), this value indicates the maximum length allowed.
  • the length of the send window WinSize is the same as the size of the buffer corresponding to the logical channel.
  • the length between the left edge of the window, LeftEdge, and the right edge of the window, RightEdge, is the length of the send window WinSize.
  • the edge TxEdge of the currently transmitted data can also be referred to as the window occupied position, and the next time data is sent, it is accumulated from here. For example, suppose the left edge of the window is LeftEdge, and the length of the first data is 64. After the first data is sent, the edge of the currently transmitted data TxEdge is 64. Assuming the length of the second data is 304, the second is sent.
  • the edge TxEdge of the currently transmitted data is 368 (64+304), and so on; when the edge TxEdge of the currently transmitted data is located between the LeftEdge of the window and the RightEdge of the right edge of the window, it indicates that the logical channel has the data to transmit. Capability, when the edge of the currently sent data TxEdge exceeds RightEdge, it indicates that the logical channel does not have the ability to send data.
  • the second rate limiting device 220 may include a basic information table of each logical channel, and the basic information of the logical channel may include, but is not limited to, an interface board identifier, a logical channel identifier, an interface type, a window position information, a feature type identifier, and the like. And each logical channel corresponds to a basic information table.
  • the basic information table of the second speed limit device 220 is similar to the basic information table of the first speed limit device 212. The difference is that the basic information table of the second speed limit device 220 has a feature type identifier, and the feature type identifier may be FeatureID, used to index the feature table, corresponding to the FeatureID of the feature table. For the rest of the basic information table, details are not described herein again.
  • the data transmission method proposed in the embodiment of the present application may include:
  • Step a After receiving the first data to be sent, the first rate limiting device 212 determines an interface board and a logical channel corresponding to the first data. Specifically, the forwarding table may be queried by using the destination address information of the first data (such as the destination IP address and/or the destination MAC address) to obtain an outbound interface corresponding to the destination address information, and the outbound interface corresponds to an interface board and A logical channel, the interface board is an interface board corresponding to the first data, and the logical channel is a logical channel corresponding to the first data.
  • the information of the interface board and the logical channel may also be notified by the processor 211, and the manner of determining is not limited.
  • Step b the first rate limiting device 212 determines whether the logical channel has the capability of transmitting the first data, and if so, performs step c; if not, the first data is not sent, but the first data is stored in the memory, Wait until the logical channel has the ability to send the first data, and then perform step c.
  • the first speed limiting device 212 may determine whether the logical channel has the capability of transmitting the first data according to the window position information in the basic information table and the length of the first data. For example, if the edge TxEdge of the currently transmitted data moves to the right by the length of the first data, and the edge TxEdge of the currently transmitted data is still located between the left edge LeftEdge of the window and the right edge of the window RightEdge, indicating that the logical channel has the first data to be sent.
  • edge TxEdge of the currently transmitted data moves to the right by the length of the first data, the edge TxEdge of the currently transmitted data exceeds the right edge RightEdge of the window, indicating that the logical channel does not have the ability to transmit the first data.
  • the first rate limiting device 212 may further adjust the edge of the currently transmitted data TxEdge according to the length of the first data and the position of the edge TxEdge of the currently transmitted data in the sending window. position.
  • the left edge of the window, LeftEdge, and the edge of the currently transmitted data, TxEdge are both zero.
  • the edge TxEdge of the currently transmitted data becomes 10K.
  • the edge TxEdge of the currently transmitted data becomes 20K.
  • FIG. 4A a schematic diagram of a data transmission completion message, after receiving a data transmission completion message, if the edge TxEdge of the current transmission data in the data transmission completion message is located between the left edge of the window, LeftEdge, and the right edge of the window, RightEdge , according to the edge TxEdge sliding window of the current sending data in the data sending completion message, for example, moving the left edge LeftEdge in the window to the right to the edge TxEdge of the current sending data in the data sending completion message, and in the window The right edge RightEdge slides to the right.
  • the length between the left edge of the sliding edge and the right edge of the right edge is the current length WinSize of the sending window.
  • edge TxEdge of the current transmission data in the data transmission completion message is not located between the left edge LeftEdge of the window and the right edge of the window RightEdge, the data transmission completion message is discarded, and the window is no longer slid.
  • the first speed limit device 212 transmits data to the second speed limit device 220, data is lost, and/or the second speed limit device 220 sends a data transmission completion message to the first speed limit device 212. Loss occurs, as long as the data is successfully sent and the corresponding data transmission completion message is successfully sent in the subsequent process, the window can slide correctly. In this way, the loss of the transmission resource will not be caused, and the packet loss will be prevented from causing the transmission to stop.
  • the window occupying position of the Nth data implies the length information of the N-1th data
  • the N-1th data is lost, if the data sending completion message for the Nth data is received, according to When the edge TxEdge sliding window of the current transmission data in the data transmission completion message is recovered, not only the transmission resource of the Nth data but also the transmission resource of the N-1th data is recovered. Therefore, even if data is lost, and/or data completion messages are lost, resources can be properly reclaimed.
  • Step c The first rate limiting device 212 adds header information for the first data, obtains the second data, sends the second data to the Ethernet controller 213, and the Ethernet controller 213 sends the second data to the second rate limiting device 220.
  • the first rate limiting device 212 may add header information to the first data to obtain modified data, and the data is the second data. As shown in FIG. 4B, it is a schematic diagram of the second data. Then, the second data can be sent to the Ethernet controller 213, and the second data is transmitted by the Ethernet controller 213 to the second speed limiting device 220.
  • the first rate limiting device 212 may include, but is not limited to, the following in the process of adding header information to the first data: interface board identifier, logical channel identifier, interface type, message type, window sending edge, and payload. length.
  • the window occupying position of the first data packet may be the data packet length of the current data transmission; the window occupying position of the second data packet may be used to accumulate the second data packet for the window occupying position of the first data packet. Length; the position of the window of the third packet, which can accumulate the length of the third packet for the window occupancy of the second packet; and so on.
  • the window information corresponding to the logical channel may also be updated, for example, the edge TxEdge of the currently transmitted data is shifted to the right by the length of the first data.
  • Step d After receiving the second data, the second rate limiting device 220 parses the logical channel identifier from the header information of the second data, and buffers the second data into a buffer corresponding to the logical channel identifier.
  • the second data may be buffered into the buffer 251 corresponding to the logical channel 241.
  • Step e When the second data needs to be sent, the second rate limiting device 220 reads the second data from the buffer corresponding to the logical channel, and obtains the interface board identifier and the logical channel identifier from the header information of the second data, and removes the second The header information of the data is obtained, and the first data is sent to the interface board corresponding to the interface board identifier.
  • the interface board can be configured to send the first data by using the logical channel to identify the corresponding logical channel, so that the interface board sends the first data by using the corresponding logical channel of the logical channel identifier.
  • the second rate limiting device 220 can read the second data from the buffer 251, and obtain the identifier of the interface board 231 and the identifier of the logical channel 241 from the header information of the second data, and then remove the header of the second data. The information is obtained, and the first data is sent to the interface board 231, and the interface board 231 is notified to send the first data through the logical channel 241.
  • the identifier of the logical channel needs to be notified to the interface board, and the notification mechanism is not limited.
  • the second rate limiting device 220 may send the logical channel identifier to the interface board, so that the interface board sends the first data by using the logical channel identifier corresponding logical channel.
  • the second rate limiting device 220 may identify the corresponding logical channel through the logical channel, and send the first data to the interface board. After receiving the first data through the logical channel, the interface board may send the first data through the logical channel. .
  • the second rate limiting device 220 may first obtain the first rate used by the interface board to send the first data through the logical channel, and send the first data to the interface board according to the first rate.
  • the second rate used in the first data is sent to the interface board based on the second rate.
  • the second speed limiting device 220 may determine, according to the feature data, a forwarding manner of the interface board, and The forwarding mode processes the first data to obtain third data to be transmitted by the interface board at the first rate; and in the process of obtaining the third data, the rate of processing the first data is determined to be the second rate.
  • the second rate is less than the first rate.
  • the second rate limiting device 220 may further store a feature table, where the feature table is used to record a data stream feature, and the data stream feature may include a feature type identifier (FeatureID) and feature data.
  • FeatureID feature type identifier
  • the feature type identifier is used to represent the feature of the class, and the feature data can be queried according to the feature type identifier.
  • the feature data may include, but is not limited to, one or any combination of the following: channel rate (Speed), such as 56 Kbits/s, 64 Kbits/s, etc.; frame interval (IFG), such as the number of padding characters inserted between frame intervals
  • the frame interval is empirically configurable; the block size BlockLen for transmitting data to the physical layer chip; and the advance amount PreTxLen for transmitting data to the physical layer chip.
  • the second rate limiting device 220 may query the basic information table based on the logical channel identifier in the header information of the second data to obtain a feature type identifier corresponding to the logical channel identifier. Then, the query feature table may be identified by the feature type to obtain feature data corresponding to the feature type identifier. Based on this, the second rate limiting device 220 can determine the forwarding mode of the interface board based on the feature data.
  • the forwarding mode is the forwarding mode used when the interface board sends data to the outside.
  • the forwarding modes corresponding to different protocols may be different or the same.
  • This forwarding mode is related to the protocol type. For example, for HDLC (High-Level Data Link Control), since HDLC data frames are separated by a flag sequence, the binary is 01111110. In a string of data bits, the same bit as the flag sequence may be generated. combination.
  • the forwarding mode may be: using bit padding technology, inserting a "0" after five consecutive "1"s to ensure transparent transmission of data.
  • the forwarding mode may also be other situations, and the forwarding mode is not limited.
  • the second rate limiting device 220 can perform analog transmission according to the forwarding mode. Specifically, the first data is processed by the forwarding manner to obtain the third data to be sent at the first rate; and in the process of obtaining the third data, the rate of processing the first data is determined to be the second rate.
  • the first rate is the rate at which the interface board actually sends data
  • the second rate is the rate at which the second rate limiting device 220 actually transmits data.
  • the process of performing analog transmission by the second speed limit device 220 according to the forwarding mode is performed in real time.
  • the reason why the second rate limiting device 220 adopts the analog transmission is: assuming that the first rate used by the interface board to send data through the logical channel is 56 Kbits/s, if the rate of providing data to the interface board is 56 Kbits/s, then When the interface board sends data, the data is processed by the above forwarding method, for example, bit padding technology is used to add additional information to the data. In this way, the final data sent by the interface board will be greater than 56Kbits/s, such as 60Kbits/s, that is, the data sent by the interface board overflows. Since the interface board cannot send 60Kbits/s of data, only 56Kbits/s of data can be sent, causing some data loss.
  • the second rate limiting device 220 can first obtain the first rate when the interface board sends data through the logical channel, such as 56 Kbits/s. Then, the data is read from the buffer, and the data is processed by the above forwarding method, such as adding information to the data by using a bit stuffing technique. In the process, determining the rate at which data is read from the buffer when generating data transmitted at 56 Kbits/s, the rate of reading the data is the second rate, such as 52 Kbits/s, so the second rate limiting device The rate at which the 220 provides data to the interface board is 52 Kbits/s.
  • the rate of data provided to the interface board is 52 Kbits/s instead of 56 Kbits/s.
  • the interface board first uses the above forwarding method to process the data.
  • the bit padding technology is used to add information to the data.
  • the final data sent by the interface board is 56 Kbits/s, and the data does not overflow, and the data is not caused. Loss, improve the efficiency of the interface board, improve the quality of data transmission, realize QOS application, avoid speech distortion caused by data loss, and the image is not clear.
  • the first rate such as the channel rate in the feature data, may be obtained from the feature data for the process of “acquiring the first rate used by the interface board to send data through the logical channel”.
  • the process of determining the forwarding mode of the interface board according to the feature data and processing the data by using the forwarding mode may include, but is not limited to, the following: if the feature data includes an interface type (such as recording an interface in the feature table) Type), the forwarding mode of the interface board can be determined based on the feature data, and the data is processed by the forwarding mode; if the interface type is not included in the feature data (for example, the interface type is not recorded in the feature table), the feature data can be based on the feature data.
  • the interface type (obtained from the header information of the data) determines the forwarding mode of the interface board, and processes the data through the forwarding mode.
  • the interface mode IFG
  • BlockLen BlockLen
  • PreTxLen PreTxLen
  • interface type and other parameters can be used to determine the forwarding mode of the interface board, and the data is processed by the forwarding mode, and the process is not limited.
  • the second rate limiting device 220 may further send a data sending completion message to the first rate limiting device 212, where the data sending completion message may carry the first data.
  • the length (the length of the first data after the second data is removed from the header information), and the data sending completion message may further carry the foregoing header information (such as an interface board identifier, a logical channel identifier, an interface type, a packet type, and a window sending edge). , payload length, etc.), the header information is the same as the header information of the second data.
  • the edge TxEdge of the current sending data in the header information of the data sending completion message may indicate that the data corresponding to the edge TxEdge of the currently transmitted data has been read from the buffer.
  • Step g After receiving the data transmission completion message, the first rate limiting device 212 updates the remaining resource size of the logical channel corresponding to the logical channel identifier to the sum of the current remaining resource size and the length of the first data. For example, moving the window occupying position to a specified length in the direction of the window starting position; or, moving the window starting position to the window occupying position by a specified length, and moving the window ending position to the moving direction of the window starting position by a specified length .
  • the specified length is the length of the first data.
  • the window start position in the transmission window may be determined according to the position of the second data in the buffer, and the window end position of the transmission window is moved according to the moving length of the window start position.
  • multiple logical channels can share the processing capability of the same main control board, and data can be stored in a buffer corresponding to each logical channel, and the data in the buffer is sent through the logical channel.
  • the problem that the rate of the main control board and the interface board does not match can be solved, and the packet loss problem of the interface board is avoided, and the QOS requirement is met.
  • the accurate speed limit of the interface board can be realized, and the performance of the main control board can be improved.
  • the data transmission rate of the logical channel 241 is 56 Kbits/s
  • the data transmission rate of the logical channel 242 is 56 Kbits/s
  • the data transmission rate of the logical channel 243 is 56 Kbits/s
  • the data transmission rate of the logical channel 244 is 56 Kbits/s.
  • the second rate limiting device 220 can store 56 Kbits/s of data into the buffer 251, store 56 Kbits/s of data into the buffer 252, store 56 Kbits/s of data into the buffer 253, and store 56 Kbits/s of data. Go to buffer 254.
  • the second rate limiting device 220 can send 56 Kbits/s of data to the logical channel 241, so that the logical channel 241 transmits 56 Kbits/s of data, and 56 Kbits/s of data is sent to the logical channel 242.
  • the logical channel 242 is sent 56 Kbits/s of data, and 56 Kbits/s of data is sent to the logical channel 243, so that the logical channel 243 transmits 56 Kbits/s of data, and 56 Kbits/s of data is sent to the logical channel 244, so that the logic Channel 244 transmits 56 Kbits/s of data.
  • a data transmission device is also provided in the embodiment of the present application, which can be applied to a network device, as shown in FIG. 5, which is a structural diagram of the device, and the device may include:
  • a determining module 501 configured to determine an interface board and a logical channel corresponding to the first data to be sent;
  • the processing module 502 is configured to: when the logical channel has the capability of sending the first data, add header information to the first data, to obtain second data; where the header information includes the interface board The interface board identifier and the logical channel identifier of the logical channel;
  • a storage module 503, configured to store the second data to a buffer corresponding to the logical channel
  • the reading module 504 is configured to read the second data from the buffer, and obtain the interface board identifier and the logical channel identifier from the read header information of the second data, and remove the read Taking the header information of the second data to obtain the first data;
  • the sending module 505 is configured to send the obtained first data to an interface board corresponding to the interface board identifier.
  • the processing module 502 is further configured to: after the determining module 501 determines an interface board and a logical channel corresponding to the first data to be sent, obtain a remaining resource size of the logical channel; if the remaining resource size And greater than or equal to the length of the first data, determining that the logical channel has the capability of transmitting the first data; when the logical channel has the capability of sending the first data, the remaining resource size of the logical channel Updating to the difference between the remaining resource size and the length of the first data; after the reading module 504 reads the second data from the buffer, updating the remaining resource size of the logical channel corresponding to the buffer to the remaining resource The sum of the size and the length of the first data.
  • the logical channel corresponds to a sending window, and the length of the sending window is the same as the size of the buffer corresponding to the logical channel; wherein the parameters of the sending window include a window starting position, a window ending position, and a window occupying position;
  • the length between the window occupied position and the window ending position is the remaining resource size of the logical channel.
  • the processing module 502 is specifically configured to: use the window occupied position to the window end position The direction moves by the specified length.
  • the processing module 502 is specifically configured to: The direction of the start position is moved by a specified length; or the window start position is moved by a specified length in the direction of the window occupying position, and the window end position is moved by the specified length in the moving direction of the window start position.
  • the specified length is the length of the first data.
  • the sending module 505 is configured to: when the first data is sent to the interface board corresponding to the interface board identifier, to obtain the first used by the interface board to send the first data by using the logical channel a rate; determining, according to the first rate, a second rate used when the first data is sent to the interface board; and sending, according to the second rate, the obtained first data to the interface board corresponding to the interface board identifier; The second rate is less than the first rate.
  • the sending module 505 is configured to: determine, according to the feature data, the interface board according to the second rate used when determining the first data to be sent to the interface board according to the first rate. Forwarding mode, the first data is processed by the forwarding manner, and the third data to be sent at the first rate is obtained; in the process of obtaining the third data, the rate of processing the first data is determined to be the second rate.
  • FIG. 6 For the network device provided in the embodiment of the present application, the hardware architecture of the device is specifically shown in FIG. 6 .
  • a machine readable storage medium 610 and a processor 620 are included, wherein:
  • Machine readable storage medium 610 stores instruction code.
  • Processor 620 in communication with machine readable storage medium 610, reading and executing the instruction code stored in machine readable storage medium 610, implementing the data transfer operations disclosed in the above examples of the present application.
  • a machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and so forth.
  • a machine-readable storage medium can be a volatile memory, a non-volatile memory, or similar storage medium.
  • the machine-readable storage medium may be a RAM (Radom Access Memory), a flash memory, a storage drive (such as a hard disk drive), a solid state drive, any type of storage disk (such as a compact disc, a DVD, etc.), or the like. Storage medium, or a combination thereof.
  • the network device further includes:
  • the first rate limiting device 212 is configured to: determine an interface board and a logical channel corresponding to the first data to be sent; if the logical channel has the capability of sending the first data, add header information to the first data. Obtaining the second data and transmitting the second data to the second rate limiting device 220.
  • the header information includes an interface board identifier of the interface board and a logical channel identifier of the logical channel.
  • the second rate limiting device 220 is configured to: after receiving the second data, acquire a logical channel identifier from the header information of the second data, and store the second data to the logical channel identifier a buffer; reading the second data from the buffer, and obtaining the interface board identifier and the logical channel identifier from the header information of the read second data, removing the header information of the read second data, and obtaining the A data is sent to the corresponding interface board of the interface board identifier.
  • the system, device, module or unit illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product having a certain function.
  • a typical implementation device is a computer, and the specific form of the computer may be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver, and a game control.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • embodiments of the present application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • these computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the instruction means implements the functions specified in one or more blocks of the flowchart or in a flow or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本申请提供一种数据传输方法、装置和网络设备。根据该方法的一个示例，在确定待发送的第一数据对应的接口板和逻辑通道后，若所述逻辑通道具有发送所述第一数据的能力，则为所述第一数据添加接口板标识和逻辑通道标识的头信息，得到第二数据，并将所述第二数据存储到所述逻辑通道对应的缓冲区。然后，在发送所述第二数据时，从所述缓冲区中读取第二数据，并从读取的第二数据的头信息中获取接口板标识和逻辑通道标识，去除读取的第二数据的头信息，得到第一数据，并将得到的第一数据发送给所述接口板标识对应的接口板。

Description

数据传输
相关申请的交叉引用
本专利申请要求于2017年9月27日提交的、申请号为201710889139.X、发明名称为“一种数据传输方法、装置和网络设备”的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。
背景技术
网络设备(如路由器、交换机等)通常包括主控板和接口板。当网络设备构造成集中式时，主控板可以通过高速接口与接口板连接；当网络设备构造成分布式时，该网络设备还包括线卡，类似地，线卡可以通过高速接口与接口板连接。这里的高速接口例如是能够达到GE级别的传输速率的以太接口。通过使用以太接口，可以减少CPU(Central Processing Unit，中央处理器)的占用，提高多核CPU的并发性，且主控板不会成为性能瓶颈。
此外，接口板通过非以太接口(如E1接口、T1接口、异步串口、同步串口、AM(Analog Modem，模拟调制解调器)接口等)与其它设备连接，而非以太接口的传输速率较慢，如100M级别的传输速率。因此，主控板或线卡向接口板发送数据的速率，与接口板向其它设备发送数据的速率严重不匹配。这导致接口板通过以太接口接收到大量数据后，只通过非以太接口发送少量数据，有可能导致丢包。
附图说明
为了更加清楚地说明本申请实施例或者现有技术中的技术方案，下面将对本申请实施例或者现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据本申请实施例的这些附图获得其他的附图。
图1是本申请一种实施方式中的数据传输方法的流程图。
图2是本申请一种实施方式中的网络设备的结构示意图。
图3A和图3B是本申请一种实施方式中的基本信息表的示意图。
图3C-图3F是本申请一种实施方式中的窗口管理的示意图。
图4A和图4B是本申请一种实施方式中的消息格式示意图。
图5是本申请一种实施方式中的数据传输装置的结构图。
图6是本申请一种实施方式中的网络设备的硬件结构图。
具体实施方式
在本申请实施例使用的术语仅仅是出于描述特定实施例的目的，而非限制本申请。本申请和权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其它含义。还应当理解，本文中使用的术语“和/或”是指包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请实施例可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，此外，所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
本申请实施例提出一种数据传输方法，可以应用于网络设备。在本文中，以该网络设备中的主控板和接口板经由高速接口相连为例进行说明，线卡和接口板经由高速接口相连的情况与此类似，不再赘述。其中，网络设备中包括的主控板的数量可以为一个或者多个，接口板的数量可以为一个或者多个。主控板可以通过以太接口、PCIE(Peripheral Component Interconnect Express，高速型外设部件互连标准)、SPI4(Serial Peripheral Interface，串行外设接口)等方式与接口板连接，接口板可以通过E1接口、T1接口、异步串口、同步串口、AM接口等方式与其它设备连接。在通常情况下，主控板与接口板之间的数据传输速率，大于接口板与其它设备之间的数据传输速率。
参见图1所示，为本申请实施例中提出的数据传输方法的流程示意图。该数据传输方法可应用于包括主控板和接口板的网络设备。
步骤101，确定待发送的第一数据对应的接口板和逻辑通道。若该逻辑通道具有发送该第一数据的能力，则为该第一数据添加头信息，得到第二数据，并将该第二数据存储到该逻辑通道对应的缓冲区。其中，该头信息可以包括但不限于该接口板的接口板标识和该逻辑通道的逻辑通道标识。
在一个例子中，针对“确定待发送的第一数据对应的接口板和逻辑通道”的过程，可 以包括但不限于：针对待发送的第一数据，可以通过第一数据的目的地址信息(如目的IP地址和/或目的MAC地址等)查询转发表，得到与该目的地址信息对应的出接口；确定与这个出接口对应的一个接口板和一个逻辑通道，该接口板就是第一数据对应的接口板，该逻辑通道就是第一数据对应的逻辑通道。
在一个例子中，在确定待发送的第一数据对应的接口板和逻辑通道后，还可以判断该逻辑通道是否具有发送该第一数据的能力。如果是，则为该第一数据添加头信息，得到第二数据；如果否，则不发送该第一数据，而是在内存中存储第一数据，等到该逻辑通道具有发送该第一数据的能力时，才从内存中读取第一数据，并为该第一数据添加头信息，得到第二数据。
在一个例子中，为了判断出逻辑通道是否具有发送第一数据的能力，可以采用如下方式：获取逻辑通道的剩余资源大小；若该剩余资源大小大于等于第一数据的长度，则确定该逻辑通道具有发送该第一数据的能力；若该剩余资源大小小于第一数据的长度，则确定该逻辑通道不具有发送该第一数据的能力。
进一步的，若该逻辑通道具有发送该第一数据的能力，则还可以将该逻辑通道的剩余资源大小更新为当前的剩余资源大小与第一数据的长度的差值。
在一个例子中，针对“为第一数据添加头信息，得到第二数据”的过程，可以包括但不限于如下方式：确定该接口板对应的唯一标识(以下又可简称为接口板标识)，并确定该逻辑通道的唯一标识(以下又可简称为逻辑通道标识)。然后，为该第一数据添加头信息，该头信息可以包括但不限于该接口板标识和该逻辑通道标识。而添加了头信息的第一数据，就可以称为第二数据。
在一个例子中，针对“将第二数据存储到该逻辑通道对应的缓冲区”的过程，每个逻辑通道可以对应有一个缓冲区；然而，也可以多个逻辑通道对应同一个缓冲区。因此，在得到第二数据之后，就可以将该第二数据存储到该逻辑通道对应的缓冲区。
步骤102，从缓冲区中读取第二数据，从该第二数据的头信息中获取接口板标识和逻辑通道标识，去除该第二数据的头信息，得到第一数据，并将得到的第一数据发送给该接口板标识对应的接口板。
在一个例子中，在从缓冲区中读取第二数据后，还可以将该缓冲区对应的逻辑通道的剩余资源大小更新为当前的剩余资源大小与第一数据的长度的和。
在一个例子中，为了判断逻辑通道是否具有发送该第一数据的能力，逻辑通道的缓 冲区还可以采用窗口机制实现。例如，逻辑通道可以对应一个发送窗口，该发送窗口的长度与该逻辑通道对应的缓冲区的大小相同。而且，该发送窗口的参数可以包括但不限于窗口起始位置、窗口结束位置、窗口占用位置；该窗口起始位置与该窗口结束位置之间的长度为该发送窗口的长度；该窗口占用位置与该窗口结束位置之间的长度为该逻辑通道的剩余资源大小。
基于此，上述“将逻辑通道的剩余资源大小更新为当前的剩余资源大小与第一数据的长度的差值”的过程，可以包括：将该窗口占用位置向该窗口结束位置的方向移动指定长度。
此外，上述“将缓冲区对应的逻辑通道的剩余资源大小更新为当前的剩余资源大小与第一数据的长度的和”，可以包括但不限于：将该窗口占用位置向该窗口起始位置的方向移动指定长度；或者，将该窗口起始位置向该窗口占用位置的方向移动指定长度，并将该窗口结束位置向该窗口起始位置的移动方向移动指定长度。其中，上述指定长度可以为所述第一数据的长度。
在一个例子中，在从缓冲区中读取第二数据之后，还可以获取该第二数据在该缓冲区中的位置，并根据该第二数据在该缓冲区的位置确定出该发送窗口的窗口起始位置；然后，还可以根据该窗口起始位置的移动长度移动该发送窗口的窗口结束位置。
在一个例子中，由于第二数据的头信息中包括接口板标识和逻辑通道标识，因此，可以从第二数据的头信息中获取接口板标识和逻辑通道标识，并去除该第二数据的头信息，从而得到第一数据。
在一个例子中，针对“将第一数据发送给该接口板标识对应的接口板”的过程，可以包括：获取该接口板通过该逻辑通道发送第一数据时使用的第一速率，根据第一速率确定向该接口板发送第一数据时使用的第二速率；基于第二速率将第一数据发送给该接口板标识对应的接口板。其中，该第二速率小于第一速率。
在一个例子中，针对“根据第一速率确定向该接口板发送第一数据时使用的第二速率”的过程，可以包括但不限于如下方式：根据特征数据确定该接口板的转发方式，并通过转发方式对第一数据进行处理，得到要以所述第一速率发送的第三数据；将处理所述第一数据的速率确定为所述第二速率。
在一个例子中，在“根据特征数据确定该接口板的转发方式”之前，还可以包括以下步骤：可以查询预先配置的基本信息表，得到与该逻辑通道标识对应的特征类型标识， 然后，可以获取与该特征类型标识对应的特征数据。该基本信息表用于记录逻辑通道标识与特征类型标识的对应关系。
基于上述技术方案，本申请实施例中，多个逻辑通道可以共享同一个主控板的处理能力，且可以将数据存储到各逻辑通道对应的缓冲区，并可以通过逻辑通道发送缓冲区中的数据，可以解决主控板与接口板速率不匹配的问题，避免接口板的丢包问题，满足QOS(Quality Of Service，服务质量)需求。
以下结合具体的应用场景，对上述方案进行详细说明。参见图2所示，为本应用场景的组网示意图，图2中以主控板210、接口板231、接口板232为例进行说明。然而，接口板的数量也可以更多。在图2中，第一限速装置212是主控板210中新增加的单元，且第二限速装置220也是新增加的单元。
第二限速装置220可以部署在主控板内，每个主控板210部署一个第二限速装置220；或者，第二限速装置220也可以部署在接口板231、232内，每个接口板231、232部署一个第二限速装置220；或者，第二限速装置220也可以单独部署，而不是部署在主控板210或者接口板231、232内，图2中以单独部署一个第二限速装置220为例进行说明。
其中，第一限速装置212是主控板210中新增加的单元，可以是一个硬件装置，对此类型不做限制。若第二限速装置220是主控板210或者接口板231、232中新增加的单元，则第二限速装置220可以是一个硬件装置，若第二限速装置220单独部署，则第二限速装置220可以是独立的单板，对此类型不做限制。
主控板210可以通过以太接口、PCIE，SPI4等方式与第二限速装置220连接，且第二限速装置220可以通过以太接口、PCIE，SPI4等方式与接口板231/接口板232连接。在图2中，主控板210与第二限速装置220是以太接口连接，而以太控制器213用于实现以太接口连接。此外，接口板231/接口板232可以通过E1接口、T1接口、异步串口、同步串口、AM接口等方式与其它设备连接。
主控板210与第二限速装置220的连接方式，与第二限速装置220与接口板231/接口板232的连接方式可以相同。这样，主控板210与第二限速装置220的最大数据传输速率，与第二限速装置220与接口板231/接口板232的最大数据传输速率相同，均大于接口板231/接口板232与其它设备的最大数据传输速率。
参见图2所示，在主控板210中，处理器211(例如，中央处理单元(CPU))可 以通过总线与第一限速装置212连接，第一限速装置212可以通过总线与以太控制器213连接。
参见图2所示，主控板210还可以创建逻辑通道，该逻辑通道是数据的传输通道，例如，当数据的走向是处理器211、第一限速装置212、以太控制器213、第二限速装置220、接口板231/接口板232上的出接口时，则逻辑通道可以是一个数据传输通道“处理器211→第一限速装置212→以太控制器213→第二限速装置220→接口板231/接口板232上的出接口”，即逻辑通道会经过上述各器件。
在图2中，虽然逻辑通道标注在接口板231、232上，但是，并不表示逻辑通道位于该接口板231、232，只是该逻辑通道的出接口位于该接口板231、232。逻辑通道的出接口可以是E1接口、T1接口、异步串口、同步串口、AM接口等，对此不做限制。
其中，逻辑通道的出接口可以是逻辑接口，也可以是物理接口。不同逻辑通道可以占用不同物理接口，不同逻辑通道也可以共用相同物理接口，一个逻辑通道也可以占用多个物理接口。例如，逻辑通道241占用物理接口1和物理接口2，逻辑通道242占用物理接口3，逻辑通道243和逻辑通道244共用物理接口4。即，逻辑通道241的数据传输速率是物理接口1和物理接口2的数据传输速率之和，逻辑通道242的数据传输速率是物理接口3的数据传输速率，逻辑通道243和逻辑通道244的数据传输速率之和是物理接口4的数据传输速率。
主控板210在创建逻辑通道的过程中，还可以为每个逻辑通道分配缓冲区，并建立逻辑通道与缓冲区的对应关系。参见图2所示，逻辑通道241对应缓冲区251，逻辑通道242对应缓冲区252，逻辑通道243对应缓冲区253，逻辑通道244对应缓冲区254。需要通过该逻辑通道241发送的数据会先缓存到缓冲区251，然后从缓冲区251中读取数据，并最终通过该逻辑通道241发送该数据。需要通过该逻辑通道242发送的数据会先缓存到缓冲区252，然后从缓冲区252中读取数据，并最终通过该逻辑通道242发送该数据。以此类推。
在创建逻辑通道的过程中，主控板210可以根据需要创建多个逻辑通道，对此逻辑通道的数量不做限制，逻辑通道可以是针对“处理器211→第一限速装置212→以太控制器213→第二限速装置220→接口板231/接口板232上的出接口”的一个逻辑通道，对此不做限制，只要逻辑通道能够对应一个出接口(位于接口板)即可，而通过逻辑通道发送数据的过程，就是通过该出接口发送数据的过程。
在逻辑通道创建完成后，主控板210可以为逻辑通道分配缓冲区，并为逻辑通道配置一个发送窗口。该缓冲区的大小与逻辑通道对应出接口的数据传输速率相关，且该发送窗口的长度与该逻辑通道对应的缓冲区的大小相同。例如，当出接口的数据传输速率为56Kbits/s时，则缓冲区的大小和发送窗口的长度均为56K。
第一限速装置212可以包括每个逻辑通道的基本信息表，且逻辑通道的基本信息可以包括但不限于：接口板标识、逻辑通道标识、接口类型、窗口位置信息等。每个逻辑通道对应一个基本信息表，该基本信息表的内容可以参见图3A或者图3B所示，图3A为初始时刻的基本信息表的示例，而图3B为某时刻的基本信息表的示例。
其中，接口板标识DownPort为主控板上与接口板连接的下行端口的标识，其是主控板的下行端口号。该下行端口号在系统中统一编号。根据此下行端口号，主控板可以知道通过哪个下行端口将数据发送给接口板。
逻辑通道标识ChID为逻辑通道的唯一标识。例如，逻辑通道标识可以由接口板所在槽位号(SlotID)、端口号(PortID)、子通道号(SubChanID)拼接而成。槽位号占最高4位，可以支持16个槽位；端口号占中间6位，可以支持64个端口；子通道号占最后12位，最多支持4096个子通道。当然，槽位号、端口号、子通道号拼接成的逻辑通道标识只是一个示例，对此不做限制。
接口类型WanType是逻辑通道对应接口的类型，如POS、CE1、CPOS、AsySer(异步串口)、E1接口、T1接口、AM接口等，对此接口类型不做限制。
窗口位置信息可以包括发送窗口的长度WinSize、窗口的左边缘LeftEdge、窗口的右边缘RightEdge、当前发送数据的边缘TxEdge。窗口的左边缘LeftEdge也可以称为窗口起始位置。窗口的右边缘RightEdge也可以称为窗口结束位置。发送窗口的长度WinSize可为，如128K字节(即0x20000)，此值表明允许的最大长度。发送窗口的长度WinSize与逻辑通道对应的缓冲区的大小相同，窗口的左边缘LeftEdge与窗口的右边缘RightEdge之间的长度就是发送窗口的长度WinSize。当前发送数据的边缘TxEdge也可以称为窗口占用位置，下一次发送数据时，从此处开始累加。例如，假设窗口的左边缘LeftEdge为0，第一个数据的长度为64，发送第一个数据后，当前发送数据的边缘TxEdge为64；假设第二个数据的长度为304，发送第二个数据后，当前发送数据的边缘TxEdge为368(64+304)，以此类推；当前发送数据的边缘TxEdge位于窗口的左边缘LeftEdge和窗口的右边缘RightEdge之间时，表明逻辑通道具有发送数据的能力，当前发送数据的边缘TxEdge超过RightEdge时，表明逻辑通道不具有发送数据的能力。
第二限速装置220可以包括每个逻辑通道的基本信息表，且逻辑通道的基本信息可以包括但不限于：接口板标识、逻辑通道标识、接口类型、窗口位置信息、特征类型标识等。且每个逻辑通道对应一个基本信息表。第二限速装置220的基本信息表与第一限速装置212的基本信息表类似，不同之处在于：第二限速装置220的基本信息表多了特征类型标识，该特征类型标识可以为FeatureID，用于索引特征表，与特征表的FeatureID对应。对于该基本信息表的其它内容，在此不再赘述。
在上述应用场景下，本申请实施例中提出的数据传输方法，可以包括：
步骤a、第一限速装置212在接收到待发送的第一数据后，确定该第一数据对应的接口板和逻辑通道。具体的，可以通过第一数据的目的地址信息(如目的IP地址和/或目的MAC地址等)查询转发表，得到与该目的地址信息对应的出接口，而这个出接口就对应一个接口板和一个逻辑通道，该接口板就是第一数据对应的接口板，该逻辑通道就是第一数据对应的逻辑通道。当然，接口板和逻辑通道的信息也可以是处理器211通知的，对此确定方式不做限制。
步骤b、第一限速装置212判断该逻辑通道是否具有发送第一数据的能力，如果是，则执行步骤c；如果否，则不发送第一数据，而是在内存中存储第一数据，等到该逻辑通道具有发送第一数据的能力时，再执行步骤c。
在发送数据时，第一限速装置212可以根据基本信息表中的窗口位置信息和第一数据的长度，判断逻辑通道是否具有发送第一数据的能力。例如，若当前发送数据的边缘TxEdge向右移动第一数据的长度后，当前发送数据的边缘TxEdge仍然位于窗口的左边缘LeftEdge和窗口的右边缘RightEdge之间时，表明逻辑通道具有发送第一数据的能力；若当前发送数据的边缘TxEdge向右移动第一数据的长度后，当前发送数据的边缘TxEdge超过窗口的右边缘RightEdge时，表明逻辑通道不具有发送第一数据的能力。
进一步的，在逻辑通道具有发送第一数据的能力时，第一限速装置212还可以根据第一数据的长度和发送窗口中当前发送数据的边缘TxEdge的位置，调整当前发送数据的边缘TxEdge的位置。
如图3C所示，在初始化时，窗口的左边缘LeftEdge和当前发送数据的边缘TxEdge均为0。如图3D所示，当发送了10K字节的数据后，当前发送数据的边缘TxEdge变为10K。如图3E所示，当发送了20K字节的数据后，当前发送数据的边缘TxEdge变为20K。当接收到数据发送完成消息后，若数据发送完成消息表明第二限速装置220已 经从缓冲区中读取12K字节的数据，则向右滑动窗口的左边缘LeftEdge如12K，向右滑动窗口的右边缘RightEdge如12K，滑动后的示意图如图3F所示。
参见图4A所示，为数据发送完成消息的示意图，当接收到数据发送完成消息后，若数据发送完成消息中的当前发送数据的边缘TxEdge位于窗口的左边缘LeftEdge与窗口的右边缘RightEdge之间，则根据数据发送完成消息中的当前发送数据的边缘TxEdge滑动窗口，例如，将窗口中的左边缘LeftEdge向右移动至数据发送完成消息中的当前发送数据的边缘TxEdge处，并将窗口中的右边缘RightEdge相应向右滑动，滑动后的左边缘LeftEdge与右边缘RightEdge之间的长度是发送窗口的当前长度WinSize。若数据发送完成消息中的当前发送数据的边缘TxEdge没有位于窗口的左边缘LeftEdge与窗口的右边缘RightEdge之间，则丢弃该数据发送完成消息，不再滑动窗口。
即使第一限速装置212向第二限速装置220发送数据时有数据发生丢失，和/或，第二限速装置220向第一限速装置212发送数据发送完成消息时有数据发送完成消息发生丢失，只要在后续过程中，有数据成功发送且相应的数据发送完成消息也成功发送，窗口就可以正确滑动。这样，不会导致发送资源的丢失，避免丢包导致发送停止。例如，由于第N个数据的窗口占用位置隐含了第N-1个数据的长度信息，当第N-1个数据丢失时，若接收到针对第N个数据的数据发送完成消息，则根据该数据发送完成消息中的当前发送数据的边缘TxEdge滑动窗口时，不仅回收了第N个数据的发送资源，同时，也回收了第N-1个数据的发送资源。因此，即使数据发生丢失，和/或，数据完成消息发生丢失，也可以正确的回收资源。
步骤c、第一限速装置212为第一数据添加头信息，得到第二数据，将第二数据发送以太控制器213，以太控制器213将第二数据发送给第二限速装置220。
具体的，如果逻辑通道具有发送第一数据的能力，则第一限速装置212可以为第一数据添加头信息，得到修改后的数据，这个数据就是第二数据。如图4B所示，为第二数据的示意图。然后，可以将第二数据发送给以太控制器213，由以太控制器213将第二数据发送给第二限速装置220。
第一限速装置212在为第一数据添加头信息的过程中，该头信息可以包括但不限于如下内容：接口板标识、逻辑通道标识、接口类型、报文类型、窗口发送边缘、有效载荷长度。其中，第一个数据包的窗口占用位置，可以为当前发送数据的数据包长度；第二个数据包的窗口占用位置，可以为第一个数据包的窗口占用位置累加第二个数据包的长度；第三个数据包的窗口占用位置，可以为第二个数据包的窗口占用位置累加第三个 数据包的长度；以此类推。
第一限速装置212将第二数据发送给以太控制器213之后，还可以更新逻辑通道对应的窗口信息，例如，将当前发送数据的边缘TxEdge向右移动第一数据的长度。
步骤d、第二限速装置220在接收到第二数据后，从第二数据的头信息中解析出逻辑通道标识，并将该第二数据缓存到该逻辑通道标识对应的缓冲区。
例如，假设第二限速装置220从第二数据的头信息中解析出的逻辑通道标识为逻辑通道241，则可以将第二数据缓存到逻辑通道241对应的缓冲区251中。
步骤e、在需要发送第二数据时，第二限速装置220从逻辑通道对应的缓冲区中读取第二数据，从第二数据的头信息获取接口板标识和逻辑通道标识，去除第二数据的头信息，得到第一数据，并将第一数据发送给该接口板标识对应的接口板。此外，还可以通知该接口板通过该逻辑通道标识对应的逻辑通道发送第一数据，以使该接口板通过该逻辑通道标识对应的逻辑通道发送第一数据。
例如，第二限速装置220可以从缓冲区251读取第二数据，并从该第二数据的头信息获取接口板231的标识和逻辑通道241的标识，然后，去除该第二数据的头信息，得到第一数据，将该第一数据发送给接口板231，并通知接口板231通过逻辑通道241发送第一数据。
其中，在将第一数据发送给接口板后，为了使接口板能够通过逻辑通道发送第一数据，则还需要将逻辑通道的标识通知给接口板，对此通知机制不做限制。例如，第二限速装置220可以将逻辑通道标识发送给接口板，以使接口板通过该逻辑通道标识对应的逻辑通道发送第一数据。或者，第二限速装置220可以通过逻辑通道标识对应的逻辑通道，将第一数据发送给接口板，接口板通过该逻辑通道接收到第一数据后，就可以通过该逻辑通道发送第一数据。
第二限速装置220在将第一数据发送给接口板的过程中，可以先获取该接口板通过该逻辑通道发送第一数据时使用的第一速率，根据第一速率确定向该接口板发送第一数据时使用的第二速率，基于第二速率将第一数据发送给该接口板。进一步的，在“根据第一速率确定向该接口板发送第一数据时使用的第二速率”的过程中，第二限速装置220可以根据特征数据确定接口板的转发方式，并通过所述转发方式对第一数据进行处理，得到要由接口板以第一速率发送的第三数据；并将在得到第三数据的过程中，处理第一数据的速率确定为第二速率。该第二速率小于第一速率。
其中，第二限速装置220还可以存储特征表，该特征表用于记录数据流特征，该数据流特征可以包括特征类型标识(FeatureID)和特征数据。其中，该特征类型标识用于表示本类特征，可以根据特征类型标识查询到特征数据。
此外，该特征数据可以包括但不限于以下内容之一或者任意组合：通道速率(Speed)，如56Kbits/s、64Kbits/s等；帧间隔(IFG)，如帧间隔之间插入的填充字符数量，该帧间隔是可以根据经验进行配置的；向物理层芯片发送数据的块大小BlockLen；向物理层芯片发送数据的提前量PreTxLen。
第二限速装置220可以基于第二数据的头信息中的逻辑通道标识，查询基本信息表，得到与该逻辑通道标识对应的特征类型标识。然后，可以通过该特征类型标识查询特征表，得到与该特征类型标识对应的特征数据。在此基础上，第二限速装置220可以基于上述特征数据确定接口板的转发方式。
其中，转发方式是接口板对外发送数据时使用的转发方式。不同协议对应的转发方式可以不同或者相同，这个转发方式与协议类型有关。例如，针对HDLC(High-level Data Link Control，高级数据链路控制协议)，由于HDLC数据帧之间由标志序列分隔，二进制为01111110，在一串数据比特中，可能产生和标志序列相同的比特组合。为了防止这种情况产生，保证对数据的透明传输，则转发方式可以是：采用比特填充技术，在连续5个“1”后面插入一个“0”，保证数据的透明传输。当然，转发方式也可以是其它情况，对此转发方式不做限制。
在得到接口板的转发方式后，第二限速装置220可以根据该转发方式进行模拟发送。具体的，通过转发方式对第一数据进行处理，得到要以第一速率发送的第三数据；并将在得到第三数据的过程中，处理第一数据的速率确定为第二速率。其中，第一速率是接口板实际发送数据的速率，第二速率是第二限速装置220实际发送数据的速率。此外，第二限速装置220根据该转发方式进行模拟发送的过程，是实时进行的。
其中，第二限速装置220采用模拟发送的原因是：假设接口板通过逻辑通道发送数据时使用的第一速率为56Kbits/s，则：若向接口板提供数据的速率为56Kbits/s，则接口板在发送数据时，先采用上述转发方式对数据进行处理，如采用比特填充技术在数据中添加额外的信息。这样，接口板最终发送的数据会大于56Kbits/s，如60Kbits/s，也就是说，接口板发送的数据发生溢出。由于接口板无法发出60Kbits/s的数据，只能发出56Kbits/s的数据，造成部分数据丢失。
由此，第二限速装置220可先获取接口板通过逻辑通道发送数据时的第一速率，如56Kbits/s。然后，从缓冲区中读取数据，并通过上述转发方式对数据进行处理，如采用比特填充技术在数据中添加信息。在该处理过程中，确定在产生以56Kbits/s发送的数据时，从缓冲区中读取数据的速率，这个读取数据的速率是第二速率，如52Kbits/s，因此第二限速装置220向接口板提供数据的速率为52Kbits/s。
综上所述，向接口板提供数据的速率为52Kbits/s，而不是56Kbits/s。接口板在发送数据时，先采用上述转发方式对数据进行处理，如采用比特填充技术在数据中添加信息，这样，接口板最终发送的数据是56Kbits/s，数据不会溢出，不会造成数据丢失，提高接口板的效率，提高数据传输质量，实现QOS应用，避免数据丢失导致的语音失真，图像不清晰等问题。
其中，针对“获取接口板通过逻辑通道发送数据时使用的第一速率”的过程，可以从特征数据中获取到该第一速率，如特征数据中的通道速率(Speed)。
其中，针对“根据特征数据确定接口板的转发方式，并通过该转发方式对数据进行处理”的过程，可以包括但不限于如下方式：若特征数据中包括接口类型(如在特征表中记录接口类型)，则可以基于特征数据确定接口板的转发方式，并通过该转发方式对数据进行处理；若特征数据中不包括接口类型(如在特征表中没有记录接口类型)，则可以基于特征数据、接口类型(从数据的头信息中获得)确定接口板的转发方式，并通过该转发方式对数据进行处理。例如，可以采用帧间隔(IFG)、BlockLen、PreTxLen、接口类型等参数确定接口板的转发方式，并通过该转发方式对数据进行处理，对此过程不做限制。
步骤f、第二限速装置220从逻辑通道对应的缓冲区中读取第二数据后，还可以向第一限速装置212发送数据发送完成消息，该数据发送完成消息可以携带第一数据的长度(即将第二数据去除头信息后的第一数据的长度)，且该数据发送完成消息还可以携带上述头信息(如接口板标识、逻辑通道标识、接口类型、报文类型、窗口发送边缘、有效载荷长度等)，该头信息与第二数据的头信息相同。
其中，数据发送完成消息的头信息中的当前发送数据的边缘TxEdge，可以表明已经从缓冲区中读取到与该当前发送数据的边缘TxEdge对应的数据。
步骤g、第一限速装置212在接收到数据发送完成消息后，将该逻辑通道标识对应的逻辑通道的剩余资源大小更新为当前的剩余资源大小与第一数据的长度的和。例如， 将窗口占用位置向窗口起始位置的方向移动指定长度；或者，将窗口起始位置向窗口占用位置的方向移动指定长度，并将窗口结束位置向窗口起始位置的移动方向移动指定长度。其中，上述指定长度为第一数据的长度。
或者，还可以根据第二数据在缓冲区中的位置确定出该发送窗口中的窗口起始位置，并根据该窗口起始位置的移动长度移动该发送窗口的窗口结束位置。
基于上述技术方案，本申请实施例中，多个逻辑通道可以共享同一个主控板的处理能力，且可以将数据存储到各逻辑通道对应的缓冲区，并通过逻辑通道发送缓冲区中的数据，可以解决主控板与接口板速率不匹配的问题，避免接口板的丢包问题，满足QOS需求。而且，可以实现接口板的精确限速，提高主控板的性能。例如，逻辑通道241的数据传输速率是56Kbits/s，逻辑通道242的数据传输速率是56Kbits/s，逻辑通道243的数据传输速率是56Kbits/s，逻辑通道244的数据传输速率是56Kbits/s，那么，以太控制器213的数据传输速率就可以是224Kbits/s(＝4*56Kbits/s)，而不是某个逻辑通道对应的56Kbits/s。第二限速装置220可以将56Kbits/s的数据存储到缓冲区251，将56Kbits/s的数据存储到缓冲区252，将56Kbits/s的数据存储到缓冲区253，将56Kbits/s的数据存储到缓冲区254。在数据发送过程中，第二限速装置220可以将56Kbits/s的数据发送给逻辑通道241，以使逻辑通道241发送56Kbits/s的数据，将56Kbits/s的数据发送给逻辑通道242，以使逻辑通道242发送56Kbits/s的数据，将56Kbits/s的数据发送给逻辑通道243，以使逻辑通道243发送56Kbits/s的数据，将56Kbits/s的数据发送给逻辑通道244，以使逻辑通道244发送56Kbits/s的数据。
基于与上述方法同样的申请构思，本申请实施例中还提出一种数据传输装置，可以应用于网络设备，如图5所示，为该装置的结构图，该装置可以包括：
确定模块501，用于确定待发送的第一数据对应的接口板和逻辑通道；
处理模块502，用于当所述逻辑通道具有发送所述第一数据的能力时，则为所述第一数据添加头信息，得到第二数据；其中，所述头信息包括所述接口板的接口板标识和所述逻辑通道的逻辑通道标识；
存储模块503，用于将所述第二数据存储到所述逻辑通道对应的缓冲区；
读取模块504，用于从所述缓冲区中读取所述第二数据，并从读取的所述第二数据的头信息中获取所述接口板标识和所述逻辑通道标识，去除读取的所述第二数据的头信息，得到所述第一数据；
发送模块505，用于将得到的所述第一数据发送给接口板标识对应的接口板。
所述处理模块502，还用于：在所述确定模块501确定待发送的所述第一数据对应的接口板和逻辑通道后，获取所述逻辑通道的剩余资源大小；若所述剩余资源大小大于等于所述第一数据的长度，确定所述逻辑通道具有发送所述第一数据的能力；当所述逻辑通道具有发送所述第一数据的能力时，将所述逻辑通道的剩余资源大小更新为该剩余资源大小与第一数据的长度的差值；在读取模块504从缓冲区中读取第二数据后，将所述缓冲区对应的逻辑通道的剩余资源大小更新为该剩余资源大小与第一数据的长度的和。
所述逻辑通道对应一个发送窗口，所述发送窗口的长度与所述逻辑通道对应的缓冲区的大小相同；其中，所述发送窗口的参数包括窗口起始位置、窗口结束位置、窗口占用位置；所述窗口占用位置与窗口结束位置之间的长度为所述逻辑通道的剩余资源大小。在将所述逻辑通道的剩余资源大小更新为该剩余资源大小与第一数据的长度的差值的过程中，所述处理模块502具体用于：将所述窗口占用位置向所述窗口结束位置的方向移动指定长度。在将所述缓冲区对应的逻辑通道的剩余资源大小更新为该剩余资源大小与第一数据的长度的和的过程中，所述处理模块502具体用于：将所述窗口占用位置向窗口起始位置的方向移动指定长度；或者，将所述窗口起始位置向窗口占用位置的方向移动指定长度，并将窗口结束位置向所述窗口起始位置的移动方向移动所述指定长度。其中，所述指定长度为所述第一数据的长度。
所述发送模块505，在将得到的第一数据发送给所述接口板标识对应的接口板的过程中，具体用于：获取所述接口板通过所述逻辑通道发送第一数据时使用的第一速率；根据所述第一速率确定向所述接口板发送第一数据时使用的第二速率；基于所述第二速率将得到的第一数据发送给所述接口板标识对应的接口板；其中，所述第二速率小于所述第一速率。
在一个例子中，所述发送模块505，在根据所述第一速率确定向所述接口板发送第一数据时使用的第二速率的过程中，具体用于：根据特征数据确定所述接口板的转发方式，通过所述转发方式对所述第一数据进行处理，得到要以第一速率发送的第三数据；将在得到第三数据的过程中，处理第一数据的速率确定为第二速率。
本申请实施例中提供的网络设备，从硬件层面而言，其硬件架构示意图具体可以参见图6所示。包括：机器可读存储介质610和处理器620，其中：
机器可读存储介质610：存储指令代码。
处理器620：与机器可读存储介质610通信，读取和执行机器可读存储介质610中存储的所述指令代码，实现本申请上述示例公开的数据传输操作。
这里，机器可读存储介质是可以是任何电子、磁性、光学或其它物理存储装置，可以包含或存储信息，如可执行指令、数据，等等。例如，机器可读存储介质可以是易失存储器、非易失性存储器或者类似的存储介质。具体地，机器可读存储介质可以是RAM(Radom Access Memory，随机存取存储器)、闪存、存储驱动器(如硬盘驱动器)、固态硬盘、任何类型的存储盘(如光盘、DVD等)，或者类似的存储介质，或者它们的组合。
本申请实施例中提供的网络设备，所述网络设备还包括：
第一限速装置212，用于：确定待发送的第一数据对应的接口板和逻辑通道；若所述逻辑通道具有发送所述第一数据的能力，则为所述第一数据添加头信息，得到第二数据，并将所述第二数据发送给第二限速装置220。其中，所述头信息包括所述接口板的接口板标识和所述逻辑通道的逻辑通道标识。
第二限速装置220，用于：在接收到所述第二数据后，从所述第二数据的头信息中获取逻辑通道标识，并将所述第二数据存储到所述逻辑通道标识对应的缓冲区；从所述缓冲区中读取第二数据，并从读取的第二数据的头信息中获取接口板标识和逻辑通道标识，去除读取的第二数据的头信息，得到第一数据，并将得到的第一数据发送给所述接口板标识对应的接口板。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本申请时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请实施例可采用在一个或多个其中包含有计算机可用 程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可以由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其它可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其它可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
而且，这些计算机程序指令也可以存储在能引导计算机或其它可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或者多个流程和/或方框图一个方框或者多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其它可编程数据处理设备上，使得在计算机或者其它可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其它可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (15)

  1. 一种数据传输方法，包括：
    确定待发送的第一数据对应的接口板和逻辑通道；
    若所述逻辑通道具有发送所述第一数据的能力，则
    为所述第一数据添加头信息，得到第二数据，并
    将所述第二数据存储到所述逻辑通道对应的缓冲区；其中，所述头信息包括所述接口板的接口板标识和所述逻辑通道的逻辑通道标识；
    从所述缓冲区中读取所述第二数据，并
    从读取的所述第二数据的头信息中获取所述接口板标识和所述逻辑通道标识，
    去除读取的所述第二数据的头信息，得到所述第一数据，并
    将得到的所述第一数据发送给所述接口板标识对应的接口板。
  2. 根据权利要求1所述的方法，其特征在于，确定待发送的所述第一数据对应的接口板和逻辑通道之后，还包括：
    获取所述逻辑通道的剩余资源大小；
    若所述剩余资源大小大于等于第一数据的长度，则确定所述逻辑通道具有发送所述第一数据的能力；
    若所述逻辑通道具有发送所述第一数据的能力，则将所述逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的差值。
  3. 根据权利要求2所述的方法，其特征在于，从所述缓冲区中读取所述第二数据之后，还包括：
    将所述缓冲区对应的逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的和。
  4. 根据权利要求3所述的方法，其特征在于，
    所述逻辑通道对应一个发送窗口，
    所述发送窗口的长度与所述逻辑通道对应的缓冲区的大小相同；
    所述发送窗口的参数包括窗口起始位置、窗口结束位置、窗口占用位置；
    所述窗口占用位置与窗口结束位置之间的长度为所述逻辑通道的剩余资源大小；
    将所述逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的差值，包括：
    将所述逻辑通道对应的发送窗口的窗口占用位置向所述发送窗口的窗口结束位置的方向移动指定长度；其中，所述指定长度为所述第一数据的长度。
  5. 根据权利要求4所述的方法，其特征在于，将所述缓冲区对应的逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的和，包括：
    将所述逻辑通道对应的发送窗口的窗口占用位置向所述发送窗口的窗口起始位置的方向移动所述指定长度；或者，
    将所述发送窗口的所述窗口起始位置向所述发送窗口的窗口占用位置的方向移动所述指定长度，并将所述发送窗口的窗口结束位置向所述发送窗口的窗口起始位置的移动方向移动所述指定长度。
  6. 根据权利要求1所述的方法，其特征在于，将得到的所述第一数据发送给所述接口板标识对应的接口板的过程，包括：
    获取所述接口板通过所述逻辑通道发送所述第一数据时使用的第一速率；
    根据所述第一速率确定向所述接口板发送所述第一数据时使用的第二速率；
    基于所述第二速率将得到的所述第一数据发送给所述接口板标识对应的接口板；
    其中，所述第二速率小于所述第一速率。
  7. 根据权利要求6所述的方法，其特征在于，根据所述第一速率确定向所述接口板发送所述第一数据时使用的第二速率的过程，具体包括：
    根据特征数据确定所述接口板的转发方式，
    通过所述转发方式对所述第一数据进行处理，得到要以所述第一速率发送的第三数据；
    将在得到所述第三数据的过程中，处理所述第一数据的速率确定为所述第二速率。
  8. 一种数据传输装置，包括：
    确定模块，用于确定待发送的第一数据对应的接口板和逻辑通道；
    处理模块，用于当所述逻辑通道具有发送所述第一数据的能力时，则为所述第一数据添加头信息，得到第二数据；其中，所述头信息包括所述接口板的接口板标识和所述逻辑通道的逻辑通道标识；
    存储模块，用于将所述第二数据存储到所述逻辑通道对应的缓冲区；
    读取模块，用于从所述缓冲区中读取所述第二数据，并从读取的所述第二数据的头信息中获取所述接口板标识和所述逻辑通道标识，去除读取的所述第二数据的头信息，得到所述第一数据；
    发送模块，用于将得到的所述第一数据发送给所述接口板标识对应的接口板。
  9. 根据权利要求8所述的装置，其特征在于，所述处理模块，还用于：
    在所述确定模块确定待发送的所述第一数据对应的接口板和逻辑通道后，获取所述 逻辑通道的剩余资源大小；
    若所述剩余资源大小大于等于所述第一数据的长度，确定所述逻辑通道具有发送所述第一数据的能力；
    当所述逻辑通道具有发送所述第一数据的能力时，将所述逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的差值。
  10. 根据权利要求9所述的装置，其特征在于，所述处理模块还用于：
    在所述读取模块从所述缓冲区中读取所述第二数据后，将所述缓冲区对应的逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的和。
  11. 根据权利要求10所述的装置，其特征在于，
    所述逻辑通道对应一个发送窗口，
    所述发送窗口的长度与所述逻辑通道对应的缓冲区的大小相同；
    所述发送窗口的参数包括窗口起始位置、窗口结束位置、窗口占用位置；
    所述窗口占用位置与窗口结束位置之间的长度为所述逻辑通道的剩余资源大小；
    在将所述逻辑通道的剩余资源大小更新为所述剩余资源大小与第一数据的长度的差值的过程中，所述处理模块具体用于：将所述逻辑通道对应的发送窗口的窗口占用位置向所述发送窗口的窗口结束位置的方向移动指定长度；其中，所述指定长度为所述第一数据的长度。
  12. 根据权利要求11所述的装置，其特征在于，在将所述缓冲区对应的逻辑通道的剩余资源大小更新为所述剩余资源大小与所述第一数据的长度的和的过程中，所述处理模块具体用于：
    将所述逻辑通道对应的发送窗口的窗口占用位置向所述发送窗口的窗口起始位置的方向移动所述指定长度；或者，
    将所述发送窗口的窗口起始位置向所述发送窗口的窗口占用位置的方向移动所述指定长度，并将所述发送窗口的窗口结束位置向所述窗口起始位置的移动方向移动所述指定长度。
  13. 根据权利要求8所述的装置，其特征在于，在将得到的第一数据发送给所述接口板标识对应的接口板的过程中，所述发送模块具体用于：
    获取所述接口板通过所述逻辑通道发送所述第一数据时使用的第一速率；
    根据所述第一速率确定向所述接口板发送所述第一数据时使用的第二速率；
    基于所述第二速率将得到的所述第一数据发送给所述接口板标识对应的接口板；
    其中，所述第二速率小于所述第一速率。
  14. 根据权利要求13所述的装置，其特征在于，在根据所述第一速率确定向所述接口板发送第一数据时使用的第二速率的过程中，所述发送模块具体用于：
    根据特征数据确定所述接口板的转发方式，
    通过所述转发方式对所述第一数据进行处理，得到要以所述第一速率发送的第三数据；
    将在得到所述第三数据的过程中，处理所述第一数据的速率确定为所述第二速率。
  15. 一种网络设备，包括：
    第一限速装置，用于
    确定待发送的第一数据对应的接口板和逻辑通道；
    若所述逻辑通道具有发送所述第一数据的能力，则为所述第一数据添加头信息，得到第二数据；其中，所述头信息包括所述接口板的接口板标识和所述逻辑通道的逻辑通道标识；
    第二限速装置，用于在接收到所述第一限速装置发送的所述第二数据后，
    从所述第二数据的头信息中获取所述逻辑通道标识，
    将所述第二数据存储到所述逻辑通道标识对应的缓冲区；
    从所述缓冲区中读所述取第二数据，
    从读取的所述第二数据的头信息中获取接口板标识和逻辑通道标识，去除读取的所述第二数据的头信息，得到所述第一数据，并
    将得到的所述第一数据发送给所述接口板标识对应的接口板。
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