WO2019062264A1 - 波谷控制电路及波谷控制方法 - Google Patents

波谷控制电路及波谷控制方法 Download PDF

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Publication number
WO2019062264A1
WO2019062264A1 PCT/CN2018/094820 CN2018094820W WO2019062264A1 WO 2019062264 A1 WO2019062264 A1 WO 2019062264A1 CN 2018094820 W CN2018094820 W CN 2018094820W WO 2019062264 A1 WO2019062264 A1 WO 2019062264A1
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Prior art keywords
voltage
circuit
pin
valley
input voltage
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PCT/CN2018/094820
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English (en)
French (fr)
Inventor
赵永宁
唐盛斌
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广州金升阳科技有限公司
深圳南云微电子有限公司
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Publication of WO2019062264A1 publication Critical patent/WO2019062264A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the field of switching converters, a flyback converter operating in a discontinuous mode, and particularly to a valley control method and a valley control circuit of a flyback converter for DCDC applications.
  • the switching power supply scheme used in the micro power section is mainly a flyback circuit because it has a series of features such as low cost, simple and reliable circuit, and mature application.
  • the flyback circuit operates in two modes, one is continuous mode (CCM) and the other is discontinuous mode (DCM).
  • CCM continuous mode
  • DCM discontinuous mode
  • the continuous mode is used in the larger power section, because the peak current in this mode is smaller, the current effective value is smaller, and the conduction loss is larger in the high power case, so the current can be reduced effectively. The value can be considerably reduced to achieve better efficiency.
  • CCM continuous mode
  • DCM discontinuous mode
  • the continuous mode is used in the larger power section, because the peak current in this mode is smaller, the current effective value is smaller, and the conduction loss is larger in the high power case, so the current can be reduced effectively. The value can be considerably reduced to achieve better efficiency.
  • disadvantages such as high turn-on loss, large reverse recovery current of the secondary side rectifier diode, and poor synchronous rectification
  • the current itself is small, so the proportion of conduction loss is small, so that the benefit of the flyback circuit continuing to operate in continuous mode is not obvious, so the intermittent operation mode is selected in many occasions.
  • the discontinuous mode the turn-on voltage of the MOS transistor is relatively low, the EMI is good, the secondary side rectifier diode has no reverse recovery loss and voltage stress problem, the synchronous rectification detection is easy to do, the loop is easy to compensate, and has many advantages.
  • the prior art has many circuits for detecting the MOSFET drain voltage resonance in the discontinuous mode, so that it is turned on at the valley every time to reach the lowest turn-on voltage.
  • the valley control is to detect and determine the exact time of the valley and select a certain valley according to the most favorable conditions for the circuit and then turn on the switch.
  • a switching tube control scheme which can reduce the turn-on voltage of the main switch tube and reduce the turn-on loss, minimize the EMI noise, optimize the operating frequency range, and reasonably control the switching loss and simplify EMI circuit design.
  • the flyback converter includes a transformer T1, a primary side circuit, a secondary side circuit and a control circuit, and a primary side circuit.
  • the utility model comprises a filter capacitor C1, a main power circuit, a clamp circuit and a current sampling circuit.
  • the main power circuit is formed by connecting a primary winding of the transformer T1 and a main switch tube TR1 (the main switch tube is a MOS tube, and the following may also be called a MOS tube) TR1);
  • the clamp module is connected by a resistor R1, a capacitor C2 and a diode D2;
  • the current sampling circuit is connected by a resistor R4.
  • the secondary circuit includes a secondary winding of the transformer T1, a rectifier diode D1, and a capacitor C3.
  • the control circuit is composed of a control chip (or control IC) U10 and a voltage sampling isolation feedback circuit, and the control chip U10 is used to implement drive control of the switch tube, including a GND pin, a CS pin, an FB pin, and a GATE pin.
  • the GND pin is the reference ground pin of the chip;
  • the CS pin is the current detection pin, which is used to detect the peak current of the primary side, and adjust the duty ratio of the MOS transistor TR1 to control the on-time of the MOS transistor TR1;
  • FB The pin is a feedback pin for receiving the secondary side feedback signal for the control chip to perform duty cycle control;
  • the GATE pin is a drive output pin that outputs a drive signal to the gate of the external MOS transistor TR1.
  • the specific connection relationship of the flyback converter is that the input terminal VIN+ is connected to one end of the resistor R1 in the clamp module and one end of the capacitor C2, the other end of the resistor R1 is connected to the other end of the capacitor C2 and is connected to the cathode of the diode D2, and the diode D2
  • the anode is connected to the same name end of the primary winding of the transformer T1, and the input terminal voltage VIN+ of the primary winding of the transformer T1 is connected;
  • the drain of the MOS transistor TR1 in the main power loop is connected to the same name end of the primary winding of the transformer T1, and the source of the MOS transistor TR1
  • One end of the resistor R4 connected to the current sampling circuit is connected to the CS pin of the control chip U10; the other end of the resistor R4 is grounded; the gate of the MOS transistor TR1 is connected to the GATE pin of the control chip U10, and the GND pin of the control chip U10 Connect to the ground GND terminal.
  • the same name end of the transformer T1 secondary winding is connected to the anode of the rectifier diode D1 in the output rectification filter circuit, the transformer T1 secondary winding is connected to the output terminal negative pole Vo-, the cathode of the rectifier diode D1 is connected to the output terminal positive Vo+, and the output filter is connected at the same time.
  • the anode of the capacitor C3, the cathode of the output filter capacitor C3 is connected to the cathode Vo- at the output end.
  • the two input ends of the voltage sampling isolation feedback circuit are respectively connected to the positive pole Vo+ and the negative pole Vo- of the output end, and the output end of the voltage sampling isolation feedback circuit is connected to the FB pin of the control chip U10.
  • the general control chip U10 has a signal FB voltage related to the load size (ie, the feedback voltage, which is fed back to the voltage of the FB pin of the control chip U10).
  • Several gear positions are assumed. It is assumed that there are 4 gear positions.
  • the FB pin voltage is before the first gear position, that is, the FB voltage is low, when the load is small, the valley is not controlled, and the valley opening function is not provided.
  • the system is in a position.
  • the operating mode of the down-conversion the operating frequency decreases as the load decreases.
  • the counter When the FB voltage reaches between the first gear and the second gear, the counter counts after four troughs; when the FB voltage reaches between the second gear and the third gear, the counter counts three troughs.
  • the counter When the FB voltage reaches between the third gear and the fourth gear, the counter counts after two troughs; when the FB voltage reaches the fourth gear, the system will work in the critical mode.
  • a trough turns on the MOS tube. The higher the gear position, the larger the load, the full load is above the fourth gear, and the number of troughs is minimized.
  • the switching period of the switching tube is composed of the on-time, the degaussing time and the valley resonance time, wherein the valley resonance refers to the primary winding and the switching junction capacitance of the flyback transformer in the DCM (intermittent) mode. Resonance. When the number of troughs decreases, the resonance time becomes shorter and the operating frequency of the switching tube increases.
  • the relationship between the input voltage VIN+ and the switching frequency f is as shown in Fig. 2.
  • the operating frequency of the switching tube is approximately linearly proportional to the input voltage, and the operating frequency is The range of variation is large, and the higher the input voltage, the higher the operating frequency.
  • FIG. 3 is a diagram showing the relationship between the output load and the operating frequency in the valley control scheme of the conventional control chip, and the resonance wave number relationship of the drain of the corresponding switch transistor TR1.
  • the control switch tube TR1 When the FB voltage corresponding to the load reaches the gear position 2, the control switch tube TR1 is turned on in the third trough, and because the switching of the valley is once, the resonance period is reduced by one, so the switching frequency will suddenly increase, and then with the load The increase and the slow decrease, and so on, finally, after the load corresponding FB voltage exceeds the gear position 4, it always works in the critical mode, and is opened in the first trough.
  • the traditional scheme achieves reasonable frequency reduction at lower load, which improves the efficiency of light load, and realizes the opening of the valley control under a heavier load to achieve the lowest voltage conduction effect.
  • the switching power supply generally requires a relatively wide input voltage range.
  • sexuality generally increases the feedforward function.
  • the FB pin voltage difference is not large under the condition of no feedforward (lower voltage is slightly lower).
  • the same load is corresponding to the high and low voltage.
  • the FB pin voltage is almost the same, so the FB voltage is the same for the same load regardless of the input voltage. That is to say, at low voltage, the FB pin voltage will enter the fourth gear position and work in the critical mode.
  • the FB pin voltage will also enter the fourth gear position and work in the critical mode.
  • the first input is 100VDC-400VDC
  • the reflected voltage is 100V
  • the second input is 9VDC-36VDC
  • the reflected voltage is 10VDC
  • Vin*D Voff*(1-D)
  • L*Ipk Vin*D*T
  • the working frequency of the prototype under high pressure is 2.56 times under low pressure
  • the operating frequency of the second prototype under high pressure is 2.73 times under low pressure.
  • the operating frequency of the switching tube of the conventional scheme varies greatly, and the EMI circuit is difficult. design. Moreover, the operating frequency is high at high input voltages, resulting in very low efficiency at high input voltages, so it can only be used in applications where the input voltage range is narrow.
  • the second defect of the trough control scheme of the traditional control chip is that when the FB voltage corresponding to the load is just near the gear position, if the FB voltage reaches the second gear position, the resonance trough number of the MOS transistor TR1 will be 4th.
  • the valleys and the third trough are constantly switching because that point is a critical value.
  • the general idea is to add a hysteresis to make the decision of the critical point more stable, but even if the hysteresis is increased under such conditions, the valley will be switched, because when the working state is from the condition of a large number of troughs, the number of troughs is small.
  • the input energy will suddenly increase, so it will inevitably cause the output voltage to rise.
  • the increase of the output voltage will inevitably cause the voltage of the FB pin to decrease, so it will jump back to the original state with more trough numbers.
  • the magnitude of the voltage change of the FB pin will exceed the magnitude of the hysteresis.
  • the root cause is that the switching of the valley must cause a sudden change in energy, and the sudden change of the energy further causes a sudden change in the voltage of the FB pin, thereby forming an oscillation.
  • the present invention provides a valley control method which can widen an input voltage range without causing valley switching oscillation.
  • the present invention also provides a valley control circuit that can widen the input voltage range without causing valley switching oscillations.
  • the present invention provides a valley control method, which is suitable for controlling the valley resonance of a switching cycle of a main power switch of a flyback converter, and enters a valley control mode when a feedback voltage is higher than a load reference voltage, that is,
  • the number of valleys controlling the switching period of the switching tube varies with the input voltage, and specifically includes the following steps: the input voltage detecting step detects the input voltage signal of the flyback converter, and sets the switching period of the switching tube according to the gear position of the input voltage. Number of troughs; trough turn-on control step, sampling the waveform of the drain of the switch tube and counting the troughs; when the number of troughs reaches the set value, the control switch is turned on.
  • the number of valleys controlling the switching period of the switching tube increases as the input voltage increases.
  • the number of troughs is constant, and only the primary peak current increased with the load increases the on-time and degaussing time of the switching period of the switch, and the natural adjustment switch The tube switching cycle becomes longer and the switching tube operating frequency decreases.
  • the present invention provides a valley control circuit suitable for valley resonance of a switching cycle of a main power switch of a flyback converter (ie, resonance of a primary winding and a switching junction capacitance of a flyback transformer in DCM mode) Control, including current detecting circuit, secondary side feedback circuit and driving output circuit, current detecting circuit is used for detecting the primary peak current of the source of the switching tube to control the opening time of the switching tube; the secondary side feedback circuit is for receiving The voltage sampling isolates the feedback feedback circuit to reflect the voltage signal of the load magnitude; the driving output circuit is configured to output a driving signal to the switching tube; and further includes an input voltage detecting circuit and a waveform detecting circuit, and an input voltage detecting circuit for detecting the flyback converter The input voltage is used by the valley control circuit to determine that the switching period of the switching tube is turned on in the first trough according to the gear position of the input voltage; the waveform detecting circuit is configured to sample the waveform of the drain of the switching tube and count the number of t
  • the valley control circuit further includes a voltage dividing circuit, and the voltage dividing circuit is connected in parallel between the input positive terminal of the flyback converter and the ground, and includes a resistor R2, a resistor R3 and a capacitor C4, and the resistor R2 and the resistor R3 are sequentially connected in series.
  • the series connection point forms a voltage dividing point
  • the capacitor C4 is connected in parallel across the resistor R3; the input end of the input voltage detecting circuit is connected to the voltage dividing point of the voltage dividing circuit.
  • the invention further provides a valley control circuit, which is suitable for controlling the valley resonance of the main power tube switching cycle of the flyback converter, and is an integrated chip structure including a ground pin, a secondary side feedback pin, a current detecting pin and a driving Output pin, ground pin for grounding; current sense pin for connecting to the source of the switch, detecting primary peak current to control the turn-on time of the switch; secondary feedback pin for isolation from voltage sampling
  • the feedback circuit is connected to receive a feedback voltage signal reflecting the magnitude of the load;
  • the driving output pin is used to output a driving signal to the switching tube; and the input voltage detecting pin and the waveform detecting pin, and the input voltage detecting pin are used for detecting
  • the input voltage of the flyback converter is used for the valley control circuit to determine that the switching period of the switching transistor is turned on in the first trough according to the gear position of the input voltage;
  • the waveform detecting pin is used to sample the waveform of the drain of the switching tube, and the number of troughs Counting is
  • the valley control circuit further includes a voltage dividing circuit, and the voltage dividing circuit is connected in parallel between the input positive terminal of the flyback converter and the ground, and includes a resistor R2, a resistor R3 and a capacitor C4, and the resistor R2 and the resistor R3 are sequentially In series, the series connection point forms a voltage dividing point, and the capacitor C4 is connected in parallel across the resistor R3; the input voltage detecting pin is connected to the voltage dividing point of the voltage dividing circuit.
  • the invention further provides a valley control circuit, which is suitable for controlling the valley resonance of the main power tube switching period of the flyback converter, and is an integrated chip structure, including a ground pin and a secondary side feedback pin, and the ground pin is used for Grounding; the secondary side feedback pin is used to connect with the voltage sampling isolation feedback circuit, and receives the feedback voltage signal reflecting the magnitude of the load; and includes a switch tube and a resistor R4, and an input voltage detection pin and a switch tube drain pin.
  • a valley control circuit which is suitable for controlling the valley resonance of the main power tube switching period of the flyback converter, and is an integrated chip structure, including a ground pin and a secondary side feedback pin, and the ground pin is used for Grounding; the secondary side feedback pin is used to connect with the voltage sampling isolation feedback circuit, and receives the feedback voltage signal reflecting the magnitude of the load; and includes a switch tube and a resistor R4, and an input voltage detection pin and a switch tube drain pin.
  • the switch tube and the resistor R4 are integrated in the chip; the input voltage detecting pin is used for detecting the input voltage of the flyback converter, so that the valley control circuit determines that the switching period of the switch tube is turned on in the first trough according to the gear position of the input voltage;
  • the drain pin of the switch tube is used to sample the waveform of the drain of the built-in switch tube and is provided to the valley control circuit to count the number of troughs; wherein the valley control circuit controls the number of troughs of the switching period of the switch tube as a function of the input voltage Variety.
  • the valley control circuit further includes a voltage dividing circuit, and the voltage dividing circuit is connected in parallel between the input positive terminal of the flyback converter and the ground, and includes a resistor R2, a resistor R3 and a capacitor C4, and the resistor R2 and the resistor R3 are sequentially In series, the series connection point forms a voltage dividing point, and the capacitor C4 is connected in parallel across the resistor R3; the input voltage detecting pin of the valley control circuit is connected to the voltage dividing point of the voltage dividing circuit.
  • the flyback converter improved by the scheme includes: a main power circuit, a clamp circuit, an output rectification filter circuit, an input voltage sampling circuit, a current sampling circuit, and a control circuit.
  • the main power circuit is formed by connecting a transformer and a main switch tube, wherein the clamp circuit is formed by a clamp resistor, a clamp capacitor and a diode, and the output rectification and filtering circuit is composed of an output rectifier diode and an output capacitor.
  • the input voltage sampling circuit is formed by connecting an upper voltage dividing resistor, a lower voltage dividing resistor and a filter capacitor.
  • the current sampling circuit is composed of a current sampling resistor, and is connected with the control chip U1, and the control chip U1 is at least
  • the UVP pin is an input voltage detection pin for detecting the input voltage to determine the opening and undervoltage protection in the first valley.
  • the GND pin is the reference ground pin of the chip.
  • the CS pin is The current detecting pin is used for detecting the peak current of the primary side to adjust the duty ratio of the MOS transistor TR1 to control the ON time of the MOS transistor TR1; the FB pin is a feedback pin for receiving the secondary side feedback signal for The control chip performs duty cycle control; the GATE pin is a drive output pin, and the drive signal is output to the gate of the external MOS transistor TR1; the VS pin is a voltage sampling pin for sampling the drain of the switch transistor TR1. Change signal, determines trough, and counts the number of troughs.
  • the control circuit is composed of a control chip U1 and a voltage sampling isolation feedback circuit.
  • the working principle of the trough control scheme of the invention firstly: sampling the input voltage through the input voltage sampling circuit, determining an accurate trough number according to different input voltages, and then sampling the trough through the drain waveform of the VS pin sampling switch tube TR1. And the internal trough counter is counted.
  • the enable voltage characteristic of the valley detection is determined by the voltage of the feedback voltage FB pin. If the voltage of the FB pin is higher than the set value, the load is large, the valley detection is effective, the number of troughs accumulated by the counter, and the input voltage sampling.
  • the number of selected troughs is the same, so that the drive output circuit (such as the circuit has a pin outside the chip, it can be called the drive output pin) output high level open MOS tube; if the FB pin voltage is lower than the set The fixed value indicates that the load is small and the valley detection is invalid. In this state, the valley detection signal and the counter signal are shielded. According to the voltage of the FB pin, the operating frequency is different. When the oscillator period is reached, the output circuit is driven. The output high level turns on the MOS transistor. The turn-off of the MOS tube is the same as the conventional scheme and will not be explained.
  • the trough control scheme of the present invention has the following beneficial effects:
  • the heavy load efficiency of the high voltage input can be improved without affecting the light load efficiency
  • Figure 1 is a schematic diagram of a conventional flyback topology circuit
  • Figure 2 is a diagram showing the relationship between frequency and input voltage under full load in the conventional valley control mode
  • Figure 3 is a diagram showing the relationship between load and frequency and the number of resonant wave valleys in the conventional valley control mode
  • FIG. 4 is a circuit schematic diagram of a flyback converter according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic block diagram of the inside of a control chip of a valley control circuit in a flyback converter according to Embodiment 1 of the present invention.
  • FIG. 6 is a diagram showing a relationship between an input voltage and a frequency of a valley control circuit and a relationship of a resonance wave number in a flyback converter according to Embodiment 1 of the present invention
  • FIG. 7 is a graph showing a trend of a change in operating frequency of a valley control circuit with a load at a same input voltage in a flyback converter according to Embodiment 1 of the present invention.
  • FIG. 8 is a circuit schematic diagram of a flyback converter according to a second embodiment of the present invention.
  • the flyback converter includes a transformer T1, a primary side circuit, a secondary side circuit, and a control circuit.
  • the primary side circuit includes a filter capacitor C1, a main power circuit, a clamp circuit, and a current.
  • the sampling circuit and the voltage dividing circuit, the main power circuit is formed by connecting the primary winding of the transformer T1 and the main switching transistor TR1 (the main switching transistor is a MOS transistor, and the following may also be referred to as a MOS transistor TR1).
  • the clamp module is formed by connecting a resistor R1, a capacitor C2 and a diode D2.
  • the current sampling circuit is connected by a resistor R4.
  • the secondary circuit consists of the secondary winding of the transformer T1 and the diode D1 and the capacitor C3.
  • the control circuit is composed of a control chip U1 and a voltage sampling isolation feedback circuit.
  • the control chip U1 is used to implement drive control of the switch tube, including a ground pin GND, a secondary feedback pin FB, a current detection pin CS, and a drive output pin GATE.
  • the input voltage detection pin UVP and the waveform detection pin VS, the ground pin GND is used for grounding;
  • the current detection pin CS is used to connect with the source of the switch tube to detect the primary side peak current; the secondary side feedback pin FB is used.
  • the drive output pin GATE is used to output the drive signal to the switch tube;
  • the input voltage detection pin UVP is used to detect the input of the flyback converter Voltage;
  • waveform detection pin VS used to sample the waveform of the drain of the switch tube, and count the number of troughs; wherein the number of troughs of the valley control circuit controlling the switching period of the switch varies with the input voltage.
  • the connection relationship of the flyback converter is: the positive terminal of the input terminal VIN+ is connected to the positive pole of the input filter capacitor C1, the negative terminal of the capacitor C1 is connected to the reference ground GND terminal, and the input terminal VIN+ is also connected to one end of the upper voltage dividing resistor R2 of the input voltage sampling circuit, the resistor The other end of R2 is respectively connected to one end of the lower voltage dividing resistor R3 and the UVP pin of the control chip U1, and is connected to the positive pole of the capacitor C4, the positive pole of the capacitor C4 and the other end of the resistor R3 are connected together and connected to the reference ground GND terminal;
  • the input terminal VIN+ is connected to one end of the resistor R1 and one end of the capacitor C2, the other end of the resistor R1 is connected to the other end of the capacitor C2 and is connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the same end of the primary winding of the transformer T1.
  • the different name end of the transformer T1 is connected to the input voltage VIN+; the drain of the MOS transistor TR1 in the main power loop is connected to the same name end of the primary winding of the transformer T1, and the VS pin of the control chip U1 is connected, and the source of the MOS transistor TR1 is connected.
  • One end of the resistor R4 connected to the current sampling circuit is connected to the CS pin of the control chip U1, and the gate of the MOS transistor TR1 is connected to the GATE pin of the control chip U1, and the control chip U1 is The GND pin is connected to the reference ground GND terminal.
  • the same name of the secondary winding of the transformer T1 is connected to the anode of the rectifier diode D1 in the output rectification filter circuit.
  • the transformer T1 secondary winding is connected to the output terminal negative pole Vo-, and the cathode connection of the rectifier diode D1 is connected.
  • the positive pole of the output terminal is Vo+, and the positive pole of the output filter capacitor C3 is connected at the same time.
  • the negative pole of the output filter capacitor C3 is connected to the negative pole of the output terminal Vo-, and the two input ends of the voltage sampling isolation feedback circuit are respectively connected to the positive pole Vo+ and the negative pole Vo- of the output terminal, and the voltage is simultaneously
  • the output of the sampling isolation feedback circuit is connected to the FB pin of the control chip U1.
  • the trough control principle of the switching tube switching cycle of the flyback converter of the present invention is: the voltage sampling isolating circuit compares and outputs the output voltage, and then isolates and transmits an FB pin voltage, and the FB pin of the control chip U1 detects the feedback voltage VFB, and the feedback The voltage VFB is changed with the load size. The higher the load, the higher the voltage.
  • the FB pin voltage is 1.2V at no load, the full load is 4V, and the effective FB voltage is set to 2.5V. This value is preset.
  • the load reference voltage is a load voltage signal characterized by a feedback voltage, and is artificially preset to divide the voltage value of the demarcation point between the light load and the heavy load.
  • the load reference voltage Vref5 is set to 2.5V.
  • the control chip U1 detects that the FB pin voltage is 2.5V or less, the valley turn-on enable signal is low level, and there is no valley control function, and the FB pin voltage corresponds to the oscillator inside the control chip U1 to generate an operating frequency, the converter Will work at this frequency, this time belongs to the frequency reduction mode.
  • the control chip U1 detects that the FB voltage is higher than 2.5V, the valley turn-on function is effective, and the input voltage is divided by the voltage dividing resistors R2 and R3, and then the UVP pin of the control chip U1 is sampled, and which trough file corresponding to the input voltage is detected.
  • the VS pin of the control chip U1 detects the resonance valley of the MOS transistor TR1, and when a valley is detected, the counting is performed once, and when the number of counts corresponds to the number of troughs corresponding to the valley position corresponding to the input voltage,
  • the GATE pin of the control chip U1 outputs a driving signal to drive the MOS transistor TR1 to turn on, realizing the valley control.
  • FIG. 5 is a schematic block diagram of the valley control chip U1 of the first embodiment, including a comparator circuit for determining the number of troughs, and a valley detecting circuit for detecting the trough, a valley selector, a trough counter, a logic control circuit, and an oscillator.
  • the connection relationship is that the UVP pin signal of the control chip U1 is connected to the four comparators comp1, comp2, comp3, comp4 of the comparator circuit therein, and both are connected to the non-inverting input terminal of the comparator, and the inverse of the four comparators A comparison reference voltage corresponding to the four-level valley position is connected to the input terminal.
  • the outputs of the four comparators are all connected to the valley selector, the output signal of the valley selector is connected to the logic control circuit; the VS pin signal is connected to the valley detection circuit, and the output of the valley detection circuit is connected to the valley counter, the counter output
  • the terminal is connected to the logic control circuit;
  • the FB pin signal is connected to the non-inverting input terminal of the comparator comp5, the load reference voltage Vref5 is connected to the negative phase input terminal of the comparator comp5, and the output terminal of the comparator comp5 is connected to the logic control circuit;
  • the FB signal is also input.
  • the output of the oscillator is connected to the logic control circuit, and the output of the logic control circuit outputs a drive signal to the GATE pin of the control chip U1.
  • the specific working principle of the valley control chip U1 is as follows:
  • the input voltage is divided by the voltages of the resistors R2 and R3 and input to the UVP pin for sampling.
  • a capacitor C4 is connected in parallel between the UVP pin and the ground to effectively filter some ripples at the input end, and the UVP pin is suppressed from being generated.
  • the ripple causes the switching of the threshold point of the trough gear.
  • the voltage of the UVP pin is sent to the comparators comp1, comp2, comp3, and comp4 for comparison.
  • the comparator comp1 corresponds to the first gear
  • the comparator comp2 corresponds to the first.
  • the comparison reference voltage Vref1 corresponding to the first gear position is the lowest, and the comparison reference voltage Vref4 is the highest, so if the corresponding input voltage is lower than the first gear position, the flyback converter is in an undervoltage state and does not operate. That is, when the input voltage is at the input undervoltage protection threshold point lower than the valley control turn-on threshold point (in this embodiment, the turn-on threshold point is the first gear voltage point), since the valley control circuit can directly use the input voltage detection reference
  • the input voltage signal provided by the pin can directly multiplex the input voltage detection signal to realize the undervoltage protection control in the valley control mode realized by the input voltage detection, so that the flyback converter enters the undervoltage protection state.
  • the valley selector selects the first valley if the corresponding input voltage is between the first gear and the second gear, and the valley selector if the corresponding input voltage is between the second gear and the third gear
  • the second trough will be selected. If the corresponding input voltage is between the third gear and the fourth gear, the valley selector will select the third trough. If the corresponding input voltage is above the fourth gear, the trough selection The device will select the fourth trough.
  • the selection signal of the valley selector is input to the logic control circuit, and the drain voltage of the MOS transistor TR1 is externally connected to the VS pin, and the drain voltage signal is input to the valley detecting circuit for valley determination. There are various determination methods, such as slope detection. Voltage comparison, etc., as long as the detection decision trough can be achieved.
  • a pulse signal is sent to the valley counter to count, and the count information is passed to the logic control circuit.
  • the feedback voltage signal FB voltage is input to the positive input terminal of the comparator comp5 on the one hand, and is input to the oscillator on the other hand.
  • the FB voltage is lower than the load reference voltage Vref5
  • the load is relatively small, and the output of the comparator is output.
  • Low level the signal is input to the logic control circuit, and the oscillator also generates a frequency according to the magnitude of the FB voltage.
  • the logic control circuit shields the signal of the valley selector and the signal of the valley counter, and directly outputs according to the oscillation period of the oscillator.
  • a drive signal control flyback converter operates in the down-convert mode and has no valley turn-on function.
  • the output of the comparator comp5 When the FB voltage is higher than the load reference voltage Vref5, it indicates that the load is relatively large.
  • the output of the comparator comp5 When the load is greater than the load corresponding to the turn-on control of the valley control, the output of the comparator comp5 outputs a high level, and the signal is input to the logic control circuit. At this time, the logic control circuit normally receives the signal of the valley selector and the signal of the valley counter.
  • the valley selector determines that the MOS transistor TR1 is turned on in the first trough, and when the drain of the MOS transistor TR1 of the flyback converter starts to resonate, the valley detecting circuit starts detecting, and when the trough is detected, the trough counter counts once, when the trough selects When the number of troughs required by the device coincides with the number of troughs counted by the trough counter, the logic control circuit outputs a drive signal to control the opening of the MOS transistor TR1 to realize the trough turn-on control.
  • Figure 6 shows the relationship between the operating frequency of the MOS transistor TR1 and the resonant valley of the drain of the MOSFET TR1 under heavy load.
  • the MOS transistor When the input voltage is at the lowest first gear, the MOS transistor is turned on in the first valley; when the input voltage is at the fourth highest gear, the MOS transistor is turned on in the fourth valley.
  • the switching cycle time of the MOS transistor TR1 increases, effectively reducing the operating frequency of the MOS transistor at the time of high input voltage, so that the flyback converter
  • the range of variation of the operating frequency of the full input voltage range is reduced, which advantageously reduces the difficulty of EMI design while minimizing the turn-on loss of the MOS transistor.
  • the trough control mode of the present invention is inversely proportional to the input voltage of the MOS transistor compared with the conventional common valley control.
  • the range of the number of troughs is adjusted in segments to make the input voltage range of the same MOS tube operating frequency range wider, and the switching frequency range of the control chip is smaller under the same input voltage range.
  • the reduction of the frequency variation range effectively reduces the difficulty of EMI circuit design.
  • the voltage at the input of the flyback converter itself is relatively stable, and a capacitor C4 is added, the voltage at the UVP pin is very stable.
  • the valley switching is based on the UVP pin voltage, when the voltage of the UVP pin is stable, plus the circuit's original hysteresis voltage setting, it will not change when the input voltage changes cause the valley switching. Repeated switching occurs back and forth, so there is no frequency jitter and oscillation caused by unstable trough numbers like the traditional valley control scheme, which eventually leads to an increase in output ripple.
  • the output ripple will become very large, especially in DCDC applications. Since the conventional ripple requirements of most products are around 50mV, the output capacitor is small, the traditional The ripple of the scheme is 100-200mV when switching, so the traditional scheme is difficult to use in the DCDC micropower field.
  • the ripple can be controlled within 50 mV after using the solution of the invention, so the solution of the invention can well meet the requirements of ripple in DCDC applications.
  • FIG. 7 is a diagram showing the relationship between the output load and the operating frequency of the valley control circuit of the present invention at a fixed input voltage, and it can be seen that the operating frequency is reduced as the load decreases when the load is light, and the operation is performed at the frequency reduction. Mode, which advantageously improves light load efficiency.
  • the trough control circuit controls the number of troughs of the MOS tube switching period to change with the input voltage.
  • the input voltage is constant, the number of troughs is constant, but as the load increases.
  • the primary peak current needs to be increased, so the on-time of the MOS transistor will increase, and the degaussing time will also increase.
  • the switch R4 is integrated into the chip of the control chip U1' to make the peripheral parameters more simplified.
  • the control chip U1' includes a UVP pin, a GND pin, a DRIN pin, and an FB pin.
  • the UVP pin is an input voltage detection pin for detecting an input voltage level to determine that the first trough is turned on and done.
  • GND pin is the reference ground pin of the chip
  • DRIN pin is the drain pin of the switch tube, used to sample the waveform of the drain of the built-in MOS transistor TR1, and is provided to the valley control circuit to count the number of troughs And as the drain terminal of the built-in MOS transistor TR1, for external circuit such as the same name of the transformer T1, etc.
  • FB pin is a feedback pin for receiving the secondary side feedback signal for the control chip to perform duty cycle control.
  • connection relationship of the circuit schematic diagram of the valley control circuit of the second embodiment is as follows: the positive terminal of the input terminal VIN+ is connected to the positive pole of the input filter capacitor C1, the negative terminal of the capacitor C1 is connected to the reference ground GND terminal, and the input terminal VIN+ is also connected to the input voltage sampling circuit.
  • One end of the resistor R2, the other end of the resistor R2 is connected to one end of the lower voltage dividing resistor R3 and the UVP pin of the control chip U1', and is connected to the anode of the filter capacitor C4, and the cathode of the capacitor C4 is connected to the other end of the R3.
  • the input terminal VIN+ is connected to one end of the resistor R1 of the clamp module and one end of the capacitor C2, the other end of the resistor R1 is connected to the other end of the capacitor C2 and is connected to the cathode of the diode D2, and the anode of the diode D2 is connected
  • the same name end of the primary winding of the transformer T1 is connected to the input voltage VIN+
  • the DRIN pin of the control chip U1' is connected to the same name end of the primary winding of the transformer T1
  • the GND pin of the control chip U1' is connected.
  • the same name end of the transformer T1 secondary winding is connected to the anode of the rectifier diode D1 in the output rectification filter circuit, and the transformer T1 secondary winding different name end Connected to the negative terminal Vo- of the output terminal, the cathode of the rectifier diode D1 is connected to the positive terminal Vo+ of the output terminal, and is connected to the positive pole of the output filter capacitor C3, the negative pole of the capacitor C3 is connected to the negative pole of the output terminal Vo-; the voltage sampling isolation feedback circuit is connected to the positive pole of the output terminal Vo+ and the positive pole Vo-, at the same time connect the FB pin of the control chip U1'.
  • the voltage sampling isolating feedback circuit compares the output voltage and compares and transmits an FB pin voltage
  • the FB pin of the control chip U1' detects the feedback voltage VFB, and the feedback voltage VFB changes with the load size.
  • the control chip U1' detects the FB pin voltage is 2.5V or less.
  • the valley turn-on enable signal is low level, and there is no valley control function.
  • the FB pin voltage corresponds to the oscillator inside the control chip U1' to generate an operating frequency, and the converter will operate at the frequency, which belongs to the frequency down mode.
  • the control chip U1' detects that the FB voltage is higher than 2.5V, the valley turn-on function is effective, and the input voltage is divided by the voltage dividing resistors R2 and R3, and then the UVP pin of the control chip U1' is sampled, and which input voltage is detected.
  • the valley gear position determines the DRIN pin detection resonance valley of the control chip U1' after the valley gear position, and performs counting once when a valley is detected. When the number of counts corresponds to the number of troughs corresponding to the valley position corresponding to the input voltage, then the control is performed. Inside the chip U1', a drive signal is generated to drive the built-in MOS transistor to turn on, enabling valley control.

Abstract

本发明提供了一种可以拓宽输入电压范围，并且不引起波谷切换震荡的波谷控制方法和波谷控制电路。其中，波谷控制电路，包括电流检测电路、副边反馈电路和驱动输出电路，电流检测电路用于检测开关管的源极的原边峰值电流，以控制开关管的开通时间；副边反馈电路用于接收电压采样隔离反馈电路反馈的反映负载大小的电压信号；驱动输出电路用于向开关管输出驱动信号；还包括输入电压检测电路和波形检测电路，输入电压检测电路，用于检测反激变换器的输入电压，以供波谷控制电路依输入电压的档位判定开关管开关周期在第几个波谷开通；波形检测电路，用于采样开关管漏极的波形，并对波谷数量进行计数。

Description

波谷控制电路及波谷控制方法 技术领域
本发明涉及开关变换器领域，工作在断续模式下的反激变换器，尤其针对DCDC应用场合的反激变换器的波谷控制方法及波谷控制电路。
背景技术
随着科技的发展，用电设备、仪器、电子产品越来越多，对开关电源的需求也越来越大，一些便携式电子产品的出现，使微功率段的开关电源需求量不断增加。
目前在微功率段使用的开关电源方案主要还是反激电路，因为它有着成本低，电路简单可靠，应用成熟等一系列特点。反激电路的工作模式分为两种，一种是连续模式(CCM)，一种是断续模式(DCM)。一般在较大功率段会使用连续模式，因为这种工作模式下的峰值电流会小一些，使电流有效值比较小，在大功率场合导通损耗所占的比例更大，所以能够降低电流有效值可以比较可观的减小损耗，达到较好的效率。但是在该工作模式下，有很多缺点，如开通损耗大，副边整流二极管反向恢复电流大，同步整流不好做等问题。在微功率场合，本身电流较小，所以导通损耗所占的比例较小，使反激电路继续工作在连续模式的好处就不明显，所以很多场合下选择断续工作模式。在断续模式下，MOS管的开通电压相对较低，EMI好，副边整流二极管没有反向恢复的损耗和电压应力问题，同步整流检测容易做，环路容易补偿，具有很多优势。为了最大限度的利用导通电压低这一优势，现有技术已经有很多检测断续模式下MOS管漏极电压谐振的电路，使它每一次都是在波谷处开启，达到最低的开通电压，使开通损耗最小化，EMI噪声最小化。针对具有电压谐振发生的电路中谐振电压达到最低值的时候称作波谷，波谷控制是检测并判定出波谷的准确时刻并根据对电路最有益的条件选择某一个波谷然后对开关管进行开通动作的一种开关管控制方案，该控制方案下除了可以实现前面提到的减小主开关管的开通电压降低开通损耗，EMI噪声最小化以外，还可以优化工作频率范围，合理地控制开关损耗并简化EMI电路设计。
目前行业内传统的反激变换器的开关管驱动控制方案是这样的：其电路示意图如图1所示，反激变换器包括变压器T1、原边电路、副边电路和控制电路，原边电路包括滤波电容C1、主功率电路、钳位电路和电流采样电路，主功率电路由变压器T1的原边绕组和主开关管TR1连接而成(主开关管为MOS管，以下也可称为MOS管TR1)；钳位模块由电阻R1、电容C2和二极管D2连接而成；电流采样电路由电阻R4连接而成。副边电路包括变压器T1的副边绕组、整流二极管D1和电容C3。控制电路由控制 芯片(或称为控制IC)U10和电压采样隔离反馈电路构成，控制芯片U10用于实现开关管的驱动控制，包括GND引脚、CS引脚、FB引脚和GATE引脚，GND引脚为芯片的参考地引脚；CS引脚为电流检测引脚，用于检测原边峰值电流大小，进行MOS管TR1的占空比调节，以控制MOS管TR1的导通时间；FB引脚为反馈引脚，用于接收副边反馈信号以供控制芯片进行占空比控制；GATE引脚为驱动输出引脚，输出驱动信号到外部MOS管TR1的栅极。反激变换器的具体连接关系是，输入端VIN+连接钳位模块中电阻R1的一端和电容C2的一端，电阻R1的另一端和电容C2的另一端相连并且连接二极管D2的阴极，二极管D2的阳极连接变压器T1原边绕组的同名端，变压器T1原边绕组的异名端连接输入电压VIN+；主功率回路中MOS管TR1的漏极连接变压器T1原边绕组的同名端，MOS管TR1的源极连接电流采样电路的电阻R4的一端，同时连接控制芯片U10的CS引脚；电阻R4的另一端接地；MOS管TR1的栅极连接控制芯片U10的GATE引脚，控制芯片U10的GND引脚连接参考地GND端。变压器T1副边绕组的同名端连接输出整流滤波回路中整流二极管D1的阳极，变压器T1副边绕组异名端连接输出端负极Vo-，整流二极管D1的阴极连接输出端正极Vo+，同时连接输出滤波电容C3的正极，输出滤波电容C3的负极连接输出端的负极Vo-。电压采样隔离反馈电路的两输入端分别连接输出端的正极Vo+和负极Vo-，电压采样隔离反馈电路的输出端连接控制芯片U10的FB引脚。
一般控制芯片U10都有一个和负载大小相关的信号FB电压(即反馈电压，是副边反馈回控制芯片U10的FB引脚的电压)，负载越大，则FB电压越高，把FB电压设定几个档位，假设有4个档位，当FB引脚电压在第一档位之前，即FB电压较低，负载较小的时候，不对波谷进行控制，无波谷开通功能，系统处于一个降频的工作模式，工作频率随着负载的降低而降低。当FB电压达到第一档位到第二档位之间的时候，计数器计数4个波谷之后开通；当FB电压达到第二档位到第三档位之间的时候，计数器计数3个波谷之后开通；当FB电压达到第三档位和第四档位之间的时候，计数器计数2个波谷之后开通；当FB电压达到第四档位以上的时候，系统就会工作在临界模式，在第一个波谷开启MOS管。档位越高就代表负载越大，满载就是处于第四档位以上的，波谷数量减至最少。在开关管占空比控制中，开关管的开关周期由导通时间、消磁时间和波谷谐振时间构成，其中波谷谐振是指DCM(断续)模式下反激变压器原边绕组和开关管结电容的谐振。当波谷数量减少时，谐振时间变短，开关管的工作频率提高。传统方案中在输出端负载不变并且带重载的情况下输入端电压VIN+和开 关频率f的关系曲线如图2所示，开关管的工作频率与输入电压呈近似线性正比例关系，工作频率的变化范围大，且输入电压越高则工作频率越高。因为在负载一定的情况下FB反馈电压基本是不变的，FB电压不变的原因在下文中有叙述，因此会选择在一个固定的波谷开通开关管，随着输入端电压VIN+的升高，假设开关频率还没有升高，输出能量和效率不变，所以峰值电流不变，根据电感激磁的公式
Figure PCTCN2018094820-appb-000001
可知开关管的开通时间会减少，消磁时间和谐振时间不变，则工作周期减少，频率增加，同时随着频率的增加根据公式Pin＝1/2*L*Ipk 2*f会导致峰值电流进一步减小所以工作频率进一步上升。
图3是传统控制芯片的波谷控制方案下输出负载与工作频率的关系图，还有对应的开关管TR1漏极的谐振波谷数关系。当负载对应的FB电压在档位1之前，因为没有进行波谷控制，所以工作在降频模式，频率随着负载的减小而降低。当负载对应的FB电压达到档位1的时候，控制开关管TR1在第4个波谷开通，在此之前一般谐振波谷数量多于4个，所以波谷谐振数量会发生一次变化，导致谐振时间减少，从而引起开关周期的一个突然变化会引起频率的突然增加，因为谐振时间减少了，继续增加负载因为波谷数不变，负载增加所以峰值电流需要增加，因此开关管TR1的导通时间增加，消磁时间增加，所以频率缓慢降低。当负载对应的FB电压达到档位2后，控制开关管TR1在第三个波谷开通，同样因为切换了一次波谷，谐振周期少了一个所以开关频率会产生一次突然的升高，然后随着负载增加又缓慢降低，依次类推，最终在负载对应的FB电压超过档位4后就一直工作在临界模式，在第一波谷开通。传统方案合理的在较低负载下实现降频，提升了轻载的效率，同时在较重的负载下实现波谷控制开启，达到最低电压导通的效果。
但是传统控制芯片的波谷控制方案有两个严重的缺陷，第一，现在开关电源一般都是要求有比较宽的输入电压范围的，在这样的情况下为了保证整个电压范围负载过流点的一致性，一般都会增加前馈的功能，同一负载，本身在没有前馈的条件下FB引脚电压差别就不大(高压略低)，现在增加了前馈功能以后，高低压下同一负载对应的FB引脚电压是几乎一样的，所以对于同一负载不管输入电压是多少，FB电压是一致的。也就是说，在低压下FB引脚电压会进入第四档位，工作在临界模式，那么在高压下FB引脚电压同样也会进入第四档位，工作在临界模式。假设两种常见的样机(第一种输入为100VDC-400VDC，反射电压为100V，第二种输入为9VDC-36VDC，反 射电压为10VDC)，忽略临界模式中谐振的那一小部分时间，根据公式Vin*D＝Voff*(1-D)、L*Ipk＝Vin*D*T、Pin＝1/2*L*Ipk 2*f，假设高低压下的效率一样，则可以得出第一种样机在高压下的工作频率是在低压下的2.56倍，第二种样机在高压下的工作频率是在低压下的2.73倍，所以传统方案的开关管工作频率的变化范围很大，EMI电路难以设计。而且在高输入电压下工作频率会很高，导致高输入电压下的效率非常低，因此只能做输入电压范围比较窄的应用。
传统控制芯片的波谷控制方案第二个缺陷是：当负载所对应的FB电压刚好在档位附近的时候，假设FB电压达到第二档位，则MOS管TR1的谐振波谷数就会在第4个波谷和第3个波谷之间不断的切换，因为那个点是一个临界值。通常的思路是增加一个回差，使临界点的判定更加稳定，但是在这种条件下就算是增加了回差也会引起波谷切换，因为当工作状态从波谷数多的条件进入波谷数少的状态后(FB引脚电压从低到高)，开关管的工作频率相当于产生一个突变，而峰值电流不能马上变化，因此根据能量公式Pin＝1/2*L*Ipk 2*f可以知道，输入的能量会突然增加，于是必然引起输出电压的升高，输出电压的升高必然会引起FB引脚电压的降低，所以又会再次跳回到波谷数更多的那种原来状态。而FB引脚电压变化的幅度是会超过回差的幅度的，根本原因是切换波谷必定引发能量的突变，能量的突变又进一步引发FB引脚电压的突变，从而形成震荡。在这样的震荡情况下，输出纹波会变得很大，尤其是在DCDC应用场合，由于大部分产品常规的纹波要求就在50mV左右，在输出电容很小的状态下，传统方案波谷切换时纹波达到100-200mV，所以传统方案在DCDC微功率领域是难以使用的。
发明内容
为解决上述问题，本发明提供了一种可以拓宽输入电压范围，并且不引起波谷切换震荡的波谷控制方法。
与此相应，本发明还提供了可以拓宽输入电压范围，并且不引起波谷切换震荡的波谷控制电路。
为实现上述发明目的，本发明提供一种波谷控制方法，适用于反激变换器的主功率开关管开关周期的波谷谐振进行控制，在反馈电压高于负载参考电压时，进入波谷控制模式，即控制开关管开关周期的波谷数量随输入电压的变化而变化，具体包括如下步骤，输入电压检测步骤，检测反激变换器的输入电压信号，并依输入电压的档位设定开关管开关周期的波谷数量；波谷开通控制步骤，采样开关管漏极的波形，并对 波谷进行计数；在波谷数量达到设定值时，控制开关管开通。
优选的，所述波谷控制模式，控制开关管开关周期的波谷数量随着输入电压的升高而增加。
优选的，所述波谷控制模式，在输入电压不变、负载增加时，波谷数量不变，仅由随负载增加的原边峰值电流增加开关管开关周期的导通时间和消磁时间，自然调节开关管开关周期变长、开关管工作频率降低。
就产品主题而言，本发明提供一种波谷控制电路，适用于对反激变换器的主功率开关管开关周期的波谷谐振(即DCM模式下反激变压器原边绕组和开关管结电容的谐振)进行控制，包括电流检测电路、副边反馈电路和驱动输出电路，电流检测电路用于检测开关管的源极的原边峰值电流，以控制开关管的开通时间；副边反馈电路用于接收电压采样隔离反馈电路反馈的反映负载大小的电压信号；驱动输出电路用于向开关管输出驱动信号；还包括输入电压检测电路和波形检测电路，输入电压检测电路，用于检测反激变换器的输入电压，以供波谷控制电路依输入电压的档位判定开关管开关周期在第几个波谷开通；波形检测电路，用于采样开关管漏极的波形，并对波谷数量进行计数；其中，波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
优选的，所述波谷控制电路，还包括分压电路，分压电路并联在反激变换器的输入正端与地之间，包括电阻R2、电阻R3和电容C4，电阻R2与电阻R3依次串联，串联连接点形成分压点，电容C4并联在电阻R3的两端；所述输入电压检测电路的输入端与分压电路的分压点连接。
本发明再提供一种波谷控制电路，适用于反激变换器的主功率管开关周期的波谷谐振进行控制，为集成芯片结构，包括接地引脚、副边反馈引脚、电流检测引脚和驱动输出引脚，接地引脚用于接地；电流检测引脚用于与开关管的源极连接，检测原边峰值电流，以控制开关管的开通时间；副边反馈引脚用于与电压采样隔离反馈电路连接，接收其反馈的反映负载大小的电压信号；驱动输出引脚用于向开关管输出驱动信号；还包括输入电压检测引脚和波形检测引脚，输入电压检测引脚，用于检测反激变换器的输入电压，以供波谷控制电路依输入电压的档位判定开关管开关周期在第几个波谷开通；波形检测引脚，用于采样开关管漏极的波形，并对波谷数量进行计数；其中，波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
优选的，所述的波谷控制电路，还包括分压电路，分压电路并联在反激变换器的 输入正端与地之间，包括电阻R2、电阻R3和电容C4，电阻R2与电阻R3依次串联，串联连接点形成分压点，电容C4并联在电阻R3的两端；所述输入电压检测引脚与分压电路的分压点连接。
本发明另再提供一种波谷控制电路，适用于反激变换器的主功率管开关周期的波谷谐振进行控制，为集成芯片结构，包括接地引脚和副边反馈引脚，接地引脚用于接地；副边反馈引脚用于与电压采样隔离反馈电路连接，接收其反馈的反映负载大小的电压信号；还包括开关管和电阻R4，以及输入电压检测引脚和开关管漏极引脚，开关管和电阻R4集成于芯片内；输入电压检测引脚，用于检测反激变换器的输入电压，以供波谷控制电路依输入电压的档位判定开关管开关周期在第几个波谷开通；开关管漏极引脚，用于采样内置开关管漏极的波形，并提供给波谷控制电路以对波谷数量进行计数；其中，波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
优选的，所述的波谷控制电路，还包括分压电路，分压电路并联在反激变换器的输入正端与地之间，包括电阻R2、电阻R3和电容C4，电阻R2与电阻R3依次串联，串联连接点形成分压点，电容C4并联在电阻R3的两端；所述波谷控制电路中输入电压检测引脚与分压电路的分压点连接。
如上所述，该方案改进得到的反激变换器包括：主功率电路、钳位电路、输出整流滤波电路、输入电压采样电路、电流采样电路、控制电路。所述的主功率电路由变压器和主开关管连接而成，所述的钳位电路由钳位电阻、钳位电容以及二极管连接而成，所述的输出整流滤波电路由输出整流二极管和输出电容连接而成，所述的输入电压采样电路由上分压电阻，下分压电阻和滤波电容连接而成，所述的电流采样电路由电流采样电阻构成，和控制芯片U1连接，控制芯片U1至少包含UVP引脚为输入电压检测引脚，用于检测输入电压的档位，以判定在第几个波谷开通和做欠压保护)、GND引脚为芯片的参考地引脚；CS引脚为电流检测引脚，用于检测原边峰值电流大小进行MOS管TR1的占空比调节，以控制MOS管TR1的导通时间；FB引脚为反馈引脚，用于接收副边反馈信号以供控制芯片进行占空比控制；GATE引脚为驱动输出引脚，输出驱动信号到外部MOS管TR1的栅极；VS引脚为电压采样引脚，用于采样开关管TR1漏极的电压变化信号，判断波谷，并对波谷数量进行计数。所述的控制电路由控制芯片U1、电压采样隔离反馈电路构成。
本发明波谷控制方案的工作原理：首先通过输入电压采样电路采样输入电压，根据不同的输入电压可以确定一个准确的波谷数量，然后通过VS引脚采样开关管TR1 的漏极波形，对波谷进行采样并使内部波谷计数器计数。另一方面通过反馈电压FB引脚电压来判定波谷检测的使能特性，若FB引脚电压高于设定值，则说明负载较大，波谷检测有效，计数器累计到的波谷数量和输入电压采样后选择的波谷数量一致则使驱动输出电路(如该电路有引出于芯片外部的引脚，则可称其为驱动输出引脚)输出高电平开通MOS管；若FB引脚电压低于设定值，则说明负载较小，波谷检测无效，在此状态下波谷检测信号和计数器的信号都被屏蔽，根据FB引脚电压大小对应不同的工作频率，当振荡器周期达到则使驱动输出电路输出高电平开通MOS管。MOS管的关断和传统方案是一样的，不再说明。
与现有技术相比，本发明波谷控制方案具有如下有益效果：
(1)不影响轻载效率的基础上使高压输入的重负载效率得以提升；
(2)保持效率的同时拓宽变换器了输入电压范围；
(3)满载工作频率范围大大减小，有利于EMI电路的设计和优化；
(4)消除了传统波谷开通方案下波谷切换引起的输出纹波。
附图说明
图1为普通反激拓扑电路原理图；
图2为传统波谷控制方式满载下频率和输入电压的关系图；
图3为传统波谷控制方式下负载和频率的关系以及谐振波谷数的关系图；
图4为本发明实施例一的反激变换器的电路原理图；
图5为本发明实施例一的反激变换器中波谷控制电路的控制芯片内部的原理框图；
图6为本发明实施例一的反激变换器中波谷控制电路的输入电压和频率的关系以及谐振波谷数的关系图；
图7为本发明实施例一的反激变换器中波谷控制电路在同一输入电压下的工作频率随负载的变化趋势图；
图8为本发明实施例二的反激变换器的电路原理图。
具体实施方式
实施例一
图4是本发明反激变换器的电路原理图，反激变换器包括变压器T1、原边电路、副边电路和控制电路，原边电路包括滤波电容C1、主功率电路、钳位电路、电流采样电路和分压电路，主功率电路由变压器T1的原边绕组和主开关管TR1连接而成(主 开关管为MOS管，以下也可称为MOS管TR1)。钳位模块由电阻R1、电容C2和二极管D2连接而成。电流采样电路由电阻R4连接而成。副边电路由变压器T1的副边绕组与二极管D1、电容C3组成。控制电路由控制芯片U1和电压采样隔离反馈电路构成，控制芯片U1用于实现开关管的驱动控制，包括接地引脚GND、副边反馈引脚FB、电流检测引脚CS、驱动输出引脚GATE、输入电压检测引脚UVP和波形检测引脚VS，接地引脚GND用于接地；电流检测引脚CS用于与开关管的源极连接，检测原边峰值电流；副边反馈引脚FB用于与电压采样隔离反馈电路连接，接收其反馈的反映负载大小的电压信号；驱动输出引脚GATE用于向开关管输出驱动信号；输入电压检测引脚UVP，用于检测反激变换器的输入电压；波形检测引脚VS，用于采样开关管漏极的波形，并对波谷数量进行计数；其中，波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
反激变换器的连接关系为：输入端正极VIN+连接输入滤波电容C1的正极，电容C1的负极连接参考地GND端，输入端VIN+还连接输入电压采样电路中上分压电阻R2的一端，电阻R2的另外一端分别连接下分压电阻R3的一端及控制芯片U1的UVP引脚，同时连接电容C4的正极，电容C4的正极和电阻R3的另一端连接在一起并连接到参考地GND端；输入端VIN+连接钳位模块中电阻R1的一端和电容C2的一端，电阻R1的另一端和电容C2的另一端相连并且连接二极管D2的阴极，二极管D2的阳极连接变压器T1原边绕组的同名端，变压器T1原边绕组的异名端连接输入电压VIN+；主功率回路中MOS管TR1的漏极连接变压器T1原边绕组的同名端，同时连接控制芯片U1的VS引脚，MOS管TR1的源极连接电流采样电路的电阻R4的一端，同时连接控制芯片U1的CS引脚，MOS管TR1的栅极连接控制芯片U1的GATE引脚，控制芯片U1的GND引脚连接参考地GND端，变压器T1副边绕组的同名端连接输出整流滤波回路中整流二极管D1的阳极，变压器T1副边绕组异名端连接输出端负极Vo-，整流二极管D1的阴极连接输出端正极Vo+，同时连接输出滤波电容C3的正极，输出滤波电容C3的负极连接输出端的负极Vo-，电压采样隔离反馈电路的两个输入端分别连接输出端的正极Vo+和负极Vo-，同时电压采样隔离反馈电路的输出端连接控制芯片U1的FB引脚。
本发明反激变换器的开关管开关周期的波谷控制原理为：通过电压采样隔离电路对输出电压采样比较后隔离传输过来一个FB引脚电压，控制芯片U1的FB引脚检测反馈电压VFB，反馈电压VFB是随着负载大小变化，负载越大，电压越高，空载时FB 引脚电压为1.2V，满载为4V，设定波谷开启有效对应的FB电压为2.5V，此值为预设的负载参考电压，是依反馈电压表征的负载电压信号，所人为预设的划分轻载、重载两种负载情况的分界点的电压值。在本实施例中，负载参考电压Vref5设为2.5V。当控制芯片U1检测到FB引脚电压为2.5V以下，则波谷开通使能信号为低电平，无波谷控制作用，FB引脚电压对应控制芯片U1内部的振荡器产生一个工作频率，变换器会工作在该频率下，此时属于降频模式。当控制芯片U1检测到FB电压高于2.5V，则波谷开通功能有效，输入电压经过分压电阻R2、R3分压后给控制芯片U1的UVP脚采样，检测输入电压对应的是哪一个波谷档位，确定了波谷档位以后控制芯片U1的VS脚检测MOS管TR1的谐振波谷，当检测到一个波谷就进行一次计数，当计数数量和输入电压对应的波谷档位对应的波谷数量符合，则控制芯片U1的GATE引脚输出驱动信号驱动MOS管TR1开通，实现波谷控制。
图5所示为具体实施例一的波谷控制芯片U1的原理框图，其中包含波谷数量判定的比较器电路，以及检测波谷的波谷检测电路、波谷选择器、波谷计数器、逻辑控制电路和振荡器。其连接关系为控制芯片U1的UVP引脚信号连接到里面的比较器电路的4个比较器comp1、comp2、comp3、comp4中，并且都连接到比较器的同相输入端，4个比较器的反向输入端分别连接与四级波谷档位对应的比较参考电压。比较参考电压，是依输入电压的变化范围，所预设的划分四个波谷档位的分界点的电压值，在本实施例中，比较参考电压为Vref1、Vref2、Vref3、Vref4四个，分别对应波谷档位的第一、二、三、四档位。4个比较器的输出端全部连接到波谷选择器，波谷选择器的输出信号连接到逻辑控制电路；VS引脚信号接到波谷检测电路中，波谷检测电路的输出端连接到波谷计数器，计数器输出端连接逻辑控制电路；FB引脚信号连接比较器comp5的正相输入端，负载参考电压Vref5连接比较器comp5的负相输入端，比较器comp5的输出端连接到逻辑控制电路；FB信号还输入到振荡器中去，振荡器的输出端连接到逻辑控制电路，逻辑控制电路的输出端输出一个驱动信号到控制芯片U1的GATE引脚。
波谷控制芯片U1的具体工作原理为：
输入电压经过电阻R2和R3分压后的电压输入到UVP脚进行采样，同时在UVP脚到地之间并联一个电容C4可以有效的对输入端的一些纹波进行滤波，抑制UVP引脚产生较大纹波引起波谷档位临界点的来回切换问题，UVP引脚的电压送到比较器comp1、comp2、comp3、comp4进行比较，比较器comp1对应的是第一档位，比较器comp2对 应的是第二档位以此类推。第一档位对应的比较参考电压Vref1是最低的，比较参考电压Vref4是最高的，所以对应的输入电压如果低于第一档位，则反激变换器处于欠压状态不工作。即当输入电压处于波谷控制开启阈值点(在本实施例中此开启阈值点为第一档位电压点)更低的输入欠压保护阈值点时，由于波谷控制电路可直接使用输入电压检测引脚提供的输入电压信号，便可以在输入电压检测实现的波谷控制模式下，直接复用输入电压检测信号来实现欠压保护控制，使反激变换器进入欠压保护状态。
如果对应的输入电压处于第一档位和第二档位之间则波谷选择器会选择第一个波谷，如果对应的输入电压处于第二档位到第三档位之间，则波谷选择器会选择第二波谷，如果对应的输入电压处于第三档位和第四档位之间，则波谷选择器会选择第三波谷，如果对应的输入电压处于第四档位之上，则波谷选择器会选择第四波谷。波谷选择器的选择信号输入到逻辑控制电路中去，VS引脚外部接MOS管TR1的漏极电压，漏极电压信号输入到波谷检测电路进行波谷判定，判定方法有多种，如斜率检测，电压比较等，在此只要能够达到检测判定波谷就可以。当检测到一个波谷后就发出一个脉冲信号给波谷计数器计数，计数信息传递到逻辑控制电路。
反馈电压信号FB电压一方面输入到比较器comp5的正向输入端，另一方面输入到振荡器中去，当FB电压低于负载参考电压Vref5的时候，说明负载比较小，比较器输出端输出低电平，该信号输入到逻辑控制电路中，振荡器同样根据FB电压大小产生一个频率，此时逻辑控制电路会屏蔽波谷选择器的信号和波谷计数器的信号，直接根据振荡器的震荡周期输出一个驱动信号控制反激变换器工作在降频模式，没有波谷开通的功能。当FB电压高于负载参考电压Vref5的时候，说明负载比较大，在负载大于波谷控制的开启使能对应的负载时，比较器comp5输出端输出高电平，该信号输入到逻辑控制电路中，此时逻辑控制电路正常接收波谷选择器的信号和波谷计数器的信号。波谷选择器确定了在第几个波谷开通MOS管TR1，当反激变换器的MOS管TR1漏极开始谐振，波谷检测电路就开始检测，检测到一个波谷时波谷计数器就计数一次，当波谷选择器需求的波谷数和波谷计数器计数到的波谷数一致的时候，逻辑控制电路就输出一个驱动信号，控制MOS管TR1开通，实现波谷开通控制。
在重载下MOS管TR1的工作频率随输入电压的变化关系图以及MOS管TR1漏极的谐振波谷数关系图如图6所示。在输入电压处于最低的第一档位时候，在第一个波谷开启MOS管；在输入电压最高的第四档位时候，在第四个波谷开启MOS管。因为输入电压升高时，MOS管TR1的开关周期中谐振波谷数量增加了，所以MOS管TR1的开关 周期时间增加，有效地降低了高输入电压时候的MOS管的工作频率，使反激变换器全输入电压范围的工作频率的变化范围减少，有利地降低了EMI设计难度，同时保证了MOS管开通损耗的最小化。因此本发明的波谷控制方式与传统普通的波谷控制相比，MOS管的工作频率与输入电压呈反比关系，输入电压越高时MOS管的工作频率越低，且MOS管开关周期按输入电压的范围划分波谷数的档位，以分段形式进行调整，使同样的MOS管工作频率范围内输入电压范围可以更宽，在同样的输入电压范围下对控制芯片的开关频率范围要求更小，开关频率变化范围的减小有效的降低了EMI电路设计难度。在另一方面因为反激变换器本身输入端的电压是比较稳定的，同时再加了一个电容C4滤波，所以UVP引脚处的电压是很稳定的。因为波谷切换是根据UVP引脚电压来进行选择的，在UVP引脚的电压稳定的情况下，再加上电路本来的回差电压设置，就会在输入电压变化引起波谷切换的时候不会再发生来回的反复切换，因此不会像传统波谷控制方案一样出现波谷数量不稳定引起的频率抖动及震荡最终导致输出纹波变大。在传统波谷控制方案的震荡情况下，输出纹波会变得很大，尤其是在DCDC应用场合，由于大部分产品常规的纹波要求就在50mV左右，在输出电容很小的状态下，传统方案波谷切换时纹波达到100-200mV，所以传统方案在DCDC微功率领域是难以使用的。而使用本发明方案后可以将纹波控制在50mV以内，所以本发明方案可很好地满足DCDC应用场合对纹波的要求。
图7为本发明的波谷控制电路在固定输入电压下输出端负载和工作频率的关系图，可以看到在负载较轻的时候工作频率是随负载的减小而减小的，工作在降频模式，有利的提高了轻载效率。在负载较重的时候，进入波谷控制模式，因为波谷控制电路控制MOS管开关周期的波谷数量随输入电压的变化而变化，输入电压不变则波谷数是不变的，但是随着负载的增加，原边峰值电流需要增加，所以MOS管的导通时间会增加，消磁时间也增加，这是反激变换器本身的电路环路调节导通时间和消磁时间而自动增加的，因此MOS管的整个开关周期是会缓慢增加的，因而导致MOS管工作频率随负载的增加而缓慢降低的，可以有利的降低开关损耗，保证重载下的效率也比较高。
实施例二
图8是本发明实施例二的波谷控制电路应用在反激变换器中的电路原理图，与实施例一相比，实施例二中把反激变换器的主MOS管TR1和电流采样电路的电阻R4集成到了控制芯片U1’的芯片里面，使外围参数更加简化。控制芯片U1’包括UVP引脚、GND引脚、DRIN引脚和FB引脚，UVP引脚为输入电压检测引脚，用于检测输入电 压的档位，以判定在第几个波谷开通和做欠压保护；GND引脚为芯片的参考地引脚；DRIN引脚为开关管漏极引脚，用于采样内置MOS管TR1漏极的波形，并提供给波谷控制电路以对波谷数量进行计数；并做为内置MOS管TR1的漏极引出端，供变压器T1的同名端等外部电路与之连接；FB引脚为反馈引脚，用于接收副边反馈信号以供控制芯片进行占空比控制。
实施例二的波谷控制电路的电路原理图的连接关系为：输入端正极VIN+连接输入滤波电容C1的正极，电容C1的负极连接参考地GND端，输入端VIN+还连接输入电压采样电路中上分压电阻R2的一端，电阻R2的另外一端分别连接下分压电阻R3的一端及控制芯片U1’的UVP引脚，同时连接滤波电容C4的正极，电容C4的负极和R3的另一端连接在一起并连接到参考地GND端；输入端VIN+连接钳位模块中电阻R1的一端和电容C2的一端，电阻R1的另一端和电容C2的另一端相连并且连接二极管D2的阴极，二极管D2的阳极连接变压器T1原边绕组的同名端，变压器T1原边绕组的异名端连接输入电压VIN+；控制芯片U1’的DRIN引脚连接变压器T1原边绕组的同名端，控制芯片U1’的GND引脚连接参考地GND端；变压器T1副边绕组的同名端连接输出整流滤波回路中整流二极管D1的阳极，变压器T1副边绕组异名端连接输出端负极Vo-，整流二极管D1的阴极连接输出端正极Vo+，同时连接输出滤波电容C3的正极，电容C3的负极连接输出端的负极Vo-；电压采样隔离反馈电路连接输出端的正极Vo+和正极Vo-，同时连接控制芯片U1’的FB引脚。
其工作原理为：通过电压采样隔离反馈电路对输出电压采样比较后隔离传输过来一个FB引脚电压，控制芯片U1’的FB引脚检测反馈电压VFB，反馈电压VFB是随着负载大小变化，负载越大，电压越高，空载时FB引脚电压为1.2V，满载为4V，设定波谷开启有效对应的FB电压为2.5V，当控制芯片U1’检测到FB引脚电压为2.5V以下则波谷开通使能信号为低电平，无波谷控制作用，FB引脚电压对应控制芯片U1’内部的振荡器产生一个工作频率，变换器会工作在该频率下，此时属于降频模式。当控制芯片U1’检测到FB电压高于2.5V，则波谷开通功能有效，输入电压经过分压电阻R2、R3分压后给控制芯片U1’的UVP脚采样，检测输入电压对应的是哪一个波谷档位，确定了波谷档位以后控制芯片U1’的DRIN脚检测谐振波谷，当检测到一个波谷就进行一次计数，当计数数量和输入电压对应的波谷档位对应的波谷数量符合，则控制芯片U1’内部会产生一个驱动信号驱动内置的MOS管开通，实现波谷控制。
以上仅是本发明的优选实施方式，应当指出的是，上述优选实施方式不应视为对本发明的限制，对于本技术领域的普通技术人员来说，在不脱离本发明的精神和范围内，还可以做出若干改进和润饰，对电路进行改进和润饰也应视为本发明的保护范围，这里不再用实施例赘述，本发明的保护范围应当以权利要求所限定的范围为准。

Claims (9)

  1. 一种波谷控制电路，适用于对反激变换器的主功率开关管开关周期的波谷谐振进行控制，包括电流检测电路、副边反馈电路和驱动输出电路，电流检测电路用于检测开关管的源极的原边峰值电流；副边反馈电路用于接收电压采样隔离反馈电路反馈的反映负载大小的电压信号；驱动输出电路用于向开关管输出驱动信号，其特征在于：
    还包括输入电压检测电路和波形检测电路；
    输入电压检测电路，用于检测反激变换器的输入电压；
    波形检测电路，用于采样开关管漏极的波形，并对波谷数量进行计数；其中，
    波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
  2. 根据权利要求1所述的波谷控制电路，其特征在于：还包括分压电路，分压电路并联在反激变换器的输入正端与地之间，包括电阻R2、电阻R3和电容C4，电阻R2与电阻R3依次串联，串联连接点形成分压点，电容C4并联在电阻R3的两端；所述输入电压检测电路的输入端与分压电路的分压点连接。
  3. 一种波谷控制电路，适用于反激变换器的主功率管开关周期的波谷谐振进行控制，为集成芯片结构，包括接地引脚、副边反馈引脚、电流检测引脚和驱动输出引脚，接地引脚用于接地；电流检测引脚用于与开关管的源极连接，检测原边峰值电流；副边反馈引脚用于与电压采样隔离反馈电路连接，接收其反馈的反映负载大小的电压信号；驱动输出引脚用于向开关管输出驱动信号，其特征在于：
    还包括输入电压检测引脚和波形检测引脚，
    输入电压检测引脚，用于检测反激变换器的输入电压；
    波形检测引脚，用于采样开关管漏极的波形，并对波谷数量进行计数；其中，
    波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
  4. 根据权利要求3所述的波谷控制电路，其特征在于：还包括分压电路，分压电路并联在反激变换器的输入正端与地之间，包括电阻R2、电阻R3和电容C4，电阻R2与电阻R3依次串联，串联连接点形成分压点，电容C4并联在电阻R3的两端；所述输入电压检测引脚与分压电路的分压点连接。
  5. 一种波谷控制电路，适用于反激变换器的主功率管开关周期的波谷谐振进行控制，为集成芯片结构，包括接地引脚和副边反馈引脚，接地引脚用于接地；副边反馈引脚用于与电压采样隔离反馈电路连接，接收其反馈的反映负载大小的电压信号，其特征在于：
    还包括开关管和电阻R4，以及输入电压检测引脚和开关管漏极引脚，
    开关管和电阻R4集成于芯片内；
    输入电压检测引脚，用于检测反激变换器的输入电压；
    开关管漏极引脚，用于采样内置开关管漏极的波形，并提供给波谷控制电路以对波谷数量进行计数；其中，
    波谷控制电路控制开关管开关周期的波谷数量随输入电压的变化而变化。
  6. 根据权利要求5所述的波谷控制电路，其特征在于：还包括分压电路，分压电路并联在反激变换器的输入正端与地之间，包括电阻R2、电阻R3和电容C4，电阻R2与电阻R3依次串联，串联连接点形成分压点，电容C4并联在电阻R3的两端；所述输入电压检测引脚与分压电路的分压点连接。
  7. 一种波谷控制方法，适用于反激变换器的主功率开关管开关周期的波谷谐振进行控制，在反馈电压高于负载参考电压时，进入波谷控制模式，即控制开关管开关周期的波谷数量随输入电压的变化而变化，具体包括如下步骤，
    输入电压检测步骤，检测反激变换器的输入电压信号，并依输入电压的档位划分设定开关管开关周期的波谷数量；
    波谷开通控制步骤，采样开关管漏极的波形，并对波谷进行计数；在波谷数量达到设定值时，控制开关管开通。
  8. 根据权利要求7所述的波谷控制方法，其特征在于：所述波谷控制模式，控制开关管开关周期的波谷数量随着输入电压的升高而增加。
  9. 根据权利要求7或8所述的波谷控制方法，其特征在于：所述波谷控制模式，在输入电压不变、负载增加时，波谷数量不变，仅由随负载增加的原边峰值电流增加开关管开关周期的导通时间和消磁时间，自然调节开关管开关周期变长、开关管工作频率降低。
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