WO2019061590A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2019061590A1
WO2019061590A1 PCT/CN2017/106959 CN2017106959W WO2019061590A1 WO 2019061590 A1 WO2019061590 A1 WO 2019061590A1 CN 2017106959 W CN2017106959 W CN 2017106959W WO 2019061590 A1 WO2019061590 A1 WO 2019061590A1
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Prior art keywords
thin film
film transistor
area
pixel
current row
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PCT/CN2017/106959
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English (en)
French (fr)
Inventor
张婷婷
王聪
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武汉华星光电技术有限公司
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Priority to US15/737,308 priority Critical patent/US10366667B2/en
Publication of WO2019061590A1 publication Critical patent/WO2019061590A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel. ⁇ Background technique ⁇
  • the thin film transistors used in liquid crystal displays usually have amorphous silicon thin film transistors and polycrystalline silicon thin film transistors, wherein the amorphous silicon thin film transistors have low mobility and severe photodegradation with increasing use time; and LTPS (Low Temperature Poly- Silicon, low temperature polysilicon technology) has high mobility and stability.
  • LTPS Low Temperature Poly- Silicon, low temperature polysilicon technology
  • the unidirectionally driven interlaced scanning mode is usually adopted, that is, GOA is provided on both the left and right sides.
  • the interval is turned on according to the timing of the scan line scan. Due to the resistance-capacitance delay on the scan line, there is a difference between the start and end of the scan line, which directly affects the pixel voltage of the pixel unit at the beginning and end of the scan line. The larger the panel is, the longer the scan line is, the more severe the resistance-capacitance delay will be.
  • the pixel voltage difference between the pixel units at both ends of the scan line will be more obvious, which will cause the brightness on both sides of the panel to be greater than the middle brightness, and display unevenness will occur.
  • the technical problem to be solved by the present invention is to provide an array substrate and a display panel, which can improve the uniformity of the display panel and improve the display quality of the panel.
  • an array substrate including:
  • Each pixel unit of the second region of TN2017/106959 includes a first thin film transistor and a control unit connected to the first thin film transistor, the control unit is configured to reduce a pixel unit where the first thin film transistor is located a pixel voltage; each of the pixel units of the first region includes a second thin film transistor.
  • another technical solution to be used in the present invention is to provide a display panel comprising the array substrate as described above.
  • the invention reduces the pixel voltage of the pixel unit of the second region by setting the control unit in each pixel unit of the second region away from the input end of the scan signal, so that the pixel voltages of the plurality of pixel units are consistent, and the left and right sides of the panel are solved.
  • the white problem makes the display panel display more uniform and the display quality is higher.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of a pixel unit of a second region in an embodiment of the array substrate of the present invention
  • FIG. 3 is a schematic diagram of driving waveforms of a pixel unit of a first region in an embodiment of the array substrate of the present invention
  • FIG. 5 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • FIG. 6 is a schematic structural view of a pixel unit of a first region of another embodiment of the array substrate of the present invention.
  • FIG. 7 is a schematic structural view of an embodiment of the display panel of the present invention.
  • the array substrate of the first embodiment includes:
  • a plurality of scanning lines Gn in this embodiment, the scanning lines G1 to G5 are taken as an example for description;
  • a plurality of data lines Dn this embodiment takes the data lines D1 to D10 as an example for description, and multiple scans. Lines Gn intersect to form a plurality of pixel units 10;
  • the plurality of pixel units 10 are divided into a first area A and a second area B along the direction of the scanning line Gn.
  • the first area A is close to the scanning signal input end, and the second area B is away from the scanning signal input end.
  • Each of the pixel units 101 of the second region B includes a first thin film transistor T1 and a control unit 1011 connected to the first thin film transistor T1, and the control unit 1011 is configured to reduce the pixel voltage of the pixel unit 101 where the first thin film transistor is located;
  • Each of the pixel units 102 of the region A includes a second thin film transistor T2.
  • the array substrate is interlaced by the GOA driving circuit (not shown) on both sides, that is, the right GOA driving circuit inputs the scanning signal to the odd-numbered scanning lines, and the left GOA driving circuit to the even-numbered lines.
  • the scan line inputs the scan signal, and the scan signals of the odd line and the even line are alternately input in sequence.
  • the scanning signal may be input to the even-numbered row scanning lines through the GOA driving circuit on the right side, and the scanning signals may be input to the odd-numbered scanning lines through the GOA circuit on the left side.
  • the first region ⁇ and the second region ⁇ may be divided by a middle line, that is, a midpoint line of each scan line Gn.
  • the current line scan signal is input from the right side, and the plurality of pixel units 10 on the right half side are the first A region A, the plurality of pixel units 10 on the left half side are the second region B; or may be divided by the white area of the current line, for example, the current line scan signal is input from the right side, and the left edge of the current line is whitened.
  • the area is divided into the second area B, and the right edge in the current line, that is, the area where the current line is not whitened, is divided into the first area A; and the white area of different lines may be divided, for example, the current scan signal is input from the right side.
  • the area where the left edge of the current line is whitened is divided into the second area B, and the area corresponding to the next line of whitening is divided into the first area A.
  • the control unit 1011 includes a third thin film transistor T3 and a first capacitor C1, and the drain of the third thin film transistor T1 is connected to the pixel of the third thin film transistor T3.
  • the pixel electrode of the unit 101, the gate of the third thin film transistor T3 is connected to the next row of scan lines G2, and the source of the third thin film transistor T3 is grounded through the first capacitor C1, wherein the first capacitor C1 is sourced by the first thin film transistor T1.
  • the pole is equivalent to the common electrode.
  • the pixel unit 101 of the second region B further includes a first liquid crystal capacitor C2 and a first storage capacitor C 3 , a source of the first thin film transistor T1 Connected to the data line m, the gate of the first thin film transistor Ti is connected to the current scan line Gi, and the drain of the first thin film transistor Ti is connected to the pixel electrode of the pixel unit 101 where the first thin film transistor T1 is located, wherein the first liquid crystal capacitor
  • the pixel electrode of the pixel unit 101 where the first thin film transistor T1 is located is equivalent to the common electrode of the color filter substrate (not shown), and the first storage capacitor C3 is composed of the pixel of the pixel unit 101 where the first thin film transistor T1 is located.
  • the electrodes are equivalent to other metal lines on the array substrate.
  • the drain of the third thin film transistor T3 is connected between one end of the first liquid crystal capacitor C2 and one end of the first storage capacitor C3.
  • the scan signal V g l is input to the current scan line G1, that is, the scan line G1 inputs the scan signal on the right side.
  • the third thin film transistor T3 of the current row is turned off, the current row
  • the first thin film transistor T1 is turned on, and the second thin film transistor T2 of the current row is turned on;
  • the input end of the scan line G2 of the next row is opposite to the input end of the current scan line G1, that is, the scan line G2 inputs the scan signal on the left side
  • the lower B unit pixel region on the second row scanning line G2 cell 101 and the current pixel of the second region B on the scanning line G1 101 are located in different data line; in this next line scanning signal input scanning line G2 V g 2, in the pixel unit 101 of the second region B, the third thin film transistor T3 is turned on, the first thin film transistor T1 of the current row is turned off, the second thin film transistor T2 of the current row is turned off, and the third thin film
  • the third thin film transistor T3 is turned off, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned on, and the data line D1 is input with voltage, and then the second The source voltage of the first thin film transistor T1 in the pixel unit 101 of the region B is V d l , the gate voltage is Vg ir , and the pixel voltage (ie, the drain voltage) is ⁇ 11'; the pixel unit in the first region A
  • the thin film transistor T2 in 102 has a source voltage of V d 2 , a gate voltage of V g ll , and a pixel voltage (ie, a drain voltage) of 11; then the scan signal V g l on the current scan line G1 is turned off, so that A thin film transistor T1 is turned off, at this time, the first thin film transistor 1 in the pixel unit 101 of the second region B has a source voltage of V d l ,
  • the pixel unit 102 in the first area A is close to the scan signal V g l, and when the first thin-moon transistor T1 and the second thin film transistor T2 are turned off, ⁇ falls in a short time, so that V g ll and V
  • the difference of g 12 is large, that is, the feedthrough voltage AV is large, the corresponding pixel voltage V s 12 is small, and the display brightness is normal
  • the pixel unit 101 of the second region B is away from the scan signal V g l , when the first thin film transistor T1 Disconnected from the second thin film transistor T2, the pixel unit 101 of the second region B generates a resistance-capacitance delay, and the V g ' drop delays, so that the difference between V g l l ' and V g 12' is small, that is, the feed-through voltage AV 'Smaller, the corresponding pixel voltage V s 12' is larger, the display brightness is higher, and a bright spot appears on the screen.
  • the pixel voltage V s 12' of the pixel unit 101 of the second region B is pulled low according to the charge sharing principle, and is pulled low.
  • the pixel voltage of the pixel unit 101 of the second region B (not shown) is equal to the value of the pixel voltage V s 12 of the pixel unit 102 of the first region A. Since the time interval between the scan signal on the current scan line G1 and the scan signal V K 2 input from the next scan line G2 is short, the human eye cannot distinguish, and the user can see the second region after being applied by the third thin film transistor T3.
  • the pixel unit 101 of B and thus the display luminance of the pixel unit 101 of the second region B is the same as the display luminance of the pixel unit 102 of the first region A.
  • the plurality of rows of scan lines are sequentially scanned, and the pixel voltage in the pixel unit 101 of the second region B near the input end of the scan signal is pulled down by the third thin film transistor T3 in the pixel unit 101 of the second region B.
  • the pixel voltage in the pixel unit 101 of the second region B is made equal to the pixel voltage in the pixel unit 102 of the first region A, and the luminances on both sides are the same.
  • the pixel voltage of the pixel unit in the second region is reduced, so that the pixel voltages of the plurality of pixel units are consistent, and the left and right sides of the panel are solved.
  • the whitening problem on the side makes the display panel display more uniform and the display quality is higher.
  • the present invention further provides the array substrate of the second embodiment.
  • the array substrate disclosed in this embodiment includes: 106959 multiple scanning lines Gn, this embodiment takes the scanning lines G1 to G5 as an example for description;
  • the present embodiment is described by taking the data lines D1 to D10 as an example, and intersecting with the plurality of scanning lines Gn to form a plurality of pixel units 10;
  • the plurality of pixel units 10 are divided into a first area A and a second area B along the direction of the scanning line Gn.
  • the first area A is close to the scanning signal input end, and the second area B is away from the scanning signal input end.
  • Each of the pixel units 101 of the second region B includes a first thin film transistor T1 and a control unit 1011 connected to the first thin film transistor T1, and the control unit 1011 is configured to reduce the pixel voltage of the pixel unit 101 where the first thin film transistor T1 is located;
  • Each of the pixel units of a region A includes a second thin film transistor T2 and a fourth thin film transistor T4.
  • each pixel unit of the first region ⁇ further includes a second liquid crystal capacitor C4, a second storage capacitor C5, a second capacitor C6, and a third capacitor C7, and a source of the second thin film transistor T2 is connected to the data line D6.
  • the gate of the second thin film transistor T2 is connected to the current scan line G1
  • the drain of the second thin film transistor T2 is connected to the pixel electrode of the pixel unit 102 where the second thin film transistor T2 is located, wherein the second liquid crystal capacitor C4 is formed by the second film.
  • the pixel electrode of the pixel unit 102 where the transistor T2 is located is equivalent to the common electrode of the color filter substrate (not shown), and the second storage capacitor C5 is formed by the pixel electrode of the pixel unit 102 of the second thin film transistor T2 and the array substrate.
  • the equivalent of other metal wires The gate of the fourth thin film transistor T4 is connected to the next row of scan lines, the source of the fourth thin film transistor T4 is grounded through the second capacitor C6, and the drain of the fourth thin film transistor T4 is grounded through the third capacitor C7, wherein the second capacitor C6
  • the source of the fourth thin film transistor T4 is equivalent to the common electrode, and the third capacitor C7 is constituted by the drain of the fourth thin film transistor T4 and the common electrode.
  • the fourth thin film transistor T4 is disposed in the pixel unit 102 of the first area A to adjust the control unit 1011 and the fourth thin film transistor ⁇ 4 according to the input direction of the scan line.
  • the connection ensures the consistency of the LCD panel.
  • a thin film transistor is disposed in each pixel unit of the first region near the input end of the scan signal, and the pixel voltage of the second region is reduced.
  • the present invention further provides a display panel according to an embodiment.
  • an embodiment of the display panel of the present invention includes:
  • first substrate 701 is an array substrate
  • the array substrate is the array substrate disclosed in the above embodiment. This will not be repeated here.
  • the pixel voltage of the pixel unit in the second region is reduced, so that the pixel voltages of the plurality of pixel units are consistent, and the left and right sides of the panel are solved.
  • the whitening problem on the side makes the display panel display more uniform and the display quality is higher.

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Abstract

一种阵列基板及显示面板，阵列基板包括多条相交设置的扫描线和数据线，以形成多个像素单元（10）；将多个像素单元（10）沿着扫描线划分为第一区域（A）和第二区域（B），第一区域（A）靠近扫描信号输入端，第二区域（B）远离扫描信号输入端，第二区域（B）的每个像素单元（101）包括第一薄膜晶体管（T1）和与第一薄膜晶体管（T1）连接的控制单元（1011），控制单元（1011）用于减小第一薄膜晶体管（T1）所在像素单元（101）的像素电压。能够改善显示面板均一性的效果，提升面板的显示质量。

Description

一种阵列基板及显示面板
【技术领域】
本发明涉及显示技术领域， 特别涉及一种阵列基板及显示面板。 【背景技术】
液晶显示器中使用的薄膜晶体管通常有非晶硅薄膜晶体管和多晶硅薄膜 晶体管， 其中， 非晶硅薄膜晶体管随着使用时间的增加， 其迁移率低， 光敏退 化性严重； 而 LTPS ( Low Temperature Poly-silicon, 低温多晶硅技术）则具有较 高的迁移率和稳定性。
本申请的发明人在长期的研发中发现， 目前 LTPS 面板进行 GOA ( Gate Driver on Array, 阵列基板栅极驱动）设计时， 通常采用单向驱动的隔行扫描模 式， 即左右两侧都设有 GOA, 按照扫描线扫描的时序进行间隔开启。 由于扫描 线上存在电阻 -电容延迟， 扫描线起始端与末端的信号就会存在差异， 直接影响 到扫描线起始端与末端的像素单元的像素电压。 面板越大， 扫描线越长， 电阻- 电容延迟就会越严重， 扫描线两端的像素单元的像素电压差异就会越明显， 导 致面板两侧的亮度大于中间的亮度， 出现显示不均。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及显示面板， 能够改善显 示面板均一性的效果， 提升面板的显示质量。
为解决上述技术问题， 本发明采用的一个技术方案是提供一种阵列基板， 包括：
多条扫描线；
多条数据线， 与所述多条扫描线相交设置， 以形成多个像素单元； 其中， 将所述多个像素单元沿着所述扫描线划分为第一区域和第二区域， 所述第一区域靠近扫描信号输入端， 所述第二区域远离所述扫描信号输入端， T N2017/106959 所述第二区域的每个像素单元包括第一薄膜晶体管和与所述第一薄膜晶体管连 接的控制单元， 所述控制单元用于减小所述第一薄膜晶体管所在像素单元的像 素电压； 所述第一区域的每个像素单元包括第二薄膜晶体管。
为解决上述技术问题， 本发明釆用的另一个技术方案是提供一种显示面板， 包括如上述的阵列基板。
本发明通过在远离扫描信号输入端的第二区域的每个像素单元设置控制单 元， 减小第二区域的像素单元的像素电压， 以使多个像素单元的像素电压一致， 解决面板左右两侧泛白的问题， 使显示面板的显示效果更均匀， 显示画面质量 更高。
【附图说明】
图 1是本发明阵列基板一实施例的结构示意图；
图 2是本发明阵列基板一实施例中第二区域的像素单元的结构示意图； 图 3是本发明阵列基板一实施例中第一区域的像素单元的驱动波形示意图； 图 4是本发明阵列基板一实施例中第二区域的像素单元的驱动波形示意图； 图 5是本发明阵列基板另一实施例的结构示意图；
图 6是是本发明阵列基板另一实施例的第一区域的像素单元的结构示意图； 图 7是本发明显示面板实施例的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行清 楚、 完整地描述。
本发明提供第一实施例的阵列基板。请参见图 1， 本实施例所揭示的阵列基 板包括：
多条扫描线 Gn， 本实施例以扫描线 G1至 G5为例进行说明；
多条数据线 Dn, 本实施例以数据线 D1至 D10为例进行说明， 与多条扫描 线 Gn相交设置， 以形成多个像素单元 10;
其中， 将多个像素单元 10沿着扫描线 Gn的方向划分为第一区域 A和第二 区域 B， 第一区域 A靠近扫描信号输入端， 第二区域 B远离所述扫描信号输入 端。第二区域 B的每个像素单元 101包括第一薄膜晶体管 T1和与第一薄膜晶体 管 T1连接的控制单元 1011 , 控制单元 1011用于减小第一薄膜晶体管所在像素 单元 101的像素电压；第一区域 A的每个像素单元 102包括第二薄膜晶体管 T2。
具体的， 阵列基板在两侧 GOA驱动电路（图中未示出）的驱动下进行隔行 扫描， 即右侧的 GOA驱动电路向奇数行扫描线输入扫描信号， 左侧的 GOA驱 动电路向偶数行扫描线输入扫描信号， 且奇数行和偶数行的扫描信号依次交替 输入。
可选的， 也可以通过右侧的 GOA驱动电路向偶数行扫描线输入扫描信号， 通过左侧的 GOA电路向奇数行扫描线输入扫描信号。
其中， 第一区域 Α和第二区域 Β可以以中间线， 即每条扫描线 Gn的中点 连线划分， 例如当前行扫描信号从右侧输入， 右半侧的多个像素单元 10为第一 区域 A, 左半侧的多个像素单元 10为第二区域 B; 也可以以当前行的泛白区域 划分， 例如当前行扫描信号从右侧输入， 将当前行中左侧边缘泛白的区域划分 为第二区域 B,将当前行中右侧边缘，即当前行无泛白的区域划分为第一区域 A; 还可以以不同行的泛白区域划分， 例如当前扫描信号从右侧输入， 将当前行中 左侧边缘泛白的区域划分为第二区域 B，将对应下一行泛白的区域划分为第一区 域 A。
参见图 1至图 4， 在第二区域 B的像素单元 101中， 控制单元 1011包括第 三薄膜晶体管 T3和第一电容 C1 , 第三薄膜晶体管 T1的漏极连接第三薄膜晶体 管 T3所在的像素单元 101的像素电极， 第三薄膜晶体管 T3的栅极连接下一行 扫描线 G2, 第三薄膜晶体管 T3的源极通过第一电容 C1接地， 其中， 第一电容 C1由第一薄膜晶体管 T1的源极与公共电极等效构成。 第二区域 B的像素单元 101还包括第一液晶电容 C2以及第一存储电容 C3， 第一薄膜晶体管 T1的源极 与数据线 m连接， 第一薄膜晶体管 Ti的栅极与当前的扫描线 Gi连接， 第一 薄膜晶体管 Ti的漏极连接第一薄膜晶体管 T1所在像素单元 101的像素电极， 其中， 第一液晶电容 C2由第一薄膜晶体管 T1所在像素单元 101的像素电极和 彩膜基板（图中未示出）上的公共电极等效构成， 第一存储电容 C3由第一薄膜 晶体管 T1所在像素单元 101的像素电极与阵列基板上的其他金属线等效构成。
其中， 第三薄膜晶体管 T3的漏极连接在第一液晶电容 C2的一端和第一存 储电容 C3的一端之间。
在当前的扫描线 G1输入扫描信号 Vgl， 即扫描线 G1在右侧输入扫描信号， 此时第二区域 B的像素单元 101中， 当前行的第三薄膜晶体管 T3断开， 当前行 的第一薄膜晶体管 T1导通， 当前行的第二薄膜晶体管 T2导通； 下一行扫描线 G2的输入端与当前扫描线 G1的输入端相反，即扫描线 G2在左侧输入扫描信号， 且下一行扫描线 G2上的第二区域 B的像素单元 101与当前扫描线 G1上的第二 区域 B的像素单元 101位于不同的数据线上；在当前行的下一行扫描线 G2输入 扫描信号 Vg2 , 此时第二区域 B的像素单元 101中， 第三薄膜晶体管 T3导通， 当前行的第一薄膜晶体管 T1断开， 当前行的第二薄膜晶体管 T2断开， 当前行 的第三薄膜晶体管 T3用于将当前行的像素电压拉低。
具体的， 当前的扫描线 G1输入扫描信号 Vgl时， 第三薄膜晶体管 T3断开， 第一薄膜晶体管 T1导通， 第二薄膜晶体管 T2导通， 数据线 D1输入电压， 此 时第二区域 B的像素单元 101中的第一薄膜晶体管 T1源极电压为 Vdl， 栅极电 压为 Vgir , 像素电压 （即漏极电压） 为\^11'； 第一区域 A中的像素单元 102中 的薄膜晶体管 T2源极电压为 Vd2， 栅极电压为 Vgl l , 像素电压 （即漏极电压） 为 11；然后当前扫描线 G1上的扫描信号 Vgl断开，使第一薄膜晶体管 T1断开， 此时第二区域 B的像素单元 101中的第一薄膜晶体管 1源极电压为 Vdl， 栅极电 压为 V 12' ,像素电压为 V 12' ; 第一区域 A中的像素单元 102中的薄膜晶体管 T2 源极电压为 Vd2 , 栅极电压为 Vg12， 像素电压 （即漏极电压） 为^12； 由于第二 区域 B的像素单元 101内的元件会在高频下产生电容联系，即产生寄生电容 Cgs， 根据电荷不减定律， 馈通（ feed through ) AV=(Vgl l-Vg12)*Cgs / (Cgs+C2+C3) ; 同时馈通电压 AV=Vd - Vs12， 所以 Vs12 = Vd -(Vgl l-Vg12)*Cgs / (Cgs+C2+C3)。
具体的， 第一区域 A中的像素单元 102靠近扫描信号 Vgl， 当第一薄月 晶体 管 T1和第二薄膜晶体管 T2断开， ^在很短的时间内下降， 使得 Vgl l与 Vg12的 差值较大， 即馈通电压 AV较大， 对应像素电压 Vs12较小， 显示亮度正常； 第二 区域 B的像素单元 101远离扫描信号 Vgl， 当第一薄膜晶体管 T1和第二薄膜晶 体管 T2断开， 第二区域 B的像素单元 101产生电阻电容延迟， Vg'下降延緩， 使得 Vgl l'与 Vg12'的差值较小， 即馈通电压 AV'较小， 对应像素电压 Vs12'较大， 显示亮度较高， 在屏幕上出现亮点。 当下一行扫描线 G2输入扫描信号 Vg2 , 第 三薄膜晶体管 T3导通，根据电荷共享原理， 将第二区域 B的像素单元 101的像 素电压 Vs12'拉低， 并且被拉低后的第二区域 B的像素单元 101的像素电压 （图 中未示出） 与第一区域 A.的像素单元 102的像素电压 Vs12的值相等。 由于当前 扫描线 G1上的扫描信号 与下一行扫描线 G2的扫描信号 VK2输入的时间间隔 较短， 人眼无法分辨， 用户能够看到的是经过第三薄膜晶体管 T3作用后第二区 域 B的像素单元 101 , 因此第二区域 B的像素单元 101的显示亮度与第一区域 A的像素单元 102的显示亮度相同。 类似的， 多行扫描线依次扫描， 在第二区 域 B的像素单元 101中的第三薄膜晶体管 T3的作用下，拉低靠近扫描信号输入 端的第二区域 B的像素单元 101中的像素电压，使得第二区域 B的像素单元 101 中的像素电压与第一区域 A的像素单元 102中的像素电压相等， 两侧显示亮度 相同。
本发明实施例通过在远离扫描信号输入端的第二区域的每个像素单元设置 控制单元， 减小第二区域的像素单元的像素电压， 以使多个像素单元的像素电 压一致， 解决面板左右两侧泛白的问题， 使显示面板的显示效果更均匀， 显示 画面质量更高。
本发明进一步提供第二实施例的阵列基板。 请参见图 5和图 6, 本实施例所 揭示的阵列基板包括： 106959 多条扫描线 Gn， 本实施例以扫描线 G1至 G5为例进 4亍说明；
多条数据线 Dn， 本实施例以数据线 D1至 D10为例进行说明， 与多条扫描 线 Gn相交设置， 以形成多个像素单元 10;
其中， 将多个像素单元 10沿着扫描线 Gn的方向划分为第一区域 A和第二 区域 B， 第一区域 A靠近扫描信号输入端， 第二区域 B远离所述扫描信号输入 端。第二区域 B的每个像素单元 101包括第一薄膜晶体管 T1和与第一薄膜晶体 管 T1连接的控制单元 1011，控制单元 1011用于减小第一薄膜晶体管 T1所在像 素单元 101 的像素电压； 第一区域 A的每个像素单元包括第二薄膜晶体管 T2 和第四薄膜晶体管 Τ4。
具体的， 第一区域 Α的每个像素单元还包括第二液晶电容 C4、 第二存储电 容 C5、 第二电容 C6和第三电容 C7， 第二薄膜晶体管 T2的源极与数据线 D6 连接， 第二薄膜晶体管 T2的栅极与当前的扫描线 G1连接， 第二薄膜晶体管 T2 的漏极连接第二薄膜晶体管 T2所在的像素单元 102的像素电极， 其中， 第二液 晶电容 C4由第二薄膜晶体管 T2所在像素单元 102的像素电极和彩膜基板 (图 中未示出） 上的公共电极等效构成， 第二存储电容 C5由第二薄膜晶体管 T2所 在像素单元 102 的像素电极与阵列基板上的其他金属线等效构成。 第四薄膜晶 体管 T4的栅极连接下一行扫描线， 第四薄膜晶体管 T4的源极通过第二电容 C6 接地， 第四薄膜晶体管 T4的漏极通过第三电容 C7接地， 其中， 第二电容 C6 由第四薄膜晶体管 T4的源极与公共电极等效构成， 第三电容 C7由第四薄膜晶 体管 T4的漏极与公共电极等效构成。 由于制备阵列基板时并不确定当前扫描线 的输入方向， 所以在第一区域 A的像素单元 102中设置第四薄膜晶体管 T4， 以 根据扫描线的输入方向调整控制单元 1011和第四薄膜晶体管 Τ4的连接， 同时 保证了液晶面板的一致性。
本发明实施例通过在远离扫描信号输入端的第二区域的每个像素单元设置 控制单元， 在靠近扫描信号输入端的第一区域的每个像素单元设置薄膜晶体管， 减小第二区域的的像素电压， 以使多个像素单元的像素电压一致， 保持面板的 一致性， 解决面板左右两侧泛白的问题， 使显示面板的显示效果更均匀， 显示 画面质量更高。
本发明进一步提供一实施例的显示面板， 请参见图 7， 本发明显示面板实施 例包括：
第一基板 701、第二基板 702和位于第一基板 701和第二基板 702之间的液 晶层 703 , 其中第一基板 701为阵列基板， 该阵列基板为上述实施例所揭示的阵 列基板， 在此不再赘述。
本发明实施例通过在远离扫描信号输入端的第二区域的每个像素单元设置 控制单元， 减小第二区域的像素单元的像素电压， 以使多个像素单元的像素电 压一致， 解决面板左右两侧泛白的问题， 使显示面板的显示效果更均匀， 显示 画面质量更高。
以上所述仅为本发明的实施方式， 并非因此限制本发明的专利范围， 凡是 利用本发明说明书及附图内容所作的等效结构或等效流程变换， 或直接或间接 运用在其他相关的技术领域， 均同理包括在本发明的专利保护范围内。

Claims

权利要求书
一种阵列基板， 其中， 所述阵列基板包括：
多条扫描线；
多条数据线， 与所述多条扫描线相交设置， 以形成多个像素单元 其中， 将所述多个像素单元沿着所述扫描线划分为第一区域和第 二区域， 所述第一区域靠近扫描信号输入端， 所述第二区域远离 所述扫描信号输入端， 所述第二区域的每个像素单元包括第一薄 膜晶体管和与所述第一薄膜晶体管连接的控制单元， 所述控制单 元用于减小所述第一薄膜晶体管所在像素单元的像素电压； 所述 第一区域的每个像素单元包括第二薄膜晶体管；
其中， 所述控制单元包括第三薄膜晶体管和第一电容， 所述第三 薄膜晶体管的漏极连接所述第三薄膜晶体管所在像素单元的像素 电极， 所述第三薄膜晶体管的栅极连接下一行扫描线； 所述第一区域的每个像素单元还包括第四薄膜晶体管， 所述第四 薄膜晶体管的栅极连接下一行扫描线。
根据权利要求 1所述的阵列基板， 其中， 所述所述第一薄膜晶体管 的源极与所述数据线连接， 所述第一薄膜晶体管的栅极与当前行 的扫描线连接， 所述第二薄膜晶体管的漏极连接所述第一薄膜晶 体管所在像素单元的的像素电极。
根据权利要求 2所述的阵列基板， 其中， 在所述当前行的扫描线输 入扫描信号吋， 所述当前行的第三薄膜晶体管断幵， 所述当前行 的第一薄膜晶体管导通， 所述当前行的第二薄膜晶体管导通； 在 所述当前行的下一行扫描线输入扫描信号吋， 所述当前行的第三 薄膜晶体管导通， 所述当前行的第一薄膜晶体管断幵， 所述当前 行的第二薄膜晶体管断幵， 所述当前行的第三薄膜晶体管用于将 所述当前行的像素电压拉低。
根据权利要求 3所述的阵列基板， 其中， 所述位于第二区域的第三 薄膜晶体管用于将所述当前行的像素电压拉低至与所述第一区域 的像素单元的像素电压相同。
根据权利要求 1所述的阵列基板， 其中， 所述第一区域和所述第二 区域以每条所述扫描线的中点连线划分。
根据权利要求 1所述的阵列基板， 其中， 所述第一区域与所述第二 区域以当前行的泛白区域划分， 所述第一区域为对应当前行无泛 白的区域， 所述第二区域为对应当前行泛白的区域。
根据权利要求 1所述的阵列基板， 其中， 所述第一区域与所述第二 区域以不同行的泛白区域划分， 所述第一区域为对应当前行的下 一行泛白的区域， 所述第二区域为对应当前行泛白的区域。
一种阵列基板， 其中， 所述阵列基板包括：
多条扫描线；
多条数据线， 与所述多条扫描线相交设置， 以形成多个像素单元 其中， 将所述多个像素单元沿着所述扫描线划分为第一区域和第 二区域， 所述第一区域靠近扫描信号输入端， 所述第二区域远离 所述扫描信号输入端， 所述第二区域的每个像素单元包括第一薄 膜晶体管和与所述第一薄膜晶体管连接的控制单元， 所述控制单 元用于减小所述第一薄膜晶体管所在像素单元的像素电压;所述第 一区域的每个像素单元包括第二薄膜晶体管。
根据权利要求 8所述的阵列基板， 其中， 所述控制单元包括第三薄 膜晶体管和第一电容， 所述第三薄膜晶体管的漏极连接所述第三 薄膜晶体管所在像素单元的像素电极， 所述第三薄膜晶体管的栅 极连接下一行扫描线。
根据权利要求 9所述的阵列基板， 其中， 所述所述第一薄膜晶体管 的源极与所述数据线连接， 所述第一薄膜晶体管的栅极与当前行 的扫描线连接， 所述第二薄膜晶体管的漏极连接所述第一薄膜晶 体管所在像素单元的的像素电极。 根据权利要求 10所述的阵列基板， 其中， 在所述当前行的扫描线 输入扫描信号吋， 所述当前行的第三薄膜晶体管断幵， 所述当前 行的第一薄膜晶体管导通， 所述当前行的第二薄膜晶体管导通； 在所述当前行的下一行扫描线输入扫描信号吋， 所述当前行的第 三薄膜晶体管导通， 所述当前行的第一薄膜晶体管断幵， 所述当 前行的第二薄膜晶体管断幵， 所述当前行的第三薄膜晶体管用于 将所述当前行的像素电压拉低。
根据权利要求 11所述的阵列基板， 其中， 所述位于第二区域的第 三薄膜晶体管用于将所述当前行的像素电压拉低至与所述第一区 域的像素单元的像素电压相同。
根据权利要求 8所述的阵列基板， 其中， 所述第一区域的每个像素 单元还包括第四薄膜晶体管， 所述第四薄膜晶体管的栅极连接下 一行扫描线。
根据权利要求 8所述的阵列基板， 其中， 所述第一区域和所述第二 区域以每条所述扫描线的中点连线划分。
根据权利要求 8所述的阵列基板， 其中， 所述第一区域与所述第二 区域以当前行的泛白区域划分， 所述第一区域为对应当前行无泛 白的区域， 所述第二区域为对应当前行泛白的区域。
根据权利要求 8所述的阵列基板， 其中， 所述第一区域与所述第二 区域以不同行的泛白区域划分， 所述第一区域为对应当前行的下 一行泛白的区域， 所述第二区域为对应当前行泛白的区域。
一种显示面板， 其中， 所述显示面板包括阵列基板， 所述阵列基 板包括：
多条扫描线；
多条数据线， 与所述多条扫描线相交设置， 以形成多个像素单元
其中， 将所述多个像素单元沿着所述扫描线划分为第一区域和第 二区域， 所述第一区域靠近扫描信号输入端， 所述第二区域远离 所述扫描信号输入端， 所述第二区域的每个像素单元包括第一薄 膜晶体管和与所述第一薄膜晶体管连接的控制单元， 所述控制单 元用于减小所述第一薄膜晶体管所在像素单元的像素电压;所述第 一区域的每个像素单元包括第二薄膜晶体管。
[权利要求 18] 根据权利要求 17所述的显示面板， 其中， 所述控制单元包括第三 薄膜晶体管和第一电容， 所述第三薄膜晶体管的漏极连接所述第 三薄膜晶体管所在像素单元的像素电极， 所述第三薄膜晶体管的 栅极连接下一行扫描线。
[权利要求 19] 根据权利要求 18所述的显示面板， 其中， 所述第一薄膜晶体管的 源极与所述数据线连接， 所述第一薄膜晶体管的栅极与当前行的 扫描线连接， 所述第二薄膜晶体管的漏极连接所述第一薄膜晶体 管所在像素单元的的像素电极。
[权利要求 20] 根据权利要求 19所述的显示面板， 其中， 在所述当前行的扫描线 输入扫描信号吋， 所述当前行的第三薄膜晶体管断幵， 所述当前 行的第一薄膜晶体管导通， 所述当前行的第二薄膜晶体管导通； 在所述当前行的下一行扫描线输入扫描信号吋， 所述当前行的第 三薄膜晶体管导通， 所述当前行的第一薄膜晶体管断幵， 所述当 前行的第二薄膜晶体管断幵， 所述当前行的第三薄膜晶体管用于 将所述当前行的像素电压拉低。
10
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109188816B (zh) * 2018-10-26 2021-06-22 昆山龙腾光电股份有限公司 阵列基板及其驱动方法和液晶显示装置及其驱动方法
CN113257134B (zh) * 2021-05-28 2022-06-10 武汉华星光电技术有限公司 显示面板及显示装置
CN114399981B (zh) * 2022-03-01 2023-07-04 Tcl华星光电技术有限公司 显示模组及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101581858A (zh) * 2008-05-16 2009-11-18 群康科技(深圳)有限公司 垂直配向型液晶显示装置及其驱动方法
CN103278951A (zh) * 2012-07-24 2013-09-04 上海天马微电子有限公司 液晶显示装置及其驱动方法
CN103926772A (zh) * 2013-10-07 2014-07-16 上海天马微电子有限公司 Tft阵列基板、显示面板和显示装置
US20140285478A1 (en) * 2013-03-22 2014-09-25 Panasonic Liquid Crystal Display Co., Ltd. Liquid crystal display device and driving method thereof
CN106873273A (zh) * 2017-02-23 2017-06-20 京东方科技集团股份有限公司 阵列基板及其分区驱动方法、显示模组和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7764329B2 (en) * 2005-12-02 2010-07-27 Au Optronics Corp. MVA LCD device and pixel circuit thereof
TWI351571B (en) * 2007-05-22 2011-11-01 Chimei Innolux Corp Active device array substrate,transflective liquid
US20090169622A1 (en) * 2007-12-27 2009-07-02 Roxane Laboratories, Inc. Delayed-release oral pharmaceutical composition for treatment of colonic disorders
KR101469028B1 (ko) * 2008-08-11 2014-12-04 삼성디스플레이 주식회사 표시 장치
KR101590945B1 (ko) * 2009-11-17 2016-02-19 삼성디스플레이 주식회사 액정 표시 장치
KR20120021537A (ko) * 2010-08-06 2012-03-09 삼성전자주식회사 액정 표시 장치
TW201232519A (en) * 2011-01-28 2012-08-01 Chunghwa Picture Tubes Ltd Compensation circuit for a liquid crystal panel
US9542015B2 (en) * 2014-07-14 2017-01-10 Lenovo (Singapore) Pte. Ltd. Pointing device having coupling structure
CN104330910B (zh) * 2014-10-24 2017-02-22 深圳市华星光电技术有限公司 用于曲面屏幕的液晶显示面板
CN104536224B (zh) * 2014-12-31 2017-10-13 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及显示面板
CN104834116B (zh) * 2015-05-26 2019-01-25 深圳市华星光电技术有限公司 一种液晶显示面板及其驱动方法
CN105278192B (zh) * 2015-11-13 2018-08-14 深圳市华星光电技术有限公司 像素驱动电路、阵列基板及液晶面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101581858A (zh) * 2008-05-16 2009-11-18 群康科技(深圳)有限公司 垂直配向型液晶显示装置及其驱动方法
CN103278951A (zh) * 2012-07-24 2013-09-04 上海天马微电子有限公司 液晶显示装置及其驱动方法
US20140285478A1 (en) * 2013-03-22 2014-09-25 Panasonic Liquid Crystal Display Co., Ltd. Liquid crystal display device and driving method thereof
CN103926772A (zh) * 2013-10-07 2014-07-16 上海天马微电子有限公司 Tft阵列基板、显示面板和显示装置
CN106873273A (zh) * 2017-02-23 2017-06-20 京东方科技集团股份有限公司 阵列基板及其分区驱动方法、显示模组和显示装置

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