WO2019061119A1 - 芯片封装模组、移动终端及芯片封装方法 - Google Patents

芯片封装模组、移动终端及芯片封装方法 Download PDF

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Publication number
WO2019061119A1
WO2019061119A1 PCT/CN2017/103867 CN2017103867W WO2019061119A1 WO 2019061119 A1 WO2019061119 A1 WO 2019061119A1 CN 2017103867 W CN2017103867 W CN 2017103867W WO 2019061119 A1 WO2019061119 A1 WO 2019061119A1
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WIPO (PCT)
Prior art keywords
pin
groove
chip
medium
pins
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PCT/CN2017/103867
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English (en)
French (fr)
Inventor
徐家林
Original Assignee
深圳传音制造有限公司
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Publication date
Application filed by 深圳传音制造有限公司 filed Critical 深圳传音制造有限公司
Priority to PCT/CN2017/103867 priority Critical patent/WO2019061119A1/zh
Publication of WO2019061119A1 publication Critical patent/WO2019061119A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads

Definitions

  • the present application relates to the field of chip packaging technologies, and in particular, to a chip package module, a mobile terminal, and a chip packaging method.
  • the chip is one of the most common electronic devices in modern technology. Whether it is a mobile phone, a computer that is common in people's life, or a laser used in industrial production, a CNC machine tool and the like are inseparable from the chip.
  • the chip is generally packaged on a Printed Circuit Board (PCB) by soldering, etc.
  • PCB Printed Circuit Board
  • the chip function is more and more powerful, and the number of pins of the chip is continuously increasing, and the chip is The volume is limited. As the number of pins increases, the spacing between the pins becomes smaller and smaller, which causes the chip to easily cause solder sticking during the process of the chip. The pins are short-circuited with each other, resulting in a defective rate during production. High, increasing production costs.
  • the technical problem to be solved by the present application is to provide a chip package module, a mobile terminal and a chip packaging method, which are used to solve the problem that the chip in the prior art is easy to cause sticking in the process of patching, resulting in a defect rate in production. Too high a problem.
  • the present application provides a chip package module including a chip, a circuit board, and a connection medium.
  • the surface of the chip is provided with a plurality of arrayed pins, and the pins include alternately arranged a pin and a second pin, a surface of the circuit board is provided with a first groove and a connection point between the adjacent first grooves, the first pin and the first concave
  • the connecting medium is correspondingly connected through the connecting medium, and the connecting medium connecting the first pin and the first groove is received in the groove, and the second pin is correspondingly connected to the connecting medium through the connecting medium The connection point.
  • the length of the first pin is not less than the length of the second pin, and the first pin is at least partially received in the first groove.
  • the top surface of the first pin is provided with a protrusion, the protrusion is received in the first groove, and at least part of the connecting medium is received in the protrusion and the inner wall of the first groove between.
  • top surface of the first pin is provided with a recess
  • the recess is received in the first recess
  • at least part of the connecting medium is received in the recess and the inner wall of the first recess between.
  • the first groove includes a side wall connecting the bottom of the groove and the notch, and the side wall is provided with a receiving hole, and at least a portion of the connecting medium is received in the receiving hole.
  • the surface of the circuit board is further provided with a second groove, the second groove is alternately arranged with the first groove, and the second pin and the second groove pass through the connecting medium
  • the connecting medium connecting the second pin and the second groove is at least partially received in the second groove, and the depth of the second groove is not greater than the first groove depth.
  • the length of the first pin is not less than the length of the second pin, the first pin is at least partially received in the first groove, and the second pin is at least partially received in the Said in the second groove.
  • the surface of the circuit board is further provided with a boss, the boss is alternately arranged with the first groove, and the second pin and the boss are correspondingly connected by the connecting medium.
  • the present application further provides a mobile terminal, including the chip package module described in any of the above.
  • the application also provides a chip packaging method, including:
  • the surface of the circuit board is provided with a plurality of first grooves arranged in an array
  • the surface of the chip is provided with a plurality of raised pins
  • the pins include first leads alternately arranged Foot with second pin
  • the chip is attached to the circuit board, the first pin is correspondingly connected to the first groove, and the second pin is correspondingly connected between the adjacent first grooves.
  • the connecting medium is generally a material such as solder
  • the first pin is correspondingly connected to the first groove
  • the connecting medium is at least partially received in the first groove
  • the second pin is corresponding to the first surface of the connecting circuit board.
  • the position between the grooves, the connection medium connecting the first pin and the connection medium connected to the second pin are staggered from each other, thereby avoiding the connection medium connecting the different pins to each other (for example, sticking tin) and improving the product yield.
  • FIG. 1 is a schematic cross-sectional view of a chip package module according to Embodiment 1 of the present application.
  • FIG. 2 is a schematic cross-sectional view of a chip according to Embodiment 1 of the present application.
  • FIG. 3 is a schematic diagram of a surface of a chip according to Embodiment 1 of the present application.
  • FIG. 4 is a schematic cross-sectional view of a circuit board according to Embodiment 1 of the present application.
  • FIG. 5 is a schematic diagram of a surface of a circuit board according to Embodiment 1 of the present application.
  • FIG. 6 is a schematic cross-sectional view showing an embodiment of a chip package module according to Embodiment 1 of the present application.
  • FIG. 7 is a schematic cross-sectional view showing another embodiment of a chip package module according to Embodiment 1 of the present application.
  • FIG. 8 is a schematic cross-sectional view showing another embodiment of a chip package module according to Embodiment 1 of the present application.
  • FIG. 9 is a schematic cross-sectional view showing another embodiment of a chip package module according to Embodiment 1 of the present application.
  • FIG. 10 is a schematic cross-sectional view of a chip package module according to Embodiment 2 of the present application.
  • FIG. 11 is a schematic diagram of a surface of a circuit board according to Embodiment 2 of the present application.
  • FIG. 12 is a schematic cross-sectional view of a chip package module according to Embodiment 3 of the present application.
  • FIG. 13 is a schematic diagram of a surface of a circuit board according to Embodiment 3 of the present application.
  • FIG. 14 is a schematic cross-sectional view showing an embodiment of a chip package module according to Embodiment 3 of the present application.
  • FIG. 15 is a schematic diagram of a mobile terminal according to an embodiment of the present application.
  • a chip package module 100 includes a chip 12 , a circuit board 14 , and a connection medium 20 .
  • the chip 12 is a semiconductor element divided by a wafer.
  • the collective name of a product is also the carrier of an integrated circuit (IC).
  • the chip 12 integrates a variety of electronic components on the silicon board to achieve a specific function. It is the most important part of the electronic device and functions as a computing and storage device.
  • the chip 12 is connected to the circuit board 14 through the connection medium 20.
  • the chip 12 and the circuit board 14 are rigidly connected to form a whole, that is, the chip package module 100; on the other hand, the chip 12 and the circuit board 14 electrical connections to pass signals to each other.
  • the connecting medium 20 is generally made of a metal material having a conductive property, such as solder, etc., and the connecting medium 20 is solidified in a molten state to a solid state, and the chip 12 is rigidly connected to the circuit board 14, while the dielectric 20 is connected to the substrate 20 with good electrical conductivity. It is electrically connected to the circuit board 14.
  • the circuit board 14 is a printed circuit board (PCB). In other embodiments, the circuit board 14 may also be a flexible printed circuit board (FPC).
  • the chip package module 100 is applied to the mobile terminal 200, such as a portable device such as a mobile phone, a tablet computer, a notebook computer, etc.
  • the circuit board 14 can be a main board of the mobile terminal 200, and the chip 12 can be used for controlling the touch screen.
  • the surface of the chip 12 is provided with a plurality of arrays of pins 120.
  • the pins 120 are led out by an integrated circuit inside the chip 12, and the chip 12 includes a first surface for connecting the circuit board 14. 1200, the pins 120 are all located on the first surface 1200, and the distance between the pins 120 is the same, so that the pins 120 are densely attached to the first surface 1200.
  • the pins 120 are all made of metal and each pin 120 has the same shape.
  • the pin 120 includes a first pin 122 and a second pin 124 which are alternately arranged. Specifically, to FIG.
  • a second pin 124 is disposed between each two first pins 122, and each of the two pins 124
  • a first pin 122 is disposed between the second pins 124, and the pins 120 adjacent to each other in the up, down, left, and right directions of the first pin 122 are second pins 124, and each of the second pins 124
  • the pins 120 adjacent in the up, down, left, and right directions are all the first pins 122 to evenly distribute the first pins 122 and the second pins 124.
  • the first pin 122 and the second pin 124 are each connected to the circuit board 14 by a connection medium 20.
  • the surface of the circuit board 14 is provided with a plurality of first grooves 16 arranged in an array and a connection point 162 between the adjacent first grooves 16.
  • the circuit board 14 A second surface 1400 for connecting the chip 12 is included, and the first recess 16 and the connection point 162 are disposed on the second surface 1400.
  • the position of each of the first recesses 16 corresponds to a first pin 122, and the position of each of the second pins 124 corresponds to a connection point 162.
  • the circuit board 14 is provided with a plurality of pads 30 for soldering.
  • the vertical projections of the discs 30 on the second surface 1400 are arranged in an array, and the pads 30 are in one-to-one correspondence with the pins 120. Further, the pads 30 corresponding to the first pins 122 are located at the groove bottoms 160 of the first recesses 16. The pad 30 corresponding to the second pin 124 is located on the first surface 1200 at the position of the connection point 162 and is located between the adjacent first grooves 16. In one embodiment, when the connection medium 20 is in a molten state, it is applied to the top surface 122a of the first pin 122 and the second pin 124. After the first pin 122 is respectively connected to the circuit board 14, the connection medium 20 is connected. Cured.
  • the first pin 122 is connected to the first groove 16 through the connection medium 20, and the connection medium 20 connecting the first pin 122 and the first groove 16 is solidified and then received in the first groove 16.
  • the second pin 124 is connected to the adjacent first groove 16 through the connection medium 20 .
  • the second pin 124 is connected to the second surface 1400 and connects the second pin 124 and the second surface 1400 .
  • the bonding medium 20 is cured on the second surface 1400.
  • connection medium 20 located in the first groove 16 is The connecting medium 20 on the second surface 1400 is also less likely to contact each other, and the sticking phenomenon is less likely to occur.
  • the connecting medium 20 is generally made of solder or the like.
  • the first pin 122 is connected to the first recess 16 , and the connecting medium 20 is at least partially received in the first recess 16 .
  • the second pin 124 corresponds to the first surface of the circuit board 14 .
  • the position between the grooves 16 is such that the connection medium 20 connecting the first pins 122 and the connection medium 20 connecting the second pins 124 are offset from each other, thereby preventing the connection medium 20 connecting the different pins 120 from being connected to each other (for example, sticking tin). To improve product yield.
  • the first pin 122 is gap-fitted with the first recess 16 so that the first recess 16 has sufficient space to accommodate the connection medium 20, and the first pin 122 is prevented from being inserted into the first recess 16 The connecting medium 20 overflows from the first recess 16.
  • the length of the first pin 122 is not less than the length of the second pin 124 , and the first pin 122 is at least partially received in the first groove 16 .
  • the length of the first pin 122 is greater than the length of the second pin 124, when the chip 12 and the circuit board 14 are bonded, the top end of the first pin 122 is inserted into the first groove 16, and the medium 20 is connected.
  • the contact area of one pin 122 is large, and the connection of the first pin 122 to the first groove 16 is stronger.
  • connection medium 20 connecting the first pin 122 and the circuit board 14 is received in the first recess 16, and the connection medium 20 connecting the second pin 124 and the circuit board 14 is located on the second surface 1400, and the connection is different.
  • the connection medium 20 of the foot 120 has a low probability of contact with each other after curing and molding, and the probability of occurrence of sticking phenomenon when the connecting medium 20 is solder is low. Improve product yield.
  • the top surface 122 a of the first pin 122 is provided with a protrusion 202 , and the protrusion 202 is received in the first groove 16 , and at least a part of the connection medium 20 is received in the protrusion 202 and the first Between the inner walls of the recess 16. Specifically, the top surface 122a of the first pin 122 protrudes from the end surface of the first surface 1200, and the vertical projection of the protrusion 202 on the first surface 1200 falls within the range of the first pin 122. And smaller than the size of the first pin 122.
  • the protrusion 202 is inserted into the first recess 16 to further increase the contact area of the first pin 122 with the connection medium 20, so that the connection of the first pin 122 to the groove is stronger.
  • the size of the protrusion 202 is small, the volume of the first groove 16 occupied by the protrusion 202 is small, and the size of the first pin 122 is prevented from being too large, and the volume of the first groove 16 is excessively occupied.
  • the connecting medium 20 in the first recess 16 does not overflow the first recess 16 and is in contact with the connecting medium 20 on the second surface 1400, that is, the sticking phenomenon is avoided.
  • the connection strength between the first chip 12 and the circuit board 14 is improved, and the sticking phenomenon is also avoided, and the product yield is improved.
  • the top surface 122 a of the first pin 122 is provided with a dimple 204 , and the dimple 204 is received in the first recess 16 , and at least a portion of the connecting medium 20 is received in the dimple 204 and the first Between the inner walls of the recess 16. Specifically, the top surface 122a of the first pin 122 protrudes from the end surface of the first surface 1200, and the vertical projection of the recess 204 on the first surface 1200 falls within the range of the first pin 122. And smaller than the size of the first pin 122.
  • the recess 204 is inserted into the first recess 16, and the connecting medium 20 can also flow into the recess 204, further increasing the contact area of the first pin 122 with the connecting medium 20, so that the first pin 122 and the recess are The connection is stronger.
  • the recess 204 since the recess 204 is recessed with the first pin 122, the recess 204 reduces the volume of the first recess 16 after the first pin 122 is inserted into the first recess 16, avoiding the first pin 122.
  • the connecting medium 20 received in the first recess 16 does not overflow the first recess 16 to contact the connecting medium 20 on the second surface 1400, that is, avoid The phenomenon of sticking tin occurs.
  • the connection strength between the first chip 12 and the circuit board 14 is improved, and the sticking phenomenon is also avoided, and the product yield is improved.
  • the top surface 122a of the first pin 122 is simultaneously provided with a plurality of alternately arranged dimples 204 and protrusions 202.
  • the dimples 204 and the protrusions 202 enhance the connection of the first chip 12 to the circuit board 14. At the same time, the sticking phenomenon is avoided and the product yield is improved.
  • the first groove 16 has a tapered cross section, and the groove bottom 160 of the first groove 16 is smaller in size than the notch size of the first groove 16 .
  • the tapered first groove 16 is enlarged
  • the volume of the first recess 16 prevents the connecting medium 20 from overflowing from the first recess 16 to avoid sticking, and facilitates alignment of the first pin 122 with the first recess 16 to improve package efficiency and improve Yield.
  • the first recess 16 includes a sidewall 162 that connects the slot bottom 160 and the slot.
  • the sidewall 162 defines a receiving hole 206 , and at least a portion of the connecting medium 20 is received in the receiving hole 206 .
  • the receiving hole 206 can be a plurality of independent blind holes disposed on the sidewall 162.
  • the receiving hole 206 can also be a strip-shaped blind hole surrounding the sidewall 162.
  • the receiving hole 206 increases the volume of the first recess 16 , and the connecting medium 20 is received in the first recess 16 and does not easily overflow, thereby avoiding the occurrence of sticking and not increasing the slot size of the first recess 16 .
  • the number of pins 120 that can be connected to the second surface 1400 is reduced.
  • the connecting medium 20 is generally made of solder or the like.
  • the first pin 122 is connected to the first recess 16 , and the connecting medium 20 is at least partially received in the first recess 16 .
  • the second pin 124 corresponds to the first surface of the circuit board 14 .
  • the position between the grooves 16 is such that the connection medium 20 connecting the first pins 122 and the connection medium 20 connecting the second pins 124 are offset from each other, thereby preventing the connection medium 20 connecting the different pins 120 from being connected to each other (for example, sticking tin). To improve product yield.
  • the chip package module 100 provided in the second embodiment of the present application is different from the first embodiment in that the surface of the circuit board 14 is further provided with a second recess 18 , and the second recess 18 and the first
  • the grooves 16 are alternately arranged, the second pin 124 and the second groove 18 are correspondingly connected by the connection medium 20, and the connection medium 20 connecting the second pin 124 and the second groove 18 is at least partially received in the second groove 18.
  • the depth of the second groove 18 is not greater than the depth of the first groove 16.
  • the distribution position of the second groove 18 corresponds to the position of the connection point 162 of the first embodiment of the present application.
  • a second recess 18 is disposed between each of the two first recesses 16.
  • a first recess 16 is disposed between each of the two recesses 18, and each of the first recesses 16 is defined.
  • a second groove 18 is disposed in each of the upper and lower left and right directions, and each of the second groove 18 is provided with a first groove 16 in the upper and lower left and right directions to uniformly distribute the first groove 16 and the second groove 18.
  • the connection medium 20 connecting the second pin 124 and the second recess 18 is at least partially received in the second recess 18, so that the connection media 20 connecting the different pins 120 are staggered from each other, thereby avoiding the connection medium 20 connecting the different pins 120. Connected to each other (such as sticking tin) to improve product yield.
  • the length of the first pin 122 is not less than the length of the second pin 124, the first pin 122 is at least partially received in the first recess 16, and the second pin 124 is at least partially received in the second Inside the groove 18.
  • the length of the first pin 122 is greater than the length of the second pin 124, the depth of the first groove 16 is greater than the depth of the second groove 18, and the first pin 122 is inserted into the first groove 16, The second pin 124 is inserted into the second recess 18, and the contact medium 20 connecting the first pin 122 has a larger contact area with the first pin 122, and the first pin 122 is more firmly connected to the first recess 16.
  • connection area of the connection medium 20 connecting the second pin 124 to the second pin 124 is larger, and the connection of the second pin 124 to the second groove 18 is stronger. Further, the connection medium 20 connecting the first pin 122 and the circuit board 14 is received in the first recess 16, and the connection medium 20 connecting the second pin 124 and the circuit board 14 is received in the second recess 18, and is connected.
  • the connection medium 20 of the different pins 120 has a low probability of contact with each other after solidification molding. When the connection medium 20 is soldered, the probability of sticking to the solder is low, and the yield of the product is improved.
  • the top surface 122a of the second pin 124 may also be provided with a protrusion 202 or a recess 204 to increase the contact area of the second pin 124 with the connection medium 20.
  • the surface of the circuit board 14 is further provided with a boss 40 .
  • the boss 40 and the first groove 16 are alternately arranged, and the second pin 124 and the boss 40 are correspondingly connected by the connection medium 20 .
  • the distribution position of the boss 40 corresponds to the position of the connection point 162 of the first embodiment of the present application.
  • a boss 40 is disposed between each of the two first recesses 16, and a first recess 16 is disposed between each of the two bosses 40.
  • Each of the bosses 40 is provided with a first recess 16 for uniformly distributing the first recess 16 and the boss 40.
  • connection medium 20 connecting the second pin 124 and the boss 40 is located on the surface of the boss 40, so that the connection media 20 connecting the different pins 120 are staggered from each other, and the connection medium 20 connecting the different pins 120 is prevented from being connected to each other (for example, soldering tin). Phenomenon), improve product yield.
  • the length of the first pin 122 is greater than the length of the second pin 124 such that the chip 12 is packaged on the circuit board 14 and the surface of the chip 12 is flat.
  • the surface of the boss 40 is provided with a dimple 400 for receiving the connection medium 20 connecting the second pin 124 and further connecting the connection medium of the first pin 122 . 20 is connected to the connecting medium 20 connected to the second pin 124 to avoid sticking and improving the yield of the product.
  • the embodiment of the present application further provides a mobile terminal 200 , which includes the chip package module 100 provided by the embodiment of the present application.
  • the mobile terminal 200 can be a portable device such as a mobile phone, a tablet computer, a notebook computer, etc.
  • the circuit board 14 can be a main board of the mobile terminal 200, and the chip 12 can be used for The touch chip 12 for controlling the touch screen, the display chip 12 for controlling the display screen, and the like.
  • the connecting medium 20 is generally made of solder or the like.
  • the first pin 122 is connected to the first recess 16 , and the connecting medium 20 is at least partially received in the first recess 16 .
  • the second pin 124 corresponds to the first surface of the circuit board 14 .
  • the position between the grooves 16 is such that the connection medium 20 connecting the first pins 122 and the connection medium 20 connecting the second pins 124 are offset from each other, thereby preventing the connection medium 20 connecting the different pins 120 from being connected to each other (for example, sticking tin). To improve product yield.
  • the embodiment of the present application further provides a chip 12 packaging method, and the specific steps include:
  • the surface of the circuit board 14 is provided with a plurality of first grooves 16 arranged in an array.
  • the surface of the chip 12 is provided with a plurality of pins 120 of the protrusions 202, and the pins 120 are arranged alternately.
  • connection medium 20 on the first pin 122 and the second pin 124;
  • the chip 12 is attached to the circuit board 14, the first pin 122 is correspondingly connected to the first groove 16, and the second pin 124 is correspondingly connected between the adjacent first grooves 16.
  • the connecting medium 20 is generally made of solder or the like.
  • the first pin 122 is connected to the first recess 16 , and the connecting medium 20 is at least partially received in the first recess 16 .
  • the second pin 124 corresponds to the first surface of the circuit board 14 .
  • the position between the grooves 16 is such that the connection medium 20 connecting the first pins 122 and the connection medium 20 connecting the second pins 124 are offset from each other, thereby preventing the connection medium 20 connecting the different pins 120 from being connected to each other (for example, sticking tin). To improve product yield.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一种芯片封装模组，包括芯片（12）、电路板（14）及连接介质（20），芯片的表面设有多个阵列排布的引脚，引脚包括交替排列的第一引脚（122）与第二引脚（124），电路板的表面设有第一凹槽（16）及位于相邻的第一凹槽之间的连接点（162），第一引脚与第一凹槽通过连接介质对应连接，连接第一引脚与第一凹槽的连接介质收容于凹槽中，第二引脚通过连接介质对应连接于连接点。一种移动终端及芯片封装方法。连接第一引脚的连接介质与连接第二引脚的连接介质相互错开，避免连接不同引脚的连接介质相互连接（例如黏锡现象），提高产品良率。

Description

芯片封装模组、移动终端及芯片封装方法 技术领域
本申请涉及芯片封装技术领域，尤其是涉及一种芯片封装模组、移动终端及芯片封装方法。
背景技术
芯片是现代技术中最常见的电子器件之一，无论是人们生活中常见的手机、电脑，还是工业生产使用的激光器、数控机床等设备都离不开芯片。芯片一般通过焊接等方式封装在印刷电路板(Printed Circuit Board，PCB)上，随着芯片工艺技术的不断发展，芯片功能的越来越强大，芯片的引脚数量也不断的增多，而芯片的体积有限，随着引脚数量增多，引脚之间的间距越来越小，导致芯片在贴片的过程中很容易造成黏锡现象，引脚之间相互短路，造成在生产时不良率过高，增大了生产成本。
申请内容
本申请要解决的技术问题是提供一种芯片封装模组、移动终端及芯片封装方法，用以解决现有技术中芯片在贴片的过程中很容易造成黏锡现象，造成在生产时不良率过高的问题。
为解决上述技术问题，本申请提供一种芯片封装模组，包括芯片、电路板及连接介质，所述芯片的表面设有多个阵列排布的引脚，所述引脚包括交替排列的第一引脚与第二引脚，所述电路板的表面设有第一凹槽及位于相邻的所述第一凹槽之间的连接点，所述第一引脚与所述第一凹槽通过所述连接介质对应连接，连接所述第一引脚与所述第一凹槽的所述连接介质收容于所述凹槽中，所述第二引脚通过所述连接介质对应连接于所述连接点。
其中，所述第一引脚的长度不小于所述第二引脚的长度，所述第一引脚至少部分收容于所述第一凹槽内。
其中，所述第一引脚的顶面设有凸起，所述凸起收容于所述第一凹槽，至少部分所述连接介质收容于所述凸起与所述第一凹槽的内壁之间。
其中，所述第一引脚的顶面设有凹坑，所述凹坑收容于所述第一凹槽，至少部分所述连接介质收容于所述凹坑与所述第一凹槽的内壁之间。
其中，所述第一凹槽包括连接槽底与槽口的侧壁，所述侧壁设有收容孔，至少部分所述连接介质收容于所述收容孔内。
其中，所述电路板的表面还设有第二凹槽，所述第二凹槽与所述第一凹槽交替排列，所述第二引脚与所述第二凹槽通过所述连接介质对应连接，连接所述第二引脚与所述第二凹槽的所述连接介质至少部分收容于所述第二凹槽中，所述第二凹槽的深度不大于所述第一凹槽的深度。
其中，所述第一引脚的长度不小于所述第二引脚的长度，所述第一引脚至少部分收容于所述第一凹槽内，所述第二引脚至少部分收容于所述第二凹槽内。
其中，所述电路板的表面还设有凸台，所述凸台与所述第一凹槽交替排列，所述第二引脚与所述凸台通过所述连接介质对应连接。
本申请还提供一种移动终端，包括以上任意一项所述的芯片封装模组。
本申请还提供一种芯片封装方法，包括：
提供芯片和电路板，所述电路板的表面设有多个阵列排列的第一凹槽，所述芯片的表面设有多个凸起的引脚，所述引脚包括交替排列的第一引脚与第二引脚，
在所述第一引脚和所述第二引脚上涂覆连接介质；
将所述芯片贴合至所述电路板，所述第一引脚与所述第一凹槽对应连接，所述第二引脚对应连接于相邻的所述第一凹槽之间。
本申请的有益效果如下：连接介质一般为焊锡等材料，第一引脚对应连接第一凹槽，连接介质至少部分收容于第一凹槽中，第二引脚对应连接电路板表面的第一凹槽之间的位置，连接第一引脚的连接介质与连接第二引脚的连接介质相互错开，避免连接不同引脚的连接介质相互连接(例如黏锡现象)，提高产品良率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述 中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的明显变形方式。
图1为本申请实施例一提供的芯片封装模组的截面示意图。
图2为本申请实施例一提供的芯片的截面示意图。
图3为本申请实施例一提供的芯片的表面示意图。
图4为本申请实施例一提供的电路板的截面示意图。
图5为本申请实施例一提供的电路板的表面示意图。
图6为本申请实施例一提供的芯片封装模组的一种实施方式的截面示意图。
图7为本申请实施例一提供的芯片封装模组的另一种实施方式的截面示意图。
图8为本申请实施例一提供的芯片封装模组的另一种实施方式的截面示意图。
图9为本申请实施例一提供的芯片封装模组的另一种实施方式的截面示意图。
图10为本申请实施例二提供的芯片封装模组的截面示意图。
图11为本申请实施例二提供的电路板的表面示意图。
图12为本申请实施例三提供的芯片封装模组的截面示意图。
图13为本申请实施例三提供的电路板的表面示意图。
图14为本申请实施例三提供的芯片封装模组的一种实施方式的截面示意图。
图15为本申请实施例提供的移动终端的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，本申请实施例一提供的芯片封装模组100包括芯片12、电路板14及连接介质20，具体的，芯片12(chip)是由晶圆分割而成的半导体元 件产品的统称，同时也是集成电路(integrated circuit，IC)的载体。芯片12在硅板上集合了多种电子元器件以实现某种特定功能，它是电子设备中最重要的部分，承担着运算和存储的功能。本实施例中，芯片12通过连接介质20与电路板14连接，一方面，芯片12与电路板14刚性连接，从而形成一个整体，即芯片封装模组100；另一方面，芯片12与电路板14电连接，以相互传递信号。连接介质20一般为具有导电特性的金属材料制成，例如焊锡等，连接介质20由熔融状态凝固至固体状态，将芯片12与电路板14刚性连接，同时连接介质20良好的导电特性将芯片12与电路板14电连接。一种实施方式中，电路板14为印刷电路板14(Printed Circuit Board，PCB)，其他实施方式中，电路板14也可以为柔性电路板14(Flexible Printed Circuit，FPC)。本实施例中，芯片封装模组100应用于移动终端200，例如手机、平板电脑、笔记本电脑等可携带的设备，电路板14可以为移动终端200的主板，芯片12可以为用于控制触摸屏的触控芯片12、用于控制显示屏的显示芯片12等。
结合图2和图3，芯片12的表面设有多个阵列排列的引脚120，具体的，引脚120由芯片12内部的集成电路引出，芯片12包括用于连接电路板14的第一表面1200，引脚120均位于第一表面1200，且引脚120之间的距离相同，从而将引脚120密布于第一表面1200。一种实施方式中，引脚120均为金属材质，并且每个引脚120的形状相同。本实施例中，引脚120包括交替排列的第一引脚122与第二引脚124，具体到图3，每两个第一引脚122之间设有一个第二引脚124，每两个第二引脚124之间设有一个第一引脚122，每个第一引脚122的上下左右方向相邻的引脚120均为第二引脚124，每个第二引脚124的上下左右方向相邻的引脚120均为第一引脚122，以将第一引脚122与第二引脚124均匀分布。
第一引脚122和第二引脚124均通过连接介质20连接至电路板14。具体的，结合图4和图5，电路板14的表面设有多个阵列排列的第一凹槽16及位于相邻的第一凹槽16之间的连接点162，具体的，电路板14包括用于连接芯片12的第二表面1400，第一凹槽16和连接点162设置于第二表面1400。每一个第一凹槽16的位置与一个第一引脚122对应，每个第二引脚124的位置与一个连接点162对应。一种实施方式中，电路板14上设有多个焊盘30，焊 盘30在第二表面1400上的垂直投影呈阵列排布，焊盘30与引脚120一一对应，进一步的，对应第一引脚122的焊盘30位于第一凹槽16的槽底160，对应第二引脚124的焊盘30位于连接点162位置的第一表面1200上，且位于相邻的第一凹槽16之间。一种实施方式中，连接介质20处于熔融状态时涂覆于第一引脚122和第二引脚124的顶面122a，将第一引脚122分别对应连接至电路板14后，连接介质20固化。本实施例中，第一引脚122与第一凹槽16通过连接介质20对应连接，连接第一引脚122与第一凹槽16的连接介质20固化后收容于第一凹槽16中，第二引脚124通过连接介质20对应连接于相邻的第一凹槽16之间，具体的，第二引脚124连接于第二表面1400，连接第二引脚124与第二表面1400的连接介质20固化后位于第二表面1400上。由于第一凹槽16的槽底160与第二表面1400之间有高度差，即使第一引脚122与第二引脚124的排布紧密，位于第一凹槽16内的连接介质20与位于第二表面1400上的连接介质20也不易相互接触，不易发生黏锡现象。
连接介质20一般为焊锡等材料，第一引脚122对应连接第一凹槽16，连接介质20至少部分收容于第一凹槽16中，第二引脚124对应连接电路板14表面的第一凹槽16之间的位置，连接第一引脚122的连接介质20与连接第二引脚124的连接介质20相互错开，避免连接不同引脚120的连接介质20相互连接(例如黏锡现象)，提高产品良率。
一种实施方式中，第一引脚122与第一凹槽16间隙配合，以使第一凹槽16有足够的空间容纳连接介质20，而避免第一引脚122插入第一凹槽16后连接介质20从第一凹槽16中溢出。
请参阅图1和图4，本实施例中，第一引脚122的长度不小于第二引脚124的长度，第一引脚122至少部分收容于第一凹槽16内。具体的，当第一引脚122的长度大于第二引脚124的长度，贴合芯片12与电路板14时，第一引脚122的顶端插入第一凹槽16内，连接介质20与第一引脚122的接触面积较大，第一引脚122与第一凹槽16的连接更牢固。进一步的，连接第一引脚122与电路板14的连接介质20收容于第一凹槽16中，连接第二引脚124与电路板14的连接介质20位于第二表面1400上，连接不同引脚120的连接介质20固化成型后相互接触的概率低，当连接介质20为焊锡时黏锡现象发生的概率低， 提高产品良率。
请参阅图6，一种实施方式中，第一引脚122的顶面122a设有凸起202，凸起202收容于第一凹槽16，至少部分连接介质20收容于凸起202与第一凹槽16的内壁之间。具体的，第一引脚122的顶面122a为第一引脚122凸出于第一表面1200的端面，凸起202在第一表面1200的垂直投影落在第一引脚122的范围内，且小于第一引脚122的尺寸。凸起202插入第一凹槽16中，进一步增大了第一引脚122与连接介质20的接触面积，使第一引脚122与凹槽的连接更牢固。与此同时，由于凸起202的尺寸较小，凸起202占用的第一凹槽16的容积较小，避免第一引脚122尺寸过大而占用第一凹槽16容积过多，收容于第一凹槽16内的连接介质20不会外溢出第一凹槽16而与第二表面1400上的连接介质20接触，即避免黏锡现象发生。提高了第一芯片12与电路板14的连接强度的同时，也避免了黏锡现象发生，提高了产品良率。
请参阅图7，一种实施方式中，第一引脚122的顶面122a设有凹坑204，凹坑204收容于第一凹槽16，至少部分连接介质20收容于凹坑204与第一凹槽16的内壁之间。具体的，第一引脚122的顶面122a为第一引脚122凸出于第一表面1200的端面，凹坑204在第一表面1200的垂直投影落在第一引脚122的范围内，且小于第一引脚122的尺寸。凹坑204插入第一凹槽16中，连接介质20也可以流动至凹坑204内，进一步增大了第一引脚122与连接介质20的接触面积，使第一引脚122与凹槽的连接更牢固。与此同时，由于凹坑204内凹与第一引脚122，凹坑204减小了第一引脚122插入第一凹槽16后占用第一凹槽16的容积，避免第一引脚122尺寸过大而占用第一凹槽16容积过多，收容于第一凹槽16内的连接介质20不会外溢出第一凹槽16而与第二表面1400上的连接介质20接触，即避免黏锡现象发生。提高了第一芯片12与电路板14的连接强度的同时，也避免了黏锡现象发生，提高了产品良率。
一种实施方式中，第一引脚122的顶面122a同时设有多个交替排列的凹坑204和凸起202，凹坑204和凸起202提高了第一芯片12与电路板14的连接强度的同时，也避免了黏锡现象发生，提高了产品良率。
请参阅图8，一种实施方式中，第一凹槽16的截面为锥形，并且第一凹槽16的槽底160尺寸小于第一凹槽16的槽口尺寸。锥形的第一凹槽16增大 了第一凹槽16的容积，连接介质20不易从第一凹槽16溢出，避免黏锡现象发生，并且有利于第一引脚122与第一凹槽16的对准，提高封装效率，提高良率。
请参阅图9，一种实施方式中，第一凹槽16包括连接槽底160与槽口的侧壁162，侧壁162设有收容孔206，至少部分连接介质20收容于收容孔206内。具体的，收容孔206可以为设置于侧壁162上的多个独立的盲孔，收容孔206也可以为环绕于侧壁162上的条状盲孔。收容孔206增大了第一凹槽16的容积，连接介质20收容于第一凹槽16中而不易溢出，避免黏锡现象发生，且没有增大第一凹槽16的槽口尺寸，没有减少第二表面1400上可以对应连接的引脚120数量。
连接介质20一般为焊锡等材料，第一引脚122对应连接第一凹槽16，连接介质20至少部分收容于第一凹槽16中，第二引脚124对应连接电路板14表面的第一凹槽16之间的位置，连接第一引脚122的连接介质20与连接第二引脚124的连接介质20相互错开，避免连接不同引脚120的连接介质20相互连接(例如黏锡现象)，提高产品良率。
请参阅图10和图11，本申请实施例二提供的芯片封装模组100与实施例一的区别在于，电路板14的表面还设有第二凹槽18，第二凹槽18与第一凹槽16交替排列，第二引脚124与第二凹槽18通过连接介质20对应连接，连接第二引脚124与第二凹槽18的连接介质20至少部分收容于第二凹槽18中，第二凹槽18的深度不大于第一凹槽16的深度。一种实施方式中，第二凹槽18的分布位置对应本申请实施例一的连接点162的位置。具体到图11，每两个第一凹槽16之间设有一个第二凹槽18，每两个第二凹槽18之间设有一个第一凹槽16，每个第一凹槽16的上下左右方向均设有第二凹槽18，每个第二凹槽18的上下左右方向均设有第一凹槽16，以将第一凹槽16与第二凹槽18均匀分布。连接第二引脚124与第二凹槽18的连接介质20至少部分收容于第二凹槽18中，使连接不同引脚120的连接介质20相互错开，避免连接不同引脚120的连接介质20相互连接(例如黏锡现象)，提高产品良率。
一种实施方式中，第一引脚122的长度不小于第二引脚124的长度，第一引脚122至少部分收容于第一凹槽16内，第二引脚124至少部分收容于第二 凹槽18内。一种实施方式中，第一引脚122的长度大于第二引脚124的长度，第一凹槽16的深度大于第二凹槽18的深度，第一引脚122插入第一凹槽16，第二引脚124插入第二凹槽18，连接第一引脚122的连接介质20与第一引脚122的接触面积较大，第一引脚122与第一凹槽16的连接更牢固，连接第二引脚124的连接介质20与第二引脚124的接触面积较大，第二引脚124与第二凹槽18的连接更牢固。进一步的，连接第一引脚122与电路板14的连接介质20收容于第一凹槽16中，连接第二引脚124与电路板14的连接介质20收容于第二凹槽18中，连接不同引脚120的连接介质20固化成型后相互接触的概率低，当连接介质20为焊锡时黏锡现象发生的概率低，提高产品良率。
一种实施方式中，第二引脚124的顶面122a也可以设有凸起202或凹坑204，以增大第二引脚124与连接介质20的接触面积。
请参阅图12和图13，电路板14的表面还设有凸台40，凸台40与第一凹槽16交替排列，第二引脚124与凸台40通过连接介质20对应连接。一种实施方式中，凸台40的分布位置对应本申请实施例一的连接点162的位置。具体到图13，每两个第一凹槽16之间设有一个凸台40，每两个凸台40之间设有一个第一凹槽16，每个第一凹槽16的上下左右方向均设有凸台40，每个凸台40的上下左右方向均设有第一凹槽16，以将第一凹槽16与凸台40均匀分布。连接第二引脚124与凸台40的连接介质20位于凸台40的表面，使连接不同引脚120的连接介质20相互错开，避免连接不同引脚120的连接介质20相互连接(例如黏锡现象)，提高产品良率。
一种实施方式中，第一引脚122的长度大于第二引脚124的长度，以使芯片12封装在电路板14上后芯片12表面平整。
请参阅图14，一种实施方式中，凸台40的表面设有凹坑400，凹坑400用于容纳连接第二引脚124的连接介质20，进一步将连接第一引脚122的连接介质20与连接第二引脚124的连接介质20错开，避免出现黏锡现象，提高产品良率。
请参阅图15，本申请实施例还提供一种移动终端200，包括本申请实施例提供的芯片封装模组100。移动终端200可以是手机、平板电脑、笔记本电脑等可携带的设备，电路板14可以为移动终端200的主板，芯片12可以为用于 控制触摸屏的触控芯片12、用于控制显示屏的显示芯片12等。
连接介质20一般为焊锡等材料，第一引脚122对应连接第一凹槽16，连接介质20至少部分收容于第一凹槽16中，第二引脚124对应连接电路板14表面的第一凹槽16之间的位置，连接第一引脚122的连接介质20与连接第二引脚124的连接介质20相互错开，避免连接不同引脚120的连接介质20相互连接(例如黏锡现象)，提高产品良率。
本申请实施例还提供一种芯片12封装方法，具体步骤包括：
S101、提供芯片12和电路板14，电路板14的表面设有多个阵列排列的第一凹槽16，芯片12的表面设有多个凸起202的引脚120，引脚120包括交替排列的第一引脚122与第二引脚124，
S102、在第一引脚122和第二引脚124上涂覆连接介质20；
S103、将芯片12贴合至电路板14，第一引脚122与第一凹槽16对应连接，第二引脚124对应连接于相邻的第一凹槽16之间。
连接介质20一般为焊锡等材料，第一引脚122对应连接第一凹槽16，连接介质20至少部分收容于第一凹槽16中，第二引脚124对应连接电路板14表面的第一凹槽16之间的位置，连接第一引脚122的连接介质20与连接第二引脚124的连接介质20相互错开，避免连接不同引脚120的连接介质20相互连接(例如黏锡现象)，提高产品良率。
以上所揭露的仅为本申请几种较佳实施例而已，当然不能以此来限定本申请之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本申请权利要求所作的等同变化，仍属于申请所涵盖的范围。

Claims (10)

  1. 一种芯片封装模组，其中，包括芯片、电路板及连接介质，所述芯片的表面设有多个阵列排布的引脚，所述引脚包括交替排列的第一引脚与第二引脚，所述电路板的表面设有第一凹槽及位于相邻的所述第一凹槽之间的连接点，所述第一引脚与所述第一凹槽通过所述连接介质对应连接，连接所述第一引脚与所述第一凹槽的所述连接介质收容于所述凹槽中，所述第二引脚通过所述连接介质对应连接于所述连接点。
  2. 根据权利要求1所述的芯片封装模组，其中，所述第一引脚的长度不小于所述第二引脚的长度，所述第一引脚至少部分收容于所述第一凹槽内。
  3. 根据权利要求2所述的芯片封装模组，其中，所述第一引脚的顶面设有凸起，所述凸起收容于所述第一凹槽，至少部分所述连接介质收容于所述凸起与所述第一凹槽的内壁之间。
  4. 根据权利要求2所述的芯片封装模组，其中，所述第一引脚的顶面设有凹坑，所述凹坑收容于所述第一凹槽，至少部分所述连接介质收容于所述凹坑与所述第一凹槽的内壁之间。
  5. 根据权利要求1所述的芯片封装模组，其中，所述第一凹槽包括连接槽底与槽口的侧壁，所述侧壁设有收容孔，至少部分所述连接介质收容于所述收容孔内。
  6. 根据权利要求1至5任意一项所述的芯片封装模组，其中，所述电路板的表面还设有第二凹槽，所述第二凹槽与所述第一凹槽交替排列，所述第二引脚与所述第二凹槽通过所述连接介质对应连接，连接所述第二引脚与所述第二凹槽的所述连接介质至少部分收容于所述第二凹槽中，所述第二凹槽的深度不大于所述第一凹槽的深度。
  7. 根据权利要求6所述的芯片封装模组，其中，所述第一引脚的长度不小于所述第二引脚的长度，所述第一引脚至少部分收容于所述第一凹槽内，所述第二引脚至少部分收容于所述第二凹槽内。
  8. 根据权利要求1至5任意一项所述的芯片封装模组，其中，所述电路板的表面还设有凸台，所述凸台与所述第一凹槽交替排列，所述第二引脚与所述 凸台通过所述连接介质对应连接。
  9. 一种移动终端，其中，包括权利要求1至8任意一项所述的芯片封装模组。
  10. 一种芯片封装方法，其中，包括：
    提供芯片和电路板，所述电路板的表面设有多个阵列排列的第一凹槽，所述芯片的表面设有多个凸起的引脚，所述引脚包括交替排列的第一引脚与第二引脚，
    在所述第一引脚和所述第二引脚上涂覆连接介质；
    将所述芯片贴合至所述电路板，所述第一引脚与所述第一凹槽对应连接，所述第二引脚对应连接于相邻的所述第一凹槽之间。
PCT/CN2017/103867 2017-09-28 2017-09-28 芯片封装模组、移动终端及芯片封装方法 WO2019061119A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7087458B2 (en) * 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
JP4566335B2 (ja) * 2000-05-30 2010-10-20 イビデン株式会社 多層プリント配線板
CN103594380A (zh) * 2013-10-24 2014-02-19 天水华天科技股份有限公司 带焊球面阵列四面扁平无引脚封装件制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4566335B2 (ja) * 2000-05-30 2010-10-20 イビデン株式会社 多層プリント配線板
US7087458B2 (en) * 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
CN103594380A (zh) * 2013-10-24 2014-02-19 天水华天科技股份有限公司 带焊球面阵列四面扁平无引脚封装件制备方法

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