WO2019059616A1 - Circuit de protection de batterie à faible résistance capable de faire face aux décharges électrostatiques - Google Patents

Circuit de protection de batterie à faible résistance capable de faire face aux décharges électrostatiques Download PDF

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Publication number
WO2019059616A1
WO2019059616A1 PCT/KR2018/010994 KR2018010994W WO2019059616A1 WO 2019059616 A1 WO2019059616 A1 WO 2019059616A1 KR 2018010994 W KR2018010994 W KR 2018010994W WO 2019059616 A1 WO2019059616 A1 WO 2019059616A1
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WO
WIPO (PCT)
Prior art keywords
fet
battery
protection circuit
control units
discharge
Prior art date
Application number
PCT/KR2018/010994
Other languages
English (en)
Korean (ko)
Inventor
허철
Original Assignee
주식회사 엘지화학
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 엘지화학 filed Critical 주식회사 엘지화학
Priority to CN201890001037.8U priority Critical patent/CN212304771U/zh
Publication of WO2019059616A1 publication Critical patent/WO2019059616A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Definitions

  • the present invention relates to a battery protection circuit provided with an ESD compatible configuration.
  • the present invention also relates to a battery protection circuit designed with low resistance.
  • the secondary rechargeable batteries are nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries, and lithium secondary batteries.
  • lithium secondary batteries have almost no memory effect compared to nickel- It is very popular because of its low self-discharge rate and high energy density.
  • a protection circuit which secures the safety of the battery by shutting off the charging / discharging current when the abnormal state of the battery is detected.
  • Figure 1 is a diagram of a conventional protection circuit.
  • a conventional protection circuit will be described.
  • a protection circuit is constructed using general FETs 11 to 14 having a 3-ohm resistance.
  • ESD Electrostatic Discharge
  • the present invention proposes a protection circuit for solving such a problem.
  • the present invention proposes a battery protection circuit capable of designing with a low resistance while having a configuration corresponding to ESD.
  • the present invention provides a battery protection circuit capable of implementing ESD while implementing a low-resistance battery protection circuit.
  • the protection circuit for protecting the battery from overcharging, overdischarging, and overcurrent includes two or more control units provided between a battery cell constituting the battery and an external input / output terminal and controlling charge / discharge of the battery And the two or more control units may be connected in parallel.
  • Each of the two or more control units may include a charge FET for controlling charging of the battery and a discharge FET for controlling discharging of the battery.
  • the charge FET and the discharge FET may be connected in series.
  • At least one of the two or more control units may be configured by connecting a plurality of charge diodes and a plurality of discharge diodes to each of the charge FETs and the discharge FETs in parallel.
  • At least one of the two or more control units may be configured by integrating the charge FET and the discharge FET into one chip of a genodiode and a FET.
  • control units may be connected to the charge FET and the discharge FET in parallel, respectively.
  • some of the two or more control units may include a charge FET and a discharge FET, each of which is formed by integrating a genodiode and a FET into one chip.
  • the present invention can constitute a low resistance battery protection circuit capable of ESD.
  • Figure 1 is a diagram of a prior art protection circuit.
  • FIG. 2 is a schematic diagram of a battery protection circuit according to an embodiment of the present invention.
  • FIG. 3 is a detailed diagram of a battery protection circuit according to an embodiment of the present invention.
  • FIG. 4 is a detailed view of a battery protection circuit according to another embodiment of the present invention.
  • first, second, etc. may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.
  • first component may be referred to as a second component
  • second component may also be referred to as a first component.
  • the terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention.
  • the singular expressions include plural expressions unless the context clearly dictates otherwise.
  • a part when referred to as being “connected” to another part, it includes not only “directly connected” but also “electrically connected” with another part in between .
  • a element when an element is referred to as " comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.
  • the word " step (or step) " or " step " used to the extent that it is used throughout the specification does not mean " step for.
  • FIG. 2 is a diagram illustrating a configuration of a battery protection circuit according to an embodiment of the present invention.
  • the battery protection circuit according to the embodiment of the present invention may include two or more control units 100 for controlling charge and discharge of the battery, and each of the two or more control units 100 may be connected in parallel.
  • the reason why the two or more control units 100 are connected in parallel to obtain the battery protection circuit is that the number of FETs used in the battery protection circuit varies depending on the capacity of the battery and the charge / discharge current of the battery.
  • control unit 100 when two or more control units 100 are connected in parallel to constitute a battery protection circuit, if an error occurs in a part of the control unit 100, the charge and discharge of the battery can be controlled through the remaining control unit 100, Can be improved.
  • the two or more control units 100 may include a charging FET for controlling the charging of the battery and a discharging FET for controlling discharging of the battery.
  • the charge FET and the discharge FET may be connected in series.
  • the two or more control units 100 may further include ESD protection structures 110 and 210 as an ESD-compliant configuration of the battery protection circuit, and a gen diode may be used as the configuration.
  • At least one of the two or more control units 100 may be configured by connecting a plurality of generators to the charge FET and the discharge FET in parallel, or a part of the two or more control units may be connected to the charge FET and the discharge FET And a junode diode connected in parallel.
  • the charge FET and the discharge FET may be constituted by integrating the generator diode and the FET into one chip.
  • FIG. 3 is a schematic diagram of a battery protection circuit according to an embodiment of the present invention
  • FIG. 4 is a specific diagram of a battery protection circuit according to an embodiment of the present invention.
  • FIG. 3 a protection circuit according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4.
  • each of the first and second control units 120 and 120 may include ESD protection units 110 and 210 for ESD protection of the battery protection circuit.
  • the ESD protection structure can be formed by configuring the charge FETs 101 and 201 and the discharge FETs 102 and 202 as elements in which the genodiode and the FET are integrated into a single chip.
  • the resistance value of a device in which the genodiode and the FET are integrated into one chip has a resistance value which is generally larger than that of the conventional FET described above.
  • the resistance of a device in which the genodiode and the FET are integrated into one chip may be 4?.
  • both the charge FETs 101 and 201 and the discharge FETs 201 and 202 constituting the first control unit 120 and the second control unit 220 are constituted by devices in which the genodiode and the FET are integrated into one chip, Can have a larger resistance value than a general FET, so that the overall resistance of the battery protection circuit can be increased.
  • the total resistance of the battery protection circuit constructed as described above is calculated as 4 OMEGA, so that the resistance value is turned on and can not satisfy the design requirement (3 OMEGA or less) of the battery pack as compared with the conventional protection circuit using only a general FET of 3 OMEGA.
  • a battery protection circuit can be designed as shown in FIG.
  • a battery protection circuit can be constructed.
  • the charging FET 101 and the discharging FET 102 of the first control unit 120 are constituted by elements in which the genodiode and the FET are integrated into one chip and the charging FET 203 and the charging FET 203 of the second control unit 200
  • the discharge FET 204 is an embodiment of a low-resistance FET.
  • the low-resistance FET may be a FET having a resistance value smaller than that of a conventional general FET.
  • the resistance of the low-resistance FET may be 2?.
  • the charging FET 101 and the discharging FET 102 of the first control unit 120 are constituted by elements in which the genodiode and the FET are integrated into one chip, and the charging FET 203 of the second control unit 220 And the discharging FET 204 are constituted by a low-resistance FET, the resistance of the battery protection circuit can be calculated from the equation since then.
  • the total resistance of the battery protection circuit of Fig. 5 calculated by the above equation is 2.7?.
  • the battery protection circuit constructed as shown in Fig. 5 can satisfy the design requirement (less than 3?) Of the battery pack while having the ESD-compatible configuration.
  • a device in which a genodiode and a FET are integrated into one chip may be realized by connecting a FET and a genodiode in parallel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Protection Of Static Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Selon un mode de réalisation, la présente invention concerne un circuit de protection pour protéger une batterie contre la surcharge, la décharge excessive et les surintensités, comprenant deux unités de commande ou plus, qui sont disposées entre une extrémité d'entrée/sortie externe et une cellule de batterie constituant une batterie et commandent la charge et la décharge de la batterie, chacune des deux unités de commande ou plus pouvant être connectée en dérivation.
PCT/KR2018/010994 2017-09-19 2018-09-18 Circuit de protection de batterie à faible résistance capable de faire face aux décharges électrostatiques WO2019059616A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201890001037.8U CN212304771U (zh) 2017-09-19 2018-09-18 电池保护电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2017-0120590 2017-09-19
KR1020170120590A KR102375844B1 (ko) 2017-09-19 2017-09-19 Esd 대응이 가능한 저저항 배터리 보호 회로

Publications (1)

Publication Number Publication Date
WO2019059616A1 true WO2019059616A1 (fr) 2019-03-28

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PCT/KR2018/010994 WO2019059616A1 (fr) 2017-09-19 2018-09-18 Circuit de protection de batterie à faible résistance capable de faire face aux décharges électrostatiques

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KR (1) KR102375844B1 (fr)
CN (1) CN212304771U (fr)
WO (1) WO2019059616A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220321019A1 (en) * 2021-03-30 2022-10-06 Tdk Corporation Power conversion apparatus and power conversion system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08237872A (ja) * 1994-12-05 1996-09-13 Fuji Photo Film Co Ltd 二次電池の充放電保護装置
JP2008283743A (ja) * 2007-05-08 2008-11-20 Fuji Electric Device Technology Co Ltd 二次電池保護装置及び半導体集積回路装置
KR20120054866A (ko) * 2010-11-22 2012-05-31 삼성에스디아이 주식회사 배터리 팩 및 이의 제어방법
JP2016054453A (ja) * 2014-09-04 2016-04-14 ローム株式会社 保護スイッチ回路、充電回路、電子機器
WO2017086113A1 (fr) * 2015-11-17 2017-05-26 株式会社オートネットワーク技術研究所 Circuit de commutation et système d'alimentation électrique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080034321A (ko) * 2006-10-16 2008-04-21 넥스콘 테크놀러지 주식회사 배터리팩의 정전기에 의한 방전과 역충전에 의한 파손 방지보호회로
KR20150108431A (ko) * 2014-03-17 2015-09-30 주식회사 엘엔피 배터리 보호 회로

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08237872A (ja) * 1994-12-05 1996-09-13 Fuji Photo Film Co Ltd 二次電池の充放電保護装置
JP2008283743A (ja) * 2007-05-08 2008-11-20 Fuji Electric Device Technology Co Ltd 二次電池保護装置及び半導体集積回路装置
KR20120054866A (ko) * 2010-11-22 2012-05-31 삼성에스디아이 주식회사 배터리 팩 및 이의 제어방법
JP2016054453A (ja) * 2014-09-04 2016-04-14 ローム株式会社 保護スイッチ回路、充電回路、電子機器
WO2017086113A1 (fr) * 2015-11-17 2017-05-26 株式会社オートネットワーク技術研究所 Circuit de commutation et système d'alimentation électrique

Also Published As

Publication number Publication date
CN212304771U (zh) 2021-01-05
KR102375844B1 (ko) 2022-03-17
KR20190032092A (ko) 2019-03-27

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