WO2019059616A1 - Low-resistance battery protective circuit capable of coping with esd - Google Patents

Low-resistance battery protective circuit capable of coping with esd Download PDF

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Publication number
WO2019059616A1
WO2019059616A1 PCT/KR2018/010994 KR2018010994W WO2019059616A1 WO 2019059616 A1 WO2019059616 A1 WO 2019059616A1 KR 2018010994 W KR2018010994 W KR 2018010994W WO 2019059616 A1 WO2019059616 A1 WO 2019059616A1
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WO
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Prior art keywords
fet
battery
protection circuit
control units
discharge
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PCT/KR2018/010994
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French (fr)
Korean (ko)
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허철
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주식회사 엘지화학
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Priority to CN201890001037.8U priority Critical patent/CN212304771U/en
Publication of WO2019059616A1 publication Critical patent/WO2019059616A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Definitions

  • the present invention relates to a battery protection circuit provided with an ESD compatible configuration.
  • the present invention also relates to a battery protection circuit designed with low resistance.
  • the secondary rechargeable batteries are nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries, and lithium secondary batteries.
  • lithium secondary batteries have almost no memory effect compared to nickel- It is very popular because of its low self-discharge rate and high energy density.
  • a protection circuit which secures the safety of the battery by shutting off the charging / discharging current when the abnormal state of the battery is detected.
  • Figure 1 is a diagram of a conventional protection circuit.
  • a conventional protection circuit will be described.
  • a protection circuit is constructed using general FETs 11 to 14 having a 3-ohm resistance.
  • ESD Electrostatic Discharge
  • the present invention proposes a protection circuit for solving such a problem.
  • the present invention proposes a battery protection circuit capable of designing with a low resistance while having a configuration corresponding to ESD.
  • the present invention provides a battery protection circuit capable of implementing ESD while implementing a low-resistance battery protection circuit.
  • the protection circuit for protecting the battery from overcharging, overdischarging, and overcurrent includes two or more control units provided between a battery cell constituting the battery and an external input / output terminal and controlling charge / discharge of the battery And the two or more control units may be connected in parallel.
  • Each of the two or more control units may include a charge FET for controlling charging of the battery and a discharge FET for controlling discharging of the battery.
  • the charge FET and the discharge FET may be connected in series.
  • At least one of the two or more control units may be configured by connecting a plurality of charge diodes and a plurality of discharge diodes to each of the charge FETs and the discharge FETs in parallel.
  • At least one of the two or more control units may be configured by integrating the charge FET and the discharge FET into one chip of a genodiode and a FET.
  • control units may be connected to the charge FET and the discharge FET in parallel, respectively.
  • some of the two or more control units may include a charge FET and a discharge FET, each of which is formed by integrating a genodiode and a FET into one chip.
  • the present invention can constitute a low resistance battery protection circuit capable of ESD.
  • Figure 1 is a diagram of a prior art protection circuit.
  • FIG. 2 is a schematic diagram of a battery protection circuit according to an embodiment of the present invention.
  • FIG. 3 is a detailed diagram of a battery protection circuit according to an embodiment of the present invention.
  • FIG. 4 is a detailed view of a battery protection circuit according to another embodiment of the present invention.
  • first, second, etc. may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.
  • first component may be referred to as a second component
  • second component may also be referred to as a first component.
  • the terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention.
  • the singular expressions include plural expressions unless the context clearly dictates otherwise.
  • a part when referred to as being “connected” to another part, it includes not only “directly connected” but also “electrically connected” with another part in between .
  • a element when an element is referred to as " comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.
  • the word " step (or step) " or " step " used to the extent that it is used throughout the specification does not mean " step for.
  • FIG. 2 is a diagram illustrating a configuration of a battery protection circuit according to an embodiment of the present invention.
  • the battery protection circuit according to the embodiment of the present invention may include two or more control units 100 for controlling charge and discharge of the battery, and each of the two or more control units 100 may be connected in parallel.
  • the reason why the two or more control units 100 are connected in parallel to obtain the battery protection circuit is that the number of FETs used in the battery protection circuit varies depending on the capacity of the battery and the charge / discharge current of the battery.
  • control unit 100 when two or more control units 100 are connected in parallel to constitute a battery protection circuit, if an error occurs in a part of the control unit 100, the charge and discharge of the battery can be controlled through the remaining control unit 100, Can be improved.
  • the two or more control units 100 may include a charging FET for controlling the charging of the battery and a discharging FET for controlling discharging of the battery.
  • the charge FET and the discharge FET may be connected in series.
  • the two or more control units 100 may further include ESD protection structures 110 and 210 as an ESD-compliant configuration of the battery protection circuit, and a gen diode may be used as the configuration.
  • At least one of the two or more control units 100 may be configured by connecting a plurality of generators to the charge FET and the discharge FET in parallel, or a part of the two or more control units may be connected to the charge FET and the discharge FET And a junode diode connected in parallel.
  • the charge FET and the discharge FET may be constituted by integrating the generator diode and the FET into one chip.
  • FIG. 3 is a schematic diagram of a battery protection circuit according to an embodiment of the present invention
  • FIG. 4 is a specific diagram of a battery protection circuit according to an embodiment of the present invention.
  • FIG. 3 a protection circuit according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4.
  • each of the first and second control units 120 and 120 may include ESD protection units 110 and 210 for ESD protection of the battery protection circuit.
  • the ESD protection structure can be formed by configuring the charge FETs 101 and 201 and the discharge FETs 102 and 202 as elements in which the genodiode and the FET are integrated into a single chip.
  • the resistance value of a device in which the genodiode and the FET are integrated into one chip has a resistance value which is generally larger than that of the conventional FET described above.
  • the resistance of a device in which the genodiode and the FET are integrated into one chip may be 4?.
  • both the charge FETs 101 and 201 and the discharge FETs 201 and 202 constituting the first control unit 120 and the second control unit 220 are constituted by devices in which the genodiode and the FET are integrated into one chip, Can have a larger resistance value than a general FET, so that the overall resistance of the battery protection circuit can be increased.
  • the total resistance of the battery protection circuit constructed as described above is calculated as 4 OMEGA, so that the resistance value is turned on and can not satisfy the design requirement (3 OMEGA or less) of the battery pack as compared with the conventional protection circuit using only a general FET of 3 OMEGA.
  • a battery protection circuit can be designed as shown in FIG.
  • a battery protection circuit can be constructed.
  • the charging FET 101 and the discharging FET 102 of the first control unit 120 are constituted by elements in which the genodiode and the FET are integrated into one chip and the charging FET 203 and the charging FET 203 of the second control unit 200
  • the discharge FET 204 is an embodiment of a low-resistance FET.
  • the low-resistance FET may be a FET having a resistance value smaller than that of a conventional general FET.
  • the resistance of the low-resistance FET may be 2?.
  • the charging FET 101 and the discharging FET 102 of the first control unit 120 are constituted by elements in which the genodiode and the FET are integrated into one chip, and the charging FET 203 of the second control unit 220 And the discharging FET 204 are constituted by a low-resistance FET, the resistance of the battery protection circuit can be calculated from the equation since then.
  • the total resistance of the battery protection circuit of Fig. 5 calculated by the above equation is 2.7?.
  • the battery protection circuit constructed as shown in Fig. 5 can satisfy the design requirement (less than 3?) Of the battery pack while having the ESD-compatible configuration.
  • a device in which a genodiode and a FET are integrated into one chip may be realized by connecting a FET and a genodiode in parallel.

Abstract

A protective circuit for protecting a battery from overcharging, overdischarging and overcurrent, according to an embodiment of the present invention, comprises two or more control units, which are provided between an external input/output end and a battery cell constituting a battery, and controls charging and discharging of the battery, wherein each of the two or more control units can be connected in parallel.

Description

ESD 대응이 가능한 저저항 배터리 보호 회로ESD-compatible low-resistance battery protection circuit
본 발명은 ESD 대응 구성이 구비된 배터리 보호 회로에 관한 것이다.The present invention relates to a battery protection circuit provided with an ESD compatible configuration.
또한, 본 발명은 저저항으로 설계되는 배터리 보호 회로에 관한 것이다.The present invention also relates to a battery protection circuit designed with low resistance.
근래에 들어서, 노트북, 비디오 카메라, 휴대용 전화기 등과 같은 휴대용 전자 제품의 수요가 급격하게 증대되고, 에너지 저장용 축전지, 로봇, 위성 등의 개발이 본격화됨에 따라, 반복적인 충방전이 가능한 고성능 이차전지에 대한 연구가 활발히 진행되고 있다.In recent years, demand for portable electronic products such as notebook computers, video cameras, and portable telephones has been rapidly increased, and development of batteries, robots, and satellites for energy storage has been accelerated. Thus, a high performance rechargeable battery Researches are being actively conducted.
현재 상용화된 이차 전지로는 니켈 카드뮴 전지, 니켈 수소 전지, 니켈 아연 전지, 리튬 이차 전지 등이 있는데, 이 중에서 리튬 이차 전지는 니켈 계열의 이차 전지에 비해 메모리 효과가 거의 일어나지 않아 충 방전이 자유롭고, 자가 방전율이 매우 낮으며 에너지 밀도가 높은 장점으로 각광을 받고 있다.The secondary rechargeable batteries are nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries, and lithium secondary batteries. Among them, lithium secondary batteries have almost no memory effect compared to nickel- It is very popular because of its low self-discharge rate and high energy density.
한편, 최근 배터리와 관련하여 사회적으로 가장 큰 이슈가 되고 있는 것이 배터리의 안전성 문제이다. 노트북이나 휴대폰과 같은 전자제품에 대한 사용 인구가 급격히 증가하고 있고, 배터리의 폭발은 휴대용 전자제품의 파손을 가져올 뿐만 아니라 화재로 연결될 수 있다는 점에서 배터리의 안전성 확보가 시급하다.On the other hand, the safety issue of the battery is one of the biggest social issues in recent years. The use population of electronic products such as notebooks and mobile phones is rapidly increasing. The battery explosion can not only lead to breakage of portable electronic products but also can lead to fire, so it is urgent to secure the safety of the battery.
이러한 배터리의 안정성 확보를 위해 배터리에는 배터리의 이상상태 감지시 충방전 전류를 차단하여 배터리의 안전성을 확보하는 보호 회로가 사용되고 있다.In order to secure the stability of such a battery, a protection circuit is used which secures the safety of the battery by shutting off the charging / discharging current when the abnormal state of the battery is detected.
도 1은 종래의 보호 회로에 대한 도면이다.Figure 1 is a diagram of a conventional protection circuit.
도 1을 참조하여 종래의 보호 회로를 설명하면, 종래의 보호 회로는, 3옴 저항을 가지는 일반적인 FET(11 내지 14)를 사용하여 보호회로를 구성해 왔다. 그러나 이와 같은 일반적인 FET(11 내지 14)를 사용하여 배터리 보호 회로를 설계하는 경우에는 ESD(Electrostatic Discharge)를 대응하기 어려운 문제점이 있었다.Referring to FIG. 1, a conventional protection circuit will be described. In the conventional protection circuit, a protection circuit is constructed using general FETs 11 to 14 having a 3-ohm resistance. However, when the general FETs 11 to 14 are used to design a battery protection circuit, ESD (Electrostatic Discharge) is difficult to cope with.
따라서, 본 발명에서는 이러한 문제점을 해결하는 보호 회로를 제언한다.Therefore, the present invention proposes a protection circuit for solving such a problem.
또한, 본 발명에서는 ESD 대응하는 구성을 구비하면서도, 저저항으로 설계 가능한 배터리 보호 회로를 제안한다.Further, the present invention proposes a battery protection circuit capable of designing with a low resistance while having a configuration corresponding to ESD.
본 발명은 배터리 보호 회로를 저저항으로 구현하면서도 ESD 대응이 가능한 배터리 보호 회로를 제공한다.The present invention provides a battery protection circuit capable of implementing ESD while implementing a low-resistance battery protection circuit.
본 발명의 실시 예에 따른 과충전, 과방전, 과전류로부터 배터리를 보호 하는 보호회로는, 배터리를 구성하고 있는 배터리 셀과 외부 입출력 단 사이에 구비되고, 배터리의 충방전을 제어하는 둘 이상의 제어부를 포함하여 구성되며, 상기 둘 이상의 제어부는 각각 병렬로 연결되어 있을 수 있다.The protection circuit for protecting the battery from overcharging, overdischarging, and overcurrent according to an embodiment of the present invention includes two or more control units provided between a battery cell constituting the battery and an external input / output terminal and controlling charge / discharge of the battery And the two or more control units may be connected in parallel.
한편, 상기 둘 이상의 제어부 각각은, 배터리의 충전을 제어하는 충전 FET 및 배터리의 방전을 제어하는 방전 FET를 포함하여 구성될 수 있다.Each of the two or more control units may include a charge FET for controlling charging of the battery and a discharge FET for controlling discharging of the battery.
한편, 상기 충전 FET와 방전 FET는 직렬로 연결될 수 있다.On the other hand, the charge FET and the discharge FET may be connected in series.
한편, 상기 둘 이상의 제어부 중 적어도 어느 하나는, 충전 FET 및 방전 FET 각각에 제노 다이오드를 병렬로 연결하여 구성될 수 있다.At least one of the two or more control units may be configured by connecting a plurality of charge diodes and a plurality of discharge diodes to each of the charge FETs and the discharge FETs in parallel.
다른 실시 예로, 상기 둘 이상의 제어부 중 적어도 어느 하나는, 충전 FET 및 방전 FET를 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성될 수 있다.In another embodiment, at least one of the two or more control units may be configured by integrating the charge FET and the discharge FET into one chip of a genodiode and a FET.
또 다른 실시 예로, 상기 둘 이상이 제어부 중 전체가 아닌 일부의 제어부가 충전 FET 및 방전 FET 각각에 제노 다이오드를 병렬로 연결하여 구성될 수 있다.In another embodiment, some of the control units, not the whole of the control units, may be connected to the charge FET and the discharge FET in parallel, respectively.
또 다른 실시 예로, 상기 둘 이상의 제어부 중 전체가 아닌 일부의 제어부가 충전 FET 및 방전 FET를 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성될 수 있다.In another embodiment, some of the two or more control units may include a charge FET and a discharge FET, each of which is formed by integrating a genodiode and a FET into one chip.
본 발명은 ESD 대응이 가능한 저저항 배터리 보호 회로를 구성할 수 있다.The present invention can constitute a low resistance battery protection circuit capable of ESD.
도 1은 종래 기술의 보호 회로의 도면이다.Figure 1 is a diagram of a prior art protection circuit.
도 2는 본 발명의 실시 예에 따른 배터리 보호 회로의 계략적인 도면이다.2 is a schematic diagram of a battery protection circuit according to an embodiment of the present invention.
도 3은 본 발명의 실시 예에 따른 배터리 보호 회로의 세부적인 도면이다.3 is a detailed diagram of a battery protection circuit according to an embodiment of the present invention.
도 4는 본 발명의 다른 실시 예에 따른 배터리 보호 회로의 세부적인 도면이다.4 is a detailed view of a battery protection circuit according to another embodiment of the present invention.
아래에서는 첨부한 도면을 참조하여 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 본 발명의 실시 예를 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시 예에 한정되지 않는다. 그리고 도면에서 본 발명을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 유사한 부분에 대해서는 유사한 도면부호를 붙였다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.
제1, 제2 등과 같이 서수를 포함하는 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되지는 않는다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용된다. 예컨대, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소도 제1 구성요소로 명명될 수 있다. 본 출원에서 사용한 용어는 단지 특정한 실시 예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다.Terms including ordinals, such as first, second, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise.
명세서 전체에서, 어떤 부분이 다른 부분과 “연결”되어 있다고 할 때, 이는 “직접적으로 연결”되어 있는 경우뿐 아니라, 그 중간에 다른 소자를 사이에 두고 “전기적으로 연결”되어 있는 경우도 포함한다. 또한 어떤 부분이 어떤 구성요소를 “포함”한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성요소를 더 포함할 수 있는 것을 의미한다. 본원 명세서 전체에서 사용되는 정도의 용어 “~(하는) 단계” 또는 “~의 단계”는 “~를 위한 단계”를 의미하지 않는다.Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as " comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise. The word " step (or step) " or " step " used to the extent that it is used throughout the specification does not mean " step for.
본 발명에서 사용되는 용어는 본 발명에서의 기능을 고려하면서 가능한 현재 널리 사용되는 일반적인 용어들을 선택하였으나, 이는 당 분야에 종사하는 기술자의 의도 또는 판례, 새로운 기술의 출현 등에 따라 달라질 수 있다. 또한, 특정한 경우는 출원인이 임의로 선정한 용어도 있으며, 이 경우 해당되는 발명의 설명 부분에서 상세히 그 의미를 기재할 것이다. 따라서 본 발명에서 사용되는 용어는 단순한 용어의 명칭이 아닌, 그 용어가 가지는 의미와 본 발명의 전반에 걸친 내용을 토대로 정의되어야 한다.While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term, not on the name of a simple term, but on the entire contents of the present invention.
1. 본 발명의 실시 예에 따른 배터리 보호 회로1. A battery protection circuit according to an embodiment of the present invention
도 2는 본 발명의 실시 예에 따른 배터리 보호 회로의 구성을 나타낸 도면이다.2 is a diagram illustrating a configuration of a battery protection circuit according to an embodiment of the present invention.
이하에서는 도 2를 참조하여 본 발명의 실시 예에 따른 배터리 보호 회로를 설명한다.Hereinafter, a battery protection circuit according to an embodiment of the present invention will be described with reference to FIG.
본 발명의 실시 예에 따른 배터리 보호 회로는, 배터리의 충방전을 제어하는 둘 이상의 제어부(100)를 포함하여 구성될 수 있으며, 상기 둘 이상의 제어부(100) 각각은 병렬로 연결되어 있을 수 있다.The battery protection circuit according to the embodiment of the present invention may include two or more control units 100 for controlling charge and discharge of the battery, and each of the two or more control units 100 may be connected in parallel.
이와 같이 둘 이상의 제어부(100)를 병렬로 연결하여 배터리 보호 회로를 구하는 이유는, 배터리의 용량 및 배터리의 충방전 전류에 따라서 배터리 보호 회로에 사용되는 FET의 개수가 달라지기 때문이다.The reason why the two or more control units 100 are connected in parallel to obtain the battery protection circuit is that the number of FETs used in the battery protection circuit varies depending on the capacity of the battery and the charge / discharge current of the battery.
또한, 둘 이상의 제어부(100)를 병렬로 연결하여 배터리 보호 회로를 구성하게 되면, 일부 제어부(100)에 이상이 생기는 경우 나머지 제어부(100)을 통하여 배터리의 충방전 제어가 가능해지므로 배터리의 안정성이 향상될 수 있다.In addition, when two or more control units 100 are connected in parallel to constitute a battery protection circuit, if an error occurs in a part of the control unit 100, the charge and discharge of the battery can be controlled through the remaining control unit 100, Can be improved.
한편, 상기 둘 이상의 제어부(100)는 배터리의 충전을 제어하는 충전 FET 및 배터리의 방전을 제어하는 방전 FET를 포함하여 구성될 수 있다.The two or more control units 100 may include a charging FET for controlling the charging of the battery and a discharging FET for controlling discharging of the battery.
한편, 상기 충전 FET와 방전 FET는 직렬로 연결될 수 있다.On the other hand, the charge FET and the discharge FET may be connected in series.
한편, 상기 둘 이상의 제어부(100) 는 배터리 보호 회로의 ESD 대응 구성으로 ESD 보호 구성(110,210)을 더 포함 할 수 있으며, 이러한 구성으로는 제노 다이오드가 사용될 수 있다.Meanwhile, the two or more control units 100 may further include ESD protection structures 110 and 210 as an ESD-compliant configuration of the battery protection circuit, and a gen diode may be used as the configuration.
구체적으로, 상기 둘 이상의 제어부(100) 중 적어도 어느 하나는 충전 FET 및 방전 FET 각각에 제노 다이오드를 병렬로 연결하여 구성 되거나, 상기 둘 이상의 제어부 중 전체가 아닌 일부의 제어부가 충전 FET 및 방전 FET 각각에 제노 다이오드를 병렬로 연결하여 구성될 수 있다.More specifically, at least one of the two or more control units 100 may be configured by connecting a plurality of generators to the charge FET and the discharge FET in parallel, or a part of the two or more control units may be connected to the charge FET and the discharge FET And a junode diode connected in parallel.
한편, 상술한 충전 FET 및 방전 FET 각각에 제노 다이오드가 병렬로 연결되어 있는 구성 대신에 충전 FET 및 방전 FET를 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성될 수도 있다.Instead of the configuration in which the charge and discharge FETs and the discharge FETs are connected in parallel with each other, the charge FET and the discharge FET may be constituted by integrating the generator diode and the FET into one chip.
한편, 이하에서는 상기 도 3 및 도 4를 참조하여, 둘 이상의 제어부가 2개로 구성되는 경우에 대해서 구체적인 실시 예를 통해서 설명하도록 한다.3 and 4, a case where two or more control units are constituted will be described with reference to specific embodiments.
도 3은 본 발명의 실시 예에 따른 배터리 보호 회로의 계략적인 도면이고, 도 4는 본 발명의 실시 예에 따른 배터리 보호 회로의 구체적인 도면이다.FIG. 3 is a schematic diagram of a battery protection circuit according to an embodiment of the present invention, and FIG. 4 is a specific diagram of a battery protection circuit according to an embodiment of the present invention.
이하에서는, 도 3 및 도 4를 참조하여 본 발명의 실시 예에 따른 보호 회로를 설명한다.Hereinafter, a protection circuit according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG.
도 3 및 도 4를 살펴보면, 상기 2개로 구성되는 제1 제어부(120)및 제2 제어부(120) 각각은 배터리 보호 회로의 ESD 대응을 위한 ESD 보호 구성(110,210)을 포함하여 구성될 수 있다,3 and 4, each of the first and second control units 120 and 120 may include ESD protection units 110 and 210 for ESD protection of the battery protection circuit.
보다 구체적으로, 상기 ESD 보호 구성으로는 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 충전 FET(101,201) 및 방전 FET(102,202)를 구성함으로써 형성될 수 있다.More specifically, the ESD protection structure can be formed by configuring the charge FETs 101 and 201 and the discharge FETs 102 and 202 as elements in which the genodiode and the FET are integrated into a single chip.
이때, 상기 제노 다이오드와 FET가 하나의 칩으로 통합된 소자의 저항 값은 상술한 종래 기술의 일반적인 FET 보다 통상적으로 큰 저항 값을 가진다. 예컨대, 상기 제노 다이오드와 FET가 하나의 칩으로 통합된 소자의 저항은 4Ω일 수 있다.At this time, the resistance value of a device in which the genodiode and the FET are integrated into one chip has a resistance value which is generally larger than that of the conventional FET described above. For example, the resistance of a device in which the genodiode and the FET are integrated into one chip may be 4?.
이와 같이 제1 제어부(120) 및 제2 제어부(220)각각를 구성하는 충전 FET(101,201)과 방전 FET(201,202) 모두를 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성하는 경우, 제노 다이오드를 포함하는 FET가 일반 FET보다 저항 값이 크므로, 배터리 보호 회로의 전체적인 저항이 커질 수 있다.In the case where both the charge FETs 101 and 201 and the discharge FETs 201 and 202 constituting the first control unit 120 and the second control unit 220 are constituted by devices in which the genodiode and the FET are integrated into one chip, Can have a larger resistance value than a general FET, so that the overall resistance of the battery protection circuit can be increased.
그런데, 배터리 보호 회로는 배터리 팩 전체의 설계 요건상 보호회로의 저저항 설계가 요구되는 경우가 있어 이를 만족하기 어려운 경우가 발생한다.However, a low-resistance design of the protection circuit on the design requirement of the entire battery pack is required for the battery protection circuit, which may be difficult to satisfy.
즉, 이와 같이 구성된 배터리 보호 회로의 전체 저항은 4Ω으로 산출 되어 일반적인 3Ω의 FET만을 사용하여 구성된 종래의 보호 회로보다 저항 값이 켜져서 배터리 팩의 설계 요건(3Ω 이하)을 만족할 수 없다.That is, the total resistance of the battery protection circuit constructed as described above is calculated as 4 OMEGA, so that the resistance value is turned on and can not satisfy the design requirement (3 OMEGA or less) of the battery pack as compared with the conventional protection circuit using only a general FET of 3 OMEGA.
따라서, 배터리 팩의 설계 요건을 만족하는 저저항 설계를 구현하기 위한 다른 다른 실시 예로, 도 5와 같이 배터리 보호 회로를 설계할 수 있다.Therefore, in another embodiment for implementing a low resistance design satisfying the design requirements of the battery pack, a battery protection circuit can be designed as shown in FIG.
보다 구체적으로, 제1 제어부(120) 또는 제2 제어부(220) 중 어느 하나의 제어부에만 제노 다이오드와 FET가 하나의 칩으로 통합된 소자를 충전 FET(101) 및 방전 FET(101)로 사용하여 배터리 보호 회로를 구성할 수 있다.More specifically, using either the first FET 120 or the second FET 220 as a charge FET 101 and a discharge FET 101 as a device integrating a genodiode and a FET into one chip A battery protection circuit can be constructed.
도 5는 제1 제어부(120)의 충전 FET(101) 및 방전 FET(102)는 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성하고 제2 제어부(200)의 충전 FET(203) 및 방전 FET(204)는 저저항 FET로 구성한 실시 예의 도면이다. 5 shows that the charging FET 101 and the discharging FET 102 of the first control unit 120 are constituted by elements in which the genodiode and the FET are integrated into one chip and the charging FET 203 and the charging FET 203 of the second control unit 200 The discharge FET 204 is an embodiment of a low-resistance FET.
한편, 상기 저저항 FET는 통상적인 일반 FET 보다 작은 저항 값을 가지는 FET일 수 있다. 예컨대 상기 저저항 FET의 저항은 2Ω일 수 있다.On the other hand, the low-resistance FET may be a FET having a resistance value smaller than that of a conventional general FET. For example, the resistance of the low-resistance FET may be 2?.
도 5와 같이 제1 제어부(120)의 충전 FET(101)와 방전 FET(102)는 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성하고, 제2 제어부(220)의 충전 FET(203)와 방전 FET(204)는 저저항 FET로 구성되는 경우, 이래 수식으로 배터리 보호 회로의 저항을 산출할 수 있다.5, the charging FET 101 and the discharging FET 102 of the first control unit 120 are constituted by elements in which the genodiode and the FET are integrated into one chip, and the charging FET 203 of the second control unit 220 And the discharging FET 204 are constituted by a low-resistance FET, the resistance of the battery protection circuit can be calculated from the equation since then.
(수식)(Equation)
Figure PCTKR2018010994-appb-I000001
Figure PCTKR2018010994-appb-I000001
상기 수식으로 산출된 도 5의 배터리 보호 회로의 전제 저항은 2.7Ω이다.The total resistance of the battery protection circuit of Fig. 5 calculated by the above equation is 2.7?.
즉, 도 5와 같이 구성된 배터리 보호 회로는 ESD 대응 구성을 가지면서도 배터리 팩의 설계 요건(3Ω 이하)을 만족 시킬 수 있다.That is, the battery protection circuit constructed as shown in Fig. 5 can satisfy the design requirement (less than 3?) Of the battery pack while having the ESD-compatible configuration.
한편, 상술한 본 발명의 실시 예 및 다른 실시 예에서 제노 다이오드와 FET가 하나의 칩으로 통합된 소자는, FET와 제노 다이오드를 병렬로 연결하여 구현할 수도 있다.Meanwhile, in the above-described embodiments of the present invention and other embodiments, a device in which a genodiode and a FET are integrated into one chip may be realized by connecting a FET and a genodiode in parallel.
한편, 본 발명의 기술적 사상은 상기 실시 예에 따라 구체적으로 기술되었으나, 상기 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지해야 한다. 또한, 본 발명의 기술분야에서 당업자는 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (7)

  1. 과충전, 과방전, 과전류로부터 배터리를 보호 하는 보호회로에 있어서,1. A protection circuit for protecting a battery from overcharge, overdischarge, and overcurrent,
    상기 보호 회로는,The protection circuit comprising:
    배터리를 구성하고 있는 배터리 셀과 외부 입출력 단 사이에 구비되고,The battery pack is provided between a battery cell constituting the battery and an external input /
    배터리의 충방전을 제어하는 둘 이상의 제어부;At least two control units for controlling charging and discharging of the battery;
    를 포함하여 구성되며,And,
    상기 둘 이상의 제어부는 각각 병렬로 연결되어 있는 것을 특징으로 하는 배터리 보호 회로.Wherein the at least two control units are connected in parallel.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 둘 이상의 제어부 각각은, Wherein each of the two or more control units comprises:
    배터리의 충전을 제어하는 충전 FET; 및A charging FET for controlling charging of the battery; And
    배터리의 방전을 제어하는 방전 FET;A discharge FET for controlling discharge of the battery;
    를 포함하여 구성되는 것을 특징으로 하는 배터리 보호 회로.Wherein the battery protection circuit comprises:
  3. 청구항 2에 있어서,The method of claim 2,
    상기 충전 FET와 방전 FET는 직렬로 연결되는 것을 특징으로 하는 배터리 보호 회로.Wherein the charging FET and the discharging FET are connected in series.
  4. 청구항 2에 있어서,The method of claim 2,
    상기 둘 이상의 제어부 중 적어도 어느 하나는,Wherein at least one of the two or more control units comprises:
    충전 FET 및 방전 FET 각각에 제노 다이오드를 병렬로 연결하여 구성되는 것을 특징으로 하는 배터리 보호 회로.A charge FET and a discharging FET connected in parallel to each other.
  5. 청구항 2에 있어서,The method of claim 2,
    상기 둘 이상의 제어부 중 적어도 어느 하나는,Wherein at least one of the two or more control units comprises:
    충전 FET 및 방전 FET를 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성되는 것을 특징으로 하는 배터리 보호 회로.Wherein the charge FET and the discharge FET are constituted by a device in which a genodiode and a FET are integrated into a single chip.
  6. 청구항 2에 있어서, The method of claim 2,
    상기 둘 이상이 제어부 중 전체가 아닌 일부의 제어부가A part of the control units, which are not all of the control units,
    충전 FET 및 방전 FET 각각에 제노 다이오드를 병렬로 연결하여 구성되는 것을 특징으로 하는 배터리 보호 회로.A charge FET and a discharging FET connected in parallel to each other.
  7. 청구항 2에 있어서,The method of claim 2,
    상기 둘 이상의 제어부 중 전체가 아닌 일부의 제어부가A part of the control units, not all of the two or more control units,
    충전 FET 및 방전 FET를 제노 다이오드와 FET가 하나의 칩으로 통합된 소자로 구성되는 것을 특징으로 하는 배터리 보호 회로.Wherein the charge FET and the discharge FET are constituted by a device in which a genodiode and a FET are integrated into a single chip.
PCT/KR2018/010994 2017-09-19 2018-09-18 Low-resistance battery protective circuit capable of coping with esd WO2019059616A1 (en)

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