WO2019056650A1

WO2019056650A1 - Method for optimizing pcb inner layer pattern, pcb, board spliced structure and laminated structure

Info

Publication number: WO2019056650A1
Application number: PCT/CN2017/120099
Authority: WO
Inventors: 程柳军; 陈蓓; 李艳国; 李华
Original assignee: 广州兴森快捷电路科技有限公司; 深圳市兴森快捷电路科技股份有限公司; 宜兴硅谷电子科技有限公司
Priority date: 2017-09-22
Filing date: 2017-12-29
Publication date: 2019-03-28
Also published as: CN107623992A

Abstract

A method for optimizing a PCB inner layer pattern, a PCB, a board spliced structure, and a laminated structure. A PCB inner layer pattern comprises a copper region (600) and a copper-free region (100); the copper-free region (100) comprises a via hole region (10) having at least one via hole (11); when a residual copper rate of the copper region (600) is less than a specific value, copper dots (12) are laid out at the positions of the via holes (11), and the diameter of the copper dot (12) is less than that of the via hole (11). Such small-size copper dots laid out can improve distribution uniformity of the pattern and reduce the volume of glue required for glue filling in the copper-free region, so that risks of wrinkling, cavities and the like of a copper foil subjected to lamination processing can be reduced. Moreover, the size of the copper dot is less than that of the via hole, so that the copper dots can be drilled off during drilling. In addition, layout of the copper dots can further promote PCB drilling quality to a certain degree and particularly has a great improvement effect on drilling haloing, so that CAF performance of the PCB is improved.

Description

Optimization method of PCB inner layer graphics and PCB, panel structure and laminated structure

Technical field

The present invention relates to the field of electronics, and more particularly to an optimized method for PCB inner layer graphics, a PCB, a panel structure, and a laminate structure.

Background technique

Traditionally, with the rapid development of the electronics industry, as an indispensable component of the transmission of electrical properties of electronic products, printed circuit boards are increasingly becoming faster and more multi-layered. The high-multi-layer circuit board is produced by laminating, drilling, electroplating, etching and the like through a plurality of core plates and prepregs for forming patterns such as lines, wherein lamination processing is one of the key processes of PCB fabrication, PCB The lamination quality is related to the further processing and application of subsequent products, such as drilling, graphic production, plug hole grinding, product reliability, PCB mounting and so on. For high-layer PCB fabrication, problems such as wrinkling of copper foil, lamination of voids, and the like, especially for high-speed PCB materials, make these problems more prominent. Compared with the FR4 material, the laminating processing window of the high-speed material is narrower, and the fluidity and the filling ability of the prepreg are worse, and the problem of wrinkling of the copper foil and lamination of the void is more likely to occur, especially when the inner layer of the graphic unit is patterned. When designing a copper-free zone with a large size, the copper-free zone is extremely prone to defects such as lack of glue and wrinkling of copper foil, while the lack of glue is likely to cause short-circuit problems after drilling and plating, and the lack of glue also affects the PCB. Reliability; wrinkling of copper foil will cause the film in the post-process to be not tight, causing defects such as plating and opening.

Summary of the invention

Based on this, the present invention overcomes the defects that the copper-free region of the prior art PCB is extremely prone to lack of glue and wrinkles of the copper foil, and provides an optimized method for the inner layer pattern of the PCB, the PCB, the panel structure and the laminated structure.

Its technical solutions are as follows:

A method for optimizing a pattern of a PCB inner layer, the inner layer pattern of the PCB includes a copper region and a copper-free region, and the copper-free region includes a via region provided with at least one via hole, and when the copper region has a residual copper ratio less than a specific In the case of a value, a copper dot is laid at the via position of the via, and the diameter of the copper dot is smaller than the diameter of the via.

Since there is an effective pattern in the via region, that is, a via hole, the prior art cannot provide a choke block in such a copper-free via region, so that there is a risk of wrinkling and lack of glue in the copper foil during the lamination process, in order to improve this. Phenomenon, and does not affect the electrical transmission performance of the PCB. When the PCB design of the engineering CAM is optimized, when the residual copper ratio of the copper region is less than a specific value, a copper point smaller than the diameter of the via hole is disposed in the via region, copper The point layout position is the same as that of the drilled drill belt, that is, copper dots are respectively arranged at each of the via holes. The small-sized copper dots arranged in this kind can improve the uniformity of pattern distribution and reduce the amount of glue required for filling without copper, thereby reducing the risk of wrinkling and voiding of copper foil after lamination processing, and at the same time, copper The size of the dots is smaller than that of the via holes, and can be drilled during drilling without affecting the electrical performance of the PCB. In addition, the layout of the copper dots can also improve the drilling quality of the PCB to a certain extent, especially for the halo of the borehole. The improvement effect is greater, thereby improving the CAF performance of the PCB.

In one embodiment, the difference between the diameter of the copper dots and the diameter of the vias ranges from 2 mils to 6 mils.

In one embodiment, when the residual copper ratio of the copper region is greater than the specific value, a copper skin is disposed in the via region, and the copper skin is disposed at a via position of the via hole. An isolation ring having a diameter greater than a diameter of the via.

In one of the embodiments, the difference between the diameter of the spacer ring and the diameter of the via hole ranges from 10 mil to 30 mils.

The technical solution also provides a PCB, which is a PCB fabricated according to an embodiment of an optimization method of any of the above-mentioned PCB inner layer patterns.

In one of the embodiments, a milling belt is included as a milling path with at least one glue point on the milling belt.

In one embodiment, the shape of the glue dot is square or circular, and the length or diameter of the glue dot ranges from 5 mil to 20 mil, and the distance from the glue point to the edge of the milling tape It is 5mil-10mil.

The technical solution further provides a PCB structure, including a PCB, the PCB is the PCB described in any of the above embodiments, the PCB includes at least two graphic units provided with the copper-free area, and adjacent graphic units The copper-free zone is staggered. Avoid excessive accumulation of copper-free areas, and it is more likely to cause wrinkling of copper foil and lamination of voids.

The technical solution further provides a laminated structure comprising a pre-laminated board comprising at least two layers of PCBs stacked in a stack, the PCB being the PCB described in any of the above embodiments; A buffer layer is provided above the upper surface layer and below the upper surface layer. In the PCB lamination process, it is necessary to use a steel plate to press the pre-laminated board. Due to the poor coating effect of the steel sheet, when there is a large-sized copper-free area in the high-layer PCB, the pressure in the copper-free area is small or even lost. Pressing, which easily leads to rubber filling defects and wrinkling of copper foil. The technical solution can effectively improve the pressure loss condition of the copper-free area of the high-layer PCB by improving the flow uniformity by adding a buffer layer to the upper and lower layers of the pre-laminated board.

In one embodiment, the buffer layer comprises a prepreg layer and a copper foil layer, the prepreg layer being disposed between the two layers of copper foil.

The beneficial effects of the invention are:

When the residual copper ratio of the copper region is less than a specific value, copper dots smaller than the diameter of the via holes are arranged in the via region, and the copper dots are arranged in the same manner as the drilled drill tapes, that is, copper is separately disposed at each via hole position. point. The small-sized copper dots arranged in this kind can improve the uniformity of pattern distribution and reduce the amount of glue required for filling without copper, thereby reducing the risk of wrinkling and voiding of copper foil after lamination processing, and at the same time, copper The size of the point is smaller than that of the through hole, and can be drilled during drilling; in addition, the layout of the copper point can also improve the drilling quality of the PCB to a certain extent, especially for the improvement of the drilling halo, thereby improving CAF performance of the PCB.

When the residual copper ratio of the copper region is greater than the specific value, a copper skin is disposed in the via region, and the copper skin is provided with an isolation ring at a via position of the via hole, and the isolation ring has a diameter larger than The diameter of the via. Such an optimization method can improve the uniformity of the pattern distribution and reduce the amount of glue required for filling the copper-free area, thereby reducing the lamination processing for the case where the residual copper ratio of the copper area around the copper-free area is large. After the copper foil is wrinkled, hollow and so on. In order to prevent the via from being turned on and the copper skin is short-circuited, an isolation ring is disposed between the via hole and the copper skin, that is, the copper skin needs to be wound around the via hole and disposed at other positions in the via hole region, the copper skin An annular hollowing process is performed along the outer circumference of the hole at the via hole to form an isolation ring.

The panel structure of the invention avoids excessive accumulation of copper-free areas, and is more likely to cause wrinkling of copper foil, lamination of voids and the like.

The invention can effectively improve the pressure loss condition of the copper-free zone of the high-layer PCB and improve the uniformity of the glue by adding a buffer layer to the upper and lower layers of the pre-laminated board.

DRAWINGS

1 is a schematic diagram 1 of an optimized structure of a PCB of the present invention;

2 is a schematic diagram 2 of an optimized structure of a PCB of the present invention;

3 is a schematic structural view of a PCB of the present invention;

Figure 4 is a partial structural view of the milling belt of Figure 3;

Figure 5 is a schematic view showing the structure of the glue blocking point of the adjacent inner layer on the milling belt of the present invention;

6 is a schematic structural view 1 of a PCB of the present invention;

7 is a schematic structural view 2 of a PCB of the present invention;

Figure 8 is a schematic structural view 3 of the PCB of the present invention;

Figure 9 is a schematic view of the laminated structure of the present invention.

Description of the reference signs:

100, no copper area; 10, via area; 11, via; 12, copper point; 13, copper; 131, isolation ring; 200, milling belt; 20, resistance point; 21, first resistance point 22, the second resistance point; 300, graphic unit; 400, pre-stacked; 500, buffer layer; 51, pre-cured layer; 52, copper foil layer; 600, with copper area.

Detailed ways

The present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of the invention.

As shown in FIG. 1, an optimization method of a PCB inner layer pattern includes a copper region 600 and a copper-free region 100, and the copper-free region 100 includes a via region 10 provided with at least one via hole 11. When the residual copper ratio of the copper region is less than a specific value, the copper dots 12 are disposed at the via locations of the via holes 11, and the diameter of the copper dots 12 is smaller than the diameter of the via holes.

Since the via pattern 10 has an effective pattern, that is, the via hole 11, the prior art cannot provide a choke block in the copper-free via-hole region 10, so that there is a risk of wrinkling and lack of glue in the copper foil during the lamination process. In order to improve this phenomenon and not affect the electrical transmission performance of the PCB, when the engineering CAM performs PCB optimization, when the residual copper ratio of the copper region is less than a specific value, the ratio of the via holes in the via region 10 is set. The copper dot 12 having a small diameter of the hole 11; in the embodiment, the specific value is 30%, that is, when the residual copper ratio of the copper region is less than 30%, the copper dot may be disposed, specifically, the copper region The residual copper ratio is selected from the residual copper ratio of the copper region around the copper-free region 100, and the residual copper ratio of the copper region within 2 cm of the copper-free region 100 can be selected as a reference value. The copper dots 12 are arranged in conformity with the drilled drill tapes, that is, copper dots 12 are respectively disposed at the via positions of each of the via holes 11. Such a small-sized copper dot 12 can improve the uniformity of the pattern distribution, reduce the amount of glue required for the glue-free area 100, and thereby reduce the risk of wrinkling and voiding of the copper foil after lamination processing, and at the same time, Because the copper dot size is smaller than the via hole, it can be drilled during drilling without affecting the electrical performance of the PCB. In addition, the copper dot 12 can also improve the drilling quality of the PCB to a certain extent, especially for drilling. The halo improvement effect is greater, thereby improving the CAF performance of the PCB.

The difference between the diameter of the copper dots 12 and the diameter of the via holes 11 ranges from 2 mil to 6 mils. The copper dots 12 of this size range can be successfully drilled during drilling, and the specific size difference can also be determined according to the copper residual rate of the copper region around the copper-free region 100.

As shown in FIG. 2, when the residual copper ratio of the copper region around the copper-free region 100 is greater than the specific value, that is, greater than 30%, a copper skin 13 is disposed in the via region 10, the copper skin 13 is provided at the position of the via hole of the via hole 11 with a spacer ring 131 having a diameter larger than the diameter of the via hole 11. Such an optimization method can improve the uniformity of the pattern distribution and reduce the amount of glue required for the filler in the copper-free region, thereby reducing the lamination of the copper in the copper-free region. There is a risk of wrinkling and voiding of the processed copper foil. In order to prevent the via hole 11 from being electrically connected to the copper skin 13 and causing a short circuit, an isolation ring 131 is disposed between the via hole 11 and the copper skin 13, that is, the copper skin 13 needs to be wound around the via hole 11 to be disposed in the via hole. At other positions of the region 10, the copper sheet 13 is annularly hollowed along the outer periphery of the hole at the via hole 11 to form the spacer ring 131. The diameter of the spacer ring 131 may be determined according to the process capability of the PCB factory and the copper residual rate of the copper region around the copper-free region 100. In the present embodiment, the diameter of the spacer ring 131 and the diameter of the via hole 11 The difference in size ranges from 10 mil to 30 mils, and the diameter of the spacer ring 131 can be set to be 10 mil to 30 mils larger than the diameter of the via hole 11.

The embodiment further provides a PCB, which is a PCB fabricated according to an embodiment of an optimization method of any of the above-mentioned PCB inner layer patterns. The PCB is fabricated according to the optimized method of the inner layer pattern of the above PCB, which reduces the risk of wrinkling and voiding of the copper foil after the PCB laminate processing.

As shown in FIGS. 3 and 4, the PCB of the present embodiment includes a milling belt 200 as a milling cutter path, and the milling belt 200 is provided with at least one rubber resistant dot 20. When a high-layer PCB is fabricated, the copper-free region 100 of each layer of the PCB is accumulated, and there are often depressions at the milled belt 200, wrinkles of the copper foil, etc., and since the milling belt 200 is next to the graphic unit 300, the milling belt 200 Insufficient position filling often affects the quality of the graphic unit. To improve this phenomenon, a certain size of the resistance point 20 can be laid on the path of the milling belt 200, and the resistance point 20 can be a copper point. The shape of the glue point 20 is square or round. In this embodiment, a round resistance point is used, and the glue point 20 is a copper point. Since the size of the milling tape 200 is generally small and the width is about 0.1 inch, the laying of the rubber resistant dot 20 also requires the use of small-sized dots or squares, and the length or diameter of the rubber-resistant dot 20 ranges from 5mil-20mil, the center spacing of adjacent glue points 20 can be set to 5-20mil. In addition, the distance from the glue point 20 to the edge of the milling belt 200 is 5 mils to 10 mils. The specific size and spacing of the resistance point 20 can be determined according to the residual copper ratio within two inches of the milling tape 200. When the residual copper loss rate is low, for example, when the residual copper ratio is less than 30%, the resistance point can be The side length or diameter of 20 is set to 5 mils, and the center spacing of adjacent glue points 20 is set to 15 mils; when the residual copper ratio of the pattern is normal, for example, 30% ≤ residual copper ratio < 50%, the resistance point 20 can be The side length or diameter is set to 10 mils, and the center distance of adjacent glue points 20 is set to 20 mils; when the residual copper ratio is large, for example, when the residual copper ratio is ≥ 50%, the side length of the resist point 20 can be Or the diameter is set to 10 mils and the center spacing of adjacent glue points 20 is set to 5 mils. Try to make the residual copper ratio of the milling tape 200 consistent with the residual copper ratio of the pattern to improve the uniformity of the thickness of the plate. In addition, as shown in FIG. 5, when the PCB has two or more layers, the glue resistance points 20 of the adjacent inner layers on the milling tape 200 are alternately arranged to further improve the uniformity of the thickness; the first layer of the L _n layer in the figure point 21 and a plastic barrier layer adjacent to L _n L _{n + 1} of the second barrier layer 22 of adhesive spots staggered.

As shown in FIG. 6 to FIG. 8 , the present embodiment further provides a panel structure, including a PCB, wherein the PCB is the PCB described in any of the above embodiments, and the PCB includes at least two copper-free regions. In the graphic unit 300 of 200, the copper-free regions 200 of the adjacent graphic units 300 are staggered to avoid excessive accumulation of the copper-free region 200, which is more likely to cause wrinkling of the copper foil and lamination of voids. As shown in FIG. 6 and FIG. 7 , there is a six-figure unit 300 in the panel structure, that is, six graphics units 300 are present in the panel, and each of the graphics units 300 includes a copper area 600 and a copper-free area 200, and each graphic unit The copper-free area 200 of 300 is staggered; as shown in FIG. 8, a three-piece puzzle structure, that is, three graphic units 300 are present in the puzzle; the layout structure of the present embodiment is also applicable to other ones. board.

The embodiment further provides a laminated structure, including a pre-laminated plate 400, which includes at least two layers of PCBs stacked in a stack, and a prepreg is disposed between the PCBs of adjacent layers, and the PCB is the above-mentioned A PCB according to an embodiment; a buffer layer 500 is disposed above the upper surface layer and below the upper surface layer of the pre-stacked board 400 to form a new stacked board structure. In the PCB lamination process, two steel plates are used to press the pre-laminated plate 400. Due to the poor coating effect of the steel plate, when the high-layer PCB has a large-sized copper-free region 100, the pressure of the copper-free region 100 is not affected. Smaller, even losing pressure, which easily leads to rubber filling defects and wrinkling of copper foil. In this embodiment, by adding a buffer layer 500 to the upper and lower layers of the pre-laminated plate 400, that is, the buffer layer 500 is disposed between the steel plate and the pre-laminated plate 400, the copper-free region 100 of the high-layer PCB can be effectively improved. Loss of pressure, improve flow uniformity.

In the present embodiment, the buffer layer 500 includes a prepreg layer 51 and a copper foil layer 52, and the prepreg layer 51 is disposed between the two copper foil layers 52. Since the expansion coefficients of different materials are different, during the PCB lamination process, the expansion amount of the steel sheet for pressing is smaller than the expansion amount of the copper foil on the pre-lamination plate 400, and the steel plate limits the expansion of the copper foil on the plane. In order to release the expansion stress, the copper foil is recessed toward the side of the prepreg in the PCB, thereby causing wrinkling of the copper foil; and the copper foil layer 52 of the buffer layer 500 is in contact with the pre-laminated plate 400 to be pressed, thereby avoiding the steel plate and the PCB. The copper foil has a thermal expansion coefficient that is inconsistent and causes a problem of wrinkling of the copper foil. Further, the thickness of the copper foil layer 52 may be 12 μm or 18 μm, and the prepreg layer 51 may be a conventional FR4 material, and the specifications may be 1080, 3313, 2116, etc., thereby reducing the cost of the buffer layer 500. At the same time, after the copper foil layer 52 of the buffer layer 500 is laminated, it can be peeled off for recycling, and can be processed and reused to avoid material waste. In addition, the laminated structure of the copper foil layer 52 and the prepreg layer 51 can not only effectively improve the wrinkles and voids of the copper foil in the high-layer PCB lamination process, but also reduce the shrinkage of the material during the lamination process. It is beneficial to the interlayer alignment control of high-layer PCB. Since the steel plate has its inherent expansion coefficient in the X direction and the Y direction, since the conventional pre-laminated plate 400 does not have the buffer layer 500, the steel plate generates a large tensile force in the X direction and the Y direction, and the present embodiment is employed. The laminated structure can provide static pressure instead of tensile pressure, which helps to balance the surface pressure, thereby improving the shrinkage and shrinkage, and the plate of the present embodiment has a shrinkage value smaller than that of the conventional laminated structure. About three points can reduce the variation of lamination shrinkage, which is more conducive to controlling the alignment quality between layers.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A method for optimizing a pattern of a PCB inner layer, characterized in that the inner layer pattern of the PCB comprises a copper region and a copper-free region, and the copper-free region comprises a via region provided with at least one via hole, and when there is a copper region When the copper ratio is less than a specific value, a copper dot is disposed at a via position of the via hole, and the diameter of the copper dot is smaller than the diameter of the via hole.
The method for optimizing a pattern of a PCB inner layer according to claim 1, wherein a difference between a diameter of the copper dot and a diameter of the via hole ranges from 2 mil to 6 mil.
The method for optimizing a pattern of a PCB inner layer according to claim 1 or 2, wherein when the residual copper ratio of the copper region is greater than the specific value, copper is disposed in the via region, The copper skin is provided with a spacer ring at a via location of the via, the spacer ring having a diameter greater than a diameter of the via.
The method for optimizing a pattern of a PCB inner layer according to claim 3, wherein a difference between a diameter of the spacer ring and a diameter of the via hole ranges from 10 mil to 30 mil.
A PCB characterized in that the PCB is a PCB fabricated according to an optimization method of a PCB inner layer pattern according to any one of claims 1-4.
A PCB according to claim 5, comprising a milling belt as a milling path, said milling belt being provided with at least one glue point.
The PCB according to claim 6, wherein the resistance dot is square or circular in shape, and the length or diameter of the glue dot ranges from 5 mil to 20 mil.
A panel structure, comprising: a PCB, wherein the PCB is the PCB of any one of claims 5-7, the PCB comprising at least two graphic units provided with the copper-free area, adjacent The copper-free zone of the graphics unit is interleaved.
A laminated structure, comprising: a pre-laminated board comprising at least two layers of PCBs stacked in a stack, the PCB being the PCB according to any one of claims 5-7; A buffer layer is disposed above the upper surface of the board and below the upper layer.
The laminate structure according to claim 9, wherein said buffer layer comprises a prepreg layer and a copper foil layer, said prepreg layer being disposed between the two layers of copper foil.