WO2019048828A1 - Régulateur de tension - Google Patents

Régulateur de tension Download PDF

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Publication number
WO2019048828A1
WO2019048828A1 PCT/GB2018/052456 GB2018052456W WO2019048828A1 WO 2019048828 A1 WO2019048828 A1 WO 2019048828A1 GB 2018052456 W GB2018052456 W GB 2018052456W WO 2019048828 A1 WO2019048828 A1 WO 2019048828A1
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WO
WIPO (PCT)
Prior art keywords
transistor
effect
voltage
field
terminal
Prior art date
Application number
PCT/GB2018/052456
Other languages
English (en)
Inventor
Lukasz FARIAN
Original Assignee
Nordic Semiconductor Asa
Samuels, Adrian James
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nordic Semiconductor Asa, Samuels, Adrian James filed Critical Nordic Semiconductor Asa
Publication of WO2019048828A1 publication Critical patent/WO2019048828A1/fr

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to voltage regulators, particularly low-dropout voltage regulators.
  • Low-dropout (or LDO) voltage regulators are linear DC voltage regulators that are capable of operating with very low input-output differential voltages. Such regulators are usually chosen because they have a low minimum operating voltage, high power efficiency and low heat dissipation.
  • a conventional LDO voltage regulator typically includes an error amplifier and a pass field-effect-transistor or "pass-FET".
  • the error amplifier compares the output voltage (or a voltage derived therefrom) being generated by the LDO to a reference voltage and alters the conductance of the pass-FET in order to drive the output voltage to the desired value.
  • LDO voltage regulators may also include a native source follower (sometimes referred to in the art as a common-drain amplifier) located between the error amplifier and the pass-FET, wherein this native source follower is arranged to reduce the impedance at the gate of the pass-FET. Such a native source follower also acts to push the pole at the gate of the pass-FET to higher frequencies.
  • Such a source follower improves the frequency response and driving capabilities of the LDO voltage regulator.
  • a transistor e.g. a transistor arranged as a source follower
  • MOSFET metal- oxide-semiconductor field-effect-transistor
  • the threshold voltage of the native source follower can vary across a range of negative and positive values. This variation in the threshold voltage of the native source follower limits the output voltage swing at the gate of the pass-FET and decreases the maximum current that can be delivered by the LDO voltage regulator.
  • LDO voltage regulators should ideally be able to operate and be stable for supply voltages close to the regulated voltage and provide low drop-out voltages (e.g. less than 30 mV).
  • large pass-FETs are required in order to obtain sufficiently low drop-out voltages and it becomes critical to be able to maximise the conductance of the pass-FET (e.g. by pulling the gate terminal of a p-channel MOSFET or "pMOSFET" based pass-FET down to ground) in order to maximise the current produced by the LDO voltage regulator.
  • the present invention provides a low-dropout voltage regulator arranged to receive an input voltage at an input thereof and produce an output voltage at an output thereof, the low-dropout voltage regulator comprising:
  • a pass field-effect-transistor having a first terminal connected to the input voltage and a second terminal arranged to produce the output voltage
  • an error amplifier circuit portion arranged to produce, at an output thereof, an error signal proportional to a difference between a feedback voltage and a reference voltage, said feedback voltage being derived from the output voltage; a source follower transistor having a gate terminal connected to the output of the error amplifier such that the error signal is applied to said gate terminal of the source follower transistor, a drain terminal thereof connected to the input voltage, and a source terminal thereof connected to a gate terminal of the pass field-effect- transistor; and
  • an adaptive biasing circuit portion arranged to measure the error signal and produce a bias current which depends on said error signal, and to supply the bias current to the source follower transistor.
  • embodiments of the present invention provide an improved LDO voltage regulator that may operate close to the supply voltage and that provides an increased maximum current output compared to conventional LDO voltage regulators.
  • This is achieved by having the adaptive biasing circuit portion provide a bias current to the source follower transistor which controls the conductance of the pass field-effect-transistor (the "pass-FET").
  • the pass-FET the pass field-effect-transistor
  • an LDO voltage regulator in accordance with embodiments of the present invention advantageously allows the use of lower supply voltage ranges than conventional LDO voltage regulators, e.g. in one example allowing a reduction in the supply voltage from 1.2 V to 1.0 V, though it will of course be appreciated that the particular value of the supply voltage will depend on the process and types of transistors used.
  • the bias current produced by the adaptive biasing circuit portion is effectively a scaled replica of a load current produced by the LDO voltage regulator, i.e. the current produced at its output and that is provided to a connected load.
  • the bias current increases and the source follower is able to produce voltages at the gate of the pass-FET that provide a greater output voltage swing than is typically possible using conventional LDO voltage regulator designs, increasing the maximum current that can be delivered by the LDO voltage regulator.
  • the source follower can almost completely disable the pass-FET in order to limit leakage.
  • the pass-FET could comprise an nMOSFET.
  • the pass field-effect-transistor comprises a p-channel metal-oxide- semiconductor field-effect-transistor.
  • the pass-FET could be a depletion mode transistor, it is preferably an enhancement mode transistor.
  • the source follower may drive the gate of the pass-FET very low and, when the load current is sufficiently high, the gate terminal may be "pulled down" as close to ground as possible in order to maximise the conductance of the pass-FET.
  • the source follower may pull up the gate of the pass-FET as close to the supply voltage as possible in order to restrict leakage as much as possible.
  • the source follower may drive the gate of the pass-FET as close to the supply voltage as possible under high loads and as close to ground as possible under low loads.
  • the source follower transistor comprises a native field- effect-transistor.
  • native as used herein when referring to a transistor (e.g. a transistor arranged as a source follower) should be understood to mean a metal-oxide- semiconductor field-effect-transistor (MOSFET) that is neither enhancement type nor depletion type and that typically exhibits a near-zero threshold voltage - typically much less than 1 V, e.g. less than 100 mV.
  • MOSFET metal-oxide- semiconductor field-effect-transistor
  • the adaptive biasing circuit portion comprises a sense field- effect-transistor and a diode-connected field-effect-transistor arranged such that: the gate terminal of the sense field-effect-transistor is connected to the output of the error amplifier; and
  • the drain terminal of the sense field-effect-transistor is connected to the drain and gate terminals of the diode-connected field-effect-transistor.
  • the sense field-effect-transistor comprises a p-channel metal-oxide- semiconductor field-effect-transistor.
  • the source terminal of the sense field-effect-transistor is connected to the input voltage.
  • the diode-connected field-effect-transistor preferably comprises an n-channel metal-oxide-semiconductor field-effect-transistor.
  • the source terminal of the diode-connected field-effect-transistor is connected to ground.
  • the adaptive biasing circuit portion comprises a bias transistor having a drain terminal thereof connected to the source terminal of the source follower transistor and to the gate terminal of the pass field-effect-transistor, wherein a gate terminal of said bias transistor is connected to the drain and gate terminals of the diode-connected transistor.
  • drain and gate terminals of the diode-connected transistor could be directly connected to the gate terminal of the bias transistor, in a set of
  • the drain and gate terminals of the diode-connected transistor are connected to the gate terminal of the bias transistor via a low-pass filter.
  • the provision of a low pass filter between the diode-connected transistor and the bias- transistor reduces the impact of high frequency fluctuations on the conductance of the bias FET, and thus on the voltage at the gate of the pass-FET.
  • the bias transistor could be turned on at all times, in a set of embodiments the bias transistor is arranged such that it is turned off if a load current at the output of the low-dropout voltage regulator is below a predetermined threshold. This advantageously reduces the power consumption of the LDO voltage regulator when the bias transistor is not needed (i.e. at relatively low load currents).
  • Fig. 1 is a circuit diagram of an LDO voltage regulator in accordance with an embodiment of the present invention
  • Fig. 2 is a graph showing waveforms typical of the LDO voltage regulator of Fig. 1 in response to a step in the load current;
  • Fig. 3 is a graph showing the output voltage and the voltage at the gate of the pass-FET of the LDO voltage regulator of Fig. 1 as a function of load current.
  • Fig. 1 is a circuit diagram of a low-dropout (LDO) voltage regulator 2 in accordance with an embodiment of the present invention.
  • the LDO voltage regulator 2 is arranged to convert an input voltage V DD to an output voltage V 0 UT, wherein the output voltage V 0 UT is regulated, i.e. the output voltage V 0 UT is maintained at a constant voltage level.
  • the LDO voltage regulator 2 comprises: an error amplifier 4; an adaptive biasing circuit portion 6; a source follower native n-channel metal- oxide-semiconductor field-effect-transistor (native nMOSFET) M NA , and a pass field- effect-transistor or "pass-FET" M PAS s-
  • the pass-FET M PA ss is a p-channel metal-oxide-semiconductor field-effect- transistor and is arranged in series with a potential divider constructed from two fixed resistors R 2 .
  • the source terminal of the pass-FET M PA ss is connected to the input voltage V DD and the drain terminal of the pass-FET M PAS s is connected to one terminal of one of the fixed resistors F ⁇ at an output node 8 from which the output voltage V 0 UT is taken.
  • the resistor F ⁇ has its other terminal connected to ground via the other fixed resistor R 2 .
  • a load capacitance C L is connected in parallel with the resistors R 2 such that it is connected to the output node 8.
  • the error amplifier 4 comprises a differential amplifier (e.g. an operational amplifier or "op-amp") and is arranged such that its inverting input is connected to a reference voltage V RE F and its non-inverting input is connected to a node 10 between the two fixed resistors R 2 which supplies a feedback voltage V F B proportional to the output voltage V 0 UT-
  • V F B depends on the ratio of istors R 2 and the value output voltage VQUT
  • the error amplifier 4 produces at its output a voltage V S F which is applied to the gate terminal of the source follower native nMOSFET M NA .
  • the drain terminal of the source follower nMOSFET M NA is connected to the input voltage V DD while the source terminal of the source follower native nMOSFET M NA is connected to the gate terminal of the pass-FET M PAS s-
  • the adaptive biasing circuit portion 6 comprises: a sense pMOSFET M S ENSE; a diode-connected native nMOSFET M D ; a low-pass filter constructed from a resistor RI_P and a capacitor C L P; and a bias transistor Mi .
  • the sense pMOSFET M S ENSE is arranged such that its gate terminal is connected to the output of the error amplifier 4 (i.e. the voltage V S F is applied to the gate terminal of the sense pMOSFET MSENSE), its source terminal is connected to the input voltage V DD , and its drain terminal is connected to the drain and gate terminals of the diode-connected nMOSFET M D .
  • the source terminal of the diode-connected nMOSFET M D is connected to ground.
  • the drain and gate terminals of the diode-connected nMOSFET M D and the drain terminal of the sense pMOSFET M S ENSE are connected to one side of the low pass filter resistor R L p, the other side of which is connected to one plate of the filter capacitor C L P and to the gate terminal of the bias transistor while the other plate of the filter capacitor C L P is connected to ground.
  • the drain terminal of the bias transistor is connected to the source terminal of the source follower native nMOSFET M NA and to the gate terminal of the pass-FET M PAS s-
  • a small constant bias current I BIAS is connected in parallel to the biasing transistor M1 and is arranged to ensure that the native nMOSFET M NA is properly biased even when there is no load current, preventing the gate terminal of the pass-FET M PA ss from floating.
  • the LDO voltage regulator 2 is arranged to compare the feedback voltage V F B to the reference voltage V RE F and, based on the difference between these, vary the conductance of the source follower native nMOSFET M NA which, in turn, varies the conductance of the pass-FET M PAS s-
  • the bias current UDAPTIVE that flow through the native nMOSFET M NA (and, by extension, the biasing transistor M 1) will, in general, be a scaled replica of the load current l L produced by the LDO voltage regulator 2, and affects the effective gate-source voltage (i.e. V SF - V GATE ) of the native source follower M NA .
  • This bias current UDAPTIVE is equal to the sum of the small constant bias current I BIAS and the current IMI that flows through the biasing transistor M 1.
  • Fig. 2 is a graph showing waveforms typical of the LDO voltage regulator 2 of Fig. 1 in response to a step in the load current l L .
  • the LDO voltage regulator 2 is only driving a small load current l L , no current flows through the sense pMOSFET MSENSE which results in the impedance of M S ENSE being very high while the impedance of the diode-connected nMOSFET M D is relatively low, which pulls V L p very close to ground.
  • the biasing transistor M 1 is turned off and only a small current (e.g. 10 nA) flows through the native source follower M NA .
  • the voltage V GA TE at the gate terminal of the pass-FET M PAS s is approximately equal to the voltage V S F applied to the gate terminal of the native source follower M NA .
  • the load current l L is increased (e.g. it is stepped or ramped up), there will be a difference between the feedback voltage V F B and the reference voltage V RE F which are input to the error amplifier 4.
  • the output of the error amplifier 4 thus decreases, which will decrease the voltage V S F applied to the gate terminal of the sense pMOSFET MSENSE- AS a result, the voltage V L p produced by the low-pass filter (i.e. the resistor R L p and capacitor C L P), applied to the gate of the biasing transistor M 1 , is increased.
  • This increase in V L p increases the bias current l M i through the biasing transistor M 1 and the current UDAPTIVE flowing through the native transistor MNA, thus decreasing the gate voltage V G ATE applied to the gate terminal of the pass-FET
  • V L p reduces the bias current l M i through the biasing transistor M1 , and thus increases the current DAPTIVE flowing through the native transistor M NA - This effectively increases V GATE , which reduces the conductance of the pass-FET M PAS s This dynamic process maintains V 0UT at (or at least close to) the desired output
  • Fig. 3 is a graph showing the output voltage V 0UT and the voltage V GATE at the gate of the pass-FET of the LDO voltage regulator 2 of Fig. 1 as a function of load current l L compared to an output voltage V 0UT * and the voltage V GATE * at the gate of a pass-FET typical of a conventional LDO voltage regulator without adaptive biasing.
  • the adaptive biasing circuit portion 6 within the LDO voltage regulator 2 described above is able to pull the voltage V GATE applied to the gate terminal of the pass-FET M PA ss down to ground (i.e. 0 V), i.e.
  • embodiments of the present invention provide an improved LDO voltage regulator that can provide a greater maximum current than conventional LDO voltage regulators.
  • an LDO voltage regulator in accordance with embodiments of the present invention may also be more stable than conventional LDO voltage regulators and may employ a pass-FET that is physically smaller than would typically be permissible with conventional designs.
  • the embodiment described above is merely exemplary and is not limiting on the scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

La présente invention concerne un régulateur de tension à faible chute de tension (2) conçu pour recevoir une tension d'entrée (VDD) et produire une tension de sortie (VOUT)-. Un transistor à effet de champ de chute (MPASS) présente une première borne connectée à la tension d'entrée et une seconde borne conçue pour produire la tension de sortie. Un amplificateur d'erreur (4) est conçu pour produire un signal d'erreur (VSF) proportionnel à une différence entre une tension de rétroaction (VFB) et une tension de référence (VREF)-. Le signal d'erreur (VSF) est appliqué à la borne de grille d'un transistor suiveur de source (MNA). La borne de drain du transistor suiveur de source (MNA) est connectée à la tension d'entrée (VDD), et sa borne de source est connectée à la borne de grille du transistor à effet de champ de chute (MPASS)-. Une partie de circuit de polarisation adaptative (6) est conçue pour mesurer le signal d'erreur (VSF) et produire un courant de polarisation (lM1, I ADAPTATIVE) qui dépend dudit signal d'erreur (VSF), et pour fournir le courant de polarisation (lM1, IADAPTATIVE) au transistor suiveur de source (MNA).
PCT/GB2018/052456 2017-09-06 2018-08-30 Régulateur de tension WO2019048828A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB1714328.0A GB201714328D0 (en) 2017-09-06 2017-09-06 Voltage regulator
GB1714328.0 2017-09-06

Publications (1)

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WO2019048828A1 true WO2019048828A1 (fr) 2019-03-14

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3933543A1 (fr) * 2020-06-29 2022-01-05 Ams Ag Régulateur à faible chute de tension pour applications basse tension
CN113970949A (zh) * 2021-12-27 2022-01-25 江苏长晶科技股份有限公司 一种快速响应的高速线性稳压器
CN117118219A (zh) * 2023-10-08 2023-11-24 西安航天民芯科技有限公司 一种片内集成的软启动电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0957421A2 (fr) * 1998-05-13 1999-11-17 Texas Instruments Incorporated Régulateur de tension, efficace en courant, à faible tension de déchet avec une régualtion de la charge et une réponse en fréquence améliorée
US7218170B1 (en) * 2003-05-23 2007-05-15 Broadcom Corporation Multi-pole current mirror filter
US20150097540A1 (en) * 2013-10-04 2015-04-09 Silicon Motion Inc. Low-drop regulator apparatus and buffer stage circuit having higher voltage transition rate
GB2539457A (en) * 2015-06-16 2016-12-21 Nordic Semiconductor Asa Voltage regulators

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0957421A2 (fr) * 1998-05-13 1999-11-17 Texas Instruments Incorporated Régulateur de tension, efficace en courant, à faible tension de déchet avec une régualtion de la charge et une réponse en fréquence améliorée
US7218170B1 (en) * 2003-05-23 2007-05-15 Broadcom Corporation Multi-pole current mirror filter
US20150097540A1 (en) * 2013-10-04 2015-04-09 Silicon Motion Inc. Low-drop regulator apparatus and buffer stage circuit having higher voltage transition rate
GB2539457A (en) * 2015-06-16 2016-12-21 Nordic Semiconductor Asa Voltage regulators

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3933543A1 (fr) * 2020-06-29 2022-01-05 Ams Ag Régulateur à faible chute de tension pour applications basse tension
WO2022002465A1 (fr) * 2020-06-29 2022-01-06 Ams Ag Régulateur à faible chute de tension pour applications basse tension
CN113970949A (zh) * 2021-12-27 2022-01-25 江苏长晶科技股份有限公司 一种快速响应的高速线性稳压器
CN113970949B (zh) * 2021-12-27 2022-03-29 江苏长晶科技股份有限公司 一种快速响应的高速线性稳压器
CN117118219A (zh) * 2023-10-08 2023-11-24 西安航天民芯科技有限公司 一种片内集成的软启动电路

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Publication number Publication date
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