WO2019044029A1 - Silicon carbide epitaxial substrate and production method for silicon carbide semiconductor device - Google Patents

Silicon carbide epitaxial substrate and production method for silicon carbide semiconductor device Download PDF

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WO2019044029A1
WO2019044029A1 PCT/JP2018/016565 JP2018016565W WO2019044029A1 WO 2019044029 A1 WO2019044029 A1 WO 2019044029A1 JP 2018016565 W JP2018016565 W JP 2018016565W WO 2019044029 A1 WO2019044029 A1 WO 2019044029A1
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silicon carbide
layer
substrate
carbide epitaxial
main surface
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PCT/JP2018/016565
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French (fr)
Japanese (ja)
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洋典 伊東
勉 堀
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住友電気工業株式会社
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Priority to JP2019538952A priority Critical patent/JP7415558B2/en
Publication of WO2019044029A1 publication Critical patent/WO2019044029A1/en

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    • HELECTRICITY
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    • H01L21/02367Substrates
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    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
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    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/36Carbides
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    • H01L21/02529Silicon carbide
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a silicon carbide epitaxial substrate and a method of manufacturing a silicon carbide semiconductor device.
  • This application claims priority based on Japanese Patent Application No. 2017-168252, which is a Japanese patent application filed on September 1, 2017. The entire contents of the description of the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 JP-A-2014-170891 discloses a method of epitaxially growing a silicon carbide layer on a silicon carbide single crystal substrate.
  • a silicon carbide epitaxial substrate includes a silicon carbide substrate and a silicon carbide epitaxial film.
  • the silicon carbide epitaxial film is on a silicon carbide substrate.
  • the polytype of the silicon carbide substrate and silicon carbide epitaxial film is 4H.
  • the silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film.
  • the silicon carbide substrate, the first layer, and the second layer contain n-type impurities.
  • the concentration of n-type impurities contained in the first layer is lower than the concentration of n-type impurities contained in the silicon carbide substrate and higher than the concentration of n-type impurities contained in the second layer.
  • the main surface of the silicon carbide substrate has basal plane dislocations having a first surface density.
  • the main surface of the silicon carbide epitaxial film has basal plane dislocations having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less.
  • the main surface of the silicon carbide epitaxial film is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  • a silicon carbide epitaxial substrate includes a silicon carbide substrate and a silicon carbide epitaxial film.
  • the silicon carbide epitaxial film is on a silicon carbide substrate.
  • the polytype of the silicon carbide substrate and silicon carbide epitaxial film is 4H.
  • the silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film.
  • the silicon carbide substrate, the first layer, and the second layer contain n-type impurities.
  • the concentration of n-type impurities contained in the first layer is lower than the concentration of n-type impurities contained in the silicon carbide substrate and higher than the concentration of n-type impurities contained in the second layer.
  • the main surface of the silicon carbide substrate has basal plane dislocations having a first surface density.
  • the main surface of the silicon carbide epitaxial film has basal plane dislocations having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less.
  • the main surface of the silicon carbide epitaxial film is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  • the maximum diameter of the main surface of the silicon carbide epitaxial film is 150 mm or more.
  • the thickness of the first layer is 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the thickness of the second layer is 5 ⁇ m or more and 30 ⁇ m or less.
  • the concentration of the n-type impurity contained in the first layer is 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less.
  • the concentration of the n-type impurity contained in the second layer is 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less.
  • FIG. 1 is a schematic plan view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 2 is a schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 3 is a partial cross-sectional schematic view showing the configuration of the apparatus for manufacturing a silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 4 is a flow chart schematically showing a method of manufacturing a silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 5 is a schematic cross sectional view showing a first step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 6 is a schematic cross sectional view showing a second step of the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 7 is a diagram showing the manufacturing conditions of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 8 is a flow chart schematically showing a method of manufacturing a silicon carbide semiconductor device according to the present embodiment.
  • FIG. 9 is a schematic cross sectional view showing a first step of a method of manufacturing a silicon carbide semiconductor device according to the present embodiment.
  • FIG. 10 is a schematic cross sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment.
  • FIG. 11 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the present embodiment.
  • FIG. 12 is a diagram showing the manufacturing conditions of the silicon carbide epitaxial substrate according to Sample 2. As shown in FIG.
  • an individual orientation is indicated by []
  • a collective orientation is indicated by ⁇ >
  • an individual plane is indicated by ()
  • a collective plane is indicated by ⁇ .
  • the fact that the crystallographic index is negative is usually expressed by adding a "-" (bar) above the numbers, but in the present specification the crystallography is indicated by putting a negative sign before the numbers. Express the negative index above.
  • a silicon carbide epitaxial substrate 100 includes a silicon carbide substrate 10 and a silicon carbide epitaxial film 20.
  • Silicon carbide epitaxial film 20 is on silicon carbide substrate 10.
  • the polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H.
  • Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10, and a second layer 22 which is on first layer 21 and which constitutes main surface 14 of silicon carbide epitaxial film 20.
  • Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities.
  • the concentration of n-type impurities contained in the first layer 21 is lower than the concentration of n-type impurities contained in the silicon carbide substrate 10 and higher than the concentration of n-type impurities contained in the second layer 22.
  • Main surface 12 of silicon carbide substrate 10 has basal plane dislocation 1 having a first surface density.
  • Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocation 1 having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less.
  • Main surface 14 of silicon carbide epitaxial film 20 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  • a value obtained by dividing the second area density by the first area density may be 1/2000 or less.
  • maximum diameter 111 of main surface 14 of silicon carbide epitaxial film 20 may be 100 mm or more.
  • the maximum diameter 111 of the main surface 14 of the silicon carbide epitaxial film 20 may be 150 mm or more.
  • the silicon carbide epitaxial substrate 100 includes the silicon carbide substrate 10 and the silicon carbide epitaxial film 20.
  • Silicon carbide epitaxial film 20 is on silicon carbide substrate 10.
  • the polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H.
  • Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10, and a second layer 22 which is on first layer 21 and which constitutes main surface 14 of silicon carbide epitaxial film 20.
  • Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities.
  • the concentration of n-type impurities contained in the first layer 21 is lower than the concentration of n-type impurities contained in the silicon carbide substrate 10 and higher than the concentration of n-type impurities contained in the second layer 22.
  • Main surface 12 of silicon carbide substrate 10 has basal plane dislocation 1 having a first surface density.
  • Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocation 1 having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less.
  • Main surface 14 of silicon carbide epitaxial film 20 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  • Main surface 14 of silicon carbide epitaxial film 20 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  • the maximum diameter 111 of the main surface 14 of the silicon carbide epitaxial film 20 is 150 mm or more.
  • the thickness of the first layer 21 is 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the thickness of the second layer 22 is 5 ⁇ m or more and 30 ⁇ m or less.
  • the concentration of the n-type impurity contained in the first layer 21 is 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less.
  • the concentration of the n-type impurity contained in the second layer 22 is 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less.
  • the method for manufacturing the silicon carbide semiconductor device 300 according to the present disclosure includes the following steps.
  • the silicon carbide epitaxial substrate 100 according to any one of the above (1) to (5) is prepared. Silicon carbide epitaxial substrate 100 is processed.
  • silicon carbide epitaxial substrate 100 includes silicon carbide substrate 10 and silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. Silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11. The silicon carbide epitaxial film 20 is in contact with the first major surface 11. Silicon carbide epitaxial film 20 has a third main surface 13 in contact with first main surface 11 and a second main surface 14 opposite to third main surface 13. The polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. As shown in FIG. 1, the silicon carbide epitaxial substrate 100 may be provided with a first flat 16 extending in the first direction 101. Silicon carbide epitaxial substrate 100 may be provided with a second flat (not shown) extending in second direction 102.
  • the second direction 102 is, for example, a ⁇ 1-100> direction.
  • the first direction 101 is a direction parallel to the second major surface 14 and perpendicular to the second direction 102.
  • the first direction 101 is, for example, a direction including a ⁇ 11-20> direction component.
  • the maximum diameter 111 (diameter) of the second main surface 14 is, for example, 100 mm or more.
  • the maximum diameter 111 may be 150 mm or more, 200 mm or more, or 250 mm or more.
  • the upper limit of the maximum diameter 111 is not particularly limited.
  • the maximum diameter 111 may be, for example, 300 mm or less.
  • Silicon carbide substrate 10 is formed of, for example, a silicon carbide single crystal. Silicon carbide substrate 10 contains an n-type impurity such as nitrogen (N), for example.
  • the conductivity type of silicon carbide substrate 10 is, for example, n-type.
  • the first major surface 11 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane. When the first major surface 11 is tilted with respect to the (000-1) plane, the tilt direction of the first major surface 11 is, for example, the ⁇ 11-20> direction.
  • the thickness of silicon carbide substrate 10 is, for example, not less than 350 ⁇ m and not more than 500 ⁇ m.
  • silicon carbide epitaxial film 20 is on first main surface 11 of silicon carbide substrate 10.
  • Silicon carbide epitaxial film 20 is an epitaxial layer. Silicon carbide epitaxial film 20 is in contact with first main surface 11.
  • Silicon carbide epitaxial film 20 contains an n-type impurity such as nitrogen, for example.
  • the conductivity type of silicon carbide epitaxial film 20 is, for example, n-type.
  • the second main surface 14 is a surface inclined at an off angle ⁇ of 8 ° or less with respect to the carbon surface or the carbon surface. In other words, the second major surface 14 is a surface inclined at an off angle ⁇ of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  • the off direction is, for example, the ⁇ 11-20> direction.
  • the off direction is not limited to the ⁇ 11-20> direction.
  • the off direction may be, for example, a ⁇ 1-100> direction or a direction having a ⁇ 1-100> direction component and a ⁇ 11-20> direction component.
  • the off angle ⁇ is an angle at which the second major surface 14 is inclined to the (000-1) plane.
  • the off angle ⁇ is, for example, greater than 0 ° and not more than 8 °.
  • the off angle ⁇ may be 1 ° or more, or 2 ° or more.
  • the off angle may be 7 ° or less or 6 ° or less.
  • the surface described by a broken line in FIG. 2 is, for example, a ⁇ 0001 ⁇ surface.
  • the third direction 103 is a direction perpendicular to the ⁇ 0001 ⁇ plane.
  • the third direction 103 is, for example, the [000-1] direction.
  • the fourth direction 104 is a direction perpendicular to the third direction 103.
  • the fourth direction 104 is, for example, the ⁇ 11-20> direction.
  • the fourth direction 104 is, for example, the off direction.
  • the normal direction of the second major surface 14 is the fifth direction 105.
  • the fifth direction is a direction inclined by an off angle ⁇ in the off direction with respect to the [000-1] direction, for example.
  • silicon carbide epitaxial film 20 includes a first layer 21 and a second layer 22.
  • the first layer is, for example, a buffer layer.
  • the second layer 22 is, for example, a drift layer.
  • the first layer 21 is in contact with the first major surface 11.
  • First layer 21 is in contact with silicon carbide substrate 10.
  • the first layer 21 constitutes a third major surface 13.
  • the second layer 22 is on the first layer 21.
  • the second layer 22 constitutes a second major surface 14.
  • the thickness of the first layer 21 is, for example, 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the thickness of the first layer 21 may be 0.7 ⁇ m or more, or may be 1.0 ⁇ m or more.
  • the thickness of the first layer 21 may be 1.8 ⁇ m or less, or 1.5 ⁇ m or less.
  • the thickness of the second layer 22 is, for example, 5 ⁇ m or more and 30 ⁇ m or less.
  • the thickness of the second layer 22 may be 7 ⁇ m or more, or 10 ⁇ m or more.
  • the thickness of the second layer 22 may be 25 ⁇ m or less, or 20 ⁇ m or less.
  • Each of the first layer 21 and the second layer 22 contains an n-type impurity such as nitrogen, for example.
  • the concentration of the n-type impurity contained in the first layer 21 is, for example, not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the concentration of the n-type impurity contained in the first layer 21 may be 3 ⁇ 10 17 cm ⁇ 3 or more, or 5 ⁇ 10 17 cm ⁇ 3 or more.
  • the concentration of the n-type impurity contained in the first layer 21 may be 7 ⁇ 10 18 cm ⁇ 3 or less, or 5 ⁇ 10 18 cm ⁇ 3 or less.
  • the concentration of the n-type impurity contained in the second layer 22 is, for example, not less than 1 ⁇ 10 15 cm ⁇ 3 and not more than 1 ⁇ 10 16 cm ⁇ 3 .
  • the concentration of the n-type impurity contained in the second layer 22 may be 2 ⁇ 10 15 cm ⁇ 3 or more, or 3 ⁇ 10 15 cm ⁇ 3 or more.
  • the concentration of the n-type impurity contained in the second layer 22 may be 9 ⁇ 10 15 cm ⁇ 3 or less, or 8 ⁇ 10 15 cm ⁇ 3 or less.
  • the concentration of n-type impurities contained in the first layer 21 is lower than the concentration of n-type impurities contained in the silicon carbide substrate 10 and higher than the concentration of n-type impurities contained in the second layer 22.
  • the concentration of the n-type impurity is measured, for example, by a mercury probe type CV measurement device.
  • the area of the probe is, for example, 0.005 cm 2 .
  • silicon carbide substrate 10 and silicon carbide epitaxial film 20 have basal plane dislocation 1.
  • the basal plane dislocation 1 is exposed, for example, to both the first major surface 11 and the first major surface 12.
  • the basal plane dislocations 1 extend in a direction parallel to the ⁇ 0001 ⁇ plane.
  • the basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
  • Silicon carbide epitaxial film 20 has, for example, second basal plane dislocations 26, third basal plane dislocations 27, and threading edge dislocations 2.
  • the third basal plane dislocations 27 and the threading edge dislocations 2 are exposed to the second main surface 14.
  • the threading edge dislocation 2 has, for example, a first threading edge dislocation 35 and a second threading edge dislocation 36.
  • the first threading edge dislocations 35 are dislocations formed by converting the first basal plane dislocations 25.
  • the second threading edge dislocations 36 are dislocations formed by converting the second basal plane dislocations 26.
  • the threading edge dislocations 2 extend along a third direction 103 substantially perpendicular to ⁇ 0001 ⁇ .
  • basal plane dislocation 1 When basal plane dislocation 1 is present in silicon carbide epitaxial substrate 100, for example, the reliability of the gate insulating film formed on silicon carbide epitaxial substrate 100 is degraded. On the other hand, the threading edge dislocations 2 hardly affect the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate, even if they are present in the silicon carbide epitaxial substrate. Therefore, it is desirable to convert basal plane dislocations 1 present in silicon carbide substrate 10 into threading edge dislocations 2 and reduce the number of basal plane dislocations 1 in silicon carbide epitaxial film 20.
  • silicon carbide epitaxial substrate 100 on first main surface 12 of silicon carbide substrate 10, there is basal plane dislocation 1 having a first surface density.
  • the second main surface 14 of the silicon carbide epitaxial film 20 has a basal plane dislocation 1 having a second surface density lower than the first surface density.
  • the value obtained by dividing the second area density by the first area density is 1/1000 or less. In other words, the rate (conversion rate) of conversion from basal plane dislocation 1 to threading edge dislocation 2 is 99.9% or more.
  • the value obtained by dividing the second area density by the first area density may be, for example, 1/2000 or less. In other words, the ratio (conversion ratio) of conversion from basal plane dislocation 1 to threading edge dislocation 2 is 99.95% or more.
  • the second area density is, for example, 10 cm ⁇ 2 or less.
  • the second area density may be, for example, 6 cm ⁇ 2 or less, or 2 cm ⁇ 2 or less.
  • the surface density of the basal plane dislocation is low, but the surface density of the threading edge dislocation is high.
  • the surface density of threading edge dislocations on the second main surface 14 of the silicon carbide epitaxial film 20 may be, for example, higher than 3990 cm ⁇ 2 .
  • the lower limit of the first surface density is limited, the first surface density may be for example 2000 cm -2 or more, or may be 2500 cm -2 or more.
  • the first surface density may be for example 6000 cm -2 or less, or may be 5500Cm -2 or less.
  • a method of measuring the surface density of basal plane dislocation For observation of basal plane dislocation, for example, a photoluminescence imaging apparatus (model number: PLIS-100) manufactured by Photon Design Co., Ltd. is used. When excitation light is irradiated to the measurement region of the silicon carbide epitaxial substrate, photoluminescence light is observed from the measurement region.
  • a mercury xenon lamp is used as an excitation light source. Excitation light from a light source passes through a band pass filter of 313 nm and is then irradiated to the measurement area.
  • the photoluminescence light passes through, for example, a low pass filter of 750 nm and then reaches a light receiving element such as a camera. As described above, the photoluminescence image of the measurement area is taken.
  • the measurement temperature is room temperature.
  • the silicon carbide epitaxial substrate is moved in a direction parallel to the main surface (specifically, second main surface 14 or first main surface 12) of the silicon carbide epitaxial substrate, a photoluminescence image of the main surface is photographed. . Thereby, the photoluminescence image in the whole area of the main surface is mapped.
  • the basal plane dislocations are identified in the acquired photoluminescence image, and the total number of the basal plane dislocations is calculated.
  • the surface density of basal plane dislocations is calculated by dividing the total number of basal plane dislocations by the total measurement area.
  • first main surface 12 is a surface inclined at an off angle of 8 ° or less with respect to the (0001) plane or the (0001) plane.
  • the calculation of the surface density of the basal plane dislocation on the first main surface 12 may be performed, for example, by counting the pits generated using a potassium hydroxide (KOH) melt.
  • KOH potassium hydroxide
  • the first major surface 12 is etched using a KOH melt.
  • the temperature of the KOH melt is, for example, about 500 ° C. or more and about 550 ° C. or less.
  • the etching time is, for example, about 5 to 10 minutes. After etching, the first major surface 12 is observed by a normal ski differential interference microscope.
  • the basal plane dislocations are etched by the KOH melt to form pits.
  • the surface density of basal plane dislocations is calculated by dividing the total number of pits by the total measurement area.
  • the threading edge dislocations also form pits in the same manner as the basal plane dislocations.
  • the pits derived from threading edge dislocations and the pits derived from basal plane dislocations are distinguished as follows. Rounded hexagonal pits are derived from threading edge dislocations, and elliptical pits are derived from basal plane dislocations.
  • the manufacturing apparatus 200 for the silicon carbide epitaxial substrate 100 is, for example, a hot wall type horizontal CVD (Chemical Vapor Deposition) apparatus.
  • the manufacturing apparatus 200 mainly includes a reaction chamber 201, a heating element 203, a quartz tube 204, a heat insulating material 205, and an induction heating coil 206.
  • the heat generating body 203 has, for example, a cylindrical shape, and forms a reaction chamber 201 inside.
  • the heating element 203 is made of, for example, graphite.
  • the heat insulating material 205 surrounds the outer periphery of the heating element 203.
  • the heat insulating material 205 is provided inside the quartz tube 204 so as to be in contact with the inner circumferential surface of the quartz tube 204.
  • the induction heating coil 206 is wound, for example, along the outer peripheral surface of the quartz tube 204.
  • the induction heating coil 206 is configured to be able to supply an alternating current by an external power supply (not shown). Thereby, the heating element 203 is induction-heated. As a result, the reaction chamber 201 is heated by the heating element 203.
  • the reaction chamber 201 is a space formed by being surrounded by the heating element 203.
  • silicon carbide substrate 10 is arranged.
  • Reaction chamber 201 is configured to be able to heat silicon carbide substrate 10.
  • a susceptor 210 for holding silicon carbide substrate 10 is provided.
  • the susceptor 210 is configured to be capable of rotating around the rotation shaft 212.
  • the manufacturing apparatus 200 has a gas inlet 207 and a gas outlet 208.
  • the gas exhaust port 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate the flow of gas.
  • the gas is introduced into the reaction chamber 201 through the gas inlet port 207 and exhausted through the gas exhaust port 208.
  • the pressure in the reaction chamber 201 is adjusted by the balance between the gas supply amount and the gas discharge amount.
  • the manufacturing apparatus 200 includes, for example, a gas supply unit (not shown) configured to be able to supply a mixed gas containing silane, ammonia, hydrogen, and propane to the reaction chamber 201.
  • the gas supply unit may have a gas cylinder capable of supplying propane gas, a gas cylinder capable of supplying hydrogen gas, a gas cylinder capable of supplying silane gas, and a gas cylinder capable of supplying ammonia gas. Good.
  • the winding density of the induction heating coil 206 may be changed.
  • the winding density [times / m] is the number of turns of the coil per unit length in the axial direction of the device.
  • the winding density of the induction heating coil 206 on the upstream side may be higher than the winding density of the induction heating coil 206 on the downstream side in order to effectively thermally decompose ammonia on the upstream side.
  • a silicon carbide single crystal substrate preparation step (S11: FIG. 4) is performed.
  • a silicon carbide single crystal of polytype 4H is manufactured by a sublimation method.
  • silicon carbide substrate 10 is prepared by slicing a silicon carbide single crystal with, for example, a wire saw.
  • Silicon carbide substrate 10 contains an n-type impurity such as nitrogen, for example.
  • the conductivity type of silicon carbide substrate 10 is, for example, n-type.
  • silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11.
  • the first major surface 11 is a surface inclined in the off direction by, for example, the off angle ⁇ with respect to the (000-1) plane.
  • the off direction is, for example, the ⁇ 11-20> direction.
  • the maximum diameter of first main surface 11 of silicon carbide substrate 10 is, for example, 100 mm or more.
  • a plurality of basal plane dislocations 1 exist in silicon carbide substrate 10.
  • the basal plane dislocations 1 extend in a direction parallel to the ⁇ 0001 ⁇ plane.
  • the basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
  • silicon carbide substrate 10 is arranged on susceptor 210 in reaction chamber 201 (see FIG. 3). Silicon carbide substrate 10 is arranged in reaction chamber 201 under atmospheric pressure (time T0). Next, the pressure in the reaction chamber 201 is reduced. As shown in FIG. 7, the pressure in the reaction chamber 201 is reduced from atmospheric pressure to about 1 ⁇ 10 ⁇ 4 Pa from time point T1 to time point T2.
  • the temperature raising step is performed. From time T2 to time T3, the temperature of the silicon carbide substrate 10 rises from room temperature to about 1100 ° C. in a state where the pressure in the reaction chamber 201 is about 1 ⁇ 10 -4 Pa. Next, from time T3 to time T4, the temperature of silicon carbide substrate 10 is maintained at 1100 ° C. for a fixed time. The temperature of silicon carbide substrate 10 rises from 1100 ° C. to 1630 ° C. from time point T4 to time point T5. At time point T4, hydrogen (H 2 ) gas is introduced into the reaction chamber 201. The flow rate of hydrogen gas is, for example, 100 slm. The pressure in the reaction chamber 201 is, for example, about 10 kPa. Thus, a hydrogen etching process is performed. While the temperature of silicon carbide substrate 10 is maintained at 1630 ° C. from time T5 to time T6, the surface of silicon carbide substrate 10 is etched by hydrogen gas.
  • H 2 hydrogen
  • a buffer layer formation step (S12: FIG. 4) is performed.
  • the source gas, the dopant gas and the carrier gas are supplied to the reaction chamber 201.
  • a mixed gas containing silane (SiH 4 ), propane (C 3 H 8 ), ammonia (NH 3 ) and hydrogen is supplied to the reaction chamber 201.
  • silicon carbide substrate 10 is maintained at about 1630 ° C. from time point T6 to time point T7.
  • the respective gases are thermally decomposed to form the buffer layer 21 on the silicon carbide substrate 10 (see FIG. 6).
  • the susceptor 210 may rotate around the rotation axis 212.
  • Silicon carbide substrate 10 may revolve around rotation axis 212 (see FIG. 3).
  • the flow rates of silane and propane are adjusted so that the growth rate is, for example, 5 ⁇ m / h.
  • the flow rate of the silane gas is adjusted to, for example, 46 sccm.
  • the flow rate of propane gas is adjusted to, for example, 29 sccm.
  • the flow rate of ammonia gas is adjusted to, for example, 1.5 sccm.
  • the flow rate of hydrogen gas is adjusted to be 100 slm.
  • the thickness of buffer layer 21 is, for example, 1 ⁇ m.
  • the pressure in the reaction chamber 201 is, for example, 10 kPa.
  • the C / Si ratio is, for example, 1.9.
  • a part of the plurality of basal plane dislocations 1 present in silicon carbide substrate 10 are converted into threading edge dislocations.
  • the first basal plane dislocations 25 are converted into first penetrating edge dislocations 35.
  • the second basal plane dislocations 26 and the third basal plane dislocations 27 are not converted into threading edge dislocations, but propagate in the buffer layer 21 as basal plane dislocations.
  • the drift layer forming step (S13: FIG. 4) is performed. Specifically, a mixed gas containing silane, propane, ammonia and hydrogen is supplied to the reaction chamber 201. Between time point T6 and time point T7, silicon carbide substrate 10 is maintained at 1630.degree. In the reaction chamber 201, each gas is thermally decomposed to form the drift layer 22 on the buffer layer 21 (see FIG. 2). In the process of forming the drift layer 22, the susceptor 210 may rotate around the rotation axis 212. Silicon carbide substrate 10 may revolve around rotation axis 212 (see FIG. 3).
  • the flow rates of silane and propane are adjusted such that the growth rate is, for example, 25 ⁇ m / h.
  • the flow rate of the silane gas is adjusted to, for example, 115 sccm.
  • the flow rate of propane gas is adjusted to, for example, 57.6 sccm.
  • the flow rate of ammonia gas is adjusted to, for example, 2.5 ⁇ 10 ⁇ 2 sccm.
  • the flow rate of hydrogen gas is adjusted to be 100 slm.
  • the thickness of drift layer 22 is, for example, 10 ⁇ m.
  • the pressure in the reaction chamber 201 is, for example, 10 kPa.
  • the C / Si ratio is, for example, 1.5.
  • a cooling process is performed. As shown in FIG. 7, the temperature of silicon carbide substrate 10 is reduced from 1630 ° C. to room temperature from time point T8 to time point T9. At time T9, the supply of hydrogen introduced into the reaction chamber 201 is stopped, and the pressure in the reaction chamber 201 returns to atmospheric pressure. As described above, silicon carbide epitaxial substrate 100 is manufactured.
  • the method for manufacturing a silicon carbide semiconductor device mainly includes an epitaxial substrate preparation step (S10: FIG. 8) and a substrate processing step (S20: FIG. 8).
  • silicon carbide epitaxial substrate 100 is prepared by the method for manufacturing a silicon carbide epitaxial substrate described above (see FIG. 2).
  • a substrate processing step (S20: FIG. 8) is performed.
  • a silicon carbide semiconductor device is manufactured by processing a silicon carbide epitaxial substrate.
  • Processing includes, for example, various processes such as ion implantation, heat treatment, etching, oxide film formation, electrode formation, dicing and the like. That is, the substrate processing step may include at least one of ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing.
  • the substrate processing step (S20: FIG. 8) includes, for example, an ion implantation step (S21: FIG. 8), an oxide film forming step (S22: FIG. 8), an electrode forming step (S23: FIG. 8) and a dicing step (S24: FIG. 8). )including.
  • an ion implantation step (S21: FIG. 8) is performed.
  • a p-type impurity such as aluminum (Al) is implanted into second main surface 14 on which a mask (not shown) having an opening is formed.
  • a body region 132 having p-type conductivity is formed.
  • an n-type impurity such as phosphorus (P) is implanted at a predetermined position in body region 132, for example.
  • a source region 133 having n-type conductivity is formed.
  • p-type impurities such as aluminum are implanted into predetermined positions in the source region 133. Thereby, a contact region 134 having p type conductivity is formed (see FIG. 9).
  • Source region 133 is separated from drift region 131 by body region 132.
  • the ion implantation may be performed by heating the silicon carbide epitaxial substrate 100 to approximately 300 ° C. or more and 600 ° C. or less.
  • activation annealing is performed on silicon carbide epitaxial substrate 100.
  • the activation annealing activates the impurities implanted in the silicon carbide epitaxial film 20, and carriers are generated in each region.
  • the atmosphere for activation annealing is, for example, an argon (Ar) atmosphere.
  • the temperature of activation annealing is, for example, about 1800.degree.
  • the activation annealing time is, for example, about 30 minutes.
  • oxide film formation step (S22: FIG. 8) is performed.
  • oxide film 136 is formed on second main surface 14 by heating silicon carbide epitaxial substrate 100 in an atmosphere containing oxygen (see FIG. 10).
  • Oxide film 136 is made of, for example, silicon dioxide or the like.
  • the oxide film 136 functions as a gate insulating film.
  • the temperature of the thermal oxidation treatment is, for example, about 1300.degree.
  • the time of thermal oxidation treatment is, for example, about 30 minutes.
  • heat treatment may be further performed in a nitrogen atmosphere.
  • heat treatment is performed at about 1100 ° C. for about one hour in an atmosphere of nitrogen monoxide.
  • heat treatment is performed in an argon atmosphere.
  • heat treatment is performed in an argon atmosphere at about 1100 ° C. or more and about 1500 ° C. or less for about one hour.
  • gate electrode 141 is formed on oxide film 136.
  • Gate electrode 141 is formed, for example, by a CVD method.
  • Gate electrode 141 is formed of, for example, polysilicon having conductivity.
  • the gate electrode 141 is formed at a position facing the source region 133 and the body region 132.
  • Interlayer insulating film 137 covering the gate electrode 141 is formed.
  • Interlayer insulating film 137 is formed, for example, by the CVD method.
  • Interlayer insulating film 137 is made of, for example, silicon dioxide or the like.
  • Interlayer insulating film 137 is formed to be in contact with gate electrode 141 and oxide film 136.
  • portions of oxide film 136 and interlayer insulating film 137 are removed by etching. Thus, source region 133 and contact region 134 are exposed from oxide film 136.
  • Source electrode 142 is formed on the exposed portion, for example, by sputtering.
  • Source electrode 142 is made of, for example, titanium, aluminum, silicon or the like.
  • source electrode 142 and silicon carbide epitaxial substrate 100 are heated, for example, at a temperature of about 900 ° C. or more and about 1100 ° C. or less. Thereby, source electrode 142 and silicon carbide epitaxial substrate 100 come into ohmic contact with each other.
  • the wiring layer 138 is formed in contact with the source electrode 142.
  • Wiring layer 138 is made of, for example, a material containing aluminum.
  • the drain electrode 143 is formed on the third major surface 13. Drain electrode 143 is made of, for example, an alloy (eg, NiSi or the like) containing nickel and silicon.
  • a dicing step (S24: FIG. 8) is performed.
  • silicon carbide epitaxial substrate 100 is divided into a plurality of semiconductor chips by dicing silicon carbide epitaxial substrate 100 along dicing lines.
  • silicon carbide semiconductor device 300 is manufactured (see FIG. 11).
  • the method of manufacturing the silicon carbide semiconductor device according to the present disclosure has been described above by exemplifying the MOSFET, the method of manufacturing the present disclosure is not limited thereto.
  • the manufacturing method according to the present disclosure is applicable to silicon carbide semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), SBDs (Schottky Barrier Diodes), thyristors, GTOs (Gate Turn Off thyristors), PiN diodes, and the like.
  • the basal plane dislocation 1 When the basal plane dislocation 1 is present in the silicon carbide epitaxial substrate 100, the basal plane dislocation 1 may be expanded to become a stacking fault at the time of energization. In that case, for example, the gate insulating film formed on silicon carbide epitaxial substrate 100 may be damaged, which may cause a decrease in withstand voltage of silicon carbide semiconductor device 300. As a result, the reliability of silicon carbide semiconductor device 300 may be reduced. On the other hand, the threading edge dislocations 2 hardly affect the reliability of the silicon carbide semiconductor device 300 even if they are present in the silicon carbide epitaxial substrate 100.
  • basal plane dislocations 1 into threading edge dislocations 2 to reduce the number of basal plane dislocations 1. It is also difficult to reduce basal plane dislocation 1 on the carbon surface as compared to the silicon surface.
  • the surface density (second surface density) of basal plane dislocation 1 in second main surface 14 can be compared to the surface density of basal plane dislocation 1 in first main surface 12 (first The value divided by 1) is 1/1000 or less.
  • the second main surface 14 is a surface inclined at an off angle of 8 ° or less with respect to the carbon surface or the carbon surface. That is, according to silicon carbide epitaxial substrate 100 according to the present embodiment, the basal plane of second main surface 14 of silicon carbide epitaxial film 20 is obtained by converting most of basal plane dislocations 1 in silicon carbide substrate 10 into threading dislocations. Dislocation 1 can be reduced. Therefore, the reliability of silicon carbide semiconductor device 300 including silicon carbide epitaxial substrate 100 having second main surface 14 inclined at an off angle of 8 ° or less with respect to the carbon surface or the carbon surface can be improved.
  • silicon carbide substrates according to samples 1 and 2 were prepared.
  • the basal plane dislocation (BPD) on the main surface of the silicon carbide substrate according to Samples 1 and 2 was 4000 cm.sup.- 2 .
  • the largest diameter of the main surface of the silicon carbide substrate according to Samples 1 and 2 was 150 mm.
  • a silicon carbide epitaxial film was grown on the silicon carbide substrate according to Samples 1 and 2.
  • a silicon carbide epitaxial film was formed using the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment. That is, for the silicon carbide substrate according to sample 1, a silicon carbide epitaxial film was formed using the temperature profile shown in FIG. Specifically, the growth rate of the buffer layer was 5 ⁇ m / h. The growth rate of the drift layer was 25 ⁇ m / h. The thickness of the buffer layer was 1 ⁇ m. The carrier concentration of the buffer layer was set to 1 ⁇ 10 18 cm ⁇ 3 . The thickness of the drift layer was 10 ⁇ m. The carrier concentration of the drift layer was 7 ⁇ 10 15 cm ⁇ 3 .
  • a silicon carbide epitaxial film was formed using the temperature profile shown in FIG. Specifically, the growth rate of the buffer layer was 5 ⁇ m / h. The growth rate of the drift layer was 10 ⁇ m / h. The thickness of the buffer layer was 1 ⁇ m. The carrier concentration of the buffer layer was set to 1 ⁇ 10 18 cm ⁇ 3 . The thickness of the drift layer was 10 ⁇ m. The carrier concentration of the drift layer was 7 ⁇ 10 15 cm ⁇ 3 .
  • the method of manufacturing a silicon carbide substrate according to sample 2 is different from the method of manufacturing a silicon carbide substrate according to sample 1 in the drift layer forming step, and the other steps are the same as the method of manufacturing a silicon carbide substrate according to sample 1 is there.
  • the flow rate of the silane gas was adjusted to, for example, 69 sccm.
  • the flow rate of propane gas was adjusted to, for example, 43.5 sccm.
  • the flow rate of ammonia gas was adjusted to be, for example, 1.0 ⁇ 10 ⁇ 2 sccm.
  • the C / Si ratio was 1.9.
  • the silicon carbide epitaxial substrates according to Samples 1 and 2 were manufactured.
  • the areal densities of basal plane dislocations on the first main surface 12 and the second main surface 14 of the silicon carbide epitaxial substrate according to Samples 1 and 2 were measured.
  • the areal density of basal plane dislocations was measured using the measurement method described above.
  • Table 1 shows the surface density (first surface density) of the basal plane dislocation (BPD) of the first main surface 12 of the silicon carbide substrate and the plane of the basal surface dislocation (BPD) of the second main surface 14 of the silicon carbide epitaxial film
  • the density (second surface density), the value obtained by dividing the second surface density by the first surface density, and the conversion ratio from basal plane dislocation to threading edge dislocation are shown.
  • the conversion ratio determined as the value obtained by subtracting the second surface density from the first surface density divided by the first surface density is 99.95% and 98, respectively. It was .955%.

Abstract

This silicon carbide epitaxial substrate has a silicon carbide substrate (10) and a silicon carbide epitaxial film (20). The silicon carbide epitaxial film includes a first layer (21) and a second layer (22). The concentration of n-type impurities contained in the first layer is lower than the concentration of n-type impurities contained in the silicon carbide substrate, and is higher than the concentration of n-type impurities contained in the second layer. The silicon carbide substrate has a main surface (12) which has a basal plane dislocation having a first surface density. The silicon carbide epitaxial film has a main surface (14) having a basal plane dislocation having a second surface density lower than the first surface density. The value obtained by dividing the second surface density by the first surface density is 1/1000 or less. The main surface of the silicon carbide epitaxial film is sloped with respect to the (000-1) plane or the (000-1) plane at an off-angle of 8° or less.

Description

炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法Silicon carbide epitaxial substrate and method of manufacturing silicon carbide semiconductor device
 本開示は、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法に関する。本出願は、2017年9月1日に出願した日本特許出願である特願2017-168252号に基づく優先権を主張する。当該日本特許出願に記載された全ての記載内容は、参照によって本明細書に援用される。 The present disclosure relates to a silicon carbide epitaxial substrate and a method of manufacturing a silicon carbide semiconductor device. This application claims priority based on Japanese Patent Application No. 2017-168252, which is a Japanese patent application filed on September 1, 2017. The entire contents of the description of the Japanese patent application are incorporated herein by reference.
 特開2014-170891号公報(特許文献1)には、炭化珪素単結晶基板上に炭化珪素層をエピタキシャル成長させる方法が開示されている。 JP-A-2014-170891 (Patent Document 1) discloses a method of epitaxially growing a silicon carbide layer on a silicon carbide single crystal substrate.
特開2014-170891号公報JP, 2014-170891, A
 本開示に係る炭化珪素エピタキシャル基板は、炭化珪素基板と、炭化珪素エピタキシャル膜とを備えている。炭化珪素エピタキシャル膜は、炭化珪素基板上にある。炭化珪素基板および炭化珪素エピタキシャル膜のポリタイプは、4Hである。炭化珪素エピタキシャル膜は、炭化珪素基板に接する第1層と、第1層上にありかつ炭化珪素エピタキシャル膜の主表面を構成する第2層とを含んでいる。炭化珪素基板と、第1層と、第2層とは、n型不純物を含んでいる。第1層が含むn型不純物の濃度は、炭化珪素基板が含むn型不純物の濃度より低く、かつ第2層が含むn型不純物の濃度より高い。炭化珪素基板の主表面には、第1面密度を有する基底面転位がある。炭化珪素エピタキシャル膜の主表面には、第1面密度よりも低い第2面密度を有する基底面転位がある。第2面密度を、第1面密度で除した値は、1/1000以下である。炭化珪素エピタキシャル膜の主表面は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である。 A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial film. The silicon carbide epitaxial film is on a silicon carbide substrate. The polytype of the silicon carbide substrate and silicon carbide epitaxial film is 4H. The silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film. The silicon carbide substrate, the first layer, and the second layer contain n-type impurities. The concentration of n-type impurities contained in the first layer is lower than the concentration of n-type impurities contained in the silicon carbide substrate and higher than the concentration of n-type impurities contained in the second layer. The main surface of the silicon carbide substrate has basal plane dislocations having a first surface density. The main surface of the silicon carbide epitaxial film has basal plane dislocations having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less. The main surface of the silicon carbide epitaxial film is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
 本開示に係る炭化珪素エピタキシャル基板は、炭化珪素基板と、炭化珪素エピタキシャル膜とを備えている。炭化珪素エピタキシャル膜は、炭化珪素基板上にある。炭化珪素基板および炭化珪素エピタキシャル膜のポリタイプは、4Hである。炭化珪素エピタキシャル膜は、炭化珪素基板に接する第1層と、第1層上にありかつ炭化珪素エピタキシャル膜の主表面を構成する第2層とを含んでいる。炭化珪素基板と、第1層と、第2層とは、n型不純物を含んでいる。第1層が含むn型不純物の濃度は、炭化珪素基板が含むn型不純物の濃度より低く、かつ第2層が含むn型不純物の濃度より高い。炭化珪素基板の主表面には、第1面密度を有する基底面転位がある。炭化珪素エピタキシャル膜の主表面には、第1面密度よりも低い第2面密度を有する基底面転位がある。第2面密度を、第1面密度で除した値は、1/1000以下である。炭化珪素エピタキシャル膜の主表面は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である。炭化珪素エピタキシャル膜の主表面の最大径は、150mm以上である。第1層の厚みは、0.5μm以上2μm以下である。第2層の厚みは、5μm以上30μm以下である。第1層が含むn型不純物の濃度は、1×1017cm-3以上1×1019cm-3以下である。第2層が含むn型不純物の濃度は、1×1015cm-3以上1×1016cm-3以下である。 A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial film. The silicon carbide epitaxial film is on a silicon carbide substrate. The polytype of the silicon carbide substrate and silicon carbide epitaxial film is 4H. The silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film. The silicon carbide substrate, the first layer, and the second layer contain n-type impurities. The concentration of n-type impurities contained in the first layer is lower than the concentration of n-type impurities contained in the silicon carbide substrate and higher than the concentration of n-type impurities contained in the second layer. The main surface of the silicon carbide substrate has basal plane dislocations having a first surface density. The main surface of the silicon carbide epitaxial film has basal plane dislocations having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less. The main surface of the silicon carbide epitaxial film is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane. The maximum diameter of the main surface of the silicon carbide epitaxial film is 150 mm or more. The thickness of the first layer is 0.5 μm or more and 2 μm or less. The thickness of the second layer is 5 μm or more and 30 μm or less. The concentration of the n-type impurity contained in the first layer is 1 × 10 17 cm −3 or more and 1 × 10 19 cm −3 or less. The concentration of the n-type impurity contained in the second layer is 1 × 10 15 cm −3 or more and 1 × 10 16 cm −3 or less.
図1は、本実施形態に係る炭化珪素エピタキシャル基板の構成を示す平面模式図である。FIG. 1 is a schematic plan view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment. 図2は、本実施形態に係る炭化珪素エピタキシャル基板の構成を示す断面模式図である。FIG. 2 is a schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment. 図3は、本実施形態に係る炭化珪素エピタキシャル基板の製造装置の構成を示す一部断面模式図である。FIG. 3 is a partial cross-sectional schematic view showing the configuration of the apparatus for manufacturing a silicon carbide epitaxial substrate according to the present embodiment. 図4は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法を概略的に示すフローチャートである。FIG. 4 is a flow chart schematically showing a method of manufacturing a silicon carbide epitaxial substrate according to the present embodiment. 図5は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法の第1工程を示す断面模式図である。FIG. 5 is a schematic cross sectional view showing a first step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment. 図6は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法の第2工程を示す断面模式図である。FIG. 6 is a schematic cross sectional view showing a second step of the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment. 図7は、本実施形態に係る炭化珪素エピタキシャル基板の製造条件を示す図である。FIG. 7 is a diagram showing the manufacturing conditions of the silicon carbide epitaxial substrate according to the present embodiment. 図8は、本実施形態に係る炭化珪素半導体装置の製造方法を概略的に示すフローチャートである。FIG. 8 is a flow chart schematically showing a method of manufacturing a silicon carbide semiconductor device according to the present embodiment. 図9は、本実施形態に係る炭化珪素半導体装置の製造方法の第1工程を示す断面模式図である。FIG. 9 is a schematic cross sectional view showing a first step of a method of manufacturing a silicon carbide semiconductor device according to the present embodiment. 図10は、本実施形態に係る炭化珪素半導体装置の製造方法の第2工程を示す断面模式図である。FIG. 10 is a schematic cross sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. 図11は、本実施形態に係る炭化珪素半導体装置の構成を示す断面模式図である。FIG. 11 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the present embodiment. 図12は、サンプル2に係る炭化珪素エピタキシャル基板の製造条件を示す図である。FIG. 12 is a diagram showing the manufacturing conditions of the silicon carbide epitaxial substrate according to Sample 2. As shown in FIG.
 [本開示の実施形態の概要]
 まず本開示の実施形態の概要について説明する。本明細書の結晶学的記載においては、個別方位を[]、集合方位を<>、個別面を()、集合面を{}でそれぞれ示す。結晶学上の指数が負であることは、通常、数字の上に”-”(バー)を付すことによって表現されるが、本明細書では数字の前に負の符号を付すことによって結晶学上の負の指数を表現する。
Overview of Embodiments of the Present Disclosure
First, an outline of an embodiment of the present disclosure will be described. In the crystallographic description of the present specification, an individual orientation is indicated by [], a collective orientation is indicated by <>, an individual plane is indicated by (), and a collective plane is indicated by {}. The fact that the crystallographic index is negative is usually expressed by adding a "-" (bar) above the numbers, but in the present specification the crystallography is indicated by putting a negative sign before the numbers. Express the negative index above.
 (1)本開示に係る炭化珪素エピタキシャル基板100は、炭化珪素基板10と、炭化珪素エピタキシャル膜20とを備えている。炭化珪素エピタキシャル膜20は、炭化珪素基板10上にある。炭化珪素基板10および炭化珪素エピタキシャル膜20のポリタイプは、4Hである。炭化珪素エピタキシャル膜20は、炭化珪素基板10に接する第1層21と、第1層21上にありかつ炭化珪素エピタキシャル膜20の主表面14を構成する第2層22とを含んでいる。炭化珪素基板10と、第1層21と、第2層22とは、n型不純物を含んでいる。第1層21が含むn型不純物の濃度は、炭化珪素基板10が含むn型不純物の濃度より低く、かつ第2層22が含むn型不純物の濃度より高い。炭化珪素基板10の主表面12には、第1面密度を有する基底面転位1がある。炭化珪素エピタキシャル膜20の主表面14には、第1面密度よりも低い第2面密度を有する基底面転位1がある。第2面密度を、第1面密度で除した値は、1/1000以下である。炭化珪素エピタキシャル膜20の主表面14は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である。 (1) A silicon carbide epitaxial substrate 100 according to the present disclosure includes a silicon carbide substrate 10 and a silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. The polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10, and a second layer 22 which is on first layer 21 and which constitutes main surface 14 of silicon carbide epitaxial film 20. Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities. The concentration of n-type impurities contained in the first layer 21 is lower than the concentration of n-type impurities contained in the silicon carbide substrate 10 and higher than the concentration of n-type impurities contained in the second layer 22. Main surface 12 of silicon carbide substrate 10 has basal plane dislocation 1 having a first surface density. Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocation 1 having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less. Main surface 14 of silicon carbide epitaxial film 20 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
 (2)上記(1)に係る炭化珪素エピタキシャル基板100において、第2面密度を、第1面密度で除した値は、1/2000以下であってもよい。 (2) In the silicon carbide epitaxial substrate 100 according to the above (1), a value obtained by dividing the second area density by the first area density may be 1/2000 or less.
 (3)上記(1)または(2)に係る炭化珪素エピタキシャル基板100において、炭化珪素エピタキシャル膜20の主表面14の最大径111は、100mm以上であってもよい。 (3) In silicon carbide epitaxial substrate 100 concerning the above (1) or (2), maximum diameter 111 of main surface 14 of silicon carbide epitaxial film 20 may be 100 mm or more.
 (4)上記(3)に係る炭化珪素エピタキシャル基板において、炭化珪素エピタキシャル膜20の主表面14の最大径111は、150mm以上であってもよい。 (4) In the silicon carbide epitaxial substrate according to (3), the maximum diameter 111 of the main surface 14 of the silicon carbide epitaxial film 20 may be 150 mm or more.
 (5)本開示に係る炭化珪素エピタキシャル基板100は、炭化珪素基板10と、炭化珪素エピタキシャル膜20とを備えている。炭化珪素エピタキシャル膜20は、炭化珪素基板10上にある。炭化珪素基板10および炭化珪素エピタキシャル膜20のポリタイプは、4Hである。炭化珪素エピタキシャル膜20は、炭化珪素基板10に接する第1層21と、第1層21上にありかつ炭化珪素エピタキシャル膜20の主表面14を構成する第2層22とを含んでいる。炭化珪素基板10と、第1層21と、第2層22とは、n型不純物を含んでいる。第1層21が含むn型不純物の濃度は、炭化珪素基板10が含むn型不純物の濃度より低く、かつ第2層22が含むn型不純物の濃度より高い。炭化珪素基板10の主表面12には、第1面密度を有する基底面転位1がある。炭化珪素エピタキシャル膜20の主表面14には、第1面密度よりも低い第2面密度を有する基底面転位1がある。第2面密度を、第1面密度で除した値は、1/1000以下である。炭化珪素エピタキシャル膜20の主表面14は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である。炭化珪素エピタキシャル膜20の主表面14は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である。炭化珪素エピタキシャル膜20の主表面14の最大径111は、150mm以上である。第1層21の厚みは、0.5μm以上2μm以下である。第2層22の厚みは、5μm以上30μm以下である。第1層21が含むn型不純物の濃度は、1×1017cm-3以上1×1019cm-3以下である。第2層22が含むn型不純物の濃度は、1×1015cm-3以上1×1016cm-3以下である。 (5) The silicon carbide epitaxial substrate 100 according to the present disclosure includes the silicon carbide substrate 10 and the silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. The polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10, and a second layer 22 which is on first layer 21 and which constitutes main surface 14 of silicon carbide epitaxial film 20. Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities. The concentration of n-type impurities contained in the first layer 21 is lower than the concentration of n-type impurities contained in the silicon carbide substrate 10 and higher than the concentration of n-type impurities contained in the second layer 22. Main surface 12 of silicon carbide substrate 10 has basal plane dislocation 1 having a first surface density. Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocation 1 having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less. Main surface 14 of silicon carbide epitaxial film 20 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane. Main surface 14 of silicon carbide epitaxial film 20 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane. The maximum diameter 111 of the main surface 14 of the silicon carbide epitaxial film 20 is 150 mm or more. The thickness of the first layer 21 is 0.5 μm or more and 2 μm or less. The thickness of the second layer 22 is 5 μm or more and 30 μm or less. The concentration of the n-type impurity contained in the first layer 21 is 1 × 10 17 cm −3 or more and 1 × 10 19 cm −3 or less. The concentration of the n-type impurity contained in the second layer 22 is 1 × 10 15 cm −3 or more and 1 × 10 16 cm −3 or less.
 (6)本開示に係る炭化珪素半導体装置300の製造方法は以下の工程を備えている。上記(1)~(5)のいずれか1項に記載の炭化珪素エピタキシャル基板100が準備される。炭化珪素エピタキシャル基板100が加工される。 (6) The method for manufacturing the silicon carbide semiconductor device 300 according to the present disclosure includes the following steps. The silicon carbide epitaxial substrate 100 according to any one of the above (1) to (5) is prepared. Silicon carbide epitaxial substrate 100 is processed.
 [本開示の実施形態の詳細]
 以下、本開示の実施形態の詳細について説明する。以下の説明では、同一または対応する要素には同一の符号を付し、それらについて同じ説明は繰り返さない。
Details of Embodiments of the Present Disclosure
Hereinafter, details of the embodiment of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description will not be repeated.
 (炭化珪素エピタキシャル基板)
 図1および図2に示されるように、本実施形態に係る炭化珪素エピタキシャル基板100は、炭化珪素基板10と、炭化珪素エピタキシャル膜20とを有している。炭化珪素エピタキシャル膜20は、炭化珪素基板10上にある。炭化珪素基板10は、第1主面11と、第1主面11と反対側の第1主表面12とを有する。炭化珪素エピタキシャル膜20は、第1主面11と接する。炭化珪素エピタキシャル膜20は、第1主面11と接する第3主面13と、第3主面13と反対側の第2主表面14とを有する。炭化珪素基板10および炭化珪素エピタキシャル膜20のポリタイプは、4Hである。図1に示されるように、炭化珪素エピタキシャル基板100には、第1方向101に延在する第1フラット16が設けられて入れてもよい。炭化珪素エピタキシャル基板100には、第2方向102に延在する第2フラット(図示せず)が設けられていてもよい。
(Silicon carbide epitaxial substrate)
As shown in FIGS. 1 and 2, silicon carbide epitaxial substrate 100 according to the present embodiment includes silicon carbide substrate 10 and silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. Silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11. The silicon carbide epitaxial film 20 is in contact with the first major surface 11. Silicon carbide epitaxial film 20 has a third main surface 13 in contact with first main surface 11 and a second main surface 14 opposite to third main surface 13. The polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. As shown in FIG. 1, the silicon carbide epitaxial substrate 100 may be provided with a first flat 16 extending in the first direction 101. Silicon carbide epitaxial substrate 100 may be provided with a second flat (not shown) extending in second direction 102.
 第2方向102は、たとえば<1-100>方向である。第1方向101は、第2主表面14に対して平行であり、かつ第2方向102に対して垂直な方向である。第1方向101は、たとえば<11-20>方向成分を含む方向である。図1に示されるように、第2主表面14の最大径111(直径)は、たとえば100mm以上である。最大径111は150mm以上でもよいし、200mm以上でもよいし、250mm以上でもよい。最大径111の上限は特に限定されない。最大径111は、たとえば300mm以下であってもよい。 The second direction 102 is, for example, a <1-100> direction. The first direction 101 is a direction parallel to the second major surface 14 and perpendicular to the second direction 102. The first direction 101 is, for example, a direction including a <11-20> direction component. As shown in FIG. 1, the maximum diameter 111 (diameter) of the second main surface 14 is, for example, 100 mm or more. The maximum diameter 111 may be 150 mm or more, 200 mm or more, or 250 mm or more. The upper limit of the maximum diameter 111 is not particularly limited. The maximum diameter 111 may be, for example, 300 mm or less.
 炭化珪素基板10は、たとえば炭化珪素単結晶から構成される。炭化珪素基板10は、たとえば窒素(N)などのn型不純物を含んでいる。炭化珪素基板10の導電型は、たとえばn型である。第1主面11は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である。第1主面11が(000-1)面に対して傾斜している場合、第1主面11の傾斜方向は、たとえば<11-20>方向である。炭化珪素基板10の厚みは、たとえば350μm以上500μm以下である。 Silicon carbide substrate 10 is formed of, for example, a silicon carbide single crystal. Silicon carbide substrate 10 contains an n-type impurity such as nitrogen (N), for example. The conductivity type of silicon carbide substrate 10 is, for example, n-type. The first major surface 11 is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane. When the first major surface 11 is tilted with respect to the (000-1) plane, the tilt direction of the first major surface 11 is, for example, the <11-20> direction. The thickness of silicon carbide substrate 10 is, for example, not less than 350 μm and not more than 500 μm.
 図2に示されるように、炭化珪素エピタキシャル膜20は、炭化珪素基板10の第1主面11上にある。炭化珪素エピタキシャル膜20は、エピタキシャル層である。炭化珪素エピタキシャル膜20は、第1主面11に接している。炭化珪素エピタキシャル膜20は、たとえば窒素などのn型不純物を含んでいる。炭化珪素エピタキシャル膜20の導電型は、たとえばn型である。第2主表面14は、カーボン面またはカーボン面に対して8°以下のオフ角θで傾斜した面である。言い換えれば、第2主表面14は、(000-1)面または(000-1)面に対して8°以下のオフ角θで傾斜した面である。オフ方向は、たとえば<11-20>方向である。なお、オフ方向は、<11-20>方向に限定されない。オフ方向は、たとえば<1-100>方向であってもよいし、<1-100>方向成分と<11-20>方向成分とを有する方向であってもよい。 As shown in FIG. 2, silicon carbide epitaxial film 20 is on first main surface 11 of silicon carbide substrate 10. Silicon carbide epitaxial film 20 is an epitaxial layer. Silicon carbide epitaxial film 20 is in contact with first main surface 11. Silicon carbide epitaxial film 20 contains an n-type impurity such as nitrogen, for example. The conductivity type of silicon carbide epitaxial film 20 is, for example, n-type. The second main surface 14 is a surface inclined at an off angle θ of 8 ° or less with respect to the carbon surface or the carbon surface. In other words, the second major surface 14 is a surface inclined at an off angle θ of 8 ° or less with respect to the (000-1) plane or the (000-1) plane. The off direction is, for example, the <11-20> direction. The off direction is not limited to the <11-20> direction. The off direction may be, for example, a <1-100> direction or a direction having a <1-100> direction component and a <11-20> direction component.
 オフ角θは、第2主表面14が(000-1)面に対して傾斜している角度である。オフ角θは、たとえば0°より大きく8°以下である。オフ角θは、1°以上であってもよいし、2°以上であってもよい。オフ角は、7°以下であってもよいし、6°以下であってもよい。 The off angle θ is an angle at which the second major surface 14 is inclined to the (000-1) plane. The off angle θ is, for example, greater than 0 ° and not more than 8 °. The off angle θ may be 1 ° or more, or 2 ° or more. The off angle may be 7 ° or less or 6 ° or less.
 図2において破線で記載された面は、たとえば{0001}面である。第3方向103は、{0001}面に対して垂直な方向である。第3方向103は、たとえば[000-1]方向である。第4方向104は、第3方向103に対して垂直な方向である。第4方向104は、たとえば<11-20>方向である。第4方向104は、たとえばオフ方向である。第2主表面14の法線方向は、第5方向105である。第5方向は、たとえば[000-1]方向に対してオフ方向にオフ角θだけ傾斜した方向である。 The surface described by a broken line in FIG. 2 is, for example, a {0001} surface. The third direction 103 is a direction perpendicular to the {0001} plane. The third direction 103 is, for example, the [000-1] direction. The fourth direction 104 is a direction perpendicular to the third direction 103. The fourth direction 104 is, for example, the <11-20> direction. The fourth direction 104 is, for example, the off direction. The normal direction of the second major surface 14 is the fifth direction 105. The fifth direction is a direction inclined by an off angle θ in the off direction with respect to the [000-1] direction, for example.
 図2に示されるように、炭化珪素エピタキシャル膜20は、第1層21と、第2層22とを含む。第1層は、たとえばバッファ層である。第2層22は、たとえばドリフト層である。第1層21は、第1主面11に接している。第1層21は、炭化珪素基板10と接している。第1層21は、第3主面13を構成する。第2層22は、第1層21上にある。第2層22は、第2主表面14を構成する。第1層21の厚みは、たとえば0.5μm以上2μm以下である。第1層21の厚みは、0.7μm以上であってもよいし、1.0μm以上であってもよい。第1層21の厚みは、1.8μm以下であってもよいし、1.5μm以下であってもよい。第2層22の厚みは、たとえば5μm以上30μm以下である。第2層22の厚みは、7μm以上であってもよいし、10μm以上であってもよい。第2層22の厚みは、25μm以下であってもよいし、20μm以下であってもよい。 As shown in FIG. 2, silicon carbide epitaxial film 20 includes a first layer 21 and a second layer 22. The first layer is, for example, a buffer layer. The second layer 22 is, for example, a drift layer. The first layer 21 is in contact with the first major surface 11. First layer 21 is in contact with silicon carbide substrate 10. The first layer 21 constitutes a third major surface 13. The second layer 22 is on the first layer 21. The second layer 22 constitutes a second major surface 14. The thickness of the first layer 21 is, for example, 0.5 μm or more and 2 μm or less. The thickness of the first layer 21 may be 0.7 μm or more, or may be 1.0 μm or more. The thickness of the first layer 21 may be 1.8 μm or less, or 1.5 μm or less. The thickness of the second layer 22 is, for example, 5 μm or more and 30 μm or less. The thickness of the second layer 22 may be 7 μm or more, or 10 μm or more. The thickness of the second layer 22 may be 25 μm or less, or 20 μm or less.
 第1層21および第2層22の各々は、たとえば窒素などのn型不純物を含んでいる。第1層21が含むn型不純物の濃度は、たとえば1×1017cm-3以上1×1019cm-3以下である。第1層21が含むn型不純物の濃度は、3×1017cm-3以上であってもよいし、5×1017cm-3以上であってもよい。第1層21が含むn型不純物の濃度は、7×1018cm-3以下であってもよいし、5×1018cm-3以下であってもよい。第2層22が含むn型不純物の濃度は、たとえば1×1015cm-3以上1×1016cm-3以下である。第2層22が含むn型不純物の濃度は、2×1015cm-3以上であってもよいし、3×1015cm-3以上であってもよい。第2層22が含むn型不純物の濃度は、9×1015cm-3以下であってもよいし、8×1015cm-3以下であってもよい。 Each of the first layer 21 and the second layer 22 contains an n-type impurity such as nitrogen, for example. The concentration of the n-type impurity contained in the first layer 21 is, for example, not less than 1 × 10 17 cm −3 and not more than 1 × 10 19 cm −3 . The concentration of the n-type impurity contained in the first layer 21 may be 3 × 10 17 cm −3 or more, or 5 × 10 17 cm −3 or more. The concentration of the n-type impurity contained in the first layer 21 may be 7 × 10 18 cm −3 or less, or 5 × 10 18 cm −3 or less. The concentration of the n-type impurity contained in the second layer 22 is, for example, not less than 1 × 10 15 cm −3 and not more than 1 × 10 16 cm −3 . The concentration of the n-type impurity contained in the second layer 22 may be 2 × 10 15 cm −3 or more, or 3 × 10 15 cm −3 or more. The concentration of the n-type impurity contained in the second layer 22 may be 9 × 10 15 cm −3 or less, or 8 × 10 15 cm −3 or less.
 第1層21が含むn型不純物の濃度は、炭化珪素基板10が含むn型不純物の濃度より低く、かつ第2層22が含むn型不純物の濃度より高い。n型不純物の濃度は、たとえば水銀プローブ方式のC-V測定装置により測定される。プローブの面積は、たとえば0.005cm2である。 The concentration of n-type impurities contained in the first layer 21 is lower than the concentration of n-type impurities contained in the silicon carbide substrate 10 and higher than the concentration of n-type impurities contained in the second layer 22. The concentration of the n-type impurity is measured, for example, by a mercury probe type CV measurement device. The area of the probe is, for example, 0.005 cm 2 .
 図2に示されるように、炭化珪素基板10および炭化珪素エピタキシャル膜20は、基底面転位1を有している。基底面転位1は、たとえば第1主面11および第1主表面12の双方に露出している。基底面転位1は、{0001}面と平行な方向に延在している。基底面転位1は、たとえば第1基底面転位25と、第2基底面転位26と、第3基底面転位27とを有する。炭化珪素エピタキシャル膜20は、たとえば第2基底面転位26と、第3基底面転位27と、貫通刃状転位2とを有する。第3基底面転位27と、貫通刃状転位2とは、第2主表面14に露出している。貫通刃状転位2は、たとえば第1貫通刃状転位35と、第2貫通刃状転位36とを有する。第1貫通刃状転位35は、第1基底面転位25が転換して形成された転位である。同様に、第2貫通刃状転位36は、第2基底面転位26が転換して形成された転位である。貫通刃状転位2は、{0001}に対してほぼ垂直な第3方向103に沿って延在している。 As shown in FIG. 2, silicon carbide substrate 10 and silicon carbide epitaxial film 20 have basal plane dislocation 1. The basal plane dislocation 1 is exposed, for example, to both the first major surface 11 and the first major surface 12. The basal plane dislocations 1 extend in a direction parallel to the {0001} plane. The basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27. Silicon carbide epitaxial film 20 has, for example, second basal plane dislocations 26, third basal plane dislocations 27, and threading edge dislocations 2. The third basal plane dislocations 27 and the threading edge dislocations 2 are exposed to the second main surface 14. The threading edge dislocation 2 has, for example, a first threading edge dislocation 35 and a second threading edge dislocation 36. The first threading edge dislocations 35 are dislocations formed by converting the first basal plane dislocations 25. Similarly, the second threading edge dislocations 36 are dislocations formed by converting the second basal plane dislocations 26. The threading edge dislocations 2 extend along a third direction 103 substantially perpendicular to {0001}.
 基底面転位1が炭化珪素エピタキシャル基板100に存在すると、たとえば炭化珪素エピタキシャル基板100上に形成されるゲート絶縁膜の信頼性が劣化する。一方、貫通刃状転位2は、炭化珪素エピタキシャル基板に存在していても、炭化珪素エピタキシャル基板上に形成されるゲート絶縁膜の信頼性にはほとんど影響を与えない。そのため、炭化珪素基板10に存在する基底面転位1を貫通刃状転位2に転換し、炭化珪素エピタキシャル膜20における基底面転位1の数を低減することが望ましい。 When basal plane dislocation 1 is present in silicon carbide epitaxial substrate 100, for example, the reliability of the gate insulating film formed on silicon carbide epitaxial substrate 100 is degraded. On the other hand, the threading edge dislocations 2 hardly affect the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate, even if they are present in the silicon carbide epitaxial substrate. Therefore, it is desirable to convert basal plane dislocations 1 present in silicon carbide substrate 10 into threading edge dislocations 2 and reduce the number of basal plane dislocations 1 in silicon carbide epitaxial film 20.
 本実施形態に係る炭化珪素エピタキシャル基板100において、炭化珪素基板10の第1主表面12には、第1面密度を有する基底面転位1がある。炭化珪素エピタキシャル膜20の第2主表面14には、第1面密度よりも低い第2面密度を有する基底面転位1がある。第2面密度を、第1面密度で除した値は、1/1000以下である。言い換えれば、基底面転位1から貫通刃状転位2に転換した割合(転換率)は、99.9%以上である。第2面密度を、第1面密度で除した値は、たとえば1/2000以下であってもよい。言い換えれば、基底面転位1から貫通刃状転位2に転換した割合(転換率)は、99.95%以上である。 In silicon carbide epitaxial substrate 100 according to the present embodiment, on first main surface 12 of silicon carbide substrate 10, there is basal plane dislocation 1 having a first surface density. The second main surface 14 of the silicon carbide epitaxial film 20 has a basal plane dislocation 1 having a second surface density lower than the first surface density. The value obtained by dividing the second area density by the first area density is 1/1000 or less. In other words, the rate (conversion rate) of conversion from basal plane dislocation 1 to threading edge dislocation 2 is 99.9% or more. The value obtained by dividing the second area density by the first area density may be, for example, 1/2000 or less. In other words, the ratio (conversion ratio) of conversion from basal plane dislocation 1 to threading edge dislocation 2 is 99.95% or more.
 第2面密度は、たとえば10cm-2以下である。第2面密度は、たとえば6cm-2以下であってもよいし、2cm-2以下であってもよい。炭化珪素エピタキシャル膜20においては、基底面転位の面密度は低くなっているが、貫通刃状転位の面密度は高くなっている。炭化珪素エピタキシャル膜20の第2主表面14における貫通刃状転位の面密度は、たとえば3990cm-2より高くてもよい。第1面密度の下限は特に限定されないが、第1面密度はたとえば2000cm-2以上であってもよいし、2500cm-2以上であってもよい。第1面密度の上限は特に限定されないが、第1面密度はたとえば6000cm-2以下であってもよいし、5500cm-2以下であってもよい。 The second area density is, for example, 10 cm −2 or less. The second area density may be, for example, 6 cm −2 or less, or 2 cm −2 or less. In the silicon carbide epitaxial film 20, the surface density of the basal plane dislocation is low, but the surface density of the threading edge dislocation is high. The surface density of threading edge dislocations on the second main surface 14 of the silicon carbide epitaxial film 20 may be, for example, higher than 3990 cm −2 . But the lower limit of the first surface density is limited, the first surface density may be for example 2000 cm -2 or more, or may be 2500 cm -2 or more. Although not limit the first surface density is limited, the first surface density may be for example 6000 cm -2 or less, or may be 5500Cm -2 or less.
 (基底面転位の面密度の測定方法)
 次に、基底面転位の面密度の測定方法について説明する。基底面転位の観察には、たとえば株式会社フォトンデザイン社製のフォトルミネッセンスイメージング装置(型番:PLIS-100)が用いられる。炭化珪素エピタキシャル基板の被測定領域に対して励起光が照射されると、被測定領域からフォトルミネッセンス光が観測される。励起光源としては、たとえば水銀キセノンランプが使用される。光源からの励起光は、313nmのバンドパスフィルターを通過した後、被測定領域に照射される。フォトルミネッセンス光は、たとえば750nmのローパスフィルタを通過した後、カメラ等の受光素子に到達する。以上のように、被測定領域のフォトルミネッセンス画像が撮影される。測定温度は、室温である。
(Method of measuring the surface density of basal plane dislocations)
Next, a method of measuring the surface density of basal plane dislocation will be described. For observation of basal plane dislocation, for example, a photoluminescence imaging apparatus (model number: PLIS-100) manufactured by Photon Design Co., Ltd. is used. When excitation light is irradiated to the measurement region of the silicon carbide epitaxial substrate, photoluminescence light is observed from the measurement region. For example, a mercury xenon lamp is used as an excitation light source. Excitation light from a light source passes through a band pass filter of 313 nm and is then irradiated to the measurement area. The photoluminescence light passes through, for example, a low pass filter of 750 nm and then reaches a light receiving element such as a camera. As described above, the photoluminescence image of the measurement area is taken. The measurement temperature is room temperature.
 たとえば炭化珪素エピタキシャル基板の主面(具体的には、第2主表面14または第1主表面12)と平行な方向に炭化珪素エピタキシャル基板を移動させながら、主面のフォトルミネッセンス画像が撮影される。これにより、主面の全領域におけるフォトルミネッセンス画像がマッピングされる。取得されたフォトルミネッセンス画像において基底面転位が特定され、当該基底面転位の合計数が計算される。基底面転位の合計数を全測定面積で除することにより、基底面転位の面密度が算出される。 For example, while the silicon carbide epitaxial substrate is moved in a direction parallel to the main surface (specifically, second main surface 14 or first main surface 12) of the silicon carbide epitaxial substrate, a photoluminescence image of the main surface is photographed. . Thereby, the photoluminescence image in the whole area of the main surface is mapped. The basal plane dislocations are identified in the acquired photoluminescence image, and the total number of the basal plane dislocations is calculated. The surface density of basal plane dislocations is calculated by dividing the total number of basal plane dislocations by the total measurement area.
 本実施形態に係る炭化珪素エピタキシャル基板100においては、第1主表面12は、(0001)面または(0001)面に対して8°以下のオフ角で傾斜した面である。第1主表面12における基底面転位の面密度の算出は、たとえば水酸化カリウム(KOH)融液を用いて発生させたピットを数えることにより行われてもよい。具体的には、第1主表面12がKOH融液を用いてエッチングされる。KOH融液の温度は、たとえば500℃以上550℃以下程度とする。エッチング時間は、たとえば5以上10分以下程度とする。エッチング後、ノルマルスキー微分干渉顕微鏡によって第1主表面12が観察される。基底面転位はKOH融液によりエッチングされてピットを形成する。ピットの合計数を全測定面積で除することにより、基底面転位の面密度が算出される。なお、貫通刃状転位も基底面転位と同様にピットを形成する。貫通刃状転位に由来するピットと、基底面転位に由来するピットとは、以下のように区別する。丸みを帯びた六角形状のピットが貫通刃状転位に由来するものであり、楕円形状のピットが基底面転位に由来するものである。 In silicon carbide epitaxial substrate 100 according to the present embodiment, first main surface 12 is a surface inclined at an off angle of 8 ° or less with respect to the (0001) plane or the (0001) plane. The calculation of the surface density of the basal plane dislocation on the first main surface 12 may be performed, for example, by counting the pits generated using a potassium hydroxide (KOH) melt. Specifically, the first major surface 12 is etched using a KOH melt. The temperature of the KOH melt is, for example, about 500 ° C. or more and about 550 ° C. or less. The etching time is, for example, about 5 to 10 minutes. After etching, the first major surface 12 is observed by a normal ski differential interference microscope. The basal plane dislocations are etched by the KOH melt to form pits. The surface density of basal plane dislocations is calculated by dividing the total number of pits by the total measurement area. The threading edge dislocations also form pits in the same manner as the basal plane dislocations. The pits derived from threading edge dislocations and the pits derived from basal plane dislocations are distinguished as follows. Rounded hexagonal pits are derived from threading edge dislocations, and elliptical pits are derived from basal plane dislocations.
 (炭化珪素エピタキシャル基板の製造装置)
 次に、本実施形態に係る炭化珪素エピタキシャル基板100の製造装置200の構成について説明する。
(Production apparatus for silicon carbide epitaxial substrate)
Next, the structure of the manufacturing apparatus 200 of the silicon carbide epitaxial substrate 100 which concerns on this embodiment is demonstrated.
 図3に示されるように、炭化珪素エピタキシャル基板100の製造装置200は、たとえばホットウォール方式の横型CVD(Chemical Vapor Deposition)装置である。製造装置200は、反応室201と、発熱体203、石英管204、断熱材205、誘導加熱コイル206とを主に有している。 As shown in FIG. 3, the manufacturing apparatus 200 for the silicon carbide epitaxial substrate 100 is, for example, a hot wall type horizontal CVD (Chemical Vapor Deposition) apparatus. The manufacturing apparatus 200 mainly includes a reaction chamber 201, a heating element 203, a quartz tube 204, a heat insulating material 205, and an induction heating coil 206.
 発熱体203は、たとえば筒状の形状を有しており、内部に反応室201を形成している。発熱体203は、たとえば黒鉛製である。断熱材205は、発熱体203の外周を取り囲んでいる。断熱材205は、石英管204の内周面に接するように石英管204の内部に設けられている。誘導加熱コイル206は、たとえば石英管204の外周面に沿って巻回されている。誘導加熱コイル206は、外部電源(図示せず)により、交流電流が供給可能に構成されている。これにより、発熱体203が誘導加熱される。結果として、反応室201が発熱体203により加熱される。 The heat generating body 203 has, for example, a cylindrical shape, and forms a reaction chamber 201 inside. The heating element 203 is made of, for example, graphite. The heat insulating material 205 surrounds the outer periphery of the heating element 203. The heat insulating material 205 is provided inside the quartz tube 204 so as to be in contact with the inner circumferential surface of the quartz tube 204. The induction heating coil 206 is wound, for example, along the outer peripheral surface of the quartz tube 204. The induction heating coil 206 is configured to be able to supply an alternating current by an external power supply (not shown). Thereby, the heating element 203 is induction-heated. As a result, the reaction chamber 201 is heated by the heating element 203.
 反応室201は、発熱体203に取り囲まれて形成された空間である。反応室201内には、炭化珪素基板10が配置される。反応室201は、炭化珪素基板10を加熱可能に構成されている。反応室201には、炭化珪素基板10を保持するサセプタ210が設けられている。サセプタ210は、回転軸212の周りを自転可能に構成されている。 The reaction chamber 201 is a space formed by being surrounded by the heating element 203. In reaction chamber 201, silicon carbide substrate 10 is arranged. Reaction chamber 201 is configured to be able to heat silicon carbide substrate 10. In reaction chamber 201, a susceptor 210 for holding silicon carbide substrate 10 is provided. The susceptor 210 is configured to be capable of rotating around the rotation shaft 212.
 製造装置200は、ガス導入口207およびガス排気口208を有している。ガス排気口208は、排気ポンプ(図示せず)に接続されている。図6中の矢印は、ガスの流れを示している。ガスは、ガス導入口207から反応室201に導入され、ガス排気口208から排気される。反応室201内の圧力は、ガスの供給量と、ガスの排気量とのバランスによって調整される。 The manufacturing apparatus 200 has a gas inlet 207 and a gas outlet 208. The gas exhaust port 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate the flow of gas. The gas is introduced into the reaction chamber 201 through the gas inlet port 207 and exhausted through the gas exhaust port 208. The pressure in the reaction chamber 201 is adjusted by the balance between the gas supply amount and the gas discharge amount.
 製造装置200は、たとえば、シランと、アンモニアと、水素と、プロパンとを含む混合ガスを、反応室201に供給可能に構成されたガス供給部(図示せず)を有している。具体的には、ガス供給部は、プロパンガスを供給可能なガスボンベと、水素ガスを供給可能なガスボンベと、シランガスを供給可能なガスボンベと、アンモニアガスを供給可能なガスボンベとを有していてもよい。 The manufacturing apparatus 200 includes, for example, a gas supply unit (not shown) configured to be able to supply a mixed gas containing silane, ammonia, hydrogen, and propane to the reaction chamber 201. Specifically, the gas supply unit may have a gas cylinder capable of supplying propane gas, a gas cylinder capable of supplying hydrogen gas, a gas cylinder capable of supplying silane gas, and a gas cylinder capable of supplying ammonia gas. Good.
 反応室201の軸方向において、誘導加熱コイル206の巻き密度を変化させてもよい。巻き密度[回/m]とは、装置の軸方向の単位長さあたりのコイルの周回数である。たとえば、上流側でアンモニアを効果的に熱分解させるために、上流側の誘導加熱コイル206の巻き密度は、下流側の誘導加熱コイル206の巻き密度よりも高くてもよい。 In the axial direction of the reaction chamber 201, the winding density of the induction heating coil 206 may be changed. The winding density [times / m] is the number of turns of the coil per unit length in the axial direction of the device. For example, the winding density of the induction heating coil 206 on the upstream side may be higher than the winding density of the induction heating coil 206 on the downstream side in order to effectively thermally decompose ammonia on the upstream side.
 (炭化珪素エピタキシャル基板の製造方法)
 次に、本実施形態に係る炭化珪素エピタキシャル基板の製造方法について説明する。
(Method of manufacturing silicon carbide epitaxial substrate)
Next, a method of manufacturing the silicon carbide epitaxial substrate according to the present embodiment will be described.
 まず、炭化珪素単結晶基板準備工程(S11:図4)が実施される。たとえば昇華法により、ポリタイプ4Hの炭化珪素単結晶が製造される。次に、たとえばワイヤーソーによって、炭化珪素単結晶をスライスすることにより、炭化珪素基板10が準備される。炭化珪素基板10は、たとえば窒素などのn型不純物を含んでいる。炭化珪素基板10の導電型は、たとえばn型である。 First, a silicon carbide single crystal substrate preparation step (S11: FIG. 4) is performed. For example, a silicon carbide single crystal of polytype 4H is manufactured by a sublimation method. Next, silicon carbide substrate 10 is prepared by slicing a silicon carbide single crystal with, for example, a wire saw. Silicon carbide substrate 10 contains an n-type impurity such as nitrogen, for example. The conductivity type of silicon carbide substrate 10 is, for example, n-type.
 図5に示されるように、炭化珪素基板10は、第1主面11と、第1主面11の反対側にある第1主表面12とを有する。第1主面11は、たとえば(000-1)面に対してオフ角θだけオフ方向に傾斜した面である。オフ方向は、たとえば<11-20>方向である。炭化珪素基板10の第1主面11の最大径は、たとえば100mm以上である。炭化珪素基板10には、たとえば複数の基底面転位1が存在する。基底面転位1は、{0001}面と平行な方向に延在している。基底面転位1は、たとえば第1基底面転位25と、第2基底面転位26と、第3基底面転位27とを有する。 As shown in FIG. 5, silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11. The first major surface 11 is a surface inclined in the off direction by, for example, the off angle θ with respect to the (000-1) plane. The off direction is, for example, the <11-20> direction. The maximum diameter of first main surface 11 of silicon carbide substrate 10 is, for example, 100 mm or more. For example, a plurality of basal plane dislocations 1 exist in silicon carbide substrate 10. The basal plane dislocations 1 extend in a direction parallel to the {0001} plane. The basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
 次に、炭化珪素基板10が反応室201内においてサセプタ210上に配置される(図3参照)。炭化珪素基板10は、大気圧の状態で反応室201内に配置される(時点T0)。次に、反応室201内が減圧される。図7に示されるように、時点T1から時点T2にかけて、反応室201内の圧力が大気圧から1×10-4Pa程度に低減される。 Next, silicon carbide substrate 10 is arranged on susceptor 210 in reaction chamber 201 (see FIG. 3). Silicon carbide substrate 10 is arranged in reaction chamber 201 under atmospheric pressure (time T0). Next, the pressure in the reaction chamber 201 is reduced. As shown in FIG. 7, the pressure in the reaction chamber 201 is reduced from atmospheric pressure to about 1 × 10 −4 Pa from time point T1 to time point T2.
 次に、昇温工程が実施される。時点T2から時点T3にかけて、反応室201内の圧力が1×10-4Pa程度の状態で、炭化珪素基板10の温度が室温から1100℃程度まで上昇する。次に、時点T3から時点T4にかけて、炭化珪素基板10の温度が1100℃で一定時間維持される。時点T4から時点T5にかけて、炭化珪素基板10の温度が1100℃から1630℃まで上昇する。時点T4において、反応室201内に水素(H)ガスが導入される。水素ガスの流量は、たとえば100slmである。反応室201内の圧力は、たとえば10kPa程度である。これにより、水素エッチング工程が実施される。時点T5から時点T6にかけて、炭化珪素基板10の温度が1630℃に維持された状態で、炭化珪素基板10の表面が水素ガスによってエッチングされる。 Next, the temperature raising step is performed. From time T2 to time T3, the temperature of the silicon carbide substrate 10 rises from room temperature to about 1100 ° C. in a state where the pressure in the reaction chamber 201 is about 1 × 10 -4 Pa. Next, from time T3 to time T4, the temperature of silicon carbide substrate 10 is maintained at 1100 ° C. for a fixed time. The temperature of silicon carbide substrate 10 rises from 1100 ° C. to 1630 ° C. from time point T4 to time point T5. At time point T4, hydrogen (H 2 ) gas is introduced into the reaction chamber 201. The flow rate of hydrogen gas is, for example, 100 slm. The pressure in the reaction chamber 201 is, for example, about 10 kPa. Thus, a hydrogen etching process is performed. While the temperature of silicon carbide substrate 10 is maintained at 1630 ° C. from time T5 to time T6, the surface of silicon carbide substrate 10 is etched by hydrogen gas.
 次に、バッファ層形成工程(S12:図4)が実施される。具体的には、反応室201に、原料ガス、ドーパントガスおよびキャリアガスが供給される。たとえば、反応室201に、シラン(SiH)とプロパン(C)とアンモニア(NH)と水素とを含む混合ガスが供給される。図7に示されるように、時点T6から時点T7までの間、炭化珪素基板10は1630℃程度で維持される。反応室201において、それぞれのガスが熱分解されることで、炭化珪素基板10上にバッファ層21が形成される(図6参照)。バッファ層21を形成する工程において、サセプタ210は回転軸212の周りを自転していてもよい。炭化珪素基板10は回転軸212の周りを公転していてもよい(図3参照)。 Next, a buffer layer formation step (S12: FIG. 4) is performed. Specifically, the source gas, the dopant gas and the carrier gas are supplied to the reaction chamber 201. For example, a mixed gas containing silane (SiH 4 ), propane (C 3 H 8 ), ammonia (NH 3 ) and hydrogen is supplied to the reaction chamber 201. As shown in FIG. 7, silicon carbide substrate 10 is maintained at about 1630 ° C. from time point T6 to time point T7. In the reaction chamber 201, the respective gases are thermally decomposed to form the buffer layer 21 on the silicon carbide substrate 10 (see FIG. 6). In the process of forming the buffer layer 21, the susceptor 210 may rotate around the rotation axis 212. Silicon carbide substrate 10 may revolve around rotation axis 212 (see FIG. 3).
 バッファ層を形成する工程においては、成長速度がたとえば5μm/hとなるように、シランおよびプロパンの流量が調整される。具体的には、シランガスの流量がたとえば46sccmとなるように調整される。プロパンガスの流量がたとえば29sccmとなるように調整される。アンモニアガスの流量がたとえば1.5sccmとなるように調整される。水素ガスの流量が100slmとなるように調整される。バッファ層21の厚みは、たとえば1μmである。反応室201の圧力は、たとえば10kPaである。C/Si比は、たとえば1.9である。 In the step of forming the buffer layer, the flow rates of silane and propane are adjusted so that the growth rate is, for example, 5 μm / h. Specifically, the flow rate of the silane gas is adjusted to, for example, 46 sccm. The flow rate of propane gas is adjusted to, for example, 29 sccm. The flow rate of ammonia gas is adjusted to, for example, 1.5 sccm. The flow rate of hydrogen gas is adjusted to be 100 slm. The thickness of buffer layer 21 is, for example, 1 μm. The pressure in the reaction chamber 201 is, for example, 10 kPa. The C / Si ratio is, for example, 1.9.
 図6に示されるように、炭化珪素基板10に存在していた複数の基底面転位1の一部が貫通刃状転位に転換される。たとえば、第1基底面転位25は、第1貫通刃状転位35に転換される。たとえば、第2基底面転位26および第3基底面転位27は、貫通刃状転位に転換されず、基底面転位としてバッファ層21内を伝搬する。 As shown in FIG. 6, a part of the plurality of basal plane dislocations 1 present in silicon carbide substrate 10 are converted into threading edge dislocations. For example, the first basal plane dislocations 25 are converted into first penetrating edge dislocations 35. For example, the second basal plane dislocations 26 and the third basal plane dislocations 27 are not converted into threading edge dislocations, but propagate in the buffer layer 21 as basal plane dislocations.
 次に、ドリフト層形成工程(S13:図4)が実施される。具体的には、反応室201に、シランとプロパンとアンモニアと水素とを含む混合ガスが供給される。時点T6から時点T7までの間、炭化珪素基板10は1630℃で維持される。反応室201において、それぞれのガスが熱分解され、バッファ層21上にドリフト層22が形成される(図2参照)。ドリフト層22を形成する工程において、サセプタ210は回転軸212の周りを自転していてもよい。炭化珪素基板10は回転軸212の周りを公転していてもよい(図3参照)。 Next, the drift layer forming step (S13: FIG. 4) is performed. Specifically, a mixed gas containing silane, propane, ammonia and hydrogen is supplied to the reaction chamber 201. Between time point T6 and time point T7, silicon carbide substrate 10 is maintained at 1630.degree. In the reaction chamber 201, each gas is thermally decomposed to form the drift layer 22 on the buffer layer 21 (see FIG. 2). In the process of forming the drift layer 22, the susceptor 210 may rotate around the rotation axis 212. Silicon carbide substrate 10 may revolve around rotation axis 212 (see FIG. 3).
 ドリフト層を形成する工程においては、成長速度がたとえば25μm/hとなるように、シランおよびプロパンの流量が調整される。具体的には、シランガスの流量がたとえば115sccmとなるように調整される。プロパンガスの流量がたとえば57.6sccmとなるように調整される。アンモニアガスの流量がたとえば2.5×10-2sccmとなるように調整される。水素ガスの流量が100slmとなるように調整される。ドリフト層22の厚みは、たとえば10μmである。反応室201の圧力は、たとえば10kPaである。C/Si比は、たとえば1.5である。以上のように、炭化珪素エピタキシャル膜のドリフト層22の成長速度を25μm/h程度に高くすることにより、基底面転位が貫通刃状転位に転換する割合(転換率)を向上することができる。 In the step of forming the drift layer, the flow rates of silane and propane are adjusted such that the growth rate is, for example, 25 μm / h. Specifically, the flow rate of the silane gas is adjusted to, for example, 115 sccm. The flow rate of propane gas is adjusted to, for example, 57.6 sccm. The flow rate of ammonia gas is adjusted to, for example, 2.5 × 10 −2 sccm. The flow rate of hydrogen gas is adjusted to be 100 slm. The thickness of drift layer 22 is, for example, 10 μm. The pressure in the reaction chamber 201 is, for example, 10 kPa. The C / Si ratio is, for example, 1.5. As described above, by increasing the growth rate of the drift layer 22 of the silicon carbide epitaxial film to about 25 μm / h, the rate (conversion rate) of conversion of basal plane dislocations into threading edge dislocations can be improved.
 次に、冷却工程が行われる。図7に示されるように、時点T8から時点T9にかけて、炭化珪素基板10の温度が1630℃から室温まで低減される。時点T9において、反応室201に導入される水素の供給が停止され、反応室201の圧力は大気圧に戻る。以上のように、炭化珪素エピタキシャル基板100が製造される。 Next, a cooling process is performed. As shown in FIG. 7, the temperature of silicon carbide substrate 10 is reduced from 1630 ° C. to room temperature from time point T8 to time point T9. At time T9, the supply of hydrogen introduced into the reaction chamber 201 is stopped, and the pressure in the reaction chamber 201 returns to atmospheric pressure. As described above, silicon carbide epitaxial substrate 100 is manufactured.
 (炭化珪素半導体装置の製造方法)
 次に、本実施形態に係る炭化珪素半導体装置300の製造方法について説明する。
(Method of manufacturing silicon carbide semiconductor device)
Next, a method of manufacturing the silicon carbide semiconductor device 300 according to the present embodiment will be described.
 本実施形態に係る炭化珪素半導体装置の製造方法は、エピタキシャル基板準備工程(S10:図8)と、基板加工工程(S20:図8)とを主に有する。 The method for manufacturing a silicon carbide semiconductor device according to the present embodiment mainly includes an epitaxial substrate preparation step (S10: FIG. 8) and a substrate processing step (S20: FIG. 8).
 まず、エピタキシャル基板準備工程(S10:図8)が実施される。具体的には、前述した炭化珪素エピタキシャル基板の製造方法によって、炭化珪素エピタキシャル基板100が準備される(図2参照)。 First, an epitaxial substrate preparation step (S10: FIG. 8) is performed. Specifically, silicon carbide epitaxial substrate 100 is prepared by the method for manufacturing a silicon carbide epitaxial substrate described above (see FIG. 2).
 次に、基板加工工程(S20:図8)が実施される。具体的には、炭化珪素エピタキシャル基板を加工することにより、炭化珪素半導体装置が製造される。「加工」には、たとえば、イオン注入、熱処理、エッチング、酸化膜形成、電極形成、ダイシング等の各種加工が含まれる。すなわち基板加工ステップは、イオン注入、熱処理、エッチング、酸化膜形成、電極形成およびダイシングのうち、少なくともいずれかの加工を含むものであってもよい。 Next, a substrate processing step (S20: FIG. 8) is performed. Specifically, a silicon carbide semiconductor device is manufactured by processing a silicon carbide epitaxial substrate. "Processing" includes, for example, various processes such as ion implantation, heat treatment, etching, oxide film formation, electrode formation, dicing and the like. That is, the substrate processing step may include at least one of ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing.
 以下では、炭化珪素半導体装置の一例としてのMOSFETの製造方法を説明する。基板加工工程(S20:図8)は、たとえばイオン注入工程(S21:図8)、酸化膜形成工程(S22:図8)、電極形成工程(S23:図8)およびダイシング工程(S24:図8)を含む。 Below, the manufacturing method of MOSFET as an example of a silicon carbide semiconductor device is explained. The substrate processing step (S20: FIG. 8) includes, for example, an ion implantation step (S21: FIG. 8), an oxide film forming step (S22: FIG. 8), an electrode forming step (S23: FIG. 8) and a dicing step (S24: FIG. 8). )including.
 まず、イオン注入工程(S21:図8)が実施される。開口部を有するマスク(図示せず)が形成された第2主表面14に対して、たとえばアルミニウム(Al)等のp型不純物が注入される。これにより、p型の導電型を有するボディ領域132が形成される。次に、ボディ領域132内の所定位置に、たとえばリン(P)等のn型不純物が注入される。これにより、n型の導電型を有するソース領域133が形成される。次に、アルミニウム等のp型不純物がソース領域133内の所定位置に注入される。これにより、p型の導電型を有するコンタクト領域134が形成される(図9参照)。 First, an ion implantation step (S21: FIG. 8) is performed. A p-type impurity such as aluminum (Al) is implanted into second main surface 14 on which a mask (not shown) having an opening is formed. Thus, a body region 132 having p-type conductivity is formed. Next, an n-type impurity such as phosphorus (P) is implanted at a predetermined position in body region 132, for example. Thus, a source region 133 having n-type conductivity is formed. Next, p-type impurities such as aluminum are implanted into predetermined positions in the source region 133. Thereby, a contact region 134 having p type conductivity is formed (see FIG. 9).
 炭化珪素エピタキシャル膜20の第2層22において、ボディ領域132、ソース領域133およびコンタクト領域134以外の部分は、ドリフト領域131となる。ソース領域133は、ボディ領域132によってドリフト領域131から隔てられている。イオン注入は、炭化珪素エピタキシャル基板100を300℃以上600℃以下程度に加熱して行われてもよい。イオン注入の後、炭化珪素エピタキシャル基板100に対して活性化アニールが行われる。活性化アニールにより、炭化珪素エピタキシャル膜20に注入された不純物が活性化し、各領域においてキャリアが生成される。活性化アニールの雰囲気は、たとえばアルゴン(Ar)雰囲気である。活性化アニールの温度は、たとえば1800℃程度である。活性化アニールの時間は、たとえば30分程度である。 In the second layer 22 of the silicon carbide epitaxial film 20, portions other than the body region 132, the source region 133, and the contact region 134 become the drift region 131. Source region 133 is separated from drift region 131 by body region 132. The ion implantation may be performed by heating the silicon carbide epitaxial substrate 100 to approximately 300 ° C. or more and 600 ° C. or less. After ion implantation, activation annealing is performed on silicon carbide epitaxial substrate 100. The activation annealing activates the impurities implanted in the silicon carbide epitaxial film 20, and carriers are generated in each region. The atmosphere for activation annealing is, for example, an argon (Ar) atmosphere. The temperature of activation annealing is, for example, about 1800.degree. The activation annealing time is, for example, about 30 minutes.
 次に、酸化膜形成工程(S22:図8)が実施される。たとえば炭化珪素エピタキシャル基板100が酸素を含む雰囲気中において加熱されることにより、第2主表面14上に酸化膜136が形成される(図10参照)。酸化膜136は、たとえば二酸化珪素等から構成される。酸化膜136は、ゲート絶縁膜として機能する。熱酸化処理の温度は、たとえば1300℃程度である。熱酸化処理の時間は、たとえば30分程度である。 Next, an oxide film formation step (S22: FIG. 8) is performed. For example, oxide film 136 is formed on second main surface 14 by heating silicon carbide epitaxial substrate 100 in an atmosphere containing oxygen (see FIG. 10). Oxide film 136 is made of, for example, silicon dioxide or the like. The oxide film 136 functions as a gate insulating film. The temperature of the thermal oxidation treatment is, for example, about 1300.degree. The time of thermal oxidation treatment is, for example, about 30 minutes.
 酸化膜136が形成された後、さらに窒素雰囲気中で熱処理が行なわれてもよい。たとえば、一酸化窒素の雰囲気中、1100℃程度で1時間程度、熱処理が実施される。さらにその後、アルゴン雰囲気中で熱処理が行なわれる。たとえば、アルゴン雰囲気中、1100℃以上1500℃以下程度で、1時間程度、熱処理が行われる。 After the oxide film 136 is formed, heat treatment may be further performed in a nitrogen atmosphere. For example, heat treatment is performed at about 1100 ° C. for about one hour in an atmosphere of nitrogen monoxide. Thereafter, heat treatment is performed in an argon atmosphere. For example, heat treatment is performed in an argon atmosphere at about 1100 ° C. or more and about 1500 ° C. or less for about one hour.
 次に、電極形成工程(S23:図8)が実施される。具体的には、ゲート電極141は、酸化膜136上に形成される。ゲート電極141は、たとえばCVD法により形成される。ゲート電極141は、たとえば導電性を有するポリシリコン等から構成される。ゲート電極141は、ソース領域133およびボディ領域132に対面する位置に形成される。 Next, an electrode formation step (S23: FIG. 8) is performed. Specifically, gate electrode 141 is formed on oxide film 136. Gate electrode 141 is formed, for example, by a CVD method. Gate electrode 141 is formed of, for example, polysilicon having conductivity. The gate electrode 141 is formed at a position facing the source region 133 and the body region 132.
 次に、ゲート電極141を覆う層間絶縁膜137が形成される。層間絶縁膜137は、たとえばCVD法により形成される。層間絶縁膜137は、たとえば二酸化珪素等から構成される。層間絶縁膜137は、ゲート電極141と酸化膜136とに接するように形成される。次に、酸化膜136および層間絶縁膜137の一部がエッチングによって除去される。これにより、ソース領域133およびコンタクト領域134が、酸化膜136から露出する。 Next, an interlayer insulating film 137 covering the gate electrode 141 is formed. Interlayer insulating film 137 is formed, for example, by the CVD method. Interlayer insulating film 137 is made of, for example, silicon dioxide or the like. Interlayer insulating film 137 is formed to be in contact with gate electrode 141 and oxide film 136. Next, portions of oxide film 136 and interlayer insulating film 137 are removed by etching. Thus, source region 133 and contact region 134 are exposed from oxide film 136.
 次に、たとえばスパッタリング法により当該露出部にソース電極142が形成される。ソース電極142は、たとえばチタン、アルミニウムおよびシリコン等から構成される。ソース電極142が形成された後、ソース電極142と炭化珪素エピタキシャル基板100が、たとえば900℃以上1100℃以下程度の温度で加熱される。これにより、ソース電極142と炭化珪素エピタキシャル基板100とがオーミック接触するようになる。次に、ソース電極142に接するように、配線層138が形成される。配線層138は、たとえばアルミニウムを含む材料から構成される。次に、第3主面13にドレイン電極143が形成される。ドレイン電極143は、たとえばニッケルおよびシリコンを含む合金(たとえばNiSi等)から構成される。 Next, the source electrode 142 is formed on the exposed portion, for example, by sputtering. Source electrode 142 is made of, for example, titanium, aluminum, silicon or the like. After source electrode 142 is formed, source electrode 142 and silicon carbide epitaxial substrate 100 are heated, for example, at a temperature of about 900 ° C. or more and about 1100 ° C. or less. Thereby, source electrode 142 and silicon carbide epitaxial substrate 100 come into ohmic contact with each other. Next, the wiring layer 138 is formed in contact with the source electrode 142. Wiring layer 138 is made of, for example, a material containing aluminum. Next, the drain electrode 143 is formed on the third major surface 13. Drain electrode 143 is made of, for example, an alloy (eg, NiSi or the like) containing nickel and silicon.
 次に、ダイシング工程(S24:図8)が実施される。たとえば炭化珪素エピタキシャル基板100がダイシングラインに沿ってダイシングされることにより、炭化珪素エピタキシャル基板100が複数の半導体チップに分割される。以上より、炭化珪素半導体装置300が製造される(図11参照)。 Next, a dicing step (S24: FIG. 8) is performed. For example, silicon carbide epitaxial substrate 100 is divided into a plurality of semiconductor chips by dicing silicon carbide epitaxial substrate 100 along dicing lines. Thus, silicon carbide semiconductor device 300 is manufactured (see FIG. 11).
 なお上記において、MOSFETを例示して、本開示に係る炭化珪素半導体装置の製造方法を説明したが、本開示に係る製造方法はこれに限定されない。本開示に係る製造方法は、たとえばIGBT(Insulated Gate Bipolar Transistor)、SBD(Schottky Barrier Diode)、サイリスタ、GTO(Gate Turn Off thyristor)、PiNダイオード等の炭化珪素半導体装置に適用可能である。 Although the method of manufacturing the silicon carbide semiconductor device according to the present disclosure has been described above by exemplifying the MOSFET, the method of manufacturing the present disclosure is not limited thereto. The manufacturing method according to the present disclosure is applicable to silicon carbide semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), SBDs (Schottky Barrier Diodes), thyristors, GTOs (Gate Turn Off thyristors), PiN diodes, and the like.
 次に、本実施形態に係る炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法の作用効果について説明する。 Next, functions and effects of the silicon carbide epitaxial substrate and the method for manufacturing a silicon carbide semiconductor device according to the present embodiment will be described.
 基底面転位1が炭化珪素エピタキシャル基板100に存在すると、通電時に基底面転位1が拡張して積層欠陥になる場合がある。その場合、たとえば炭化珪素エピタキシャル基板100上に形成されるゲート絶縁膜がダメージを受け、炭化珪素半導体装置300の耐圧の低下を引き起こすおそれがある。結果として、炭化珪素半導体装置300の信頼性が低下する場合がある。一方、貫通刃状転位2は、炭化珪素エピタキシャル基板100に存在していても、炭化珪素半導体装置300の信頼性にはほとんど影響を与えない。そのため、炭化珪素半導体装置300の信頼性を高めるためには、基底面転位1を貫通刃状転位2に転換して、基底面転位1の数を低減することが望ましい。またシリコン面と比較して、カーボン面上の基底面転位1を低減することは困難であった。 When the basal plane dislocation 1 is present in the silicon carbide epitaxial substrate 100, the basal plane dislocation 1 may be expanded to become a stacking fault at the time of energization. In that case, for example, the gate insulating film formed on silicon carbide epitaxial substrate 100 may be damaged, which may cause a decrease in withstand voltage of silicon carbide semiconductor device 300. As a result, the reliability of silicon carbide semiconductor device 300 may be reduced. On the other hand, the threading edge dislocations 2 hardly affect the reliability of the silicon carbide semiconductor device 300 even if they are present in the silicon carbide epitaxial substrate 100. Therefore, in order to enhance the reliability of silicon carbide semiconductor device 300, it is desirable to convert basal plane dislocations 1 into threading edge dislocations 2 to reduce the number of basal plane dislocations 1. It is also difficult to reduce basal plane dislocation 1 on the carbon surface as compared to the silicon surface.
 本実施形態に係る炭化珪素エピタキシャル基板100によれば、第2主表面14における基底面転位1の面密度(第2面密度)を、第1主表面12における基底面転位1の面密度(第1面密度)で除した値は、1/1000以下である。また第2主表面14は、カーボン面またはカーボン面に対して8°以下のオフ角で傾斜した面である。つまり本実施形態に係る炭化珪素エピタキシャル基板100によれば、炭化珪素基板10における基底面転位1の大部分を貫通転位に転換することにより、炭化珪素エピタキシャル膜20の第2主表面14における基底面転位1を低減することができる。そのため、カーボン面またはカーボン面に対して8°以下のオフ角で傾斜した第2主表面14を有する炭化珪素エピタキシャル基板100を含む炭化珪素半導体装置300の信頼性を向上することができる。 According to silicon carbide epitaxial substrate 100 in accordance with the present embodiment, the surface density (second surface density) of basal plane dislocation 1 in second main surface 14 can be compared to the surface density of basal plane dislocation 1 in first main surface 12 (first The value divided by 1) is 1/1000 or less. The second main surface 14 is a surface inclined at an off angle of 8 ° or less with respect to the carbon surface or the carbon surface. That is, according to silicon carbide epitaxial substrate 100 according to the present embodiment, the basal plane of second main surface 14 of silicon carbide epitaxial film 20 is obtained by converting most of basal plane dislocations 1 in silicon carbide substrate 10 into threading dislocations. Dislocation 1 can be reduced. Therefore, the reliability of silicon carbide semiconductor device 300 including silicon carbide epitaxial substrate 100 having second main surface 14 inclined at an off angle of 8 ° or less with respect to the carbon surface or the carbon surface can be improved.
 次に、実施例について説明する。まず、サンプル1および2に係る炭化珪素基板が準備された。サンプル1および2に係る炭化珪素基板の主面における基底面転位(BPD)は、4000cm-2であった。サンプル1および2に係る炭化珪素基板の主面の最大径は、150mmであった。次に、サンプル1および2に係る炭化珪素基板上に炭化珪素エピタキシャル膜を成長させた。 Next, an example will be described. First, silicon carbide substrates according to samples 1 and 2 were prepared. The basal plane dislocation (BPD) on the main surface of the silicon carbide substrate according to Samples 1 and 2 was 4000 cm.sup.- 2 . The largest diameter of the main surface of the silicon carbide substrate according to Samples 1 and 2 was 150 mm. Next, a silicon carbide epitaxial film was grown on the silicon carbide substrate according to Samples 1 and 2.
 サンプル1に係る炭化珪素基板に対しては、本実施形態に係る炭化珪素エピタキシャル基板の製造方法を用いて、炭化珪素エピタキシャル膜を形成した。つまり、サンプル1に係る炭化珪素基板に対しては、図7で示した温度プロファイルを用いて、炭化珪素エピタキシャル膜を形成した。具体的には、バッファ層の成長速度を5μm/hとした。ドリフト層の成長速度を25μm/hとした。バッファ層の厚みを1μmとした。バッファ層のキャリア濃度を1×1018cm-3とした。ドリフト層の厚みを10μmとした。ドリフト層のキャリア濃度を7×1015cm-3とした。 For the silicon carbide substrate according to Sample 1, a silicon carbide epitaxial film was formed using the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment. That is, for the silicon carbide substrate according to sample 1, a silicon carbide epitaxial film was formed using the temperature profile shown in FIG. Specifically, the growth rate of the buffer layer was 5 μm / h. The growth rate of the drift layer was 25 μm / h. The thickness of the buffer layer was 1 μm. The carrier concentration of the buffer layer was set to 1 × 10 18 cm −3 . The thickness of the drift layer was 10 μm. The carrier concentration of the drift layer was 7 × 10 15 cm −3 .
 サンプル2に係る炭化珪素基板に対しては、図12で示した温度プロファイルを用いて、炭化珪素エピタキシャル膜を形成した。具体的には、バッファ層の成長速度を5μm/hとした。ドリフト層の成長速度を10μm/hとした。バッファ層の厚みを1μmとした。バッファ層のキャリア濃度を1×1018cm-3とした。ドリフト層の厚みを10μmとした。ドリフト層のキャリア濃度を7×1015cm-3とした。 For the silicon carbide substrate according to sample 2, a silicon carbide epitaxial film was formed using the temperature profile shown in FIG. Specifically, the growth rate of the buffer layer was 5 μm / h. The growth rate of the drift layer was 10 μm / h. The thickness of the buffer layer was 1 μm. The carrier concentration of the buffer layer was set to 1 × 10 18 cm −3 . The thickness of the drift layer was 10 μm. The carrier concentration of the drift layer was 7 × 10 15 cm −3 .
 サンプル2に係る炭化珪素基板の製造方法は、ドリフト層形成工程においてサンプル1に係る炭化珪素基板の製造方法と異なっており、その他の工程においてはサンプル1に係る炭化珪素基板の製造方法と同様である。サンプル2に係る炭化珪素基板のドリフト層形成工程においては、シランガスの流量がたとえば69sccmとなるように調整された。プロパンガスの流量がたとえば43.5sccmとなるように調整された。アンモニアガスの流量がたとえば1.0×10-2sccmとなるように調整された。C/Si比は、1.9であった。 The method of manufacturing a silicon carbide substrate according to sample 2 is different from the method of manufacturing a silicon carbide substrate according to sample 1 in the drift layer forming step, and the other steps are the same as the method of manufacturing a silicon carbide substrate according to sample 1 is there. In the step of forming the drift layer of the silicon carbide substrate according to sample 2, the flow rate of the silane gas was adjusted to, for example, 69 sccm. The flow rate of propane gas was adjusted to, for example, 43.5 sccm. The flow rate of ammonia gas was adjusted to be, for example, 1.0 × 10 −2 sccm. The C / Si ratio was 1.9.
 以上のように、サンプル1および2に係る炭化珪素エピタキシャル基板が製造された。次に、サンプル1および2に係る炭化珪素エピタキシャル基板の第1主表面12および第2主表面14における基底面転位の面密度が測定された。基底面転位の面密度は、前述の測定方法を用いて測定された。 As described above, the silicon carbide epitaxial substrates according to Samples 1 and 2 were manufactured. Next, the areal densities of basal plane dislocations on the first main surface 12 and the second main surface 14 of the silicon carbide epitaxial substrate according to Samples 1 and 2 were measured. The areal density of basal plane dislocations was measured using the measurement method described above.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 表1は、炭化珪素基板の第1主表面12の基底面転位(BPD)の面密度(第1面密度)と、炭化珪素エピタキシャル膜の第2主表面14の基底面転位(BPD)の面密度(第2面密度)と、第2面密度を第1面密度で除した値と、基底面転位から貫通刃状転位への転換率とを示している。表1に示されるように、サンプル1および2に係る炭化珪素基板エピタキシャル基板の第2主表面14における基底面転位の面密度を、第1主表面12における基底面転位の面密度で除した値は、それぞれ0.0005および0.01045であった。またサンプル1および2に係る炭化珪素基板エピタキシャル基板において、第1面密度から第2面密度を引いた値を第1面密度で除した値として求められる転換率は、それぞれ99.95%および98.955%であった。 Table 1 shows the surface density (first surface density) of the basal plane dislocation (BPD) of the first main surface 12 of the silicon carbide substrate and the plane of the basal surface dislocation (BPD) of the second main surface 14 of the silicon carbide epitaxial film The density (second surface density), the value obtained by dividing the second surface density by the first surface density, and the conversion ratio from basal plane dislocation to threading edge dislocation are shown. As shown in Table 1, a value obtained by dividing the areal density of basal plane dislocations on the second main surface 14 of the silicon carbide substrate epitaxial substrate according to Samples 1 and 2 by the areal density of basal plane dislocations on the first main surface 12 Of 0.0005 and 0.01045, respectively. In the silicon carbide substrate epitaxial substrate according to Samples 1 and 2, the conversion ratio determined as the value obtained by subtracting the second surface density from the first surface density divided by the first surface density is 99.95% and 98, respectively. It was .955%.
 以上の結果より、図7の製造条件を用いて炭化珪素エピタキシャル基板を製造する場合は、図12の製造条件を用いて炭化珪素エピタキシャル基板を製造する場合よりも、基底面転位を貫通刃状転位に転換する割合を高め、結果として、炭化珪素エピタキシャル膜における基底面転位の面密度を低減可能であることが確認された。 From the above results, in the case of manufacturing a silicon carbide epitaxial substrate using the manufacturing conditions of FIG. 7, the basal plane dislocation is penetrated like dislocation as compared to the case of manufacturing a silicon carbide epitaxial substrate using the manufacturing conditions of FIG. As a result, it has been confirmed that the surface density of basal plane dislocations in a silicon carbide epitaxial film can be reduced.
 今回開示された実施形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した実施形態ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the embodiments described above but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.
1 基底面転位、2 貫通刃状転位、10 炭化珪素基板、11 第1主面、12 第1主表面、13 第3主面、14 第2主表面、16 第1フラット、20 炭化珪素エピタキシャル膜、21 第1層(バッファ層)、22 第2層(ドリフト層)、25 第1基底面転位、26 第2基底面転位、27 第3基底面転位、35 第1貫通刃状転位、36 第2貫通刃状転位、100 炭化珪素エピタキシャル基板、101 第1方向、102 第2方向、103 第3方向、104 第4方向、105 第5方向、111 最大径、131 ドリフト領域、132 ボディ領域、133 ソース領域、134 コンタクト領域、136 酸化膜、137 層間絶縁膜、138 配線層、141 ゲート電極、142 ソース電極、143 ドレイン電極、200 製造装置、201 反応室、203 発熱体、204 石英管、205 断熱材、206 誘導加熱コイル、207 ガス導入口、208 ガス排気口、210 サセプタ、212 回転軸、300 炭化珪素半導体装置。 1 basal plane dislocation, 2 threading edge dislocation, 10 silicon carbide substrate, 11 first main surface, 12 first main surface, 13 third main surface, 14 second main surface, 16 first flat, 20 silicon carbide epitaxial film 21 first layer (buffer layer) 22 second layer (drift layer) 25 first basal plane dislocation 26 second basal plane dislocation 27 third basal plane dislocation 35 first threading edge dislocation 36 third 2 threading edge dislocation, 100 silicon carbide epitaxial substrate, 101 first direction, 102 second direction, 103 third direction, 104 fourth direction, 105 fifth direction, 111 maximum diameter, 131 drift region, 132 body region, 133 Source region, 134 contact region, 136 oxide film, 137 interlayer insulating film, 138 wiring layer, 141 gate electrode, 142 source electrode, 1 Reference Signs List 3 drain electrode, 200 manufacturing apparatus, 201 reaction chamber, 203 heating element, 204 quartz tube, 205 heat insulator, 206 induction heating coil, 207 gas inlet, 208 gas outlet, 210 susceptor, 212 rotating shaft, 300 silicon carbide semiconductor apparatus.

Claims (6)

  1.  炭化珪素基板と、
     前記炭化珪素基板上にある炭化珪素エピタキシャル膜とを備え、
     前記炭化珪素基板および前記炭化珪素エピタキシャル膜のポリタイプは、4Hであり、
     前記炭化珪素エピタキシャル膜は、前記炭化珪素基板と接する第1層と、前記第1層上にありかつ前記炭化珪素エピタキシャル膜の主表面を構成する第2層とを含み、
     前記炭化珪素基板と、前記第1層と、前記第2層とは、n型不純物を含み、
     前記第1層が含むn型不純物の濃度は、前記炭化珪素基板が含むn型不純物の濃度より低く、かつ前記第2層が含むn型不純物の濃度より高く、
     前記炭化珪素基板の主表面には、第1面密度を有する基底面転位があり、
     前記炭化珪素エピタキシャル膜の主表面には、前記第1面密度よりも低い第2面密度を有する基底面転位があり、
     前記第2面密度を、前記第1面密度で除した値は、1/1000以下であり、
     前記炭化珪素エピタキシャル膜の主表面は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面である、炭化珪素エピタキシャル基板。
    A silicon carbide substrate,
    And a silicon carbide epitaxial film on the silicon carbide substrate,
    The polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H,
    The silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film.
    The silicon carbide substrate, the first layer, and the second layer contain an n-type impurity,
    The concentration of the n-type impurity contained in the first layer is lower than the concentration of the n-type impurity contained in the silicon carbide substrate, and higher than the concentration of the n-type impurity contained in the second layer.
    There is a basal plane dislocation having a first surface density on the main surface of the silicon carbide substrate,
    The main surface of the silicon carbide epitaxial film has a basal plane dislocation having a second surface density lower than the first surface density,
    A value obtained by dividing the second area density by the first area density is 1/1000 or less,
    The silicon carbide epitaxial substrate, wherein the main surface of the silicon carbide epitaxial film is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane.
  2.  前記第2面密度を、前記第1面密度で除した値は、1/2000以下である、請求項1に記載の炭化珪素エピタキシャル基板。 The silicon carbide epitaxial substrate according to claim 1, wherein a value obtained by dividing the second area density by the first area density is 1/2000 or less.
  3.  前記炭化珪素エピタキシャル膜の主表面の最大径は、100mm以上である、請求項1または請求項2に記載の炭化珪素エピタキシャル基板。 The silicon carbide epitaxial substrate according to claim 1 or 2, wherein the largest diameter of the main surface of said silicon carbide epitaxial film is 100 mm or more.
  4.  前記炭化珪素エピタキシャル膜の主表面の最大径は、150mm以上である、請求項3に記載の炭化珪素エピタキシャル基板。 The silicon carbide epitaxial substrate according to claim 3, wherein the largest diameter of the main surface of said silicon carbide epitaxial film is 150 mm or more.
  5.  炭化珪素基板と、
     前記炭化珪素基板上にある炭化珪素エピタキシャル膜とを備え、
     前記炭化珪素基板および前記炭化珪素エピタキシャル膜のポリタイプは、4Hであり、
     前記炭化珪素エピタキシャル膜は、前記炭化珪素基板と接する第1層と、前記第1層上にありかつ前記炭化珪素エピタキシャル膜の主表面を構成する第2層とを含み、
     前記炭化珪素基板と、前記第1層と、前記第2層とは、n型不純物を含み、
     前記第1層が含むn型不純物の濃度は、前記炭化珪素基板が含むn型不純物の濃度より低く、かつ前記第2層が含むn型不純物の濃度より高く、
     前記炭化珪素基板の主表面には、第1面密度を有する基底面転位があり、
     前記炭化珪素エピタキシャル膜の主表面には、前記第1面密度よりも低い第2面密度を有する基底面転位があり、
     前記第2面密度を、前記第1面密度で除した値は、1/1000以下であり、
     前記炭化珪素エピタキシャル膜の主表面は、(000-1)面または(000-1)面に対して8°以下のオフ角で傾斜した面であり、
     前記炭化珪素エピタキシャル膜の主表面の最大径は、150mm以上であり、
     前記第1層の厚みは、0.5μm以上2μm以下であり、
     前記第2層の厚みは、5μm以上30μm以下であり、
     前記第1層が含むn型不純物の濃度は、1×1017cm-3以上1×1019cm-3以下であり、
     前記第2層が含むn型不純物の濃度は、1×1015cm-3以上1×1016cm-3以下である、炭化珪素エピタキシャル基板。
    A silicon carbide substrate,
    And a silicon carbide epitaxial film on the silicon carbide substrate,
    The polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H,
    The silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film.
    The silicon carbide substrate, the first layer, and the second layer contain an n-type impurity,
    The concentration of the n-type impurity contained in the first layer is lower than the concentration of the n-type impurity contained in the silicon carbide substrate, and higher than the concentration of the n-type impurity contained in the second layer.
    There is a basal plane dislocation having a first surface density on the main surface of the silicon carbide substrate,
    The main surface of the silicon carbide epitaxial film has a basal plane dislocation having a second surface density lower than the first surface density,
    A value obtained by dividing the second area density by the first area density is 1/1000 or less,
    The main surface of the silicon carbide epitaxial film is a surface inclined at an off angle of 8 ° or less with respect to the (000-1) plane or the (000-1) plane,
    The largest diameter of the main surface of the silicon carbide epitaxial film is 150 mm or more,
    The thickness of the first layer is 0.5 μm or more and 2 μm or less,
    The thickness of the second layer is 5 μm or more and 30 μm or less,
    The concentration of the n-type impurity contained in the first layer is 1 × 10 17 cm −3 or more and 1 × 10 19 cm −3 or less.
    The silicon carbide epitaxial substrate, wherein the concentration of the n-type impurity contained in the second layer is 1 × 10 15 cm −3 or more and 1 × 10 16 cm −3 or less.
  6.  請求項1~請求項5のいずれか1項に記載の炭化珪素エピタキシャル基板を準備する工程と、
     前記炭化珪素エピタキシャル基板を加工する工程と、を備える、炭化珪素半導体装置の製造方法。
    Preparing a silicon carbide epitaxial substrate according to any one of claims 1 to 5;
    And b. Processing the silicon carbide epitaxial substrate.
PCT/JP2018/016565 2017-09-01 2018-04-24 Silicon carbide epitaxial substrate and production method for silicon carbide semiconductor device WO2019044029A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021060366A1 (en) * 2019-09-27 2021-04-01 学校法人関西学院 Method of manufacturing sic semiconductor device and sic semiconductor device
CN115003866A (en) * 2020-01-29 2022-09-02 住友电气工业株式会社 Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device
CN115003866B (en) * 2020-01-29 2024-05-03 住友电气工业株式会社 Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005167035A (en) * 2003-12-03 2005-06-23 Kansai Electric Power Co Inc:The Silicon carbide semiconductor device and manufacturing method thereof
WO2009107188A1 (en) * 2008-02-25 2009-09-03 財団法人地球環境産業技術研究機構 METHOD FOR GROWING SINGLE CRYSTAL SiC
JP2012246168A (en) * 2011-05-26 2012-12-13 Central Research Institute Of Electric Power Industry Silicon carbide substrate, silicon carbide wafer, method for manufacturing silicon carbide wafer, and silicon carbide semiconductor device
US20130143396A1 (en) * 2011-11-23 2013-06-06 University Of South Carolina Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial
US20140054609A1 (en) * 2012-08-26 2014-02-27 Cree, Inc. Large high-quality epitaxial wafers
JP2016166101A (en) * 2015-03-09 2016-09-15 新日鐵住金株式会社 Production of silicon carbide single crystal epitaxial wafer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1619276B1 (en) 2004-07-19 2017-01-11 Norstel AB Homoepitaxial growth of SiC on low off-axis SiC wafers
JP2009088223A (en) 2007-09-28 2009-04-23 Hitachi Cable Ltd Silicon carbide semiconductor substrate and silicon carbide semiconductor device using the same
US8536582B2 (en) 2008-12-01 2013-09-17 Cree, Inc. Stable power devices on low-angle off-cut silicon carbide crystals
JP5888774B2 (en) 2011-11-18 2016-03-22 一般財団法人電力中央研究所 Method for manufacturing silicon carbide wafer
JP5865777B2 (en) * 2012-05-16 2016-02-17 三菱電機株式会社 Method for manufacturing silicon carbide epitaxial wafer
JP6584253B2 (en) * 2015-09-16 2019-10-02 ローム株式会社 SiC epitaxial wafer, SiC epitaxial wafer manufacturing apparatus, SiC epitaxial wafer manufacturing method, and semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005167035A (en) * 2003-12-03 2005-06-23 Kansai Electric Power Co Inc:The Silicon carbide semiconductor device and manufacturing method thereof
WO2009107188A1 (en) * 2008-02-25 2009-09-03 財団法人地球環境産業技術研究機構 METHOD FOR GROWING SINGLE CRYSTAL SiC
JP2012246168A (en) * 2011-05-26 2012-12-13 Central Research Institute Of Electric Power Industry Silicon carbide substrate, silicon carbide wafer, method for manufacturing silicon carbide wafer, and silicon carbide semiconductor device
US20130143396A1 (en) * 2011-11-23 2013-06-06 University Of South Carolina Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial
US20140054609A1 (en) * 2012-08-26 2014-02-27 Cree, Inc. Large high-quality epitaxial wafers
JP2016166101A (en) * 2015-03-09 2016-09-15 新日鐵住金株式会社 Production of silicon carbide single crystal epitaxial wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021060366A1 (en) * 2019-09-27 2021-04-01 学校法人関西学院 Method of manufacturing sic semiconductor device and sic semiconductor device
CN114423890A (en) * 2019-09-27 2022-04-29 学校法人关西学院 Method for manufacturing SiC semiconductor device and SiC semiconductor device
CN115003866A (en) * 2020-01-29 2022-09-02 住友电气工业株式会社 Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device
CN115003866B (en) * 2020-01-29 2024-05-03 住友电气工业株式会社 Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device

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