WO2019034037A1

WO2019034037A1 - Manufacturing method for semiconductor device

Info

Publication number: WO2019034037A1
Application number: PCT/CN2018/100353
Authority: WO
Inventors: 苏佳乐; 张新伟; 夏长奉; 周国平
Original assignee: 无锡华润上华科技有限公司
Priority date: 2017-08-15
Filing date: 2018-08-14
Publication date: 2019-02-21
Also published as: CN109399553A

Abstract

A manufacturing method for a semiconductor device, comprising: providing an SOI substrate, the SOI substrate comprising, from bottom to top, a bulk silicon (201), a buried oxide layer (202) and a top silicon (203); patterning the top silicon (203) so that a plurality of holes spaced from one another are formed in the top silicon (203); executing an annealing step so that the top silicon (203) separated by the holes migrates to form a cavity top wall and a cavity; forming a plurality of piezoresistive bars (204) on the surface of the cavity top wall; and forming a conductive lead on the plurality of piezoresistive bars (204). The manufacturing method for the semiconductor device is compatible with a CMOS process, and can implement the integration of an SON device and a film sensor; and the manufacturing process is simple and has low requirement for equipment. Therefore, the method reduces the process cost, and improves the performance and the yield of the device.

Description

Method for preparing semiconductor device

Technical field

The present invention relates to the field of semiconductors, and in particular, to a method of fabricating a semiconductor device.

Background technique

With the continuous development of semiconductor technology, in the market of motion sensor products, smart phones, integrated CMOS and microelectromechanical systems (MEMS) devices are increasingly becoming the most mainstream and advanced technologies, and with the update of technology, The development of such transmission sensor products is smaller in size, high quality electrical performance and lower loss.

Among them, MEMS sensors are widely used in automotive electronics: such as TPMS, engine oil pressure sensors, automotive brake system air pressure sensors, automotive engine intake manifold pressure sensors (TMAP), diesel common rail pressure sensors; consumer electronics: such as tire pressure gauges , sphygmomanometer, cabinet scale, health scale, washing machine, dishwasher, refrigerator, microwave oven, oven, vacuum pressure sensor, air conditioning pressure sensor, washing machine, water dispenser, dishwasher, solar water heater liquid level control pressure sensor Industrial electronics: such as digital pressure gauges, digital flow meters, industrial batching weighing, etc., electronic audio and video fields: microphones and other equipment.

At present, MEMS sensors are usually thin film sensors, such as depositing a film having a thickness of several tens of nanometers to several micrometers on a supporting silicon wafer, and removing the silicon wafer in a subsequent process to obtain a partial film region, the sensor Various structures are fabricated in the middle region of the film. MEMS pressure sensors are an important thin film sensor. The thin film sensor can be manufactured in high precision and low cost by using design techniques and manufacturing processes similar to integrated circuits, thereby opening up a convenient way for consumer electronics and industrial process control products to use MEMS sensors at a low cost. Pressure control is simple, easy to use and intelligent. The traditional mechanical pressure sensor is based on the deformation of the metal elastomer, which is elastically deformed by the mechanical quantity to the power conversion output. Therefore, it is not as small as the MEMS pressure sensor, and the cost is much higher than the MEMS pressure. sensor. Compared to traditional mechanical sensors, MEMS pressure sensors are smaller in size, up to a maximum of one centimeter, and have a significant price/performance ratio over traditional "mechanical" manufacturing techniques.

A key structure of the MEMS pressure sensor is the cavity film (i.e., having a cavity in the film), so that a method for manufacturing a cavity film suitable for mass production has become a technical problem to be solved by those skilled in the art.

Summary of the invention

A series of simplified forms of concepts are introduced in the Summary of the Invention section, which will be described in further detail in the Detailed Description section. The summary of the invention is not intended to limit the key features and essential technical features of the claimed invention, and is not intended to limit the scope of protection of the claimed embodiments.

The present invention provides a method of fabricating a semiconductor device, the method comprising:

Providing an SOI substrate comprising bottom-up bulk silicon, a buried oxide layer, and a top layer of silicon;

Patterning the top layer of silicon to form a plurality of spaced apart holes in the top layer of silicon;

Performing an annealing step to migrate the top layer of silicon separated by the pores to form a cavity top wall and a cavity;

Forming a plurality of piezoresistive strips on a surface of the top wall of the cavity;

Conductive leads are formed on a plurality of said piezoresistive strips.

Details of one or more embodiments of the present application are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the invention will be apparent from the description and appended claims.

DRAWINGS

The following drawings of the present application are hereby incorporated by reference in its entirety in its entirety herein in its entirety herein in its entirety The embodiments of the present application and the description thereof are shown in the drawings to explain the apparatus and principles of the present application. In the drawing,

1 is a flow chart of a process for preparing a semiconductor device according to the present application;

2a-2f are schematic views showing the preparation process of the semiconductor device described in the present application.

Detailed ways

In the following description, numerous specific details are set forth to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present application may be practiced without one or more of these details. In other instances, some of the technical features well known in the art have not been described in order to avoid confusion with the present application.

It should be understood that the present application can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the application will be In the drawings, the size and relative dimensions of the layers and regions may be exaggerated for clarity. The same reference numbers indicate the same elements throughout.

It will be understood that when an element or layer is referred to as "on", "adjacent", "connected to" or "coupled" to another element or layer, On, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or Floor. It should be understood that the terms, components, regions, layers, and/or portions may not be limited by the terms of the first, second, third, etc. The terms are only used to distinguish one element, component, region, layer, Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section.

Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned "on" or "below" or "below" or "under" the element or feature is to be "on" the other element or feature. Thus, the exemplary terms "below" and "include" can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing the particular embodiments and embodiments The singular forms "a", "the", and "the" The term "composition" and/or "comprising", when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to fully understand the present application, detailed steps and detailed structures are set forth in the following description in order to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail below, but the present application may have other embodiments in addition to the detailed description.

Embodiment 1

In order to solve the problems existing in the prior art, the present application provides a method for fabricating a semiconductor device, which will be further described below in conjunction with the accompanying drawings.

2a-2f are schematic diagrams showing the preparation process of the semiconductor device described in the present application.

1 is a flow chart of a process for preparing a semiconductor device according to the present application, which specifically includes the following steps:

Step S1: providing an SOI substrate, the SOI substrate comprising bottom-up bulk silicon, a buried oxide layer, and a top layer of silicon;

Step S2: patterning the top silicon to form a plurality of mutually spaced holes in the top silicon;

Step S3: performing an annealing step to migrate the top layer silicon separated by the holes to form a cavity top wall and a cavity;

Step S4: forming a plurality of piezoresistive strips on the surface of the top wall of the cavity;

Step S5: forming conductive leads on a plurality of the piezoresistive strips.

The present application provides a method of fabricating a semiconductor device in which the substrate is an SOI substrate, and a SON process (silicon on nothing) is performed on the SOI substrate to be on the SOI substrate. A cavity is formed and then a piezoresistive strip and conductive leads are formed. The preparation method of the cavity provided by the present application is compatible with the CMOS process, and can realize the integration of the SON (silicon on nothing) device and the thin film sensor; the manufacturing process is relatively simple, the requirements on the device are low, the process cost is greatly reduced, and further Improve device performance and yield.

The method development will be described in detail below based on the process flow chart in FIG.

Step 1 is performed to provide an SOI substrate comprising bottom-up bulk silicon, a buried oxide layer, and top layer silicon.

Specifically, as shown in FIG. 2a, silicon-on-insulator (SOI) includes bottom-up bulk silicon 201, buried oxide layer 202, and top layer silicon 203.

Wherein, the semiconductor device described in the present application includes various MEMS devices, and various MEMS sensors, for example, applied to automotive electronics: such as TPMS, engine oil pressure sensor, automobile brake system air pressure sensor, automobile engine intake manifold pressure Sensor (TMAP), diesel common rail pressure sensor; used in consumer electronics: pressure gauges such as tire pressure gauges, blood pressure monitors, cabinet scales, health scales, washing machines, dishwashers, refrigerators, microwave ovens, ovens, vacuum cleaners, Air conditioning pressure sensor, washing machine, water dispenser, dishwasher, liquid level control pressure sensor for solar water heater; used in industrial electronics: such as digital pressure gauge, digital flow meter, industrial batch weighing, etc., electronic audio and video field: microphone and other equipment .

In the present application, the method for fabricating the semiconductor device is described by taking a differential pressure sensor as an example, but is not limited to this example, and can be applied to various MEMS devices mentioned above, and details are not described herein again.

In the present application, since the SOI is formed to have an oxide buried layer under the active region of the device, the buried oxide layer is buried in the semiconductor substrate layer, thereby providing the device with more excellent performance.

In addition, an oxide buried layer is formed in the SOI substrate, and the buried oxide layer can be used as isolation in a subsequent step, which simplifies the process steps and reduces the cost.

Step 2 is performed to pattern the top layer of silicon to form a plurality of spaced apart holes in the top layer of silicon.

Specifically, as shown in FIG. 2a, the top layer silicon 203 is changed to the top layer silicon having pores by an electrochemical etching process in this step.

In the embodiment of the present application, the top layer silicon has a porosity of 20% to 80%.

In the embodiment of the present application, the reaction solution used in the electrochemical etching process is a mixed solution of hydrogen fluoride and an alcohol. For example, an electrochemical etching process is performed using a mixed solution of HF and C ₂ H ₅ OH in a volume ratio of 1:1.

Optionally, the etching current for the electrochemical etching process of the top silicon is: 20 mA/cm ² to 120 mA/cm ² .

Wherein, the critical dimension of the pore is 0.5 μm-1 μm. The critical dimension of the aperture in this application refers to the aperture size of the aperture, such as diameter, length or width, and the like.

Specifically, the diameter or side length of the pores can be made 0.5 to 1 μm by the electrochemical etching.

Optionally, the pores have a depth of from 1 μm to 20 μm.

Alternatively, the holes are spaced apart from each other with a cylindrical structure between adjacent holes, the holes being spaced from 0.5 μm to 1 μm.

As an alternative embodiment of the present application, in addition to electrochemical etching, the top silicon may be etched by deep reactive ion etching (DRIE) to form the holes.

Specifically, in the deep reactive ion etching (DRIE) step, a gas hexafluoride (SF ₆ ) is selected as a process gas, and a radio frequency power source is applied to cause the silicon hexafluoride to react to form a high ionization, and the etching step The medium control working pressure is 20mTorr-8Torr, the power is 600W, the frequency is 13.5MHz, and the DC bias voltage can be continuously controlled within -500V-1000V to ensure the need of anisotropic etching. Deep reactive ion etching (DRIE) can be used to maintain Very high etch photoresist selection ratio. The deep reactive ion etching (DRIE) system can select equipment commonly used in the art, and is not limited to a certain model.

In another embodiment, the buried oxide layer is patterned while patterning the top silicon to form the holes spaced apart from each other in the top silicon and the buried oxide layer.

Step 3 is performed to perform an annealing step to migrate the top layer of silicon separated by the holes to form a cavity top wall and a cavity.

Specifically, as shown in FIG. 2b, an annealing process is performed to migrate the top layer silicon to the top of the hole, and the top layer silicon on both sides of the hole is combined to form a closed film over the bulk silicon Cavity.

At the same time, during the migration of the top layer of silicon to form the top wall of the cavity, the top wall acts as a seed layer for the subsequent epitaxial process.

For example, when the top layer silicon is silicon, the seed layer formed by migration is single crystal silicon, and the epitaxial layer formed after epitaxy is still a single crystal structure.

In this step, the top layer silicon having pores is migrated to form a cavity by an annealing process which is carried out under a non-oxygen atmosphere, for example, between hydrogen, nitrogen or another inert gas. The annealing temperature is greater than 800 °C.

For example, the conditions of the annealing process are: reaction gas: hydrogen; reaction temperature: 800 ° C to 1200 ° C, for example, about 1000 ° C.

Step 4 is performed to form a plurality of piezoresistive strips on the surface of the top wall of the cavity.

Specifically, as shown in FIG. 2c, the surface of the top wall of the cavity is ion doped in this step to form a plurality of the piezoresistive strips.

Wherein, the ion doping type is not limited to one type, and may be selected according to actual needs, such as N type or P type.

In a specific embodiment of the present application, a piezoresistive strip 204 is disposed on the top wall of the cavity using a light boron doping process.

The number of the piezoresistive strips 204 is not limited to a certain range of values, and may be selected according to actual needs.

For example, in one embodiment of the present application, the piezoresistive strips 204 are disposed in a central region of the top wall of the cavity and are two in number.

Wherein, the resistance value of the piezoresistive strip 204 is changed after being pressed, and the resistance signal is led out through the lead wire.

Step 5 is performed to form conductive leads on the plurality of piezoresistive strips.

Specifically, as shown in FIG. 2d, conductive leads are formed on the piezoresistive strip in this step, for example, forming metal lines.

The material of the metal wire may be selected from copper or aluminum, but is not limited to the above examples, and other commonly used conductive materials may also be selected.

Wherein, the conductive lead is used to lead out a resistance change signal generated by the piezoresistive strip.

Step 6 is performed to pattern the bulk silicon to form a back cavity to expose the buried oxide layer.

Specifically, as shown in FIG. 2e, a portion of the bulk silicon is removed to form a back cavity.

Optionally, the bulk silicon is etched using a Buffered Oxide Etch to form a back cavity.

Wherein, the buffer etching process uses a buffer etchant, and the buffer etchant BOE is formed by mixing HF and NH ₄ F in different ratios.

For example, 6:1 BOE etching means that a mixture of 49% HF aqueous solution: 40% NH ₄ F aqueous solution = 1:6 (volume ratio) is mixed. Among them, HF is the main etching liquid, and NH ₄ F is used as a buffer. Among them, the concentration of H ⁺ is fixed by NH ₄ F to maintain a certain etching rate.

Step 7 is performed to remove the buried oxide layer between the cavity and the back cavity.

Specifically, as shown in FIG. 2f, the buried oxide layer between the cavity and the back cavity is etched away to communicate the cavity and the back cavity.

The buried oxide layer is removed using a hydrofluoric acid vapor (VHF) etching system in this step.

Among them, hydrofluoric acid vapor is a dry etchant method which can selectively remove the oxide layer. Since conventional wet etching causes adhesion, the use of hydrofluoric acid vapor etching prevents both the exposed metal from being oxidized and the smaller structure. In the conventional wet etching process, the process of pulling the microstructure and the liner causes the drying of the corrosive agent of the liquid surface tension, causing adhesion and damaging the structure of the device. The hydrofluoric acid vapor scheme avoids these problems and increases the yield of the device.

The piezoresistive pressure sensor of the present application is generally connected to a Wheatstone bridge through a conductive lead. Usually, the sensitive piezoresistive bar has no external pressure, and the bridge is in equilibrium (called zero position). When the sensor is pressed, the resistance of the piezoresistive bar changes, and the bridge will lose its balance. If a constant current or voltage supply is applied to the bridge, the bridge will output a voltage signal corresponding to the pressure, so that the resistance change of the sensor is converted into a pressure signal output through the bridge. Four integrated circuit fabrication methods for pressure sensors can be used to form four resistor bars of equal resistance and joined to form a Wheatstone bridge. The Wheatstone bridge is powered by constant current, so that the output of the bridge is not affected by the temperature. The Wheatstone bridge detects the change of the resistance value. After the amplifier is amplified, it is converted into the corresponding voltage and current. The current signal is compensated by the nonlinear correction loop, that is, a standard output signal of 4-20 mA which is linearly corresponding to the input voltage is generated, thereby obtaining pressure-related information.

So far, the introduction of the preparation process of the semiconductor device of the embodiment of the present application has been completed. After the above steps, other related steps may also be included, and details are not described herein again. Moreover, in addition to the above steps, the preparation method of the embodiment may further include other steps among the above various steps or between different steps, and the steps may be implemented by various processes in the prior art, where No longer.

The present application provides a method of fabricating a semiconductor device in which the substrate is an SOI substrate, and a SON process (silicon on nothing) is performed on the SOI substrate to be on the SOI substrate. A cavity is formed and then a piezoresistive strip and conductive leads are formed. The preparation method of the cavity provided by the present application is compatible with the CMOS process, and can realize the integration of the SON (silicon on nothing) device and the thin film sensor; the manufacturing process is relatively simple, the requirements on the device are low, the process cost is greatly reduced, and further Improve device performance and yield. An oxide buried layer is formed in the SOI substrate, and the buried oxide layer can be used as isolation in a subsequent step, which simplifies the process steps and reduces the cost.

The present application has been described by the above-described embodiments, but it should be understood that the above-described embodiments are only for the purpose of illustration and description. In addition, those skilled in the art can understand that the present application is not limited to the above embodiments, and various modifications and changes can be made according to the teachings of the present application. These modifications and modifications are all claimed in the present application. Within the scope. The scope of protection of the application is defined by the appended claims and their equivalents.

Claims

A method of fabricating a semiconductor device, the method comprising:

Providing an SOI substrate comprising bottom-up bulk silicon, a buried oxide layer, and a top layer of silicon;

Patterning the top layer of silicon to form a plurality of spaced apart holes in the top layer of silicon;

Performing an annealing step to migrate the top layer of silicon separated by the pores to form a cavity top wall and a cavity;

Forming a plurality of piezoresistive strips on a surface of the top wall of the cavity;

Conductive leads are formed on a plurality of said piezoresistive strips.
The method of claim 1 wherein the method further comprises:

The bulk silicon is patterned to form a back cavity to expose the buried oxide layer.
The method of claim 2, wherein the method further comprises:

The buried oxide layer between the cavity and the back cavity is removed.
The method of claim 3 wherein said step of removing said buried oxide layer between said cavity and said back cavity is to remove said buried oxide layer using a hydrofluoric acid vapor etching system.
The method of claim 1 wherein said step of forming a plurality of spaced apart holes in said top layer silicon forms a key having a critical dimension of from 0.5 μm to 1 μm.
The method according to claim 1, wherein said step of forming a plurality of mutually spaced holes in said top layer silicon forms a hole having a depth of from 1 μm to 20 μm.
The method according to claim 1, wherein said step of forming a plurality of mutually spaced holes in said top layer silicon is formed by a hole having an interval of from 0.5 μm to 1 μm.
The method of claim 1 wherein said annealing step is performed under a non-oxygen atmosphere.
The method of claim 8 wherein said annealing step is carried out under a hydrogen atmosphere.
The method of claim 1 wherein the annealing step has a temperature greater than 800 °C.
The method according to claim 9, wherein the annealing step has a temperature of from 800 ° C to 1200 ° C.
The method of claim 1 wherein said semiconductor device comprises a piezoresistive differential pressure sensor structure.
The method of claim 1 wherein said step of forming a plurality of spaced apart pores in said top layer silicon comprises forming pores having a porosity of from 20% to 80%.
The method according to claim 1, wherein said step of forming a plurality of mutually spaced pores in said top layer silicon is formed by electrochemical etching, wherein said electrochemical etching uses a reaction solution of hydrogen fluoride and an alcohol. Mixed solution.
The method according to claim 14, wherein the reaction solution is a mixed solution of HF and C 2 H 5 OH in a volume ratio of 1:1.
The method according to claim 14, wherein the electrochemical etching process has a corrosion current of 20 mA/cm 2 to 120 mA/cm 2 .
The method of claim 1 wherein said step of forming a plurality of spaced apart apertures in said top layer of silicon is formed by deep reactive ion etching using an etchant gas of silicon hexafluoride.
The method of claim 1 wherein said step of forming a plurality of piezoresistive bars on the surface of said top wall of said cavity is ion doping to form said plurality of piezoresistive bars.
The method of claim 2, wherein the step of forming the back cavity to expose the buried oxide layer is to etch the bulk silicon using a buffer etch process to form a back cavity.
The method according to claim 19, wherein said buffer etching process employs a buffer etchant in which HF and NH 4 F are mixed.