WO2019028868A1 - 信号传输方法及系统 - Google Patents

信号传输方法及系统 Download PDF

Info

Publication number
WO2019028868A1
WO2019028868A1 PCT/CN2017/097185 CN2017097185W WO2019028868A1 WO 2019028868 A1 WO2019028868 A1 WO 2019028868A1 CN 2017097185 W CN2017097185 W CN 2017097185W WO 2019028868 A1 WO2019028868 A1 WO 2019028868A1
Authority
WO
WIPO (PCT)
Prior art keywords
convolutional
data
data stream
input
codewords
Prior art date
Application number
PCT/CN2017/097185
Other languages
English (en)
French (fr)
Inventor
肖治宇
李沫
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2017/097185 priority Critical patent/WO2019028868A1/zh
Priority to EP17920755.0A priority patent/EP3657697B1/en
Priority to CN201780085583.4A priority patent/CN110249554B/zh
Publication of WO2019028868A1 publication Critical patent/WO2019028868A1/zh
Priority to US16/786,566 priority patent/US10958488B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers
    • H04B10/616—Details of the electronic signal processing in coherent optical receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03891—Spatial equalizers
    • H04L25/03898—Spatial equalizers codebook-based design
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6331—Error control coding in combination with equalisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/54—Intensity modulation
    • H04B10/541—Digital intensity or amplitude modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a signal transmission method and system.
  • a high speed fiber optic transmission system can be referred to as a coherent optical transmission system.
  • the coherent optical transmission system includes: a forward error correction code (English: Forward Error Correction; FEC) encoder, a channel interleaver, and a digital-to-analog converter (English: Digital-Analog) Converter; abbreviation: DAC), coherent receiver, analog-to-digital converter (English: Analog-Digital Converter; abbreviation: ADC), channel equalizer, multi-symbol detector, FEC decoder and decider.
  • FEC Forward Error Correction
  • ADC Analog-Digital Converter
  • the FEC encoder, the channel interleaver and the DAC are located at the transmitting end
  • the coherent receiver, the ADC, the channel equalizer, the multi-symbol detector, the FEC decoder and the decider are located at the receiving end
  • the DAC and the coherent receiver are connected by the optical fiber.
  • the data stream at the transmitting end is sequentially transmitted by the encoding of the FEC encoder, the modulation of the channel interleaver, and the digital-to-analog conversion of the DAC, and then transmitted to the coherent receiver through the optical fiber.
  • the coherent receiver recovers the baseband signal through the coherent receiving technique
  • the ADC performs the baseband signal.
  • the channel equalizer performs equalization processing (such as dispersion compensation, clock recovery, depolarization multiplexing, carrier phase estimation, etc.) on the analog-to-digital converted signal through a digital processing algorithm, and inputs the equalized processed signal.
  • equalization processing such as dispersion compensation, clock recovery, depolarization multiplexing, carrier phase estimation, etc.
  • the FEC decoder decodes the detected signal, and finally the judger determines the decoded signal to recover. Out of the data stream.
  • a plurality of multi-symbol detectors and a plurality of FEC decoders are generally provided at the receiving end, and an input end of each multi-symbol detector is connected to an output end of the channel equalizer.
  • the output of each multi-symbol detector is coupled to the input of a corresponding FEC decoder, and the output of each FEC decoder is coupled to the input of the decider and the corresponding multi-symbol detector, respectively.
  • the signals output by the channel equalizer are respectively input to each multi-symbol detector, and after each multi-symbol detector performs multi-symbol detection processing on the signal, a plurality of iterative processes are performed, and each iterative process includes: inputting the detected signals into corresponding The FEC decoder performs decoding, and the FEC decoder feeds back the decoded signal to the corresponding multi-symbol detector, and the multi-symbol detector inputs the signal from the channel equalizer to the multi-symbol detector according to the signal fed back by the FEC decoder.
  • the signal is multi-symbol detected. In this way, the signal can be iteratively processed between the FEC decoder and the multi-symbol detector.
  • the coherent optical transmission system in the related art requires multiple iterative processes, the coherent optical transmission system has a high complexity in transmitting signals.
  • the present application provides a signal transmission method and system.
  • the technical solution is as follows:
  • a signal transmission system in a first aspect, includes: an equalization module, a first decoder, and a feedback module.
  • the equalization module is coupled to the first decoder, and the equalization module includes at least two multi-symbol detectors.
  • the feedback module is respectively connected to the first decoder and the at least two multi-symbol detectors,
  • the equalization module is configured to perform equalization processing on the convolved data stream to obtain an equalized data stream, wherein each of the at least two multi-symbol detectors is used in the equalization processing of the convolutional data stream by the equalization module. Performing multi-symbol detection processing on input respective convolutional data streams;
  • the first decoder is configured to decode the equalized data stream to obtain a decoded data stream
  • the feedback module is configured to determine a feedback data stream according to the decoded data stream, and feed back the feedback data stream to the at least two multi-symbol detectors of the equalization module;
  • the equalization module is further configured to perform equalization processing on the convolved data stream according to the feedback data stream, wherein each of the at least two multi-symbol detectors is used in the equalization processing of the convolution data stream by the equalization module
  • the multi-symbol detection process is performed on the input respective convolution data streams according to the feedback data stream fed back by the feedback module.
  • the signal transmission system further includes: a convolution module, the convolution module, the equalization module, and the first decoder are sequentially connected, and the convolution module is configured to perform convolution processing on the input encoded data stream to obtain convolution data. flow;
  • the encoded data stream includes m coded codewords corresponding one-to-one with consecutive m unit times, and each of the m coded codewords includes k+1 coded data blocks, m>1, k>0, And m and k are both integers;
  • g equalized codewords m equalized codewords corresponding to consecutive m unit times are in one-to-one correspondence with m coded codewords, and each of the m equalized codewords includes corresponding codewords All of the encoded data blocks are sequentially subjected to convolution processing and equalization processing to obtain equalized data blocks;
  • the decoded data stream includes g decoding codewords one-to-one corresponding to consecutive g unit times, and the g decoding codewords are obtained by decoding g equalized codewords, and in the g decoding codewords Each decoded codeword includes k+1 decoded data blocks.
  • the convolution module comprises: a first blocker, a first combiner and k first delays, wherein the k first delay devices are connected in series, and the first blocker and the k first delays The timing device and the first combiner are connected in series, and the output ends of each of the k first delay devices are respectively connected to the input ends of the first combiner, and the first one of the k first delay devices The input end of the first delay is connected to the input of the first combiner,
  • the first blocker is configured to divide each of the m coded codewords into k+1 coded data blocks, and input one of the k+1 coded data blocks into the first combiner, k coded data blocks are input to the first first delayer;
  • Each of the k first delays is used to delay the input of the respective p coded data blocks by n unit times to obtain p delay coded data blocks, and p delay coded data blocks
  • One delay coded data block in the block is input to the first combiner, and p-1 delayed coded data blocks are input to the next first delay device respectively connected, 1 ⁇ p ⁇ k, and p is an integer;
  • the first combiner is configured to combine the coded data blocks corresponding to the input m codewords of the own to obtain a convolved data stream.
  • the first combiner is configured to combine the coded data blocks corresponding to the m coded codewords of the input into the chronological order to obtain a convolutional data stream, where the convolutional data stream includes w convolutional codewords; In the convolutional codeword:
  • the n*k convolutional codeword corresponding to the first n*k unit time in w unit time includes k convolutional codeword groups, each The convolutional codeword group includes n convolutional codewords, each convolutional codeword comprising i first convolutional data blocks and k+1-i second convolutional data blocks, wherein i first volumes
  • Each of the first convolutional data blocks in the product data block is one of the i coded code words of the n*i coded codewords corresponding to the first n*i unit code times of m unit time
  • i first convolutional data blocks are one-to-one corresponding to i coded codewords
  • k+1-i second convolutional data blocks are initial data blocks, k ⁇ i>0, and i is an integer; optional Ground, the data in the initial data block is 0.
  • the n*k convolutional codeword corresponding to the last n*k unit time in w unit time includes k convolutional codeword groups, each convolutional codeword group including n convolutional codewords, each volume
  • the product codeword includes k+1-j first convolutional data blocks and j second convolutional data blocks, wherein each of the first convolutional data blocks of k+1-j first convolutional data blocks Is one of the k+1-j coded code words in the n*j coded codewords corresponding to the last n*j unit code times in m unit time, k+1-j first
  • the convolutional data blocks are one-to-one corresponding to k+1-j encoded codewords, and the j second encoded data blocks are initial data blocks, k ⁇ j>0, and j is an integer; optionally, in the initial data block The data is 0.
  • the convolutional codeword corresponding to each unit time in the intermediate unit time includes k+1 first convolutional data blocks, and each of the first convolutional data blocks in the k+1 first convolutional data blocks is m
  • One of the k+1 coded codewords in the codeword word, k+1 first convolutional data blocks are one-to-one corresponding to the k+1 codewords, and the intermediate unit time is w unit time In addition to the unit time before the first n*k unit time and the last n*k unit time.
  • the equalization module includes: a second combiner, k second delays, k+1 multiple symbol detectors, k+1 second blockers, and k+1 first data extractors.
  • the output end of the k+1 multi-symbol detector is connected one-to-one with the input end of the k+1 second blocker, and the output end of the k+1 second blocker and the k+1 first data extractor
  • the input ends of the first data extractor are connected to the input end of the second combiner, and the k second delay devices are connected in series.
  • the output ends of the k second delay devices are connected in one-to-one correspondence with the input ends of the k multi-symbol detectors in the k+1 multi-symbol detectors, and the first second delay in the k second delay devices
  • the input end of the timer is connected to the input end of the multi-symbol detector except the k multi-symbol detectors, and the input end of the first second delayer is also connected to the convolution module.
  • the convolution module is configured to input the convolved data stream into the first second delay device and the multi-symbol detector connected to the input end of the first second delay device;
  • Each of the k second delays is configured to delay the input convolution data stream by n unit times to obtain a delayed convolution data stream, and input the delayed convolution data stream separately.
  • a respective connected multi-symbol detector and a next second delay each delayed convolution data stream comprising w delay convolutional code words one-to-one corresponding to consecutive w unit times;
  • Each of the k+1 multi-symbol detectors is configured to perform multi-symbol detection processing on the input convolutional data streams to obtain a multi-symbol detection convolutional data stream, and input the multi-symbol detection convolutional data stream.
  • a second blocker connected to each, each multi-symbol detection convolution data stream comprising w multi-symbol detection convolutional code words one-to-one corresponding to consecutive w unit times;
  • Each of the k+1 second blockers is configured to divide each multi-symbol convolutional codeword in the input multi-symbol detection convolutional data stream into k+1 convolutional data blocks, Obtaining k+1 convolutional data block streams, and inputting k+1 convolutional data block streams into respective connected first data extractors;
  • Each of the k+1 first data extractors is configured to extract a target convolutional data block stream from the input k+1 convolutional data block streams, and extract the extracted target convolution
  • the data block stream is input to the second combiner;
  • the second combiner is configured to combine the input k+1 target convolutional data block streams to obtain an equalized data stream.
  • the second combiner is configured to combine the input k+1 target convolution data block streams in chronological order And obtaining an equalized data stream, wherein the equalized data stream comprises k+1 target convolutional data block streams, and each target convolutional data block stream comprises one equalized data block in each of the equalized codewords of the g equalized codewords.
  • the equalized data stream comprises k+1 target convolutional data block streams
  • each target convolutional data block stream comprises one equalized data block in each of the equalized codewords of the g equalized codewords.
  • the equalization codeword corresponding to each of the first n*k unit time and the last n*k unit time in g unit time includes k+1 initial data blocks;
  • the equalization codeword corresponding to each unit time in the intermediate unit time in g unit time includes: equalization obtained by sequentially performing convolution processing and equalization processing on k+1 coded data blocks in the corresponding coded codeword
  • the data block, the intermediate unit time is g unit time, except the unit time of the previous n*k unit time and the last n*k unit time.
  • the feedback module comprises: k third delay devices, wherein the k third delay devices are connected in series, and the first third delay of the output of the first decoder and the k third delay devices
  • the input of the device is connected, the output of the qth third delayer of the k third delays and the input of the k+1-q multi-symbol detectors of the k+1 multi-symbol detectors Connected, k+1-q multi-symbol detectors are multi-symbol detectors connected to the output of the inverse k+1-q second delays in the k second delays, k third extensions
  • Each third delayer in the timer is configured to delay the input decoded data stream by n unit time to obtain a delayed decoded data stream, and input the delayed decoded data stream into the connected multi-symbol detection.
  • each of the k+1 multi-symbol detectors is configured to decode the data stream according to the delayed delay of the respective connected third delay, for inputting the
  • the decoded data stream includes k+1 decoded data block streams, and the k+1 decoded data block streams are k+1 target convolution data block streams in the first decoder pair equalized data stream.
  • the feedback module further comprises: an external information calculator and k second data extractors, wherein the input ends of the external information calculator are respectively connected with the output of the first decoder and the input of the first decoder End connection, the output of the external information calculator is connected with the first third delay of the k third delays, and each of the k third delays passes a second data
  • the extractor is connected to the input of the corresponding multi-symbol detector,
  • the external information calculator is configured to calculate an external information stream of the first decoder according to the decoded data stream output by the first decoder and the equalized data stream input to the first decoder, where the external information stream includes k+1 outer information blocks Flow, k+1 outer information block streams are calculated by the external information calculator according to k+1 decoded data block streams and k+1 target convolution data block streams;
  • Each of the k third delays is configured to delay the input of each external information stream by n unit time to obtain a delayed external information stream, and input the delayed external information stream into the respective connected first a second data extractor and a next third delay, each of the delayed external information streams comprising k+1 delayed outer information block streams;
  • Each of the k second data extractors is configured to extract a target delayed outer block flow from the k+1 delayed outer block flows input to the respective delayed external information streams, and extracts The target delay time block flow into the respective connected multi-symbol detector;
  • Each of the k+1 multi-symbol detectors is configured to perform multi-symbol detection processing on the input respective convolutional data streams according to the target delayed outer block flow fed back by the respective second data extractor.
  • the first blocker is specifically configured to: divide each of the m coded codewords into k+1 coded data blocks that are sequentially arranged, and insert the first of the k+1 coded data blocks.
  • 1 code data block is input to the first combiner, and the 2nd to k+1th code data blocks are input to the first first delay device;
  • each of the k first delay devices is specifically used for : delaying p coding data blocks sequentially input by n unit time, obtaining p delay coded data blocks, and inputting the first delay coded data block in the p delay coded data blocks into the first A combiner, the second through pth delayed coded data blocks are input to the next first delay connected to each other.
  • the signal transmission system further includes: an encoder and a second decoder, and the encoder is connected to the convolution module,
  • the second decoder is coupled to the first decoder, the encoder is configured to encode the data stream of the input itself to obtain an encoded data stream, and the second decoder is configured to perform secondary decoding on the decoded data stream.
  • a signal transmission method includes:
  • Equalizing the convolved data stream to obtain an equalized data stream wherein each of the at least two multi-symbol detectors is used to input respective volumes during equalization processing of the convolved data stream
  • the product data stream is subjected to multi-symbol detection processing
  • each multi-symbol detector of the at least two multi-symbol detectors is configured to input the input according to the feedback data stream during the equalization processing of the convolved data stream
  • the respective convolutional data streams are subjected to multi-symbol detection processing.
  • the signal transmission method further includes: performing convolution processing on the encoded data stream to obtain a convolved data stream;
  • the encoded data stream includes m coded codewords corresponding one-to-one with consecutive m unit times, and each of the m coded codewords includes k+1 coded data blocks, m>1, k>0, And m and k are both integers;
  • g equalized codewords m equalized codewords corresponding to consecutive m unit times are in one-to-one correspondence with m coded codewords, and each of the m equalized codewords includes corresponding codewords All of the encoded data blocks are sequentially subjected to convolution processing and equalization processing to obtain equalized data blocks;
  • the decoded data stream includes g decoding codewords one-to-one corresponding to consecutive g unit times, and the g decoding codewords are obtained by decoding g equalized codewords, and in the g decoding codewords Each decoded codeword includes k+1 decoded data blocks.
  • performing convolution processing on the encoded data stream to obtain a convolved data stream includes:
  • the encoded data blocks corresponding to the m encoded codewords are combined to obtain a convolved data stream.
  • the coded data blocks corresponding to the m codewords are combined to obtain a convolved data stream, including:
  • the coded data blocks corresponding to the m coded codewords are combined in time sequence to obtain a convolutional data stream, and the convolutional data stream includes w convolutional codewords; in w convolutional codewords:
  • the n*k convolutional codeword corresponding to the first n*k unit times in w unit time includes k convolutional codeword groups, each convolutional codeword group including n convolutional codewords, each volume
  • the product codeword includes i first convolutional data blocks and k+1-i second convolutional data blocks, wherein each of the first convolutional data blocks is m and m
  • the codeword, k+1-i second convolutional data blocks are initial data blocks, k ⁇ i>0, and i is an integer; alternatively, the data in the initial data block is 0.
  • the n*k convolutional codeword corresponding to the last n*k unit time in w unit time includes k convolutional codeword groups, each Each convolutional codeword group includes n convolutional codewords, each convolutional codeword comprising k+1-j first convolutional data blocks and j second convolutional data blocks, where k+1-j Each of the first convolutional data blocks is k+1-j codes in n*j coded codewords corresponding to the last n*j unit time in m unit time
  • One coded data block in the codeword, k+1-j first convolutional data blocks are one-to-one corresponding to k+1-j coded codewords, and j second coded data blocks are initial data blocks, k ⁇ j>0, and j is an integer; alternatively, the data in the initial data block is 0.
  • the convolutional codeword corresponding to each unit time in the intermediate unit time includes k+1 first convolutional data blocks, and each of the first convolutional data blocks in the k+1 first convolutional data blocks is m
  • One of the k+1 coded codewords in the codeword word, k+1 first convolutional data blocks are one-to-one corresponding to the k+1 codewords, and the intermediate unit time is w unit time In addition to the unit time before the first n*k unit time and the last n*k unit time.
  • the convolution data stream is equalized to obtain an equalized data stream, including:
  • each delayed convolutional data stream comprising w delay convolutional codewords corresponding one-to-one with consecutive w unit times;
  • Multi-symbol detection processing is performed on the convolved data stream to obtain a multi-symbol detection convolution data stream, and each multi-symbol detection convolution data stream includes w multi-symbol detection convolutional code words one-to-one corresponding to consecutive w unit times ;
  • the target convolutional data block streams are combined to obtain an equalized data stream.
  • the target convolutional data block stream is merged to obtain an equalized data stream, including:
  • the k+1 target convolutional data block streams are combined in time sequence to obtain an equalized data stream, and the equalized data stream includes k+1 target convolutional data block streams, and each target convolutional data block stream includes g equalization codes.
  • the equalization codeword corresponding to each of the first n*k unit time and the last n*k unit time in g unit time includes k+1 initial data blocks; and in the middle of g unit time
  • the equalization codeword corresponding to each unit time in the unit time includes: an equalization data block obtained by sequentially performing convolution processing and equalization processing on k+1 coded data blocks in the corresponding coded codeword, and the intermediate unit time is g. In unit time, except for the first n*k unit time and the unit time after n*k unit time.
  • determining the feedback data stream according to the decoded data stream includes:
  • the delayed decoded data stream is determined to be a feedback data stream.
  • the decoded data stream includes k+1 decoded data block streams, and the k+1 decoded data block streams are decoded by processing k+1 target convolution data block streams in the equalized data stream. Determining the feedback data stream according to the decoded data stream, including:
  • the outer information stream includes k+1 outer information block streams, and the k+1 outer information block streams are based on k+1 decoded data block streams and k+1 Calculated by the target convolutional data block stream;
  • the external information flow is delayed by n unit time, and the delayed external information flow is obtained;
  • the delayed external information stream is determined as a feedback data stream.
  • each of the m coded codewords is divided into k+1 coded data blocks, including:
  • Delaying p units of data blocks by n unit times, resulting in p delay-coded data blocks including:
  • the p coded data blocks arranged in sequence are delayed by n unit times to obtain p delay coded data blocks.
  • the signal transmission method provided by the present application may be implemented by a processor executing a program.
  • the encoder, the convolution module, and the DAC may be sent by a functional unit in a processor of the transmitting device.
  • the processor of the end device can implement the method corresponding to the encoder, the convolution module and the DAC in the above method by executing a program, the coherent receiver, the ADC, the equalization module, the feedback module, the first decoder, the second decoder and
  • the decider may be a functional unit in the processor of the receiving end device, and the processor of the receiving end device may implement the coherent receiver, the ADC, the equalization module, the feedback module, the first decoder, and the second translation in the above method by executing a program.
  • the method corresponding to the coder and the decider may be a functional unit in the processor of the receiving end device, and the processor of the receiving end device may implement the coherent receiver, the ADC, the equalization module, the feedback module, the first decoder, and the second translation in the above method by executing a program.
  • the equalization module includes at least two multi-symbol detectors
  • at least two multi-symbol detectors perform multi-symbol detection processing on the convolved data stream according to the feedback data stream, and the feedback data stream is based on Decoding the data stream, so that the signal can be fed back between the first decoder and the at least two multi-symbol detectors without having to set up multiple decoders, and in the decoder and multi-symbol detection
  • the device performs multiple iterations to solve the problem of high complexity of the transmitted signal, which helps to reduce the complexity of the transmitted signal.
  • 1 is a schematic structural view of a conventional coherent optical transmission system
  • FIG. 2 is a schematic structural diagram of a coherent optical transmission system provided by the related art
  • FIG. 3 is a schematic structural diagram of a signal transmission system according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another signal transmission system according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a partial area of a signal transmission system according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another part of a signal transmission system according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a process of processing a data stream by a signal transmission system according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a process of processing a data stream by a signal transmission system according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a process of processing a data stream by a signal transmission system according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a process of processing a data stream by a signal transmission system according to an embodiment of the present application
  • FIG. 11 is a state transition diagram according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a multi-symbol detector provided by an embodiment of the present application.
  • the coherent optical transmission system includes: an FEC encoder, a channel interleaver, and a DAC connected in sequence from a transmitting end to a receiving end. , coherent receiver, ADC, channel equalizer, multi-symbol detector, FEC decoder and decider.
  • the FEC encoder, the channel interleaver and the DAC are located at the transmitting end, the coherent receiver, the ADC, the channel equalizer, the multi-symbol detector, the FEC decoder and the decider are located at the receiving end, and the DAC and the coherent receiver are connected by the optical fiber.
  • the data stream at the transmitting end is sequentially transmitted by the encoding of the FEC encoder, the modulation of the channel interleaver, and the digital-to-analog conversion of the DAC, and then transmitted to the coherent receiver through the optical fiber.
  • the coherent receiver recovers the baseband signal through the coherent receiving technique, and the ADC performs the baseband signal.
  • Analog-to-digital conversion the channel equalizer equalizes the analog-to-digital converted signal, and inputs the equalized signal into the multi-symbol detector. After the multi-symbol detector performs multi-symbol detection on the equalized signal, the FEC translation The coder decodes the detected signal, and finally the determiner determines the decoded signal to recover the data stream.
  • a plurality of multi-symbol detectors and a plurality of FEC decoders are generally provided at the receiving end, and the input end of each multi-symbol detector and the channel are equalized.
  • the outputs of the multi-symbol detectors are connected to the inputs of the respective FEC decoders, and the outputs of each FEC decoder are respectively associated with the decision maker and the corresponding multi-symbol detector input. connection.
  • the signals output by the channel equalizer are respectively input to each multi-symbol detector, and after each multi-symbol detector performs multi-symbol detection processing on the signal, a plurality of iterative processes are performed, and each iterative process includes: inputting the detected signals into corresponding The FEC decoder performs decoding, and the FEC decoder feeds back the decoded signal to the corresponding multi-symbol detector, and the multi-symbol detector inputs the signal from the channel equalizer to the multi-symbol detector according to the signal fed back by the FEC decoder.
  • the signal is multi-symbol detected.
  • the signal can be iteratively processed between the FEC decoder and the multi-symbol detector.
  • the coherent optical transmission system needs to perform multiple iterative processes, the coherent optical transmission system has a high complexity of transmitting signals.
  • the coherent optical transmission system shown in FIG. 2 if the number of iterations is small, the accuracy of the data fed back to the multi-symbol detector by the FEC decoder is low, which affects the iterative performance.
  • the signal transmission system provided by the embodiment of the present application can ensure data accuracy and reduce the complexity of the transmission signal without performing multiple iterations.
  • FIG. 3 is a schematic structural diagram of a signal transmission system according to an embodiment of the present application.
  • the signal transmission system may be a coherent optical transmission system.
  • the signal transmission system includes: an equalization module 01, A decoder 02 and a feedback module 03, the equalization module 01 and the first decoder 02 are connected, the equalization module 01 comprises at least two multi-symbol detectors (not shown in FIG. 3), and the feedback module 03 and the first translation respectively
  • the encoder 02 is coupled to at least two multi-symbol detectors.
  • the equalization module 01 is configured to perform equalization processing on the convolved data stream to obtain an equalized data stream, wherein each of the at least two multi-symbol detectors is in the process of equalizing the convolution data stream by the equalization module 01.
  • the detector is configured to perform multi-symbol detection processing on the input respective convolutional data streams;
  • the first decoder 02 is configured to decode the equalized data stream to obtain a decoded data stream;
  • the feedback module 03 is configured to determine according to the decoded data stream.
  • each of the at least two multi-symbol detectors is configured to perform multi-symbol detection processing on the input respective convolution data streams according to the feedback data stream fed back by the feedback module 03.
  • the equalization module includes at least two multi-symbol detectors
  • at least two multi-symbol detectors perform multi-symbol detection processing on the convolved data stream according to the feedback data stream, and The feedback data stream is determined according to the decoded data stream. Therefore, the signal can be feedback-transmitted between the first decoder and the at least two multi-symbol detectors without setting multiple decoders and decoding
  • the device and the multi-symbol detector perform multiple iterations to solve the problem of high complexity of the transmitted signal, which helps to reduce the complexity of the transmitted signal.
  • FIG. 4 is a schematic structural diagram of another signal transmission system according to an embodiment of the present application.
  • the signal transmission system further includes: a convolution module 04, a convolution module. 04.
  • the equalization module 01 and the first decoder 02 are sequentially connected, and the convolution module 04 is configured to perform convolution processing on the input encoded data stream to obtain a convolved data stream.
  • the signal transmission system further includes: an encoder 05 and a second decoder 06, the encoder 05 is connected to the convolution module 04, and the second decoder 06 is connected to the first decoder 02, and the encoder 05 is used.
  • Row coding yields an encoded data stream; second decoder 06 is used to perform secondary decoding of the decoded data stream.
  • the signal transmission system further includes: a DAC-07, a coherent receiver 08, an ADC-09, and a decider 10.
  • the encoder 05, the convolution module 04, and the DAC-07 are sequentially connected, and the encoder 05 and the convolution module are sequentially connected.
  • the coherent receiver 08, the ADC-09, the equalization module 01, the first decoder 02, the second decoder 06, and the decider 10 are sequentially connected, and the coherent receiver 08, ADC-09, equalization module 01, first decoder 02, second decoder 06 and decider 10 are located at the receiving end of the signal transmission system, DAC-07 and the coherent receiver are connected through the optical fiber, and the feedback module 03 respectively It is connected to the first decoder 02 and the equalization module 01.
  • the structure and function of the DAC-07, the coherent receiver 08, the ADC-09, and the determinator 10 can be referred to the related art, and details are not described herein again.
  • the encoder 05 may be an FEC encoder
  • both the first decoder 02 and the second decoder 06 may be FEC decoders
  • the decider 10 may be a soft decider
  • the encoder 05 is used to encode the data stream of the input itself to obtain an encoded data stream.
  • the data stream input to the encoder 05 may be a service data stream on the client side, and the service data stream may include m service code words corresponding to one-to-one consecutive time units, and the encoder 05 performs the service data stream.
  • the encoded data stream is obtained, and the encoded data stream is input to the convolution module 04.
  • the encoded data stream includes m encoded codewords corresponding to one-to-one consecutive units of m units, each of which The coded codeword is obtained by encoding the corresponding service codeword, and each of the m coded codewords includes k+1 coded data blocks, m>1, k>0, and m and k are both Integer.
  • the convolutional data stream can be sent to the equalization module 01 through the DAC-07, the coherent receiver 08, and the ADC-09, and in the process, the DAC-07, the coherent The receiver 08 and the ADC-09 can also perform corresponding processing on the convolutional data stream.
  • the process of the process reference may be made to the related art, and details are not described herein again.
  • the equalization module 01 is configured to perform equalization processing on the convolved data stream to obtain an equalized data stream, and input the equalized data stream to the first decoder 02, where the equalized data stream includes g equalizations corresponding to consecutive g unit times.
  • the equalization codeword is in one-to-one correspondence with the m coded codewords, and each of the m equalization codewords includes an equalization obtained by sequentially performing convolution processing and equalization processing on all the coded data blocks in the corresponding coded codeword. data block.
  • the first decoder 02 is configured to decode the equalized data stream to obtain a decoded data stream, and input the decoded data stream to the feedback module 03 and the second decoder 06, respectively.
  • the decoded data stream includes g decoding codewords that are in one-to-one correspondence with consecutive g unit times, and the g decoding codewords are obtained by decoding g equalized codewords, and g decoding codewords are obtained.
  • Each decoded codeword in the block includes k+1 decoded data blocks.
  • the feedback module 03 is configured to determine a feedback data stream according to the decoded data stream, and feed back the feedback data stream to at least two multi-symbol detectors of the equalization module 01; the second decoder 06 is configured to perform the second time on the decoded data stream Decoding to improve decoding accuracy.
  • the convolution module 04 includes: a first blocker 041, a first combiner 042, and k
  • the first delay device, the k first delay devices are connected in series, and the first blocker 041, the k first delay devices and the first combiner 042 are sequentially connected in series, and each of the k first delay devices
  • the outputs of the first delays are respectively connected to the input ends of the first combiner 042, and the input of the first first delays of the k first delays is connected to the input of the first combiner 042.
  • FIG. 5 shows a schematic structural diagram of the area A of FIG. 4.
  • the convolution module 04 includes: a first blocker 041, a first combiner 042, and k
  • the first delay device, the k first delay devices are connected in series, and the first blocker 041, the k first delay devices and the first combiner 042 are sequentially connected in series, and each of the k first delay devices
  • the outputs of the first delays are respectively connected to the input ends of the first combiner 042, and the input of the
  • the k first delay devices include the first delay device 1 to the first delay device k as an example, and the output end of the first delay device 1 and the first delay device 2
  • the input terminal is connected, the output end of the first delay device 2 is connected to the input end of the first delay device 3 (not shown in FIG. 5), and so on, until the first delay device k, the first blocker
  • the output end of the 041 is connected to the input end of the first delay device 1, and the output end of each of the first delay device 1 to the first delay device k is respectively input to the first combiner 042.
  • the first first delay in the k first delays may be the first delay 1, and the input of the first delay 1 is connected to the input of the first combiner 042. It should be noted that, in practical applications, the first blocker 041 is also connected to the encoder 05.
  • the encoder 05 is operative to input the encoded data stream into the first blocker 041, the encoded data stream comprising m coded code words that correspond one-to-one with successive m unit times.
  • the first blocker 041 is configured to divide each of the m coded codewords into k+1 coded data blocks, and input one of the k+1 coded data blocks into the first merged block.
  • the number of k coded data blocks is input to the first first delayer; for example, the first blocker 041 divides each of the m coded codewords into k+1 coded data blocks, k+ One of the one coded data block is input to the first combiner 042, and the k coded data blocks are input to the first delayer 1.
  • Each of the k first delays is used to delay the input of the respective p coded data blocks by n unit times to obtain p delay coded data blocks, and p delay coded data blocks
  • the first combiner 042 is configured to combine the encoded data blocks corresponding to the m encoded codewords input by itself to obtain a convolved data stream.
  • the coded data block that is combined by the first combiner 042 may include the coded data block that is not delayed by the first delay device 1 and the first delay device 2 and the first delay device 2 to the first delay.
  • Each of the first delays in the timer k inputs the delayed coded data block of the first combiner 042.
  • the first blockter 041 is specifically configured to divide each of the m coded codewords into k+1 coded data blocks that are sequentially arranged, and k+1
  • the first coded data block in the coded data block is input to the first combiner, and the second to k+1th coded data block is input to the first first delay device 1; each of the k first delay devices
  • the first delay device is specifically configured to delay the input of the p consecutive blocks of coded data blocks by n unit time to obtain p delay coded data blocks, and the first one of the p delay coded data blocks.
  • the delayed encoded data block is input to the first combiner, and the second through pth delayed encoded data blocks are input to the next first delay connected to each other.
  • the first combiner 042 is configured to combine the coded data blocks corresponding to the m encoded codewords of the input into the chronological order to obtain a convolutional data stream, where the convolutional data stream includes w convolutional codewords; wherein, in the w In the convolutional codeword:
  • the n*k convolutional codeword corresponding to the first n*k unit times in w unit time includes k convolutional codeword groups, each convolutional codeword group including n convolutional codewords, each volume
  • the product codeword includes i first convolutional data blocks and k+1-i second convolutional data blocks, wherein each of the first convolutional data blocks is m and m
  • the i first convolutional data blocks are one-to-one corresponding to the i codewords
  • k+ 1-i second convolutional data blocks are initial data blocks, k ⁇ i>0, and i is an integer; in the embodiment of the present application, in the n*k convolutional codeword corresponding to the first n*k unit time
  • the number of the convolutional codeword group may be arranged in chronological order, i denotes the number of the convolutional codeword group, and the data in the
  • the n*k convolutional codeword corresponding to the last n*k unit time in w unit time includes k convolutional codeword groups, each convolutional codeword group including n convolutional codewords, each volume
  • the product codeword includes k+1-j first convolutional data blocks and j second convolutional data blocks, wherein each of the first convolutional data blocks of k+1-j first convolutional data blocks Is one of the k+1-j coded code words in the n*j coded codewords corresponding to the last n*j unit code times in m unit time, k+1-j first
  • the convolutional data blocks are one-to-one corresponding to the k+1-j coded codewords, and the j second coded data blocks are the initial data blocks, k ⁇ j>0, and j is an integer; in the embodiment of the present application,
  • the number of the convolutional codeword group may be arranged in chronological order
  • the convolutional codeword corresponding to each unit time in the intermediate unit time includes k+1 first convolutional data blocks, and each of the first convolutional data blocks in the k+1 first convolutional data blocks is m
  • One of the k+1 coded codewords in the codeword word, k+1 first convolutional data blocks are one-to-one corresponding to the k+1 codewords, and the intermediate unit time is w unit time In addition to the unit time before the first n*k unit time and the last n*k unit time.
  • FIG. 6 shows a schematic structural diagram of a region B in FIG. 4, where the region B includes an equalization module 01, a first decoder 02, and a feedback module 03, which are balanced in conjunction with FIG. 4 and FIG.
  • Module 01 includes: a second combiner 011, k second delays, k+1 multiple symbol detectors, k+1 second blockers, and k+1 first data extractors, k+1
  • the output of the multi-symbol detector is connected one-to-one with the input of the k+1 second blocker, and the output of the k+1 second blocker and the input of the k+1 first data extractor
  • the output of each of the first data extractors of the k+1 first data extractors is connected to the input end of the second combiner 011, and the k second delay devices are connected in series, and k
  • the output of the second delay is connected one-to-one with the input of the k multi-symbol detectors of the k+1 multi-symbol
  • the FIG. 6 includes a second delayer 1 to a second delayer k in k second delays, and k+1 multi-symbol detectors include a multi-symbol detector 1 to a multi-symbol detector k+1
  • the k+1 second blockers include the second blocker 1 to the second blocker k+1
  • the k+1 first data extractors include the first data extractor 1 to the first data extractor k +1 is taken as an example for explanation.
  • the output of the multi-symbol detector 1 is connected to the input of the second blocker 1, the output of the multi-symbol detector 2 is connected to the input of the second blocker 2, and so on, the output of the multi-symbol detector k
  • the end is connected to the input end of the second blocker k, the output end of the multi-symbol detector k+1 is connected to the input end of the second blocker k+1; the output end of the second blocker 1 and the first data
  • the input end of the extractor 1 is connected, the output end of the second blocker 2 is connected to the input end of the first data extractor 2, and so on, the output of the second blocker k and the input of the first data extractor k End connection, the output of the second blocker k+1 is connected to the input of the first data extractor k+1;
  • the output of the second delay 1 is connected to the input of the multi-symbol detector 2, second The output of the delayer 2 is connected to the input of the multi-sy
  • the first delay in the k second delays may be the second delay 1 , and the input of the second delay 1 is connected to the input of the multi-symbol detector 1
  • an input of the second delay is also connected to the convolution module 04, and the second input terminal of the delay 1 and DAC-07 is particularly a convolution module 04 and the receiver 08 is connected by a coherent.
  • the convolution module 04 is configured to input the convolved data stream into the first second delay and the multi-symbol detector connected to the input of the first second delay; for example, the convolution module 04 convolves the data.
  • the stream is input to the second delayer 1 and the multi-symbol detector 1, respectively.
  • Each of the k second delays is configured to delay the input convolution data stream by n unit times to obtain a delayed convolution data stream, and input the delayed convolution data stream separately.
  • a respective multi-symbol detector and a second second delay each delayed convolution data stream comprising w delay convolutional codewords corresponding one-to-one with consecutive w unit times; for example, a second delay
  • the timer 1 delays the convolution data stream input to the second delay device 1 by n unit times to obtain a delayed convolution data stream, and inputs the delayed convolution data stream into the multi-symbol detector 2 and the second extension, respectively.
  • the second delay device 2 delays the convolution data stream input to the second delay device 2 by n unit time to obtain a delayed convolution data stream, and inputs the delayed convolution data stream into the multi-symbol respectively.
  • Each of the k+1 multi-symbol detectors is configured to perform multi-symbol detection processing on the input convolutional data streams to obtain a multi-symbol detection convolutional data stream, and input the multi-symbol detection convolutional data stream.
  • each multi-symbol detection convolution data stream includes w multi-symbol detection convolutional code words one-to-one corresponding to consecutive w unit times; for example, multi-symbol detector 1 has multiple inputs
  • the convolutional data stream of the symbol detector 1 performs multi-symbol detection processing to obtain a multi-symbol detection convolutional data stream, and inputs the multi-symbol detection convolutional data stream into the second blocker 1, and the multi-symbol detector 2 pairs the input multi-symbol
  • the convolutional data stream of the detector 2 performs multi-symbol detection processing to obtain a multi-symbol detection convolutional data stream, and inputs the multi-symbol detection convolutional data stream into the second deblocker 2, and so on, until the multi-symbol detector k+ 1.
  • Each of the k+1 second blockers is configured to divide each multi-symbol convolutional codeword in the input multi-symbol detection convolutional data stream into k+1 convolutional data blocks, Obtaining k+1 convolutional data block streams, and inputting k+1 convolutional data block streams into respective connected first data extractors; for example, the second blocker 1 is input to the second blocker 1
  • Each multi-symbol convolutional codeword in the symbol detection convolutional data stream is divided into k+1 convolutional data blocks to obtain k+1 convolutional data block streams, and k+1 convolutional data block streams are input into the first a data extractor 1
  • the second blocker 2 divides each multi-symbol convolutional codeword in the multi-symbol detection convolutional data stream input to the second blocker 2 into k+1 convolutional data blocks to obtain k +1 convolutional data block streams, and k+1 convolutional data block streams are input to the first data extractor 2, and so on,
  • Each of the k+1 first data extractors is configured to extract a target convolutional data block stream from the input k+1 convolutional data block streams, and extract the extracted target convolution
  • the data block stream is input to the second combiner; for example, the first data extractor 1 extracts the target convolutional data block stream from the k+1 convolutional data block stream input to the first data extractor 1, and convolves the target
  • the data block stream is input to the second combiner 011; the first data extractor 2 extracts the target convolutional data block stream from the k+1 convolutional data block streams input to the first data extractor 2, and the target convolution data
  • the block stream is input to the second combiner 011, and so on, up to the first data extractor k+1, at which time a total of k+1 target convolutional data block streams are input to the second combiner 011.
  • the second combiner 011 is configured to combine the input k+1 target convolutional data block streams to obtain an equalized data stream. Specifically, the second combiner 011 merges the target convolutional data block streams input by all of the first data extractor 1 to the first data extractor k+1.
  • the second combiner 011 is configured to combine the input k+1 target convolution data block streams in time sequence to obtain an equalized data stream, where the equalized data stream includes k+1. a target convolutional data block stream, each target convolutional data block stream comprising one equalized data block of each of the equalized codewords; wherein, among the g equalized codewords: and g Each of the first n*k unit time and the last n*k unit time in unit time
  • the equalization codeword corresponding to the unit time includes k+1 initial data blocks, and the data in the initial data block is 0;
  • the equalization codeword corresponding to each unit time in the intermediate unit time in g unit time includes:
  • the k+1 coded data blocks in the corresponding coded codeword are successively subjected to convolution processing and equalization processing, and the intermediate unit time is g unit time, except for the first n*k unit time and after n *k unit time outside unit time.
  • the feedback module 03 includes: k third delay devices, k third delay devices are sequentially connected in series, and the output ends of the first decoder 02 and k third delays The input of the first third delay in the timer is connected, the output of the qth third delay in the k third delays and the k+1 in the k+1 multi-symbol detector The input terminals of the -q multi-symbol detectors are connected, and the k+1-q multi-symbol detectors are connected to the outputs of the reciprocal k+1-q second delays in the k second delays Multi-symbol detector.
  • the k third delay devices include the third delay device 1 to the third delay device k, and the output of the third delay device 1 and the third delay device 2 The input terminal is connected, and the output end of the third delay device 2 is connected to the input end of the third delay device 3 (not shown in FIG.
  • the third delay device k, k third delays The first third delay in the device is the third delay 1, the output of the first decoder 02 is connected to the input of the third delay 1, and the first of the k third delays The output of the third delay (third delay 1) and the multi-symbol detector k+1, the multi-symbol detector k, and the multi-symbol detector k-1 in the k+1 multi-symbol detectors ( The input terminals of the k multi-symbol detectors are not connected in FIG.
  • the output of the second third delay device (third delay 2) of the k third delay devices is coupled with k+
  • the input terminals of k-1 multi-symbol detectors such as multi-symbol detector k+1, multi-symbol detector k, multi-symbol detector k-1 (not shown in FIG. 6) in one multi-symbol detector are connected ,And so on.
  • each of the k third delays is configured to delay the input decoded data stream by n unit times to obtain a delayed decoded data stream, and the delayed decoded data stream Inputting the connected multi-symbol detector and the next third delay; for example, the third delay 1 delays the decoded data stream input to the third delay 1 by n unit times to obtain delayed decoding.
  • Data stream, and input the delayed decoding data stream into k multi-symbol detectors such as multi-symbol detector k+1, multi-symbol detector k, multi-symbol detector k-1 (not shown in FIG.
  • the third delay device 2 delays the decoded data stream input to the third delay device 2 by n unit time, obtains a delayed decoding data stream, and inputs the delayed decoding data stream.
  • Each of the k+1 multi-symbol detectors is configured to perform multi-symbol detection processing on the input respective convolutional data streams according to the delayed decoded data streams fed back by the respective connected third delays.
  • the convolutional data stream here includes a convolutional data stream that has not been subjected to delay processing and a delayed convolutional data stream that has undergone delay processing.
  • the multi-symbol detector 2 performs multi-symbol detection processing on the convolved data stream input to the multi-symbol detector 2 according to the delayed-decoded data stream fed back by the third delayer 1, and the multi-symbol detector 3 according to the third delay
  • the delayed decoded data stream fed by the device 1 and the delayed decoded data stream fed back by the third delay 2 perform multi-symbol detection processing on the convolved data stream input to the multi-symbol detector 3, and so on.
  • the decoded data stream includes k+1 decoded data block streams, and the k+1 decoded data block streams are k+ in the equalized data stream of the first decoder 02.
  • the target convolution data block stream is obtained by decoding processing.
  • the feedback module 03 further includes: an external information calculator 031 and k second data extractors, and an input end of the external information calculator 031
  • the output of the external decoder 031 is connected to the output of the first decoder 02 and the input of the first decoder 02, and the output of the external information calculator 031 is connected to the first third delay of the k third delays.
  • Each of the k third delays is coupled to the input of the corresponding multi-symbol detector by a second data extractor.
  • the k second data extractors include the second data extractor 1 to the second data extractor k as an example, and the output of the external information calculator 031 and the input of the third delay 1 End connection, third delay 1 passes through the second data extractor 1 Connected to the input of k multi-symbol detectors such as multi-symbol detector k+1, multi-symbol detector k, multi-symbol detector k-1, and third delay 2 through second data extractor 2 and multi-symbol
  • the input terminals of k-1 multi-symbol detectors such as detector k+1, multi-symbol detector k, multi-symbol detector k-1 are connected, and so on.
  • the external information calculator 031 is configured to calculate the external information stream of the first decoder 02 according to the decoded data stream output by the first decoder 02 and the equalized data stream input to the first decoder 02, the external information stream including k+ 1 outer information block stream, k+1 outer information block stream is calculated by the external information calculator according to k+1 decoded data block streams and k+1 target convolution data block streams.
  • Each of the k third delays is configured to delay the input of each external information stream by n unit time to obtain a delayed external information stream, and input the delayed external information stream into the respective connected first a second data extractor and a next third delay, each of the delayed external information streams comprising k+1 delayed outer information block streams; for example, the third delay 1 is external to the input third delay 1
  • the information flow is delayed by n unit time, and the delayed external information flow is obtained, and the delayed external information flow is input to the second data extractor 1 and the third delay device 2, and the third delay device 2 inputs the third delay.
  • the external information flow of the device 2 is delayed by n unit time, and the delayed external information flow is obtained, and the delayed external information flow is input to the second data extractor 2 and the third delay device 3, and so on, until the third delay. k.
  • Each of the k second data extractors is configured to extract a target delayed outer block flow from the k+1 delayed outer block flows input to the respective delayed external information streams, and extracts The target delay outer block stream is input to the respective connected multi-symbol detector; for example, the second data extractor 1 inputs k+1 delay outer information blocks from the delayed outer information stream input to the second data extractor 1.
  • the second data extractor 2 extracts the target delayed outer block flow from the k+1 delayed outer block flow input to the delayed outer information stream of the second data extractor 2, and delays the target outer block flow.
  • Input k-1 multi-symbol detectors such as multi-symbol detector k+1, multi-symbol detector k, multi-symbol detector k-1, and so on.
  • Each of the k+1 multi-symbol detectors is configured to perform multi-symbol detection processing on the input respective convolutional data streams according to the target delayed outer block flow fed back by the respective second data extractor.
  • the convolutional data stream here includes a convolutional data stream that has not been subjected to delay processing and a delayed convolutional data stream that has undergone delay processing.
  • the multi-symbol detector 2 performs multi-symbol detection processing on the convolutional data stream input to the multi-symbol detector 2 according to the target delayed-outer information block stream fed back by the third delayer 1, and the multi-symbol detector 3 according to the third extension
  • the target delayed outer block stream fed back by the timer 1 and the target delayed outer block stream fed back by the third delay 2 perform multi-symbol detection processing on the convolved data stream input to the multi-symbol detector 3, and so on.
  • the values of m, n, and k may be set according to actual conditions.
  • a schematic diagram of the process of processing the data stream by the area A may be as shown in FIG. 7, and a schematic diagram of the processing procedure of the data stream of the area B of FIG. 4 may be as shown in FIG. 8 to FIG.
  • the convolution module 04 includes: a first blocker 041, a first combiner 042, and three first delays, wherein the three first delays are respectively the first delayer 1
  • the first delay device 2 and the first delay device 3 the output end of the first delay device 1 is connected to the input end of the first delay device 2, the output end of the first delay device 2 and the first delay
  • the input end of the device 3 is connected, the first blocker 041, the three first delay devices and the first combiner 042 are connected in series, and the output end of the first delay device 1 and the output end of the first delay device 2
  • the output of the first delayer 3 is connected to the input of the first combiner 042, and the input of the first delayer 1 is connected to the input of the first combiner 042.
  • the input of the first blocker 041 is also connected to the encoder 05.
  • the encoder 05 encodes the data stream of the input itself to obtain an encoded data stream, and
  • the code data stream is input to the first blocker 041, and the coded data stream includes four code code words corresponding to one-to-one consecutive ones of the unit time, the four code code words including the code code word a corresponding to the time one, and The coded codeword b corresponding to time 2, the coded codeword c corresponding to time 3, and the coded codeword d corresponding to time 4, wherein each time can be one unit time.
  • the first blocker 041 may divide each of the four coded codewords in the encoded data stream into four coded data blocks, and input one of the four coded data blocks into the first merged block.
  • the 042 code data block is input to the first delay device 1.
  • the first blocker 041 divides each of the four coded codewords into four coded data blocks that are sequentially arranged, and inputs the first coded data block of the four coded data blocks into the first block.
  • the combiner, the second to fourth encoded data blocks are input to the first delayer 1. As shown in FIG.
  • the first blocker 041 divides the coded codeword a into coded data blocks 1a, coded data blocks 2a, coded data blocks 3a, and coded data blocks 4a which are sequentially arranged, and blocks the coded data block 1a (1st)
  • the first codec block 2) is input to the first combiner 042, and the coded data block 2a, the coded data block 3a, and the coded data block 4a (the second to fourth coded data blocks) are input to the first delayer 1;
  • the blocker 041 divides the coded codeword b into the coded data block 1b, the coded data block 2b, the coded data block 3b, and the coded data block 4b which are sequentially arranged, and inputs the coded data block 1b (the first coded codeword block) into the first block.
  • the combiner 042 inputs the encoded data block 2b, the encoded data block 3b, and the encoded data block 4b (the second to fourth encoded data blocks) into the first delayer 1; the first blocker 041 divides the encoded codeword c into The encoded data block 1c, the encoded data block 2c, the encoded data block 3c, and the encoded data block 4c are sequentially arranged, and the encoded data block 1c (the first encoded codeword block) is input to the first combiner 042, and the encoded data block 2c is obtained.
  • the coded data block 3c and the coded data block 4c are input to the first delayer 1; the first point
  • the blocker 041 divides the coded codeword d into the coded data block 1d, the coded data block 2d, the coded data block 3d, and the coded data block 4d which are sequentially arranged, and inputs the coded data block 1d (the first coded codeword block) into the first block.
  • the combiner 042 inputs the encoded data block 2d, the encoded data block 3d, and the encoded data block 4d (the second to fourth encoded data blocks) to the first delayer 1.
  • Each of the three first delays delays the input of the respective p coded data blocks by one unit time (that is, one time), and obtains p delay coded data blocks, and One delay coded data block of the p delayed coded data blocks is input to the first combiner 042, and the p-1 delayed coded data blocks are input to the next first delay device respectively connected, 1 ⁇ p ⁇ 3 And p is an integer.
  • the p coded data blocks are sequentially arranged, and each of the three first delays delays the input of the respective p code blocks of the data by one unit time, and obtains p delays.
  • the first delayer 1 delays the sequentially arranged coded data block 2a, coded data block 3a, and coded data block 4a (3 coded data blocks) input to the first delayer 1.
  • the delayed coded data block 2a, the delayed coded data block 3a, and the delayed coded data block 4a are sequentially arranged in one unit time, and the delayed coded data block 2a (the first delayed coded data block) is input into the first block.
  • the combiner 042 inputs the delayed coded data block 3a and the delayed coded data block 4a (the second to third delayed coded data blocks) into the first delay device 2; the first delay device 1 inputs the first delay
  • the coded data block 2b, the coded data block 3b, and the coded data block 4b (3 coded data blocks) of the sequencer 1 are delayed by 1 unit time to obtain the delayed coded data block 2b, which is sequentially arranged, and the delayed coded data block is delayed.
  • the delay coded data block 2b (the first delay coded data block) is input to the first combiner 042, and the delay coded data block 3b and the delayed coded data block 4b (the 2 to 3rd delayed coded data block) input to the first delay device 2; the first delay device 1 sequentially arranges the input first delay device 1
  • the coded data block 2c, the coded data block 3c, and the coded data block 4c (three coded data blocks) are delayed by one unit time to obtain the delayed coded data block 2c, the delayed coded data block 3c, and the delayed coded data which are sequentially arranged.
  • Block 4c, and delay coded data block 2c (first 1 delay coded data block) is input to the first combiner 042, the delay coded data block 3c and the delayed coded data block 4c (the second to third delay coded data blocks) are input to the first delay 2;
  • the first delayer 1 delays the coded data block 2d, the coded data block 3d and the coded data block 4d (3 coded data blocks) input to the first delayer 1 by one unit time to obtain a sequence of delays.
  • Time coded data block 2d, delayed coded data block 3d and delayed coded data block 4d, and delayed coded data block 2d (first delayed coded data block) is input to the first combiner 042, and the delayed coded data is The block 3d and the delayed coded data block 4d (the 2nd to 3rd delayed coded data blocks) are input to the first delayer 2.
  • the first delay device 2 pairs the coded data block 3a and the coded data block 4a (the two coded data blocks) which are sequentially arranged into the first delay device 2, and the two coded data blocks are delayed by the first delay device 1
  • the delayed coded data block is delayed by 1 unit time to obtain the delayed coded data block 3a and the delayed coded data block 4a, and the delayed coded data block 3a (the first delayed coded data block)
  • the first combiner 042 inputting the delayed encoded data block 4a (the second delayed encoded data block) into the first delay device 3; the first delay device 2 is sequentially arranged to input the first delay device 2
  • the coded data block 3b and the coded data block 4b (two coded data blocks, which are delayed coded data blocks after being delayed by the first delayer 1) are sequentially arranged for one unit time.
  • Block 3c and delay coded data block 4c, and delay coded data block 3c (first delayed coded data block) is input to first combiner 042, and delayed coded data block 4c (2nd delayed coded data) Block) inputting the first delayer 3; the first delayer 2 pairs the coded data block 3d and the coded data block 4d (the two coded data blocks, which are sequentially arranged for inputting the first delayer 2, the two coded data blocks Is the delay coded data block after the delay of the first delay device 1) delaying one unit time to obtain the delayed coded data block 3d and the delayed coded data block 4d, and delaying the coded data block 3d
  • the (first delayed coded data block) is input to the first combiner 042, and the delayed coded data block 4d (the second delayed coded data block) is input to the first delayer 3.
  • the first delay device 3 delays the encoded data block 4a input to the first delay device 3 (the delayed encoded data block after the delay of the first delay device 1 and the first delay device 2) by one unit time. Obtaining the delayed coded data block 4a, and inputting the delayed coded data block 4a into the first combiner 042; the first delayer 3 pairs the coded data block 4b input to the first delayer 3 (via the first delayer 1) And delaying the encoded data block after the delay of the first delay device 2) delaying the encoded data block 4b by 1 unit time, and inputting the delayed encoded data block 4b into the first combiner 042; the first delay The device 3 delays the encoding of the encoded data block 4c input to the first delay device 3 (the delayed encoded data block after the delay of the first delay device 1 and the first delay device 2) by one unit time.
  • the data block 4c, and the delay coded data block 4c is input to the first combiner 042; the first delayer 3 pairs the coded data block 4d input to the first delayer 3 (via the first delayer 1 and the first delay)
  • the delay coded data block after the delay of the timer 2 is delayed by 1 unit time to obtain the delayed coded data block 4d, and the delayed coded data block 4d is input to the first combiner 042.
  • 3 convolutional codewords corresponding to the first 3 unit time out of 7 unit time include 3 convolutional codeword groups, each convolutional codeword group including 1 convolution a codeword, each convolutional codeword comprising i first convolutional data blocks and 4-i second convolutional data blocks, wherein each of the first convolutional data blocks of the first convolutional data blocks Is one of the i coded code words in the i coded codewords corresponding to the first i unit time of the 4 unit time, i first The convolutional data blocks are one-to-one corresponding to i coded codewords, and the 4-i second convolutional data blocks are initial data blocks, and the data in the initial data block is 0, 4 ⁇ i > 0, and i is an integer.
  • the 3 convolutional codeword corresponding to the last 3 unit time of 7 unit time includes 3 convolutional codeword groups, each convolutional codeword group including 1 convolutional codeword, and each convolutional codeword includes 4-j first convolutional data blocks and j second convolutional data blocks, wherein each of the first convolutional data blocks of the 4-j first convolutional data blocks is in 4 unit time
  • One of the 4-j coded codewords of the j codewords corresponding to the last j unit time, and the 4-j first convolutional data blocks are one-to-one correspondingly from the 4-j codewords
  • the j second encoded data blocks are initial data blocks, and the data in the initial data block is 0, 4 ⁇ j > 0, and j is an integer.
  • the convolutional codeword corresponding to each unit time in the intermediate unit time includes four first convolutional data blocks, and each of the four first convolutional data blocks is in the four encoded codewords.
  • One of the four encoded codewords, the four first convolutional data blocks are one-to-one corresponding from the four encoded codewords, and the intermediate unit time is 7 unit time, except for the first three unit time and after Unit time outside 3 unit hours.
  • the convolutional data stream includes a convolutional codeword A, a convolutional codeword B, a convolutional codeword C, a convolutional codeword D, a convolutional codeword E, a convolutional codeword F, and
  • the seven convolutional codewords of the convolutional codeword G correspond to the first three unit time (i.e., time 1, time 2, and time 3) of the seven unit time periods among the seven convolutional code words.
  • the 3 convolutional codewords include convolutional codewords 1 (not shown in Figure 7), convolutional codewords 2 (not shown in Figure 7), and convolutional codewords 3 (not shown in Figure 7).
  • the three convolutional codeword groups the convolutional codeword group 1 comprises a convolutional codeword A
  • the convolutional codeword group 2 comprises a convolutional codeword B
  • the convolutional codeword group 3 comprises a convolutional codeword C
  • the 1st convolutional data block is a convolutional data block 1a
  • the 3 convolutional codeword corresponding to the last 3 unit times (i.e., time 5, time 6 and time 7) of 7 unit times includes 3 convolutional codeword groups including convolutional codeword group 1 (Fig. 7
  • the three convolutional codeword groups, convolutional codeword group 1 are not shown in the convolutional codeword group 2 (not shown in FIG. 7) and the convolutional codeword group 3 (not shown in FIG. 7).
  • convolutional codeword set 2 includes convolutional codeword F
  • convolutional codeword set 3 includes convolutional codeword G
  • the convolutional codeword corresponding to the intermediate unit time is a convolutional codeword D
  • the convolutional codeword D includes four first convolutional data blocks, and the four first convolutional data blocks are respectively volumes.
  • the product data block 1d, the convolution data block 2c, the convolution data block 3b, and the convolution data block 4a is a convolutional codeword D
  • the convolutional codeword D includes four first convolutional data blocks, and the four first convolutional data blocks are respectively volumes.
  • the equalization module 01 includes: a second combiner 011, three second delays, four multi-symbol detectors, four second blockers, and four first data extractors.
  • the three second delay devices are a second delay device 1, a second delay device 2 and a second delay device 3, respectively, and the four multi-symbol detectors are respectively a multi-symbol detector 1 and a multi-symbol detector. 2.
  • Multi-symbol detector 3 and multi-symbol detector 4, 4 second blockers are second blocker 1, second blocker 2, second blocker 3 and second blocker 4, respectively , the four first data extractors are the first data extractor 1, respectively a data extractor 2, a first data extractor 3 and a first data extractor 4, the output of the multi-symbol detector 1 is connected to the input of the second blocker 1, and the output of the multi-symbol detector 2
  • the input of the second blocker 2 is connected, the output of the multi-symbol detector 3 is connected to the input of the second blocker 3, and the output of the multi-symbol detector 4 is connected to the input of the second blocker 4.
  • the output of the second blocker 1 is connected to the input of the first data extractor 1, the output of the second blocker 2 is connected to the input of the first data extractor 2, and the output of the second blocker 3
  • the end is connected to the input end of the first data extractor 3
  • the output end of the second blocker 4 is connected to the input end of the first data extractor 4, the output end of the first data extractor 1 and the first data extractor 2
  • the output end, the output end of the first data extractor 3 and the output end of the first data extractor 4 are respectively connected to the input end of the second combiner 011, and the output end of the second delay device 1 and the second delay respectively
  • the input end of the second delay device 2 is connected to the input end of the multi-symbol detector 2, and the output end of the second delay device 2 is respectively connected to the second extension
  • the input of the device 3 is connected to the input of the multi-symbol detector 3, the output of the second delay 3 is connected to the input of the multi-symbol detector 4, the input
  • the convolution module 04 inputs the convolved data stream into the second delayer 1 and the multi-symbol detector 1, respectively, the convolutional data stream including the convolutional codeword A corresponding to time 1, and the time 2 corresponding convolutional codeword B, convolutional codeword C corresponding to time 3, convolutional codeword D corresponding to time 4, convolutional codeword E corresponding to time 5, convolutional code corresponding to time 6 Word F and convolutional codeword G corresponding to time 7.
  • Each of the three second delays delays the input convolution data stream by one unit time to obtain a delayed convolution data stream, and inputs the delayed convolution data streams into respective The connected multi-symbol detector and the next second delay, each delayed convolution data stream comprising seven delayed convolutional codewords one-to-one corresponding to successive seven unit times.
  • the second delayer 1 delays the convolutional data stream input to the second delayer 1 by one unit time to obtain a delayed convolutional data stream, and convolves the delay.
  • the data stream is respectively input to the multi-symbol detector 2 and the second delay 2; the second delay 2 delays the delayed convolution data stream input to the second delay 2 by 1 unit time, and obtains a delay of 2 Deferred convolution data stream per unit time, and input the delayed convolution data stream into the multi-symbol detector 3 and the second delay device 3 respectively; the delay of the second delay device 3 to the input second delay device 3
  • the time convolution data stream is delayed by one unit time, and a delayed convolution data stream with a delay of 3 unit time is obtained, and the delayed convolution data stream is input to the multi-symbol detector 4.
  • Each of the four multi-symbol detectors performs multi-symbol detection processing on the input convolutional data streams to obtain a multi-symbol detection convolutional data stream, and inputs the multi-symbol detection convolutional data stream into respective connections.
  • a second blocker each multi-symbol detection convolution data stream comprising seven multi-symbol detection convolutional code words one-to-one corresponding to successive seven unit times.
  • the multi-symbol detector 1 performs multi-symbol detection processing on the convolutional data stream input to the multi-symbol detector 1, obtains a multi-symbol detection convolutional data stream, and detects a convolutional data stream with multiple symbols.
  • the second blocker 1 is input, and the multi-symbol detection convolution data stream includes a multi-symbol detection convolutional codeword A1 corresponding to time 1 and a multi-symbol detection convolutional codeword B1 corresponding to time 2, corresponding to time 3 Multi-symbol detection convolutional codeword C1, multi-symbol detection convolutional codeword D1 corresponding to time 4, multi-symbol detection convolutional codeword E1 corresponding to time 5, multi-symbol detection convolutional codeword F1 corresponding to time 6 And a multi-symbol detection convolutional codeword G1 corresponding to time 7; the multi-symbol detector 2 performs multi-symbol detection processing on the convolutional data stream (delayed convolutional data stream) input to the multi-symbol detector 2 to obtain multi-symbol detection Convolving the data stream and inputting the multi-symbol detection convolution data stream to the second blocker 2, the multi-symbol
  • Each of the four second blockers divides each multi-symbol convolutional codeword in the respective multi-symbol detection convolutional data stream into four convolutional data blocks, resulting in four convolutions.
  • the data block stream is streamed and the four convolutional data block streams are input to the first data extractor to which they are connected.
  • the second blocker 1 divides the multi-symbol convolutional codeword A1 input into the multi-symbol detection convolutional data stream of the second blocker 1 into convolutional data blocks 1a1 arranged in order.
  • the symbol convolutional codeword B1 is divided into four convolutional data blocks of convolutional data block 1b1, convolutional data block 2a1, convolutional data block 0, and convolutional data block 0 which are sequentially arranged, and the second blocker 1 will input the first
  • the multi-symbol convolutional codeword C1 in the multi-symbol detection convolutional data stream of the second blocker 1 is divided into a convolutional data block 1c1, a convolutional data block 2b1, a convolutional data block 3a1, and a convolutional data block 0 which are sequentially arranged.
  • the second blocker 1 divides the multi-symbol convolutional codeword D1 input into the multi-symbol detection convolutional data stream of the second blocker 1 into convolutional data blocks 1d1, convolutions arranged in sequence 4 convolutional data blocks of data block 2c1, convolutional data block 3b1 and convolutional data block 4a1, and second blocker 1 will input multi-symbol detection volume of second blocker 1
  • the multi-symbol convolutional codeword E1 in the data stream is divided into a convolutional data block 0, a convolutional data block 2d1, a convolutional data block 3c1, and a convolutional data block 4b1 which are sequentially arranged, and the second blocker 1 inputs the second sub-portion
  • the multi-symbol convolutional codeword F1 in the multi-symbol detection convolutional data stream of the blocker 1 is divided into a convolutional data block 0, a convolutional data block 0, a convolutional data block 3d
  • convolutional data block 4d1 after that, the second blocker 1 can obtain four convolutional data block streams, which are respectively: convolutional data block 1a1, convolution arranged in order of time.
  • the convolutional data block stream of the product block 0 includes convolutional data block 0, convolutional data block 0, convolutional data block 3a1, convolutional data block 3b1, convolutional data block 3c1, and convolutional data arranged in order of time.
  • the block 4b1, the convolutional data block 4c1, and the convolutional data block 4d1 are convoluted data block streams, after which the second blocker 1 can input the four convolutional data block streams into the first data extractor 1.
  • the blocking process of the second blocker 2, the second blocker 3 and the second blocker 4 can refer to the second blocker 1 The block process is not repeated here.
  • Each of the first data extractors of the four first data extractors extracts a target convolutional data block stream from the input four convolutional data block streams, and inputs the extracted target convolutional data block stream into the first Two combiner 011.
  • the first data extractor 1 extracts, from the four convolutional data block streams input to the first data extractor 1, the convolutional data block 0 arranged in order from time 1 to time 7.
  • a convolutional data block 0, a convolutional data block 0, a convolutional data block 4a1, a convolutional data block 4b1, a convolutional data block 4c1, and a convolutional data block 4d1 are convoluted data block streams as a target convolutional data block stream, And inputting the target convolutional data block stream into the second combiner 011; the first data extractor 2 extracts from the four convolutional data block streams input to the first data extractor 2, including in order from time 2 to time 8
  • the convolutional data block 0, the convolutional data block 0, the convolutional data block 3a1, the convolutional data block 3b1, the convolutional data block 3c1, the convolutional data block 3d1, and the convolutional data block 0 convolutional data block stream are arranged as The target convolution data block stream, and the target convolutional data block stream is input to the second combiner 011; the first data extractor 3 is extracted from the four convolutional data block streams input to the first data extractor 3, including Convolution
  • the convolutional data block 2c1, the convolutional data block 2d1, the convolutional data block 0, and the convolutional data block 0 convolutional data block stream are used as the target convolutional data block stream, and the target convolutional data block stream is input into the The second combiner 011;
  • the first data extractor 4 extracts from the four convolutional data block streams input to the first data extractor 4, and includes convolutional data blocks 1a1 and convolutional data arranged in order from time 4 to time 10 a block 1b1, a convolutional data block 1c1, a convolutional data block 1d1, a convolutional data block 0, a convolutional data block 0, and a convolutional data block 0 convolutional data block stream are used as a target convolutional data block stream, and the target is The convolutional data block stream is input to the second combiner 011.
  • the second combiner 011 combines the four target convolutional data block streams input to itself to obtain an equalized data stream.
  • the second combiner 011 combines the four target convolutional data block streams of the input itself in time sequence to obtain an equalized data stream, and the equalized data stream includes four target convolutional data block streams, each target convolution.
  • the equalization codeword corresponding to each of the first 3 unit time and the last 3 unit time in 10 unit time includes 4 initial data blocks, and the data in the initial data block is 0;
  • the equalization codeword corresponding to each unit time in the intermediate unit time of the 10 unit time includes: an equalization data block obtained by sequentially performing convolution processing and equalization processing on the four encoded data blocks in the corresponding encoded codeword,
  • the intermediate unit time is 10 unit time, except for the first 3 unit time and the last 3 unit time. For example, as shown in FIG.
  • the second combiner 011 combines its own four target convolutional data block streams to obtain an equalized data stream, and each target convolutional data block stream includes each of 10 equalized codewords.
  • One equalized data block in the equalized codeword wherein, among the 10 equalized codewords, with time 1, time 2, and time 3 (time 1, time 2, and time 3 are the first three unit time), time 8,
  • the equalization codeword corresponding to each time instant in time 9 and time 10 (time 8, time 9 and time 10 is the last 3 unit time) includes 4 initial data blocks, and the data in the initial data block is 0, and
  • the equalization codeword corresponding to time 4 includes an equalization data block 1a1, an equalization data block 2a1, an equalization data block 3a1, and an equalization data block 4a1.
  • the equalization data block 1a1, the equalization data block 2a1, the equalization data block 3a1, and the equalization data block 4a1 are The coded data block 1a, the coded data block 2a, the coded data block 3a, and the coded data block 4a are respectively subjected to convolution processing and equalization processing, and the equalized codeword corresponding to the time 5 includes the equalized data block 1b1, the equalized data block 2b1, and the equalized data block.
  • the weight data block 1b1, the equalization data block 2b1, the equalization data block 3b1, and the equalization data block 4b1 are obtained by performing convolution processing and equalization processing on the coded data block 1b, the coded data block 2b, the coded data block 3b, and the coded data block 4b, respectively.
  • the equalization codeword corresponding to the time 6 includes an equalization data block 1c1, an equalization data block 2c1, an equalization data block 3c1, and an equalization data block 4c1, the equalization data block 1c1, the equalization data block 2c1, the equalization data block 3c1, and the equalization data block 4c1.
  • the coded data block 2c, the coded data block 3c, and the coded data block 4c are respectively subjected to convolution processing and equalization processing, and the equalized codeword corresponding to the time 7 includes the equalization data block 1d1, the equalization data block 2d1, the equalization data block 3d1, and the equalization.
  • the data block 4d1, the equalized data block 1d1, the equalized data block 2d1, the equalized data block 3d1, and the equalized data block 4d1 are respectively subjected to convolution processing of the encoded data block 1d, the encoded data block 2d, the encoded data block 3d, and the encoded data block 4d. And equalization processing.
  • the feedback module 03 includes: an external information calculator 031, three third delay devices, and three second data extractors, and the third third delay devices are respectively the third delay device 1.
  • the third delay device 2 and the third delay device 3, the three second data extractors are the second data extractor 1, the second data extractor 2 and the second data extractor 3, respectively, the external information calculator 031
  • the input end is respectively connected with the output end of the first decoder 02 and the input end of the first decoder 02, and the output end of the external information calculator 031 is connected to the input end of the third delay device 1, and the third delay device 1 is connected.
  • the output ends are respectively connected to the input end of the third delay device 2 and the input end of the second data extractor 1, and the output end of the third delay device 2 and the input end of the third delay device 3 and the second data respectively
  • the input end of the extractor 2 is connected
  • the output end of the third delay device 3 is connected to the input end of the second data extractor 3
  • the output end of the second data extractor 1 is respectively connected to the input end of the multi-symbol detector 4
  • the input of the symbol detector 3 is connected to the input of the multi-symbol detector 2
  • the output of the second data extractor 2 is respectively detected by multi-symbol
  • An input terminal and an input terminal 4 of the multi-symbol detector 3 is connected to an input terminal of the second output data extractor 3 and the multiple symbol detector 4 is connected.
  • the external information calculator 031 calculates the external information stream of the first decoder 02 based on the decoded data stream output by the first decoder 02 and the equalized data stream input to the first decoder 02, and the external information stream includes four external information.
  • the block stream and the four outer block streams are calculated by the external information calculator based on the four target convolution block streams of the four decoded block streams and the equalized data stream.
  • the external information calculator 031 may be a subtractor, and the external information calculator 031 may subtract the decoded data stream from the equalized data stream to obtain an external information stream.
  • the external information calculator 031 subtracts each codeword block in the decoded data stream from each codeword block in the equalized data stream to obtain an outer information block, thereby obtaining an outer information block stream, and finally obtaining the outer information block. flow.
  • the external information stream includes four outer information block streams, and the four outer information block streams are respectively: an outer information block 0, an outer information block 0, an outer information block 0, and an outer block arranged in chronological order.
  • each of the three third delays delays the input of the external information stream by one unit time, obtains the delayed external information stream, and inputs the delayed external information stream into the second connected respective stream.
  • the data extractor and the next third delay, each of the delayed external information streams includes four delayed outer information block streams.
  • the third delayer 1 delays the external information flow input to the third delayer 1 by one unit time to obtain a delayed external information stream, and inputs the delayed external information stream into the second.
  • the data extractor 1 and the third delay device 2 delays the external information flow input to the third delay device 2 by one unit time to obtain the delayed external information flow, and delays the external information flow.
  • the third delay device 3 delays the external information flow input to the third delay device 3 by one unit time to obtain the delayed external information flow, and delays The external information stream is input to the second data extractor 3.
  • Each of the three second data extractors extracts the target delayed outer block flow from the four delayed outer block flows that input the respective delayed outer information streams, and extracts the extracted target The delayed outer block stream is input to the respective connected multi-symbol detectors.
  • the target delayed outer block flow from the four delayed outer block flows that input the respective delayed outer information streams, and extracts the extracted target The delayed outer block stream is input to the respective connected multi-symbol detectors.
  • the second data extractor 1 extracts the target delayed outer block flow from the four delayed outer block flows input to the delayed outer stream of the second data extractor 1, and
  • the target delay outer block flow is input to the multi-symbol detector 4, the multi-symbol detector 3 and the multi-symbol detector 2, and the target-delayed outer block flow is: including the delays arranged in order from time 2 to time 11 Information block 0, delay outer information block 0, delay outer information block 0, delay outer information block 4, delay outer information block 4a2, delay outer information block 4b2, delay outer information block 4c2, delay outer information block 4d2, delay information Block 0, the delayed outer information block 0 and the delayed outer information block stream of the delayed outer information block 0;
  • the second data extractor 2 is outside the 4 delays of the delayed external information flow input to the second data extractor 2 Extracting the target delayed outer block flow in the information block stream, and inputting the target delayed outer block flow into the multi-symbol detector 4 and the multi-symbol detector 3, the target delayed outer block flow is: including according to time
  • the multi-symbol detector 4 is input, and the target delay outer block flow is: including the delayed outer information block 0, the delayed outer information block 0, the delayed outer information block 0, and the delay according to the time sequence from the time 4 to the time 13 Delay of time block 2a2, time delay outer information block 2b2, delay outer information block 2c2, delay outer information block 2d2, delay outer information block 0, delay outer information block 0 and delay outer information block 0 Outer block flow.
  • Each of the four multi-symbol detectors performs multi-symbol detection processing on the input respective convolutional data streams according to the target delayed outer block flow fed back by the respective second data extractor.
  • the multi-symbol detector 2 performs multi-symbol detection processing on the convolutional data stream input to the multi-symbol detector 2 according to the target delayed-outer information block stream fed back by the second data extractor 1, and the multi-symbol detector 3 according to the second
  • the target delay outer block flow fed back by the data extractor 1 and the target delayed outer block flow fed back by the second data extractor 2 perform multi-symbol detection processing on the convolved data stream input to the multi-symbol detector 3;
  • the detector 4 is based on the target delayed outer block flow fed back by the second data extractor 1, the target delayed outer block flow fed back by the second data extractor 2, and the target delayed outer block fed back by the second data extractor 3.
  • the stream performs multi-symbol detection processing on the convo
  • the multi-symbol detector can perform multi-symbol detection based on the maximum likelihood sequence detection (English: Maimum-likelihood Sequence Detection; MLSD) technology, and the main idea of the multi-symbol detector can be
  • the process of transmitting information in the channel is regarded as a state transition process, and the information at any time corresponds to a state.
  • the state of the channel is modeled as four states, and the four states are states respectively.
  • transmitting data causes the state of the channel to shift, for example, the initial state (initial state) of the channel is -1-1, data 11 makes The channel transitions from state-1-1 to state +1+1, and data 01 causes the channel to transition from state +1+1 to state +1-1, and so on. Interference during data transmission causes the state of the channel to be transmitted incorrectly.
  • the main function of the multi-symbol detector is to correct the state of the error during the channel transmission, thereby restoring the correct data.
  • FIG. 12 illustrates a working principle diagram of a multi-symbol detector provided by an embodiment of the present application. Referring to FIG.
  • the working principle of the multi-symbol detector is explained in the case of 4, in the first case, receiving bits.
  • the received data bits are all bit-unknown bits. It is assumed that the bit error rate (Bit Error Rate; BER for short) of the multi-symbol detection process is BER0.
  • the received bits are assumed. There is one known bit in every four received bits (the known bit is the correct bit, which may be the bit fed back by the feedback module), and the multi-symbol detector at this time
  • the bit error rate for performing multi-symbol detection processing is BER1.
  • the bit error rate of the multi-symbol detector for multi-symbol detection processing is BER3, then BER0>BER1>BER2 > BER3. Therefore, in the embodiment of the present application, the multi-symbol detector performs multi-symbol detection according to the fed back data stream, which can reduce the bit error rate of multi-symbol detection.
  • the final error rate of the signal transmission system may be sum(BER0 ⁇ BER(N-1))/N, which is better than BER0, sum represents summation, N represents the number of feedbacks, BER(N-1 ) indicates the bit error rate of multi-symbol detection based on the Nth feedback.
  • the signal transmission system may include a sender device and a receiver device, and the encoder 05, the convolution module 04, and the DAC-07 may be in the processor of the sender device.
  • the functional unit, the coherent receiver 08, the ADC-09, the equalization module 01, the feedback module 03, the first decoder 02, the second decoder 06 and the decider 10 can all be functions in the processor of the receiving device unit.
  • the equalization module includes at least two multi-symbol detectors
  • at least two multi-symbol detectors perform multi-symbol detection processing on the convolved data stream according to the feedback data stream, and The feedback data stream is determined according to the decoded data stream. Therefore, the signal can be feedback-transmitted between the first decoder and the at least two multi-symbol detectors without setting multiple decoders and decoding
  • the device and the multi-symbol detector perform multiple iterations to solve the problem of high complexity of the transmitted signal, which helps to reduce the complexity of the transmitted signal.
  • the signal transmission system provided by the embodiment of the present invention achieves the auxiliary equalization of the multi-symbol detector through multi-loop feedback, reduces the bit error rate with limited complexity, effectively reduces the system complexity, and improves the system performance.
  • the embodiment of the present application further provides a signal transmission method, which can be used in the signal transmission system shown in FIG. 3 or FIG. 4, where the signal transmission system includes: an equalization module, a first decoder, and a feedback module, and the equalization The module is coupled to the first decoder, the equalization module includes at least two multi-symbol detectors, and the feedback module is respectively coupled to the first decoder and the at least two multi-symbol detectors, the signal transmission method comprising:
  • Step S1 The equalization module performs equalization processing on the convolved data stream to obtain an equalized data stream, wherein each multi-symbol detection in at least two multi-symbol detectors is performed during the equalization processing of the convolutional data stream by the equalization module.
  • the device performs multi-symbol detection processing on input respective convolutional data streams.
  • Step S2 The first decoder decodes the equalized data stream to obtain a decoded data stream.
  • Step S3 The feedback module determines the feedback data stream according to the decoded data stream, and feeds the feedback data stream to at least two multi-symbol detectors of the equalization module.
  • Step S4 The equalization module performs equalization processing on the convolved data stream according to the feedback data stream, wherein each multi-symbol detector of the at least two multi-symbol detectors is performed during the equalization processing of the convolution data stream by the equalization module.
  • the multi-symbol detection process is performed on the input respective convolution data streams according to the feedback data stream fed back by the feedback module.
  • the signal transmission system further includes: a convolution module, a convolution module, an equalization module, and a first decoder are sequentially connected, and the signal transmission method further includes:
  • the convolution module convolves the input encoded data stream to obtain a convolved data stream
  • the encoded data stream includes m coded codewords corresponding one-to-one with consecutive m unit times, and each of the m coded codewords includes k+1 coded data blocks, m>1, k>0, And m and k are both integers;
  • g equalized codewords m equalized codewords corresponding to consecutive m unit times are in one-to-one correspondence with m coded codewords, and each of the m equalized codewords includes corresponding codewords All of the encoded data blocks are sequentially subjected to convolution processing and equalization processing to obtain equalized data blocks;
  • the decoded data stream includes g decoding codewords one-to-one corresponding to consecutive g unit times, and the g decoding codewords are obtained by decoding g equalized codewords, and in the g decoding codewords Each decoded codeword includes k+1 decoded data blocks.
  • the convolution module comprises: a first blocker, a first combiner and k first delays, wherein the k first delay devices are connected in series, and the first blocker and the k first delays The timing device and the first combiner are connected in series, and the output ends of each of the k first delay devices are respectively connected to the input ends of the first combiner, and the first one of the k first delay devices The input end of the first delay is connected to the input of the first combiner,
  • the convolution module convolves the input encoded data stream to obtain a convolved data stream, including:
  • the first blocker divides each of the m coded codewords into k+1 coded data blocks, and inputs one of the k+1 coded data blocks into the first combiner, k
  • the encoded data block is input to the first first delay device;
  • Each of the k first delays delays the input of the respective p coded data blocks by n unit times to obtain p delay coded data blocks, and p delay coded data blocks
  • One of the delayed coded data blocks is input to the first combiner, and the p-1 delayed coded data blocks are input to the next first delay connected to each other, 1 ⁇ p ⁇ k, and p is an integer;
  • the first combiner combines the coded data blocks corresponding to the m coded codewords input to itself to obtain a convolved data stream.
  • the first combiner combines the coded data blocks corresponding to the m codewords of the input code to obtain a convolved data stream, including: the first combiner corresponds to the m coded codewords input to itself according to the time sequence.
  • the encoded data blocks are combined to obtain a convolved data stream, and the convolutional data stream includes w convolutional code words; in w convolutional code words:
  • the n*k convolutional codeword corresponding to the first n*k unit times in w unit time includes k convolutional codeword groups, each convolutional codeword group including n convolutional codewords, each volume
  • the product codeword includes i first convolutional data blocks and k+1-i second convolutional data blocks, wherein each of the first convolutional data blocks is m and m
  • the i first convolutional data blocks are one-to-one corresponding from the i codes a codeword
  • k+1-i second convolutional data blocks are initial data blocks, k ⁇ i>0, and i is an integer;
  • the n*k convolutional codeword corresponding to the last n*k unit time in w unit time includes k convolutional codeword groups, each convolutional codeword group including n convolutional codewords, each volume
  • the product codeword includes k+1-j first convolutional data blocks and j second convolutional data blocks, wherein each of the first convolutional data blocks of k+1-j first convolutional data blocks Is one of the k+1-j coded code words in the n*j coded codewords corresponding to the last n*j unit code times in m unit time, k+1-j first
  • the convolutional data blocks are one-to-one corresponding to k+1-j encoded codewords, and j second encoded data blocks are initial data blocks, k ⁇ j>0, and j is an integer;
  • the convolutional codeword corresponding to each unit time in the intermediate unit time includes k+1 first convolutional data blocks, and each of the first convolutional data blocks in the k+1 first convolutional data blocks is m
  • One of the k+1 coded codewords in the codeword word, k+1 first convolutional data blocks are one-to-one corresponding to the k+1 codewords, and the intermediate unit time is w unit time In addition to the unit time before the first n*k unit time and the last n*k unit time.
  • the equalization module includes: a second combiner, k second delays, k+1 multiple symbol detectors, and k+1
  • the second blocker and the k+1 first data extractors, the output ends of the k+1 multi-symbol detectors are connected one-to-one with the input ends of the k+1 second blockers, k+1 first
  • the output of the second blocker is connected in one-to-one correspondence with the input ends of the k+1 first data extractors, and the output of each of the first data extractors of the k+1 first data extractors is merged with the second
  • the input ends of the devices are connected, the k second delay devices are connected in series, and the output ends of the k second delay devices correspond one-to-one with the input ends of the k multi-symbol detectors in the k+1 multi-symbol detectors.
  • the input of the first second delayer of the k second delays is connected to the input of the multi-symbol detector of the k+1 multi-symbol detectors other than the k multi-symbol detectors, first The input of the second delay is also connected to the convolution module.
  • the signal transmission method further includes: the convolution module respectively inputting the convolved data stream into the first second delay device, and the multi-symbol detector connected to the input end of the first second delay device; and the step S4 includes:
  • Each of the k second delays delays the input convolution data stream by n unit time to obtain a delayed convolution data stream, and inputs the delayed convolution data streams into respective a connected multi-symbol detector and a next second delay, each delayed convolution data stream comprising w delay convolutional code words one-to-one corresponding to consecutive w unit times;
  • Each of the k+1 multi-symbol detectors performs multi-symbol detection processing on the input convolutional data streams to obtain a multi-symbol detection convolutional data stream, and inputs the multi-symbol detection convolutional data stream into respective a connected second blocker, each multi-symbol detection convolution data stream comprising w multi-symbol detection convolutional code words one-to-one corresponding to consecutive w unit times;
  • Each of the k+1 second blockers divides each multi-symbol convolutional codeword in the respective multi-symbol detection convolutional data stream into k+1 convolutional data blocks, k+1 convolutional data block streams, and k+1 convolutional data block streams are input to the respective first data extractors connected;
  • Each of the k+1 first data extractors extracts a target convolutional data block stream from the input k+1 convolutional data block streams, and extracts the extracted target convolution data
  • the block stream is input to the second combiner;
  • the second combiner combines the k+1 target convolutional data block streams input to itself to obtain an equalized data stream.
  • the second combiner combines the input k+1 target convolutional data block streams to obtain an equalized data stream, including: the second combiner chronologically inputs the k+1 target convolutions of the input itself.
  • the data block stream is combined to obtain an equalized data stream, and the equalized data stream includes k+1 target convolutional data block streams, and each target convolutional data block stream includes 1 in each of the equalized code words of the g equalized code words.
  • the equalization codeword corresponding to each of the first n*k unit time and the last n*k unit time in g unit time includes k+1 initial data blocks;
  • the equalization codeword corresponding to each unit time in the intermediate unit time in g unit time includes: equalization obtained by sequentially performing convolution processing and equalization processing on k+1 coded data blocks in the corresponding coded codeword
  • the data block, the intermediate unit time is g unit time, except the unit time of the previous n*k unit time and the last n*k unit time.
  • the feedback module comprises: k third delay devices, wherein the k third delay devices are connected in series, and the first third delay of the output of the first decoder and the k third delay devices The input of the device is connected, the output of the qth third delayer of the k third delays and the input of the k+1-q multi-symbol detectors of the k+1 multi-symbol detectors Connected, k+1-q multi-symbol detectors are multi-symbol detectors connected to the outputs of the reciprocal k+1-q second delays in the k second delays,
  • Step S3 includes: each third delayer of the k third delays delays the input decoded data stream by n unit time, obtains a delayed decoded data stream, and decodes the delayed data.
  • the stream inputs the respective connected multi-symbol detector and the next third delay, and each of the k+1 multi-symbol detectors is used for the third delay according to the respective connection
  • the feedback delays the decoded data stream and performs multi-symbol detection processing on the input respective convolutional data streams.
  • the decoded data stream includes k+1 decoded data block streams, and the k+1 decoded data block streams are k+1 target convolution data block streams in the first decoder pair equalized data stream.
  • the feedback module further comprises: an external information calculator and k second data extractors, wherein the input ends of the external information calculator are respectively connected with the output of the first decoder and the input of the first decoder End connection, the output of the external information calculator is connected with the first third delay of the k third delays, and each of the k third delays passes a second data
  • the extractor is connected to the input of the corresponding multi-symbol detector, and step S3 comprises:
  • the external information calculator calculates the external information stream of the first decoder according to the decoded data stream output by the first decoder and the equalized data stream input to the first decoder, and the external information stream includes k+1 external information block streams. , k+1 outer information block streams are calculated by the external information calculator according to k+1 decoded data block streams and k+1 target convolution data block streams;
  • Each of the k third delays delays the input of each external information stream by n unit time to obtain a delayed external information stream, and inputs the delayed external information stream into the second connected respective stream.
  • a data extractor and a next third delay each of the delayed external information streams including k+1 delayed outer information block streams;
  • Each of the k second data extractors extracts a target delayed outer block flow from the k+1 delayed outer block flows input to the respective delayed outer information streams, and extracts the extracted The target delay outer block flow is input to the respective connected multi-symbol detector;
  • Each of the k+1 multi-symbol detectors performs multi-symbol detection processing on the input respective convolutional data streams according to the target delayed outer block flow fed back by the respective second data extractor.
  • the first blocker divides each of the m coded codewords into k+1 coded data blocks, and inputs one of the k+1 coded data blocks into the first block.
  • the combiner, the k coded data blocks are input to the first first delay, including:
  • the first blocker divides each of the m coded codewords into k+1 coded data blocks arranged in sequence, and inputs the first coded data block of the k+1 coded data blocks into the first block.
  • a combiner the second to k+1th coded data blocks are input to the first first delayer;
  • Each of the k first delays delays the input of the respective p coded data blocks by n unit times to obtain p delay coded data blocks, and p delay coded data blocks
  • One of the delayed coded data blocks is input to the first combiner, and the p-1 delayed coded data blocks are input to the next first delay device respectively connected, including:
  • Each of the k first delays delays the input of the p-coded data blocks in sequence by n unit time, and obtains p delay-coded data blocks, and delays p times.
  • the first delayed coded data block in the encoded data block is input to the first combiner, and the second through pth delayed coded data blocks are input to the next first delay connected to each other.
  • the data in the initial data block is zero.
  • the signal transmission system further includes: an encoder and a second decoder, the encoder is connected to the convolution module, and the second decoder is connected to the first decoder, the signal transmission method further includes:
  • the encoder encodes the data stream of the input itself to obtain an encoded data stream
  • the second decoder performs a second decoding of the decoded data stream.
  • the signal transmission method provided by the embodiment of the present application has been described in detail in the embodiment of the signal transmission system.
  • the specific implementation process of the signal transmission method reference may be made to the foregoing system embodiment. This will not be repeated here.
  • the signal transmission method provided by the present application may be implemented by a processor executing a program.
  • the encoder, the convolution module, and the DAC may be processors of the transmitting device.
  • the processor of the transmitting device can implement the method corresponding to the encoder, the convolution module and the DAC in the above method by executing the program, the coherent receiver, the ADC, the equalization module, the feedback module, the first decoder,
  • the second decoder and the decider may be functional units in the processor of the receiving end device, and the processor of the receiving end device may implement the coherent receiver, the ADC, the equalization module, the feedback module, and the first translation in the foregoing method by executing a program.
  • the equalization module includes at least two multi-symbol detectors
  • at least two multi-symbol detectors perform multi-symbol detection processing on the convolutional data stream according to the feedback data stream, and The feedback data stream is determined according to the decoded data stream. Therefore, the signal can be feedback-transmitted between the first decoder and the at least two multi-symbol detectors without setting multiple decoders and decoding
  • the device and the multi-symbol detector perform multiple iterations to solve the problem of high complexity of the transmitted signal, which helps to reduce the complexity of the transmitted signal.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Electromagnetism (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Error Detection And Correction (AREA)

Abstract

本申请提供一种信号传输方法及系统，涉及通信技术领域，系统包括均衡模块、第一译码器和反馈模块，均衡模块包括至少两个多符号检测器，反馈模块分别与第一译码器和至少两个多符号检测器连接，均衡模块对卷积数据流进行均衡处理得到均衡数据流，在此过程中每个多符号检测器对输入各自的卷积数据流进行多符号检测处理；第一译码器对均衡数据流进行译码得到译码数据流；反馈模块将反馈数据流反馈至至少两个多符号检测器；均衡模块根据反馈数据流对卷积数据流进行均衡处理，在此过程中每个多符号检测器根据反馈数据流对输入各自的卷积数据流进行多符号检测处理。本申请通解决了传输信号的复杂度较高的问题，降低传输信号的复杂度。

Description

信号传输方法及系统 技术领域
本申请涉及通信技术领域，特别涉及一种信号传输方法及系统。
背景技术
随着高速光纤传输系统的传输速率的提升，例如，传输速率从40Gb/s(吉字节每秒)到100Gb/s，甚至到400Gb/s，相干接收技术被广泛应用，基于相干接收技术的高速光纤传输系统可以称为相干光传输系统。
目前，相干光传输系统包括：从发送端到接收端依次连接的前向纠错码(英文：Forward Error Correction；简称：FEC)编码器、信道交织器、数模转换器(英文：Digital-Analog Converter；简称：DAC)、相干接收器、模数转换器(英文：Analog-Digital Converter；简称：ADC)、信道均衡器、多符号检测器、FEC译码器和判决器。其中，FEC编码器、信道交织器和DAC位于发送端，相干接收器、ADC、信道均衡器、多符号检测器、FEC译码器和判决器位于接收端，DAC与相干接收器通过光纤连接。发送端的数据流依次经过FEC编码器的编码、信道交织器的调制以及DAC的数模转换之后，通过光纤发送至相干接收器，相干接收器通过相干接收技术恢复出基带信号，ADC对基带信号进行模数转换，信道均衡器通过数字处理算法对模数转换后的信号进行均衡处理(如色散补偿、时钟恢复、解偏振复用、载波相位估计等处理)，并将均衡处理后的信号输入多符号检测器，多符号检测器对均衡处理后的信号进行多符号检测处理之后，FEC译码器对检测处理后的信号进行译码，最终由判决器对译码后的信号进行判决，以恢复出数据流。
相关技术中，为了实现信道均衡，通常在接收端设置一一对应的多个多符号检测器和多个FEC译码器，每个多符号检测器的输入端与信道均衡器的输出端连接，每个多符号检测器的输出端与相应的FEC译码器的输入端连接，每个FEC译码器的输出端分别与判决器以及相应的多符号检测器的输入端连接。信道均衡器输出的信号分别输入每个多符号检测器，每个多符号检测器对信号进行多符号检测处理之后，执行多次迭代过程，每次迭代过程包括：将检测处理后的信号输入相应的FEC译码器进行译码，FEC译码器将译码后的信号反馈至相应的多符号检测器，多符号检测器根据FEC译码器反馈的信号对从信道均衡器输入至多符号检测器的信号进行多符号检测。这样一来，可以在FEC译码器与多符号检测器之间对信号实现迭代处理。
但是，由于相关技术中的相干光传输系统需要进行多次迭代过程，因此该相干光传输系统传输信号的复杂度较高。
发明内容
为了解决相关技术中的相干光传输系统传输信号的复杂度较高的问题，本申请提供了一种信号传输方法及系统。所述技术方案如下：
第一方面，提供一种信号传输系统，该信号传输系统包括：均衡模块、第一译码器和反馈模块，均衡模块和第一译码器连接，均衡模块包括至少两个多符号检测器，反馈模块分别与第一译码器和至少两个多符号检测器连接，
均衡模块用于对卷积数据流进行均衡处理，得到均衡数据流，其中，在均衡模块对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理；
第一译码器用于对均衡数据流进行译码，得到译码数据流；
反馈模块用于根据译码数据流确定反馈数据流，并将反馈数据流反馈至均衡模块的至少两个多符号检测器；
均衡模块还用于根据反馈数据流对卷积数据流进行均衡处理，其中，在均衡模块对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于根据反馈模块反馈的反馈数据流对输入各自的卷积数据流进行多符号检测处理。
可选地，信号传输系统还包括：卷积模块，卷积模块、均衡模块和第一译码器依次连接，卷积模块用于对输入自身的编码数据流进行卷积处理，得到卷积数据流；
编码数据流包括与连续的m个单位时间一一对应的m个编码码字，m个编码码字中的每个编码码字包括k+1个编码数据块，m>1，k>0，且m和k均为整数；
卷积数据流包括与连续的w个单位时间一一对应的w个卷积码字，w＝m+n*k，w个卷积码字中的每个卷积码字包括k+1个卷积数据块，每个卷积码字包括m个编码码字中的至少一个编码码字中的1个编码数据块，n>0，且n为整数；
均衡数据流包括与连续的g个单位时间一一对应的g个均衡码字，g＝m+2n*k，g个均衡码字中的每个均衡码字包括k+1个均衡数据块，g个均衡码字中，与连续的m个单位时间对应的m个均衡码字与m个编码码字一一对应，m个均衡码字中的每个均衡码字包括对相应的编码码字中的所有编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块；
译码数据流包括与连续的g个单位时间一一对应的g个译码码字，g个译码码字是对g个均衡码字进行译码得到的，g个译码码字中的每个译码码字包括k+1个译码数据块。
可选地，卷积模块包括：第一分块器、第一合并器和k个第一延时器，k个第一延时器依次串联，且第一分块器、k个第一延时器和第一合并器依次串联，k个第一延时器中每个第一延时器的输出端分别与第一合并器的输入端连接，k个第一延时器中的首个第一延时器的输入端与第一合并器的输入端连接，
第一分块器用于将m个编码码字中的每个编码码字分成k+1个编码数据块，并将k+1个编码数据块中的1个编码数据块输入第一合并器，k个编码数据块输入首个第一延时器；
k个第一延时器中的每个第一延时器用于对输入各自的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的1个延时编码数据块输入第一合并器，p-1个延时编码数据块输入各自连接的下一第一延时器，1≤p≤k，且p为整数；
第一合并器用于对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流。可选地，第一合并器用于按照时间顺序对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流，卷积数据流包括w个卷积码字；在w个卷积码字中：
与w个单位时间中的前n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每 个卷积码字组包括n个卷积码字，每个卷积码字包括i个第一卷积数据块和k+1-i个第二卷积数据块，其中，i个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的前n*i个单位时间对应的n*i个编码码字中的i个编码码字中的一个编码数据块，i个第一卷积数据块一一对应来自于i个编码码字，k+1-i个第二卷积数据块为初始数据块，k≥i>0，且i为整数；可选地，初始数据块中的数据为0。
与w个单位时间中的后n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括k+1-j个第一卷积数据块和j个第二卷积数据块，其中，k+1-j个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的后n*j个单位时间对应的n*j个编码码字中的k+1-j个编码码字中的一个编码数据块，k+1-j个第一卷积数据块一一对应来自于k+1-j个编码码字，j个第二编码数据块为初始数据块，k≥j>0，且j为整数；可选地，初始数据块中的数据为0。
中间单位时间中的每个单位时间对应的卷积码字包括k+1个第一卷积数据块，k+1个第一卷积数据块中的每个第一卷积数据块是m个编码码字中的k+1个编码码字中的一个编码数据块，k+1个第一卷积数据块一一对应来自于k+1个编码码字，中间单位时间为w个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，均衡模块包括：第二合并器、k个第二延时器、k+1个多符号检测器、k+1个第二分块器和k+1个第一数据提取器，k+1个多符号检测器的输出端与k+1个第二分块器的输入端一一对应连接，k+1个第二分块器的输出端与k+1个第一数据提取器的输入端一一对应连接，k+1个第一数据提取器中的每个第一数据提取器的输出端与第二合并器的输入端连接，k个第二延时器依次串联，且k个第二延时器的输出端与k+1个多符号检测器中的k个多符号检测器的输入端一一对应连接，k个第二延时器中的首个第二延时器的输入端与k+1个多符号检测器除k个多符号检测器之外的多符号检测器的输入端连接，首个第二延时器的输入端还与卷积模块连接，
卷积模块用于将卷积数据流分别输入首个第二延时器，以及与首个第二延时器的输入端连接的多符号检测器；
k个第二延时器中的每个第二延时器用于对输入各自的卷积数据流延时n个单位时间，得到延时卷积数据流，并将延时卷积数据流分别输入各自连接的多符号检测器和下一第二延时器，每个延时卷积数据流包括与连续的w个单位时间一一对应的w个延时卷积码字；
k+1个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入各自连接的第二分块器，每个多符号检测卷积数据流包括与连续的w个单位时间一一对应的w个多符号检测卷积码字；
k+1个第二分块器中的每个第二分块器用于将输入各自的多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流，并将k+1个卷积数据块流输入各自连接的第一数据提取器；
k+1个第一数据提取器中的每个第一数据提取器用于从输入各自的k+1个卷积数据块流中，提取目标卷积数据块流，并将提取到的目标卷积数据块流输入第二合并器；
第二合并器用于对输入自身的k+1个目标卷积数据块流进行合并，得到均衡数据流。
可选地，第二合并器用于按照时间顺序对输入自身的k+1个目标卷积数据块流进行合 并，得到均衡数据流，均衡数据流包括k+1个目标卷积数据块流，每个目标卷积数据块流包括g个均衡码字中的每个均衡码字中的1个均衡数据块；其中，在g个均衡码字中：
与g个单位时间中的前n*k个单位时间和后n*k个单位时间中的每个单位时间对应的均衡码字包括k+1个初始数据块；
与g个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的k+1个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，中间单位时间为g个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，反馈模块包括：k个第三延时器，k个第三延时器依次串联，第一译码器的输出端与k个第三延时器中的首个第三延时器的输入端连接，k个第三延时器中的第q个第三延时器的输出端与k+1个多符号检测器中的k+1-q个多符号检测器的输入端连接，k+1-q个多符号检测器为与k个第二延时器中的倒数k+1-q个第二延时器的输出端连接的多符号检测器，k个第三延时器中的每个第三延时器用于对输入各自的译码数据流延时n个单位时间，得到延时译码数据流，并将延时译码数据流输入各自连接的多符号检测器和下一第三延时器；k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第三延时器反馈的延时译码数据流，对输入各自的卷积数据流进行多符号检测处理。
可选地，译码数据流包括k+1个译码数据块流，k+1个译码数据块流是第一译码器对均衡数据流中的k+1个目标卷积数据块流进行译码处理得到的，反馈模块还包括：外信息计算器和k个第二数据提取器，外信息计算器的输入端分别与第一译码器的输出端和第一译码器的输入端连接，外信息计算器的输出端与k个第三延时器中的首个第三延时器连接，k个第三延时器中的每个第三延时器通过一个第二数据提取器与相应的多符号检测器的输入端连接，
外信息计算器用于根据第一译码器输出的译码数据流和输入第一译码器的均衡数据流计算第一译码器的外信息流，外信息流包括k+1个外信息块流，k+1个外信息块流是外信息计算器根据k+1个译码数据块流和k+1个目标卷积数据块流计算得到的；
k个第三延时器中的每个第三延时器用于对输入各自的外信息流延时n个单位时间，得到延时外信息流，并将延时外信息流输入各自连接的第二数据提取器和下一第三延时器，每个延时外信息流包括k+1个延时外信息块流；
k个第二数据提取器中的每个第二数据提取器用于从输入各自的延时外信息流的k+1个延时外信息块流中提取目标延时外信息块流，并将提取到的目标延时外信息块流输入各自连接的多符号检测器；
k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第二数据提取器反馈的目标延时外信息块流，对输入各自的卷积数据流进行多符号检测处理。
可选地，第一分块器具体用于：将m个编码码字中的每个编码码字分成依次排列的k+1个编码数据块，并将k+1个编码数据块中的第1个编码数据块输入第一合并器，第2至第k+1个编码数据块输入首个第一延时器；k个第一延时器中的每个第一延时器具体用于：对输入各自的依次排列的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的第1个延时编码数据块输入第一合并器，第2至第p个延时编码数据块输入各自连接的下一第一延时器。
可选地，该信号传输系统还包括：编码器和第二译码器，编码器与卷积模块连接，第 二译码器与第一译码器连接，编码器用于对输入自身的数据流进行编码，得到编码数据流；第二译码器用于对译码数据流进行二次译码。
第二方面，提供一种信号传输方法，该信号传输方法包括：
对卷积数据流进行均衡处理，得到均衡数据流，其中，在对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理；
对均衡数据流进行译码，得到译码数据流；
根据译码数据流确定反馈数据流；
根据反馈数据流对卷积数据流进行均衡处理，其中，在对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于根据反馈数据流对输入各自的卷积数据流进行多符号检测处理。
可选地，该信号传输方法还包括：对编码数据流进行卷积处理，得到卷积数据流；
编码数据流包括与连续的m个单位时间一一对应的m个编码码字，m个编码码字中的每个编码码字包括k+1个编码数据块，m>1，k>0，且m和k均为整数；
卷积数据流包括与连续的w个单位时间一一对应的w个卷积码字，w＝m+n*k，w个卷积码字中的每个卷积码字包括k+1个卷积数据块，每个卷积码字包括m个编码码字中的至少一个编码码字中的1个编码数据块，n>0，且n为整数；
均衡数据流包括与连续的g个单位时间一一对应的g个均衡码字，g＝m+2n*k，g个均衡码字中的每个均衡码字包括k+1个均衡数据块，g个均衡码字中，与连续的m个单位时间对应的m个均衡码字与m个编码码字一一对应，m个均衡码字中的每个均衡码字包括对相应的编码码字中的所有编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块；
译码数据流包括与连续的g个单位时间一一对应的g个译码码字，g个译码码字是对g个均衡码字进行译码得到的，g个译码码字中的每个译码码字包括k+1个译码数据块。
可选地，对编码数据流进行卷积处理，得到卷积数据流，包括：
将m个编码码字中的每个编码码字分成k+1个编码数据块；
对p个编码数据块延时n个单位时间，得到p个延时编码数据块，1≤p≤k，且p为整数；
对m个编码码字对应的编码数据块进行合并，得到卷积数据流。
可选地，对m个编码码字对应的编码数据块进行合并，得到卷积数据流，包括：
按照时间顺序对m个编码码字对应的编码数据块进行合并，得到卷积数据流，卷积数据流包括w个卷积码字；在w个卷积码字中：
与w个单位时间中的前n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括i个第一卷积数据块和k+1-i个第二卷积数据块，其中，i个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的前n*i个单位时间对应的n*i个编码码字中的i个编码码字中的一个编码数据块，i个第一卷积数据块一一对应来自于i个编码码字，k+1-i个第二卷积数据块为初始数据块，k≥i>0，且i为整数；可选地，初始数据块中的数据为0。
与w个单位时间中的后n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每 个卷积码字组包括n个卷积码字，每个卷积码字包括k+1-j个第一卷积数据块和j个第二卷积数据块，其中，k+1-j个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的后n*j个单位时间对应的n*j个编码码字中的k+1-j个编码码字中的一个编码数据块，k+1-j个第一卷积数据块一一对应来自于k+1-j个编码码字，j个第二编码数据块为初始数据块，k≥j>0，且j为整数；可选地，初始数据块中的数据为0。
中间单位时间中的每个单位时间对应的卷积码字包括k+1个第一卷积数据块，k+1个第一卷积数据块中的每个第一卷积数据块是m个编码码字中的k+1个编码码字中的一个编码数据块，k+1个第一卷积数据块一一对应来自于k+1个编码码字，中间单位时间为w个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，对卷积数据流进行均衡处理，得到均衡数据流，包括：
对卷积数据流延时n个单位时间，得到延时卷积数据流，每个延时卷积数据流包括与连续的w个单位时间一一对应的w个延时卷积码字；
对卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，每个多符号检测卷积数据流包括与连续的w个单位时间一一对应的w个多符号检测卷积码字；
将多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流；
从每个多符号卷积码字的k+1个卷积数据块流中，提取目标卷积数据块流；
对目标卷积数据块流进行合并，得到均衡数据流。
可选地，对目标卷积数据块流进行合并，得到均衡数据流，包括：
按照时间顺序对k+1个目标卷积数据块流进行合并，得到均衡数据流，均衡数据流包括k+1个目标卷积数据块流，每个目标卷积数据块流包括g个均衡码字中的每个均衡码字中的1个均衡数据块；其中，在g个均衡码字中：
与g个单位时间中的前n*k个单位时间和后n*k个单位时间中的每个单位时间对应的均衡码字包括k+1个初始数据块；与g个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的k+1个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，中间单位时间为g个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，根据译码数据流确定反馈数据流，包括：
对译码数据流延时n个单位时间，得到延时译码数据流；
将延时译码数据流确定为反馈数据流。
可选地，译码数据流包括k+1个译码数据块流，k+1个译码数据块流是对均衡数据流中的k+1个目标卷积数据块流进行译码处理得到的，根据译码数据流确定反馈数据流，包括：
根据译码数据流和均衡数据流计算外信息流，外信息流包括k+1个外信息块流，k+1个外信息块流是根据k+1个译码数据块流和k+1个目标卷积数据块流计算得到的；
对外信息流延时n个单位时间，得到延时外信息流；
将延时外信息流确定为反馈数据流。
可选地，将m个编码码字中的每个编码码字分成k+1个编码数据块，包括：
将m个编码码字中的每个编码码字分成依次排列的k+1个编码数据块；
对p个编码数据块延时n个单位时间，得到p个延时编码数据块，包括：
对依次排列的p个编码数据块延时n个单位时间，得到p个延时编码数据块。
需要说明的是，实际应用中，本申请提供的信号传输方法可以通过处理器执行程序来实现，此时，编码器、卷积模块和DAC可以为发送端设备的处理器中的功能单元，发送端设备的处理器可以通过执行程序实现上述方法中编码器、卷积模块和DAC所对应的方法，相干接收器、ADC、均衡模块、反馈模块、第一译码器、第二译码器和判决器可以为接收端设备的处理器中的功能单元，接收端设备的处理器可以通过执行程序实现上述方法中相干接收器、ADC、均衡模块、反馈模块、第一译码器、第二译码器和判决器所对应的方法。
本申请提供的技术方案的有益效果是：
本申请提供的信号传输方法及系统，由于均衡模块包括至少两个多符号检测器，至少两个多符号检测器根据反馈数据流对卷积数据流进行多符号检测处理，且反馈数据流是根据译码数据流确定的，因此，可以在第一译码器与至少两个多符号检测器之间对信号进行反馈传输，而无需设置多个译码器，并在译码器与多符号检测器进行多次迭代过程，解决了传输信号的复杂度较高的问题，有助于降低传输信号的复杂度。
附图说明
图1是一种传统的相干光传输系统的结构示意图；
图2是相关技术提供的一种相干光传输系统的结构示意图；
图3是本申请实施例提供的一种信号传输系统的结构示意图；
图4是本申请实施例提供的另一种信号传输系统的结构示意图；
图5是本申请实施例提供的信号传输系统的部分区域的结构示意图；
图6是本申请实施例提供的信号传输系统的另一部分区域的结构示意图；
图7是本申请实施例提供的信号传输系统对数据流进行处理的过程示意图；
图8是本申请实施例提供的信号传输系统对数据流进行处理的过程示意图；
图9是本申请实施例提供的信号传输系统对数据流进行处理的过程示意图；
图10是本申请实施例提供的信号传输系统对数据流进行处理的过程示意图；
图11是本申请实施例所涉及的一种状态转移图；
图12是本申请实施例提供的多符号检测器的原理图。
具体实施方式
请参考图1，其示出了一种传统的相干光传输系统的结构示意图，参见图1，该相干光传输系统包括：从发送端到接收端依次连接的FEC编码器、信道交织器、DAC、相干接收器、ADC、信道均衡器、多符号检测器、FEC译码器和判决器。其中，FEC编码器、信道交织器和DAC位于发送端，相干接收器、ADC、信道均衡器、多符号检测器、FEC译码器和判决器位于接收端，DAC与相干接收器通过光纤连接。发送端的数据流依次经过FEC编码器的编码、信道交织器的调制以及DAC的数模转换之后，通过光纤发送至相干接收器，相干接收器通过相干接收技术恢复出基带信号，ADC对基带信号进行模数转换，信道均衡器对模数转换后的信号进行均衡处理，并将均衡处理后的信号输入多符号检测器，多符号检测器对均衡处理后的信号进行多符号检测处理之后，FEC译码器对检测处理后的信号进行译码，最终由判决器对译码后的信号进行判决，以恢复出数据流。
相关技术中，为了实现信道均衡，如图2所示，通常在接收端设置一一对应的多个多符号检测器和多个FEC译码器，每个多符号检测器的输入端与信道均衡器的输出端连接，每个多符号检测器的输出端与相应的FEC译码器的输入端连接，每个FEC译码器的输出端分别与判决器以及相应的多符号检测器的输入端连接。信道均衡器输出的信号分别输入每个多符号检测器，每个多符号检测器对信号进行多符号检测处理之后，执行多次迭代过程，每次迭代过程包括：将检测处理后的信号输入相应的FEC译码器进行译码，FEC译码器将译码后的信号反馈至相应的多符号检测器，多符号检测器根据FEC译码器反馈的信号对从信道均衡器输入至多符号检测器的信号进行多符号检测。这样一来，可以在FEC译码器与多符号检测器之间对信号实现迭代处理。但是由于该相干光传输系统需要进行多次迭代过程，因此该相干光传输系统传输信号的复杂度较高。此外，在图2所示的相干光传输系统中，若迭代次数较少，则FEC译码器向多符号检测器反馈的数据的精度较低，影响迭代性能。本申请实施例提供的信号传输系统，无需进行多次迭代就能够保证数据精度，降低传输信号的复杂度。本申请实施例提供的信号传输方法及系统的详细描述请参考下述各个实施例。
请参考图3，其示出了本申请实施例提供的一种信号传输系统的结构示意图，该信号传输系统可以为相干光传输系统，参见图3，该信号传输系统包括：均衡模块01、第一译码器02和反馈模块03，均衡模块01和第一译码器02连接，均衡模块01包括至少两个多符号检测器(图3中未示出)，反馈模块03分别与第一译码器02和至少两个多符号检测器连接。
均衡模块01用于对卷积数据流进行均衡处理，得到均衡数据流，其中，在均衡模块01对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理；第一译码器02用于对均衡数据流进行译码，得到译码数据流；反馈模块03用于根据译码数据流确定反馈数据流，并将反馈数据流反馈至均衡模块01的至少两个多符号检测器；均衡模块01还用于根据反馈数据流对卷积数据流进行均衡处理，其中，在均衡模块01对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于根据反馈模块03反馈的反馈数据流对输入各自的卷积数据流进行多符号检测处理。
综上所述，本申请实施例提供的信号传输系统，由于均衡模块包括至少两个多符号检测器，至少两个多符号检测器根据反馈数据流对卷积数据流进行多符号检测处理，且反馈数据流是根据译码数据流确定的，因此，可以在第一译码器与至少两个多符号检测器之间对信号进行反馈传输，而无需设置多个译码器，并在译码器与多符号检测器进行多次迭代过程，解决了传输信号的复杂度较高的问题，有助于降低传输信号的复杂度。
进一步地，请参考图4，其示出了本申请实施例提供的另一种信号传输系统的结构示意图，在图3的基础上，该信号传输系统还包括：卷积模块04，卷积模块04、均衡模块01和第一译码器02依次连接，卷积模块04用于对输入自身的编码数据流进行卷积处理，得到卷积数据流。
进一步地，该信号传输系统还包括：编码器05和第二译码器06，编码器05与卷积模块04连接，第二译码器06与第一译码器02连接，编码器05用于对输入自身的数据流进 行编码，得到编码数据流；第二译码器06用于对译码数据流进行二次译码。
进一步地，该信号传输系统还包括：DAC-07、相干接收器08、ADC-09和判决器10，编码器05、卷积模块04和DAC-07依次连接，且编码器05、卷积模块04和DAC-07位于信号传输系统的发送端，相干接收器08、ADC-09、均衡模块01、第一译码器02、第二译码器06和判决器10依次连接，且相干接收器08、ADC-09、均衡模块01、第一译码器02、第二译码器06和判决器10位于信号传输系统的接收端，DAC-07与相干接收器通过光纤连接，反馈模块03分别与第一译码器02和均衡模块01连接。其中，DAC-07、相干接收器08、ADC-09和判决器10的结构和功能均可以参考相关技术，本申请实施例在此不再赘述。
可选地，在本申请实施例中，编码器05可以为FEC编码器，第一译码器02和第二译码器06均可以为FEC译码器，判决器10可以为软判决器。
编码器05用于对输入自身的数据流进行编码，得到编码数据流。其中，输入编码器05的数据流可以为客户侧的业务数据流，该业务数据流可以包括与连续的m个时间单位一一对应的m个业务码字，编码器05对该业务数据流进行编码之后，可以得到编码数据流，并将编码数据流输入卷积模块04，在本申请实施例中，编码数据流包括与连续的m个单位时间一一对应的m个编码码字，每个编码码字是对相应的业务码字进行编码得到的，m个编码码字中的每个编码码字包括k+1个编码数据块，m>1，k>0，且m和k均为整数。
卷积模块04用于对输入自身的编码数据流进行卷积处理，得到卷积数据流，卷积数据流包括与连续的w个单位时间一一对应的w个卷积码字，w＝m+n*k，w个卷积码字中的每个卷积码字包括k+1个卷积数据块，每个卷积码字包括m个编码码字中的至少一个编码码字中的1个编码数据块，n>0，且n为整数。其中，卷积模块04得到卷积数据流之后，可以依次通过DAC-07、相干接收器08和ADC-09将卷积数据流发送至均衡模块01，并且在此过程中，DAC-07、相干接收器08和ADC-09还可以对卷积数据流进行相应的处理，处理的过程可以参考相关技术，本申请实施例在此不再赘述。
均衡模块01用于对卷积数据流进行均衡处理，得到均衡数据流，并将均衡数据流输入第一译码器02，均衡数据流包括与连续的g个单位时间一一对应的g个均衡码字，g＝m+2n*k，g个均衡码字中的每个均衡码字包括k+1个均衡数据块，g个均衡码字中，与连续的m个单位时间对应的m个均衡码字与m个编码码字一一对应，m个均衡码字中的每个均衡码字包括对相应的编码码字中的所有编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块。
第一译码器02用于对均衡数据流进行译码，得到译码数据流，并将译码数据流分别输入反馈模块03和第二译码器06。其中，译码数据流包括与连续的g个单位时间一一对应的g个译码码字，g个译码码字是对g个均衡码字进行译码得到的，g个译码码字中的每个译码码字包括k+1个译码数据块。
反馈模块03用于根据译码数据流确定反馈数据流，并将反馈数据流反馈至均衡模块01的至少两个多符号检测器；第二译码器06用于对译码数据流进行二次译码，以提高译码准确性。
可选地，请参考图5，其示出了图4的区域A的结构示意图，结合图4和图5，卷积模块04包括：第一分块器041、第一合并器042和k个第一延时器，k个第一延时器依次串联，且第一分块器041、k个第一延时器和第一合并器042依次串联，k个第一延时器中每 个第一延时器的输出端分别与第一合并器042的输入端连接，k个第一延时器中的首个第一延时器的输入端与第一合并器042的输入端连接。可选地，该图5以k个第一延时器包括第一延时器1至第一延时器k为例进行说明，第一延时器1的输出端与第一延时器2的输入端连接，第一延时器2的输出端与第一延时器3(图5中未示出)的输入端连接，依次类推，直至第一延时器k，第一分块器041的输出端与第一延时器1的输入端连接，第一延时器1至第一延时器k中的每个第一延时器的输出端分别与第一合并器042的输入端连接，k个第一延时器中的首个第一延时器可以为第一延时器1，第一延时器1的输入端与第一合并器042的输入端连接。需要说明的是，实际应用中，第一分块器041还与编码器05连接。
编码器05用于将编码数据流输入第一分块器041，编码数据流包括与连续的m个单位时间一一对应的m个编码码字。
第一分块器041用于将m个编码码字中的每个编码码字分成k+1个编码数据块，并将k+1个编码数据块中的1个编码数据块输入第一合并器042，k个编码数据块输入首个第一延时器；例如，第一分块器041将m个编码码字中的每个编码码字分成k+1个编码数据块，将k+1个编码数据块中的1个编码数据块输入第一合并器042，k个编码数据块输入第一延时器1。
k个第一延时器中的每个第一延时器用于对输入各自的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的1个延时编码数据块输入第一合并器，p-1个延时编码数据块输入各自连接的下一第一延时器，1≤p≤k，且p为整数；例如，第一延时器1将输入第一延时器1的p(p＝k)个编码数据块延时n个时间单位，得到p个延时编码数据块，将p个延时编码数据块中的1个延时编码数据块输入第一合并器042，p-1(p-1＝k-1)个延时编码数据块输入第一延时器2；第一延时器2将输入第一延时器2的p(p＝k-1)个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的1个延时编码数据块输入第一合并器042，p-1(p-1＝k-2)个延时编码数据块输入第一延时器3，依次类推，直至第一延时器k。
第一合并器042用于对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流。其中，该第一合并器042进行合并的编码数据块可以包括第一延时器1输入该第一合并器042的未经过延时处理的编码数据块和第一延时器2至第一延时器k中的每个第一延时器输入该第一合并器042的经过延时处理后的延时编码数据块。
可选地，在本申请实施例中，第一分块器041具体用于将m个编码码字中的每个编码码字分成依次排列的k+1个编码数据块，并将k+1个编码数据块中的第1个编码数据块输入第一合并器，第2至第k+1个编码数据块输入首个第一延时器1；k个第一延时器中的每个第一延时器具体用于对输入各自的依次排列的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的第1个延时编码数据块输入第一合并器，第2至第p个延时编码数据块输入各自连接的下一第一延时器。
第一合并器042用于按照时间顺序对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流，卷积数据流包括w个卷积码字；其中，在该w个卷积码字中：
与w个单位时间中的前n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括i个第一卷积数据块和k+1-i个第二卷积数据块，其中，i个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的前 n*i个单位时间对应的n*i个编码码字中的i个编码码字中的一个编码数据块，i个第一卷积数据块一一对应来自于i个编码码字，k+1-i个第二卷积数据块为初始数据块，k≥i>0，且i为整数；本申请实施例中，在前n*k个单位时间对应的n*k卷积码字中，卷积码字组的编号可以按照时间顺序排列，i表示卷积码字组的编号，初始数据块中的数据为0。
与w个单位时间中的后n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括k+1-j个第一卷积数据块和j个第二卷积数据块，其中，k+1-j个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的后n*j个单位时间对应的n*j个编码码字中的k+1-j个编码码字中的一个编码数据块，k+1-j个第一卷积数据块一一对应来自于k+1-j个编码码字，j个第二编码数据块为初始数据块，k≥j>0，且j为整数；本申请实施例中，在后n*k个单位时间对应的n*k卷积码字中，卷积码字组的编号可以按照时间顺序排列，j表示卷积码字组的编号，初始数据块中的数据为0。
中间单位时间中的每个单位时间对应的卷积码字包括k+1个第一卷积数据块，k+1个第一卷积数据块中的每个第一卷积数据块是m个编码码字中的k+1个编码码字中的一个编码数据块，k+1个第一卷积数据块一一对应来自于k+1个编码码字，中间单位时间为w个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，请参考图6，其示出了图4中区域B的结构示意图，该区域B中包括均衡模块01、第一译码器02和反馈模块03，结合图4和图6，均衡模块01包括：第二合并器011、k个第二延时器、k+1个多符号检测器、k+1个第二分块器和k+1个第一数据提取器，k+1个多符号检测器的输出端与k+1个第二分块器的输入端一一对应连接，k+1个第二分块器的输出端与k+1个第一数据提取器的输入端一一对应连接，k+1个第一数据提取器中的每个第一数据提取器的输出端与第二合并器011的输入端连接，k个第二延时器依次串联，且k个第二延时器的输出端与k+1个多符号检测器中的k个多符号检测器的输入端一一对应连接，k个第二延时器中的首个第二延时器的输入端与k+1个多符号检测器除k个多符号检测器之外的多符号检测器的输入端连接，首个第二延时器的输入端还与卷积模块04连接，且该首个第二延时器的输入端具体是通过相干接收器08和DAC-07与卷积模块04连接。示例地，该图6以k个第二延时器包括第二延时器1至第二延时器k，k+1个多符号检测器包括多符号检测器1至多符号检测器k+1，k+1个第二分块器包括第二分块器1至第二分块器k+1，k+1个第一数据提取器包括第一数据提取器1至第一数据提取器k+1为例进行说明。多符号检测器1的输出端与第二分块器1的输入端连接，多符号检测器2的输出端与第二分块器2的输入端连接，依次类推，多符号检测器k的输出端与第二分块器k的输入端连接，多符号检测器k+1的输出端与第二分块器k+1的输入端连接；第二分块器1的输出端与第一数据提取器1的输入端连接，第二分块器2的输出端与第一数据提取器2的输入端连接，依次类推，第二分块器k的输出端与第一数据提取器k的输入端连接，第二分块器k+1的输出端与第一数据提取器k+1的输入端连接；第二延时器1的输出端与多符号检测器2的输入端连接，第二延时器2的输出端与多符号检测器3(图6中未示出)的输入端连接，依次类推，第二延时器k的输出端与多符号检测器k+1的输入端连接，k个第二延时器中的首个延时器可以为第二延时器1，第二延时器1的输入端与多符号检测器1的输入端连接，此外，第二延时器1的输入端还与卷积模块04连接，且该第二延时器1的输入端具体是通过相干接收器08和DAC-07与卷积模块04连接。
卷积模块04用于将卷积数据流分别输入首个第二延时器，以及与首个第二延时器的输入端连接的多符号检测器；例如，卷积模块04将卷积数据流分别输入第二延时器1和多符号检测器1。
k个第二延时器中的每个第二延时器用于对输入各自的卷积数据流延时n个单位时间，得到延时卷积数据流，并将延时卷积数据流分别输入各自连接的多符号检测器和下一第二延时器，每个延时卷积数据流包括与连续的w个单位时间一一对应的w个延时卷积码字；例如，第二延时器1将输入第二延时器1的卷积数据流延时n个单位时间，得到延时卷积数据流，并将延时卷积数据流分别输入多符号检测器2和第二延时器2，第二延时器2将输入第二延时器2的卷积数据流延时n个单位时间，得到延时卷积数据流，并将延时卷积数据流分别输入多符号检测器3和第二延时器3，依次类推，直至第二延时器k。
k+1个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入各自连接的第二分块器，每个多符号检测卷积数据流包括与连续的w个单位时间一一对应的w个多符号检测卷积码字；例如，多符号检测器1对输入多符号检测器1的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入第二分块器1，多符号检测器2对输入多符号检测器2的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入第二分块器2，依次类推，直至多符号检测器k+1。
k+1个第二分块器中的每个第二分块器用于将输入各自的多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流，并将k+1个卷积数据块流输入各自连接的第一数据提取器；例如，第二分块器1对输入第二分块器1的多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流，并将k+1个卷积数据块流输入第一数据提取器1，第二分块器2对输入第二分块器2的多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流，并将k+1个卷积数据块流输入第一数据提取器2，依次类推，直至第二分块器k+1。
k+1个第一数据提取器中的每个第一数据提取器用于从输入各自的k+1个卷积数据块流中，提取目标卷积数据块流，并将提取到的目标卷积数据块流输入第二合并器；例如，第一数据提取器1从输入第一数据提取器1的k+1个卷积数据块流中提取目标卷积数据块流，并将该目标卷积数据块流输入第二合并器011；第一数据提取器2从输入第一数据提取器2的k+1个卷积数据块流中提取目标卷积数据块流，并将该目标卷积数据块流输入第二合并器011，以此类推，直至第一数据提取器k+1，此时，总共有k+1个目标卷积数据块流输入第二合并器011。
第二合并器011用于对输入自身的k+1个目标卷积数据块流进行合并，得到均衡数据流。具体地，第二合并器011对第一数据提取器1至第一数据提取器k+1中的所有第一数据提取器输入的目标卷积数据块流进行合并。
可选地，在本申请实施例中，第二合并器011用于按照时间顺序对输入自身的k+1个目标卷积数据块流进行合并，得到均衡数据流，均衡数据流包括k+1个目标卷积数据块流，每个目标卷积数据块流包括g个均衡码字中的每个均衡码字中的1个均衡数据块；其中，在g个均衡码字中：与g个单位时间中的前n*k个单位时间和后n*k个单位时间中的每个 单位时间对应的均衡码字包括k+1个初始数据块，该初始数据块中的数据为0；与g个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的k+1个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，中间单位时间为g个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
进一步地，请继续结合图4和图6，反馈模块03包括：k个第三延时器，k个第三延时器依次串联，第一译码器02的输出端与k个第三延时器中的首个第三延时器的输入端连接，k个第三延时器中的第q个第三延时器的输出端与k+1个多符号检测器中的k+1-q个多符号检测器的输入端连接，k+1-q个多符号检测器为与k个第二延时器中的倒数k+1-q个第二延时器的输出端连接的多符号检测器。示例地，该图6以k个第三延时器包括第三延时器1至第三延时器k为例进行说明，第三延时器1的输出端与第三延时器2的输入端连接，第三延时器2的输出端与第三延时器3(图6中未示出)的输入端连接，依次类推，直至第三延时器k，k个第三延时器中的首个第三延时器为第三延时器1，第一译码器02的输出端与第三延时器1的输入端连接，k个第三延时器中的第1个第三延时器(第三延时器1)的输出端与k+1个多符号检测器中的多符号检测器k+1、多符号检测器k、多符号检测器k-1(图6中未示出)等k个多符号检测器的输入端连接，k个第三延时器中的第2个第三延时器(第三延时器2)的输出端与k+1个多符号检测器中的多符号检测器k+1、多符号检测器k、多符号检测器k-1(图6中未示出)等k-1个多符号检测器的输入端连接，依次类推。
其中，k个第三延时器中的每个第三延时器用于对输入各自的译码数据流延时n个单位时间，得到延时译码数据流，并将延时译码数据流输入各自连接的多符号检测器和下一第三延时器；例如，第三延时器1对输入第三延时器1的译码数据流延时n个单位时间，得到延时译码数据流，并将延时译码数据流输入多符号检测器k+1、多符号检测器k、多符号检测器k-1(图6中未示出)等k个多符号检测器和下一第三延时器，第三延时器2对输入第三延时器2的译码数据流延时n个单位时间，得到延时译码数据流，并将延时译码数据流输入多符号检测器k+1、多符号检测器k、多符号检测器k-1(图6中未示出)等k-1个多符号检测器和下一第三延时器，依次类推。
k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第三延时器反馈的延时译码数据流，对输入各自的卷积数据流进行多符号检测处理。其中，此处的卷积数据流包括未经过延时处理的卷积数据流和经过延时处理的延时卷积数据流。例如，多符号检测器2根据第三延时器1反馈的延时译码数据流对输入多符号检测器2的卷积数据流进行多符号检测处理，多符号检测器3根据第三延时器1馈的延时译码数据流和第三延时器2反馈的延时译码数据流对输入多符号检测器3的卷积数据流进行多符号检测处理，依次类推。
可选地，在本申请实施例中，译码数据流包括k+1个译码数据块流，k+1个译码数据块流是第一译码器02对均衡数据流中的k+1个目标卷积数据块流进行译码处理得到的，结合图4和图6，反馈模块03还包括：外信息计算器031和k个第二数据提取器，外信息计算器031的输入端分别与第一译码器02的输出端和第一译码器02的输入端连接，外信息计算器031的输出端与k个第三延时器中的首个第三延时器连接，k个第三延时器中的每个第三延时器通过一个第二数据提取器与相应的多符号检测器的输入端连接。示例地，该图6以k个第二数据提取器包括第二数据提取器1至第二数据提取器k为例进行说明，外信息计算器031的输出端与第三延时器1的输入端连接，第三延时器1通过第二数据提取器1 与多符号检测器k+1、多符号检测器k、多符号检测器k-1等k个多符号检测器的输入端连接，第三延时器2通过第二数据提取器2与多符号检测器k+1、多符号检测器k、多符号检测器k-1等k-1个多符号检测器的输入端连接，依次类推。
外信息计算器031用于根据第一译码器02输出的译码数据流和输入第一译码器02的均衡数据流计算第一译码器02的外信息流，外信息流包括k+1个外信息块流，k+1个外信息块流是外信息计算器根据k+1个译码数据块流和k+1个目标卷积数据块流计算得到的。
k个第三延时器中的每个第三延时器用于对输入各自的外信息流延时n个单位时间，得到延时外信息流，并将延时外信息流输入各自连接的第二数据提取器和下一第三延时器，每个延时外信息流包括k+1个延时外信息块流；例如，第三延时器1对输入第三延时器1的外信息流延时n个单位时间，得到延时外信息流，并将延时外信息流输入第二数据提取器1和第三延时器2，第三延时器2对输入第三延时器2的外信息流延时n个单位时间，得到延时外信息流，并将延时外信息流输入第二数据提取器2和第三延时器3，依次类推，直至第三延时器k。
k个第二数据提取器中的每个第二数据提取器用于从输入各自的延时外信息流的k+1个延时外信息块流中提取目标延时外信息块流，并将提取到的目标延时外信息块流输入各自连接的多符号检测器；例如，第二数据提取器1从输入第二数据提取器1的延时外信息流的k+1个延时外信息块流中提取目标延时外信息块流，并将目标延时外信息块流输入多符号检测器k+1、多符号检测器k、多符号检测器k-1等k个多符号检测器，第二数据提取器2从输入第二数据提取器2的延时外信息流的k+1个延时外信息块流中提取目标延时外信息块流，并将目标延时外信息块流输入多符号检测器k+1、多符号检测器k、多符号检测器k-1等k-1个多符号检测器，依次类推。
k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第二数据提取器反馈的目标延时外信息块流，对输入各自的卷积数据流进行多符号检测处理。其中，此处的卷积数据流包括未经过延时处理的卷积数据流和经过延时处理的延时卷积数据流。例如，多符号检测器2根据第三延时器1反馈的目标延时外信息块流对输入多符号检测器2的卷积数据流进行多符号检测处理，多符号检测器3根据第三延时器1反馈的目标延时外信息块流和第三延时器2反馈的目标延时外信息块流对输入多符号检测器3的卷积数据流进行多符号检测处理，依次类推。
在本申请实施例中，m、n和k的取值可以根据实际情况设置，下面以m＝4，n＝1，k＝3对本申请实施例提供的信号传输系统进行说明，则图4的区域A对数据流的处理过程示意图可以如图7所示，图4的区域B对数据流的处理过程示意图可以如图8至图10所示。
结合图4和图7，卷积模块04包括：第一分块器041、第一合并器042和3个第一延时器，该3个第一延时器分别为第一延时器1、第一延时器2和第一延时器3，第一延时器1的输出端与第一延时器2的输入端连接，第一延时器2的输出端与第一延时器3的输入端连接，第一分块器041、3个第一延时器和第一合并器042依次串联，且第一延时器1的输出端、第一延时器2的输出端和第一延时器3的输出端分别与第一合并器042的输入端连接，第一延时器1的输入端与第一合并器042的输入端连接。第一分块器041的输入端还与编码器05连接。
结合图4和图7，编码器05对输入自身的数据流进行编码，得到编码数据流，并将编 码数据流输入第一分块器041，编码数据流包括与连续的4个单位时间一一对应的4个编码码字，该4个编码码字包括与时刻1对应的编码码字a，与时刻2对应的编码码字b，与时刻3对应的编码码字c以及与时刻4对应的编码码字d，其中，每个时刻可以为一个单位时间。
第一分块器041可以将编码数据流中的4个编码码字中的每个编码码字分成4个编码数据块，并将4个编码数据块中的1个编码数据块输入第一合并器042，3个编码数据块输入第一延时器1。具体地，第一分块器041将4个编码码字中的每个编码码字分成依次排列的4个编码数据块，并将4个编码数据块中的第1个编码数据块输入第一合并器，第2至第4个编码数据块输入第一延时器1。如图7所示，第一分块器041将编码码字a分成依次排列的编码数据块1a、编码数据块2a、编码数据块3a和编码数据块4a，并将编码数据块1a(第1个编码码字块)输入第一合并器042，将编码数据块2a、编码数据块3a和编码数据块4a(第2至第4个编码数据块)输入第一延时器1；第一分块器041将编码码字b分成依次排列的编码数据块1b、编码数据块2b、编码数据块3b和编码数据块4b，并将编码数据块1b(第1个编码码字块)输入第一合并器042，将编码数据块2b、编码数据块3b和编码数据块4b(第2至第4个编码数据块)输入第一延时器1；第一分块器041将编码码字c分成依次排列的编码数据块1c、编码数据块2c、编码数据块3c和编码数据块4c，并将编码数据块1c(第1个编码码字块)输入第一合并器042，将编码数据块2c、编码数据块3c和编码数据块4c(第2至第4个编码数据块)输入第一延时器1；第一分块器041将编码码字d分成依次排列的编码数据块1d、编码数据块2d、编码数据块3d和编码数据块4d，并将编码数据块1d(第1个编码码字块)输入第一合并器042，将编码数据块2d、编码数据块3d和编码数据块4d(第2至第4个编码数据块)输入第一延时器1。
3个第一延时器中的每个第一延时器对输入各自的p个编码数据块延时1个单位时间(也即是1个时刻)，得到p个延时编码数据块，并将p个延时编码数据块中的1个延时编码数据块输入第一合并器042，p-1个延时编码数据块输入各自连接的下一第一延时器，1≤p≤3，且p为整数。具体地，p个编码数据块依次排列，3个第一延时器中的每个第一延时器对输入各自的依次排列的p个编码数据块延时1个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的第1个延时编码数据块输入第一合并器042，第2至第p个延时编码数据块输入各自连接的下一第一延时器。示例地，如图7所示，第一延时器1对输入第一延时器1的依次排列的编码数据块2a、编码数据块3a和编码数据块4a(3个编码数据块)延时1个单位时间得到依次排列的延时编码数据块2a、延时编码数据块3a和延时编码数据块4a，并将延时编码数据块2a(第1个延时编码数据块)输入第一合并器042，将延时编码数据块3a和延时编码数据块4a(第2至第3个延时编码数据块)输入第一延时器2；第一延时器1对输入第一延时器1的依次排列的编码数据块2b、编码数据块3b和编码数据块4b(3个编码数据块)延时1个单位时间得到依次排列的延时编码数据块2b，延时编码数据块3b和延时编码数据块4b，并将延时编码数据块2b(第1个延时编码数据块)输入第一合并器042，将延时编码数据块3b和延时编码数据块4b(第2至第3个延时编码数据块)输入第一延时器2；第一延时器1对输入第一延时器1的依次排列的编码数据块2c、编码数据块3c和编码数据块4c(3个编码数据块)延时1个单位时间得到依次排列的延时编码数据块2c、延时编码数据块3c和延时编码数据块4c，并将延时编码数据块2c(第 1个延时编码数据块)输入第一合并器042，将延时编码数据块3c和延时编码数据块4c(第2至第3个延时编码数据块)输入第一延时器2；第一延时器1对输入第一延时器1的依次排列的编码数据块2d，编码数据块3d和编码数据块4d(3个编码数据块)延时1个单位时间得到依次排列的延时编码数据块2d、延时编码数据块3d和延时编码数据块4d，并将延时编码数据块2d(第1个延时编码数据块)输入第一合并器042，将延时编码数据块3d和延时编码数据块4d(第2至第3个延时编码数据块)输入第一延时器2。第一延时器2对输入第一延时器2的依次排列的编码数据块3a和编码数据块4a(2个编码数据块，该2个编码数据块是经过第一延时器1延时后的延时编码数据块)延时1个单位时间得到依次排列的延时编码数据块3a和延时编码数据块4a，并将延时编码数据块3a(第1个延时编码数据块)输入第一合并器042，将延时编码数据块4a(第2个延时编码数据块)输入第一延时器3；第一延时器2对输入第一延时器2的依次排列的编码数据块3b和编码数据块4b(2个编码数据块，该2个编码数据块是经过第一延时器1延时后的延时编码数据块)延时1个单位时间得到依次排列的延时编码数据块3b和延时编码数据块4b，并将延时编码数据块3b(第1个延时编码数据块)输入第一合并器042，将延时编码数据块4b(第2个延时编码数据块)输入第一延时器3；第一延时器2对输入第一延时器2的依次排列的编码数据块3c和编码数据块4c(2个编码数据块，该2个编码数据块是经过第一延时器1延时后的延时编码数据块)延时1个单位时间得到依次排列的延时编码数据块3c和延时编码数据块4c，并将延时编码数据块3c(第1个延时编码数据块)输入第一合并器042，将延时编码数据块4c(第2个延时编码数据块)输入第一延时器3；第一延时器2对输入第一延时器2的依次排列的编码数据块3d和编码数据块4d(2个编码数据块，该2个编码数据块是经过第一延时器1延时后的延时编码数据块)延时1个单位时间得到依次排列的延时编码数据块3d和延时编码数据块4d，并将延时编码数据块3d(第1个延时编码数据块)输入第一合并器042，将延时编码数据块4d(第2个延时编码数据块)输入第一延时器3。第一延时器3对输入第一延时器3的编码数据块4a(经过第一延时器1和第一延时器2延时后的延时编码数据块)延时1个单位时间得到延时编码数据块4a，并将延时编码数据块4a输入第一合并器042；第一延时器3对输入第一延时器3的编码数据块4b(经过第一延时器1和第一延时器2延时后的延时编码数据块)延时1个单位时间得到延时编码数据块4b，并将延时编码数据块4b输入第一合并器042；第一延时器3对输入第一延时器3的编码数据块4c(经过第一延时器1和第一延时器2延时后的延时编码数据块)延时1个单位时间得到延时编码数据块4c，并将延时编码数据块4c输入第一合并器042；第一延时器3对输入第一延时器3的编码数据块4d(经过第一延时器1和第一延时器2延时后的延时编码数据块)延时1个单位时间得到延时编码数据块4d，并将延时编码数据块4d输入第一合并器042。
第一合并器042对输入自身的4个编码码字对应的编码数据块进行合并，得到卷积数据流。具体地，第一合并器042可以按照时间顺序对输入自身的4个编码码字对应的编码数据块进行合并，得到卷积数据流，卷积数据流包括7(w＝m+n*k＝4+1*3)个卷积码字。在该7个卷积码字中：与7个单位时间中的前3个单位时间对应的3卷积码字包括3个卷积码字组，每个卷积码字组包括1个卷积码字，每个卷积码字包括i个第一卷积数据块和4-i个第二卷积数据块，其中，i个第一卷积数据块中的每个第一卷积数据块是与4个单位时间中的前i个单位时间对应的i个编码码字中的i个编码码字中的一个编码数据块，i个第一 卷积数据块一一对应来自于i个编码码字，4-i个第二卷积数据块为初始数据块，初始数据块中的数据为0，4≥i>0，且i为整数。与7个单位时间中的后3个单位时间对应的3卷积码字包括3个卷积码字组，每个卷积码字组包括1个卷积码字，每个卷积码字包括4-j个第一卷积数据块和j个第二卷积数据块，其中，4-j个第一卷积数据块中的每个第一卷积数据块是与4个单位时间中的后j个单位时间对应的j个编码码字中的4-j个编码码字中的一个编码数据块，4-j个第一卷积数据块一一对应来自于4-j个编码码字，j个第二编码数据块为初始数据块，初始数据块中的数据为0，4≥j>0，且j为整数。中间单位时间中的每个单位时间对应的卷积码字包括4个第一卷积数据块，4个第一卷积数据块中的每个第一卷积数据块是4个编码码字中的4个编码码字中的一个编码数据块，4个第一卷积数据块一一对应来自于4个编码码字，中间单位时间为7个单位时间中，除前3个单位时间和后3个单位时间之外的单位时间。
示例地，如图7所示，卷积数据流包括卷积码字A、卷积码字B、卷积码字C、卷积码字D、卷积码字E、卷积码字F和卷积码字G这7个卷积码字，在该7个卷积码字中，与7个单位时间中的前3个单位时间(也即是时刻1、时刻2和时刻3)对应的3卷积码字包括卷积码字组1(图7中未标出)、卷积码字组2(图7中未标出)和卷积码字组3(图7中未标出)这3个卷积码字组，卷积码字组1包括卷积码字A，卷积码字组2包括卷积码字B，卷积码字组3包括卷积码字C，卷积码字A包括1(i＝1)个第一卷积数据块和3个第二卷积数据块，该1个第一卷积数据块为卷积数据块1a，3个第二卷积数据块中的数据都为0，卷积码字B包括2(i＝2)个第一卷积数据块和2个第二卷积数据块，该2个第一卷积数据块为卷积数据块1b和卷积数据块2a，2个第二卷积数据块中的数据都为0，卷积码字C包括3(i＝3)个第一卷积数据块和1个第二卷积数据块，该3个第一卷积数据块为卷积数据块1c、卷积数据块2b和卷积数据块3a，1个第二卷积数据块中的数据都为0。
与7个单位时间中的后3个单位时间(也即是时刻5、时刻6和时刻7)对应的3卷积码字包括3个卷积码字组包括卷积码字组1(图7中未标出)、卷积码字组2(图7中未标出)和卷积码字组3(图7中未标出)这3个卷积码字组，卷积码字组1包括卷积码字E，卷积码字组2包括卷积码字F，卷积码字组3包括卷积码字G，卷积码字E包括3(j＝1，4-j＝3)个第一卷积数据块和1个第二卷积数据块，该3个第一卷积数据块为卷积数据块2d、卷积数据块3c和卷积数据块4b，1个第二卷积数据块中的数据都为0，卷积码字F包括2(j＝2，4-j＝2)个第一卷积数据块和2个第二卷积数据块，该2个第一卷积数据块为卷积数据块3d和卷积数据块4c，2个第二卷积数据块中的数据都为0，卷积码字G包括1(j＝3，4-j＝1)个第一卷积数据块和3个第二卷积数据块，该1个第一卷积数据块为卷积数据块4d，3个第二卷积数据块中的数据都为0。中间单位时间(也即是时刻4)对应的卷积码字为卷积码字D，卷积码字D包括4个第一卷积数据块，该4个第一卷积数据块分别为卷积数据块1d、卷积数据块2c、卷积数据块3b和卷积数据块4a。
结合图4以及图8至图10，均衡模块01包括：第二合并器011、3个第二延时器、4个多符号检测器、4个第二分块器和4个第一数据提取器，3个第二延时器分别为第二延时器1、第二延时器2和第二延时器3，4个多符号检测器分别为多符号检测器1、多符号检测器2、多符号检测器3和多符号检测器4，4个第二分块器分别为第二分块器1、第二分块器2、第二分块器3和第二分块器4，4个第一数据提取器分别为第一数据提取器1、第 一数据提取器2、第一数据提取器3和第一数据提取器4，多符号检测器1的输出端与第二分块器1的输入端连接，多符号检测器2的输出端与第二分块器2的输入端连接，多符号检测器3的输出端与第二分块器3的输入端连接，多符号检测器4的输出端与第二分块器4的输入端连接，第二分块器1的输出端与第一数据提取器1的输入端连接，第二分块器2的输出端与第一数据提取器2的输入端连接，第二分块器3的输出端与第一数据提取器3的输入端连接，第二分块器4的输出端与第一数据提取器4的输入端连接，第一数据提取器1的输出端、第一数据提取器2的输出端、第一数据提取器3的输出端和第一数据提取器4的输出端分别与第二合并器011的输入端连接，第二延时器1的输出端分别与第二延时器2的输入端和多符号检测器2的输入端连接，第二延时器2的输出端分别与第二延时器3的输入端和多符号检测器3的输入端连接，第二延时器3的输出端与多符号检测器4的输入端连接，第二延时器1的输入端与多符号检测器1的输入端连接，且第二延时器1的输入端还与卷积模块04连接，该第二延时器1的输入端具体是通过相干接收器08和DAC-07与卷积模块04连接。
结合图4和图8，卷积模块04将卷积数据流分别输入第二延时器1和多符号检测器1，该卷积数据流包括与时刻1对应的卷积码字A，与时刻2对应的卷积码字B，与时刻3对应的卷积码字C，与时刻4对应的卷积码字D，与时刻5对应的卷积码字E，与时刻6对应的卷积码字F和与时刻7对应的卷积码字G。
3个第二延时器中的每个第二延时器对输入各自的卷积数据流延时1个单位时间，得到延时卷积数据流，并将延时卷积数据流分别输入各自连接的多符号检测器和下一第二延时器，每个延时卷积数据流包括与连续的7个单位时间一一对应的7个延时卷积码字。示例地，如图8所示，第二延时器1对输入第二延时器1的卷积数据流延时1个单位时间，得到延时卷积数据流，并将该延时卷积数据流分别输入多符号检测器2和第二延时器2；第二延时器2对输入第二延时器2的延时卷积数据流延时1个单位时间，得到延时2个单位时间的延时卷积数据流，并将该延时卷积数据流分别输入多符号检测器3和第二延时器3；第二延时器3对输入第二延时器3的延时卷积数据流延时1个单位时间，得到延时3个单位时间的延时卷积数据流，并将该延时卷积数据流输入多符号检测器4。
4个多符号检测器中的每个多符号检测器对输入各自的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入各自连接的第二分块器，每个多符号检测卷积数据流包括与连续的7个单位时间一一对应的7个多符号检测卷积码字。示例地，如图8所示，多符号检测器1对输入多符号检测器1的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入第二分块器1，该多符号检测卷积数据流包括与时刻1对应的多符号检测卷积码字A1，与时刻2对应的多符号检测卷积码字B1，与时刻3对应的多符号检测卷积码字C1，与时刻4对应的多符号检测卷积码字D1，与时刻5对应的多符号检测卷积码字E1，与时刻6对应的多符号检测卷积码字F1和与时刻7对应的多符号检测卷积码字G1；多符号检测器2对输入多符号检测器2的卷积数据流(延时卷积数据流)进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入第二分块器2，该多符号检测卷积数据流包括与时刻2对应的多符号检测卷积码字A1，与时刻3对应的多符号检测卷积码字B1，与时刻4对应的多符号检测卷积码字C1，与时刻5对应的多符号检测卷积码字D1，与时刻6对应的多符号检测卷 积码字E1，与时刻7对应的多符号检测卷积码字F1和与时刻8对应的多符号检测卷积码字G1；多符号检测器3对输入多符号检测器3的卷积数据流(延时卷积数据流)进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入第二分块器3，该多符号检测卷积数据流包括与时刻3对应的多符号检测卷积码字A1，与时刻4对应的多符号检测卷积码字B1，与时刻5对应的多符号检测卷积码字C1，与时刻6对应的多符号检测卷积码字D1，与时刻7对应的多符号检测卷积码字E1，与时刻8对应的多符号检测卷积码字F1和与时刻9对应的多符号检测卷积码字G1；多符号检测器4对输入多符号检测器4的卷积数据流(延时卷积数据流)进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入第二分块器4，该多符号检测卷积数据流包括与时刻4对应的多符号检测卷积码字A1，与时刻5对应的多符号检测卷积码字B1，与时刻6对应的多符号检测卷积码字C1，与时刻7对应的多符号检测卷积码字D1，与时刻8对应的多符号检测卷积码字E1，与时刻9对应的多符号检测卷积码字F1和与时刻10对应的多符号检测卷积码字G1。
4个第二分块器中的每个第二分块器将输入各自的多符号检测卷积数据流中的每个多符号卷积码字分成4个卷积数据块，得到4个卷积数据块流，并将4个卷积数据块流输入各自连接的第一数据提取器。示例地，如图9所示，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字A1分成依次排列的卷积数据块1a1、卷积数据块0、卷积数据块0和卷积数据块0这4个卷积数据块，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字B1分成依次排列的卷积数据块1b1、卷积数据块2a1、卷积数据块0和卷积数据块0这4个卷积数据块，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字C1分成依次排列的卷积数据块1c1、卷积数据块2b1、卷积数据块3a1和卷积数据块0这4个卷积数据块，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字D1分成依次排列的卷积数据块1d1、卷积数据块2c1、卷积数据块3b1和卷积数据块4a1这4个卷积数据块，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字E1分成依次排列的卷积数据块0、卷积数据块2d1、卷积数据块3c1和卷积数据块4b1，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字F1分成依次排列的卷积数据块0、卷积数据块0、卷积数据块3d1和卷积数据块4c1，第二分块器1将输入第二分块器1的多符号检测卷积数据流中的多符号卷积码字G1分成依次排列的卷积数据块0、卷积数据块0、卷积数据块0和卷积数据块4d1；之后，第二分块器1可以得到4个卷积数据块流，该4个卷积数据块流分别为：包括按照时间依次排列的卷积数据块1a1、卷积数据块1b1、卷积数据块1c1、卷积数据块1d1、卷积数据块0、卷积数据块0和卷积数据块0的卷积数据块流，包括按照时间依次排列的卷积数据块0、卷积数据块2a1、卷积数据块2b1、卷积数据块2c1、卷积数据块2d1、卷积数据块0和卷积数据块0的卷积数据块流，包括按照时间依次排列的卷积数据块0、卷积数据块0、卷积数据块3a1、卷积数据块3b1、卷积数据块3c1、卷积数据块3d1和卷积数据块0的卷积数据块流，以及，包括按照时间依次排列的卷积数据块0、卷积数据块0、卷积数据块0、卷积数据块4a1、卷积数据块4b1、卷积数据块4c1和卷积数据块4d1的卷积数据块流，之后，第二分块器1可以将该4个卷积数据块流输入第一数据提取器1。第二分块器2、第二分块器3和第二分块器4的分块过程可以参考第二分块器1 的分块过程，在此不再赘述。
4个第一数据提取器中的每个第一数据提取器从输入各自的4个卷积数据块流中，提取目标卷积数据块流，并将提取到的目标卷积数据块流输入第二合并器011。示例地，如图9所示，第一数据提取器1从输入第一数据提取器1的4个卷积数据块流中，提取包括按照从时刻1到时刻7依次排列的卷积数据块0、卷积数据块0、卷积数据块0、卷积数据块4a1、卷积数据块4b1、卷积数据块4c1和卷积数据块4d1的卷积数据块流作为目标卷积数据块流，并将该目标卷积数据块流输入第二合并器011；第一数据提取器2从输入第一数据提取器2的4个卷积数据块流中，提取包括按照从时刻2到时刻8依次排列的卷积数据块0、卷积数据块0、卷积数据块3a1、卷积数据块3b1、卷积数据块3c1、卷积数据块3d1和卷积数据块0的卷积数据块流作为目标卷积数据块流，并将该目标卷积数据块流输入第二合并器011；第一数据提取器3从输入第一数据提取器3的4个卷积数据块流中，提取包括按照从时刻3到时刻9依次排列的卷积数据块0、卷积数据块2a1、卷积数据块2b1、卷积数据块2c1、卷积数据块2d1、卷积数据块0和卷积数据块0的卷积数据块流作为目标卷积数据块流，并将该目标卷积数据块流输入第二合并器011；第一数据提取器4从输入第一数据提取器4的4个卷积数据块流中，提取包括按照从时刻4到时刻10依次排列的卷积数据块1a1、卷积数据块1b1、卷积数据块1c1、卷积数据块1d1、卷积数据块0、卷积数据块0和卷积数据块0的卷积数据块流作为目标卷积数据块流，并将该目标卷积数据块流输入第二合并器011。
第二合并器011对输入自身的4个目标卷积数据块流进行合并，得到均衡数据流。可选地，第二合并器011按照时间顺序对输入自身的4个目标卷积数据块流进行合并，得到均衡数据流，均衡数据流包括4个目标卷积数据块流，每个目标卷积数据块流包括10(g＝m+2n*k＝4+2*1*3＝10)个均衡码字中的每个均衡码字中的1个均衡数据块；其中，在10个均衡码字中：与10个单位时间中的前3个单位时间和后3个单位时间中的每个单位时间对应的均衡码字包括4个初始数据块，该初始数据块中的数据为0；与10个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的4个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，中间单位时间为10个单位时间中，除前3个单位时间和后3个单位时间之外的单位时间。示例地，如图9所示，第二合并器011对自身的4个目标卷积数据块流进行合并得到均衡数据流，每个目标卷积数据块流包括10个均衡码字中的每个均衡码字中的1个均衡数据块；其中，在10个均衡码字中，与时刻1、时刻2、时刻3(时刻1、时刻2和时刻3为前3个单位时间)、时刻8、时刻9和时刻10(时刻8、时刻9和时刻10为后3个单位时间)中的每个时刻时间对应的均衡码字包括4个初始数据块，该初始数据块中的数据为0，与时刻4对应的均衡码字包括均衡数据块1a1、均衡数据块2a1、均衡数据块3a1和均衡数据块4a1，该均衡数据块1a1、均衡数据块2a1、均衡数据块3a1和均衡数据块4a1是对编码数据块1a、编码数据块2a、编码数据块3a和编码数据块4a分别进行卷积处理和均衡处理得到的，与时刻5对应的均衡码字包括均衡数据块1b1、均衡数据块2b1、均衡数据块3b1和均衡数据块4b1，该均衡数据块1b1、均衡数据块2b1、均衡数据块3b1和均衡数据块4b1是对编码数据块1b、编码数据块2b、编码数据块3b和编码数据块4b分别进行卷积处理和均衡处理得到的，与时刻6对应的均衡码字包括均衡数据块1c1、均衡数据块2c1、均衡数据块3c1和均衡数据块4c1，该均衡数据块1c1、均衡数据块2c1、均衡数据块3c1和均衡数据块4c1是对编码数据块1c、 编码数据块2c、编码数据块3c和编码数据块4c分别进行卷积处理和均衡处理得到的，与时刻7对应的均衡码字包括均衡数据块1d1、均衡数据块2d1、均衡数据块3d1和均衡数据块4d1，该均衡数据块1d1、均衡数据块2d1、均衡数据块3d1和均衡数据块4d1是对编码数据块1d、编码数据块2d、编码数据块3d和编码数据块4d分别进行卷积处理和均衡处理得到的。
结合图4和图10，反馈模块03包括：外信息计算器031、3个第三延时器和3个第二数据提取器，3个第三延时器分别为第三延时器1、第三延时器2和第三延时器3，3个第二数据提取器分别为第二数据提取器1、第二数据提取器2和第二数据提取器3，外信息计算器031的输入端分别与第一译码器02的输出端和第一译码器02的输入端连接，外信息计算器031的输出端第三延时器1的输入端连接，第三延时器1的输出端分别与第三延时器2的输入端和第二数据提取器1的输入端连接，第三延时器2的输出端分别与第三延时器3的输入端和第二数据提取器2的输入端连接，第三延时器3的输出端与第二数据提取器3的输入端连接，第二数据提取器1的输出端分别与多符号检测器4的输入端、多符号检测器3的输入端和多符号检测器2的输入端连接，第二数据提取器2的输出端分别与多符号检测器4的输入端和多符号检测器3的输入端连接，第二数据提取器3的输出端与多符号检测器4的输入端连接。
外信息计算器031根据第一译码器02输出的译码数据流和输入第一译码器02的均衡数据流计算第一译码器02的外信息流，外信息流包括4个外信息块流，4个外信息块流是外信息计算器根据4个译码数据块流和均衡数据流的4个目标卷积数据块流计算得到的。可选地，外信息计算器031可以为减法器，外信息计算器031可以将译码数据流与均衡数据流相减得到外信息流。具体地，外信息计算器031将译码数据流中的每个码字块与均衡数据流中的每个码字块相减得到外信息块，进而得到外信息块流，并最终得到外信息流。如图10所示，外信息流包括4个外信息块流，该4个外信息块流分别为：包括按照时间顺序依次排列的外信息块0、外信息块0、外信息块0、外信息块1a2、外信息块1b2、外信息块1c2、外信息块1d2、外信息块0、外信息块0和外信息块0的外信息块流，按照时间顺序依次排列的外信息块0、外信息块0、外信息块0、外信息块2a2、外信息块2b2、外信息块2c2、外信息块2d2、外信息块0、外信息块0和外信息块0的外信息块流，按照时间顺序依次排列的外信息块0、外信息块0、外信息块0、外信息块3a2、外信息块3b2、外信息块3c2、外信息块3d2、外信息块0、外信息块0和外信息块0的外信息块流，以及，按照时间顺序依次排列的外信息块0、外信息块0、外信息块0、外信息块4a2、外信息块4b2、外信息块4c2、外信息块4d2、外信息块0、外信息块0和外信息块0的外信息块流。
3个第三延时器中的每个第三延时器对输入各自的外信息流延时1个单位时间，得到延时外信息流，并将延时外信息流输入各自连接的第二数据提取器和下一第三延时器，每个延时外信息流包括4个延时外信息块流。示例地，如图10所示，第三延时器1对输入第三延时器1的外信息流延时1个单位时间得到延时外信息流，并将延时外信息流输入第二数据提取器1和第三延时器2，第三延时器2对输入第三延时器2的外信息流延时1个单位时间得到延时外信息流，并将延时外信息流输入第二数据提取器2和第三延时器3；第三延时器3对输入第三延时器3的外信息流延时1个单位时间得到延时外信息流，并将延时外信息流输入第二数据提取器3。
3个第二数据提取器中的每个第二数据提取器从输入各自的延时外信息流的4个延时外信息块流中提取目标延时外信息块流，并将提取到的目标延时外信息块流输入各自连接的多符号检测器。示例地，如图10所示，第二数据提取器1从输入第二数据提取器1的延时外信息流的4个延时外信息块流中提取目标延时外信息块流，并将目标延时外信息块流输入多符号检测器4、多符号检测器3和多符号检测器2，该目标延时外信息块流为：包括按照从时刻2到时刻11依次排列的延时外信息块0、延时外信息块0、延时外信息块0、延时外信息块4a2、延时外信息块4b2、延时外信息块4c2、延时外信息块4d2、延时外信息块0、延时外信息块0和延时外信息块0的延时外信息块流；第二数据提取器2从输入第二数据提取器2的延时外信息流的4个延时外信息块流中提取目标延时外信息块流，并将目标延时外信息块流输入多符号检测器4和多符号检测器3，该目标延时外信息块流为：包括按照从时刻3到时刻12依次排列的延时外信息块0、延时外信息块0、延时外信息块0、延时外信息块3a2、延时外信息块3b2、延时外信息块3c2、延时外信息块3d2、延时外信息块0、延时外信息块0和延时外信息块0的延时外信息块流，第二数据提取器3从输入第二数据提取器3的延时外信息流的4个延时外信息块流中提取目标延时外信息块流，并将目标延时外信息块流输入多符号检测器4，该目标延时外信息块流为：包括按照从时刻4到时刻13依次排列的延时外信息块0、延时外信息块0、延时外信息块0、延时外信息块2a2、延时外信息块2b2、延时外信息块2c2、延时外信息块2d2、延时外信息块0、延时外信息块0和延时外信息块0的延时外信息块流。
4个多符号检测器中的每个多符号检测器根据各自连接的第二数据提取器反馈的目标延时外信息块流，对输入各自的卷积数据流进行多符号检测处理。例如，多符号检测器2根据第二数据提取器1反馈的目标延时外信息块流，对输入多符号检测器2的卷积数据流进行多符号检测处理；多符号检测器3根据第二数据提取器1反馈的目标延时外信息块流和第二数据提取器2反馈的目标延时外信息块流，对输入多符号检测器3的卷积数据流进行多符号检测处理；多符号检测器4根据第二数据提取器1反馈的目标延时外信息块流、第二数据提取器2反馈的目标延时外信息块流和第二数据提取器3反馈的目标延时外信息块流，对输入多符号检测器4的卷积数据流进行多符号检测处理。
需要说明的是，在本申请实施例中，多符号检测器可以基于最大似然序列检测(英文：Maimum-likelihood Sequence Detection；简称：MLSD)技术进行多符号检测，多符号检测器的主要思想可以为：将信息在信道中的传递过程看做状态转移过程，任意时刻的信息对应了一个状态，如图11所示，信道的状态被建模为4个状态，该4个状态分别为状态-1-1，状态-1+1，状态+1-1和状态+1+1，发送数据使信道的状态发生转移，例如，信道的初态(初始状态)为-1-1，数据11使信道从状态-1-1转移至状态+1+1，数据01使信道从状态+1+1转移至状态+1-1，依次类推。数据传输过程中干扰会使信道的状态转移发送错误，多符号检测器的主要作用就是将信道传输过程中的错误的状态转移纠正，从而恢复正确的数据。请参考图12，其示出了本申请实施例提供的多符号检测器的工作原理图，参见图12，分4中情况对多符号检测器的工作原理进行说明，第一种情况，接收比特(接收的数据比特)全部为位未知比特，假设此时多符号检测器进行多符号检测处理的误码率(英文：Bit Error Rate；简称：BER)为BER0，第二种情况，假设接收比特中，每4个接收比特中存在1个已知比特(该已知比特为正确的比特，可以是反馈模块反馈的比特)，此时多符号检测器 进行多符号检测处理的误码率为BER1，第三种情况，假设接收比特中，每4个接收比特中存在2个已知比特，此时多符号检测器进行多符号检测处理的误码率为BER2，第四种情况，假设接收比特中，每4个接收比特中存在3个已知比特，此时多符号检测器进行多符号检测处理的误码率为BER3，则BER0>BER1>BER2>BER3，因此，本申请实施例中，多符号检测器根据反馈的数据流进行多符号检测，可以减小多符号检测的误码率。本申请实施例提供的信号传输系统最终的误码率可以为sum(BER0～BER(N-1))/N，优于BER0，sum表示求和，N表示反馈的次数，BER(N-1)表示根据第N次反馈进行多符号检测的误码率。
需要说明的是，实际应用中，本申请实施例提供的信号传输系统可以包括发送端设备和接收端设备，上述编码器05、卷积模块04和DAC-07可以为发送端设备的处理器中的功能单元，相干接收器08、ADC-09、均衡模块01、反馈模块03、第一译码器02、第二译码器06和判决器10均可以为接收端设备的处理器中的功能单元。
综上所述，本申请实施例提供的信号传输系统，由于均衡模块包括至少两个多符号检测器，至少两个多符号检测器根据反馈数据流对卷积数据流进行多符号检测处理，且反馈数据流是根据译码数据流确定的，因此，可以在第一译码器与至少两个多符号检测器之间对信号进行反馈传输，而无需设置多个译码器，并在译码器与多符号检测器进行多次迭代过程，解决了传输信号的复杂度较高的问题，有助于降低传输信号的复杂度。
本申请实施例提供的信号传输系统，通过多环反馈，实现了对多符号检测器的辅助均衡，用有限的复杂度，降低了误码率，有效降低了系统复杂度，提升了系统性能。
本申请实施例还提供了一种信号传输方法，该信号传输方法可以用于图3或图4所示的信号传输系统，信号传输系统包括：均衡模块、第一译码器和反馈模块，均衡模块和第一译码器连接，均衡模块包括至少两个多符号检测器，反馈模块分别与第一译码器和至少两个多符号检测器连接，该信号传输方法包括：
步骤S1、均衡模块对卷积数据流进行均衡处理，得到均衡数据流，其中，在均衡模块对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器对输入各自的卷积数据流进行多符号检测处理。
步骤S2、第一译码器对均衡数据流进行译码，得到译码数据流。
步骤S3、反馈模块根据译码数据流确定反馈数据流，并将反馈数据流反馈至均衡模块的至少两个多符号检测器。
步骤S4、均衡模块根据反馈数据流对卷积数据流进行均衡处理，其中，在均衡模块对卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器根据反馈模块反馈的反馈数据流对输入各自的卷积数据流进行多符号检测处理。
可选地，信号传输系统还包括：卷积模块，卷积模块、均衡模块和第一译码器依次连接，该信号传输方法还包括：
卷积模块对输入自身的编码数据流进行卷积处理，得到卷积数据流；
编码数据流包括与连续的m个单位时间一一对应的m个编码码字，m个编码码字中的每个编码码字包括k+1个编码数据块，m>1，k>0，且m和k均为整数；
卷积数据流包括与连续的w个单位时间一一对应的w个卷积码字，w＝m+n*k，w个卷积码字中的每个卷积码字包括k+1个卷积数据块，每个卷积码字包括m个编码码字中的至 少一个编码码字中的1个编码数据块，n>0，且n为整数；
均衡数据流包括与连续的g个单位时间一一对应的g个均衡码字，g＝m+2n*k，g个均衡码字中的每个均衡码字包括k+1个均衡数据块，g个均衡码字中，与连续的m个单位时间对应的m个均衡码字与m个编码码字一一对应，m个均衡码字中的每个均衡码字包括对相应的编码码字中的所有编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块；
译码数据流包括与连续的g个单位时间一一对应的g个译码码字，g个译码码字是对g个均衡码字进行译码得到的，g个译码码字中的每个译码码字包括k+1个译码数据块。
可选地，卷积模块包括：第一分块器、第一合并器和k个第一延时器，k个第一延时器依次串联，且第一分块器、k个第一延时器和第一合并器依次串联，k个第一延时器中每个第一延时器的输出端分别与第一合并器的输入端连接，k个第一延时器中的首个第一延时器的输入端与第一合并器的输入端连接，
卷积模块对输入自身的编码数据流进行卷积处理，得到卷积数据流，包括：
第一分块器将m个编码码字中的每个编码码字分成k+1个编码数据块，并将k+1个编码数据块中的1个编码数据块输入第一合并器，k个编码数据块输入首个第一延时器；
k个第一延时器中的每个第一延时器对输入各自的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的1个延时编码数据块输入第一合并器，p-1个延时编码数据块输入各自连接的下一第一延时器，1≤p≤k，且p为整数；
第一合并器对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流。
可选地，第一合并器对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流，包括：第一合并器按照时间顺序对输入自身的m个编码码字对应的编码数据块进行合并，得到卷积数据流，卷积数据流包括w个卷积码字；在w个卷积码字中：
与w个单位时间中的前n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括i个第一卷积数据块和k+1-i个第二卷积数据块，其中，i个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的前n*i个单位时间对应的n*i个编码码字中的i个编码码字中的一个编码数据块，i个第一卷积数据块一一对应来自于i个编码码字，k+1-i个第二卷积数据块为初始数据块，k≥i>0，且i为整数；
与w个单位时间中的后n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括k+1-j个第一卷积数据块和j个第二卷积数据块，其中，k+1-j个第一卷积数据块中的每个第一卷积数据块是与m个单位时间中的后n*j个单位时间对应的n*j个编码码字中的k+1-j个编码码字中的一个编码数据块，k+1-j个第一卷积数据块一一对应来自于k+1-j个编码码字，j个第二编码数据块为初始数据块，k≥j>0，且j为整数；
中间单位时间中的每个单位时间对应的卷积码字包括k+1个第一卷积数据块，k+1个第一卷积数据块中的每个第一卷积数据块是m个编码码字中的k+1个编码码字中的一个编码数据块，k+1个第一卷积数据块一一对应来自于k+1个编码码字，中间单位时间为w个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，均衡模块包括：第二合并器、k个第二延时器、k+1个多符号检测器、k+1个 第二分块器和k+1个第一数据提取器，k+1个多符号检测器的输出端与k+1个第二分块器的输入端一一对应连接，k+1个第二分块器的输出端与k+1个第一数据提取器的输入端一一对应连接，k+1个第一数据提取器中的每个第一数据提取器的输出端与第二合并器的输入端连接，k个第二延时器依次串联，且k个第二延时器的输出端与k+1个多符号检测器中的k个多符号检测器的输入端一一对应连接，k个第二延时器中的首个第二延时器的输入端与k+1个多符号检测器除k个多符号检测器之外的多符号检测器的输入端连接，首个第二延时器的输入端还与卷积模块连接，
该信号传输方法还包括：卷积模块将卷积数据流分别输入首个第二延时器，以及与首个第二延时器的输入端连接的多符号检测器；步骤S4包括：
k个第二延时器中的每个第二延时器对输入各自的卷积数据流延时n个单位时间，得到延时卷积数据流，并将延时卷积数据流分别输入各自连接的多符号检测器和下一第二延时器，每个延时卷积数据流包括与连续的w个单位时间一一对应的w个延时卷积码字；
k+1个多符号检测器中的每个多符号检测器对输入各自的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将多符号检测卷积数据流输入各自连接的第二分块器，每个多符号检测卷积数据流包括与连续的w个单位时间一一对应的w个多符号检测卷积码字；
k+1个第二分块器中的每个第二分块器将输入各自的多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流，并将k+1个卷积数据块流输入各自连接的第一数据提取器；
k+1个第一数据提取器中的每个第一数据提取器从输入各自的k+1个卷积数据块流中，提取目标卷积数据块流，并将提取到的目标卷积数据块流输入第二合并器；
第二合并器对输入自身的k+1个目标卷积数据块流进行合并，得到均衡数据流。
可选地，第二合并器对输入自身的k+1个目标卷积数据块流进行合并，得到均衡数据流，包括：第二合并器按照时间顺序对输入自身的k+1个目标卷积数据块流进行合并，得到均衡数据流，均衡数据流包括k+1个目标卷积数据块流，每个目标卷积数据块流包括g个均衡码字中的每个均衡码字中的1个均衡数据块；其中，在g个均衡码字中：
与g个单位时间中的前n*k个单位时间和后n*k个单位时间中的每个单位时间对应的均衡码字包括k+1个初始数据块；
与g个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的k+1个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，中间单位时间为g个单位时间中，除前n*k个单位时间和后n*k个单位时间之外的单位时间。
可选地，反馈模块包括：k个第三延时器，k个第三延时器依次串联，第一译码器的输出端与k个第三延时器中的首个第三延时器的输入端连接，k个第三延时器中的第q个第三延时器的输出端与k+1个多符号检测器中的k+1-q个多符号检测器的输入端连接，k+1-q个多符号检测器为与k个第二延时器中的倒数k+1-q个第二延时器的输出端连接的多符号检测器，
步骤S3包括：k个第三延时器中的每个第三延时器对输入各自的译码数据流延时n个单位时间，得到延时译码数据流，并将延时译码数据流输入各自连接的多符号检测器和下一第三延时器，k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第三延时器 反馈的延时译码数据流，对输入各自的卷积数据流进行多符号检测处理。
可选地，译码数据流包括k+1个译码数据块流，k+1个译码数据块流是第一译码器对均衡数据流中的k+1个目标卷积数据块流进行译码处理得到的，反馈模块还包括：外信息计算器和k个第二数据提取器，外信息计算器的输入端分别与第一译码器的输出端和第一译码器的输入端连接，外信息计算器的输出端与k个第三延时器中的首个第三延时器连接，k个第三延时器中的每个第三延时器通过一个第二数据提取器与相应的多符号检测器的输入端连接，步骤S3包括：
外信息计算器根据第一译码器输出的译码数据流和输入第一译码器的均衡数据流计算第一译码器的外信息流，外信息流包括k+1个外信息块流，k+1个外信息块流是外信息计算器根据k+1个译码数据块流和k+1个目标卷积数据块流计算得到的；
k个第三延时器中的每个第三延时器对输入各自的外信息流延时n个单位时间，得到延时外信息流，并将延时外信息流输入各自连接的第二数据提取器和下一第三延时器，每个延时外信息流包括k+1个延时外信息块流；
k个第二数据提取器中的每个第二数据提取器从输入各自的延时外信息流的k+1个延时外信息块流中提取目标延时外信息块流，并将提取到的目标延时外信息块流输入各自连接的多符号检测器；
k+1个多符号检测器中的每个多符号检测器根据各自连接的第二数据提取器反馈的目标延时外信息块流，对输入各自的卷积数据流进行多符号检测处理。
可选地，第一分块器将m个编码码字中的每个编码码字分成k+1个编码数据块，并将k+1个编码数据块中的1个编码数据块输入第一合并器，k个编码数据块输入首个第一延时器，包括：
第一分块器将m个编码码字中的每个编码码字分成依次排列的k+1个编码数据块，并将k+1个编码数据块中的第1个编码数据块输入第一合并器，第2至第k+1个编码数据块输入首个第一延时器；
k个第一延时器中的每个第一延时器对输入各自的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的1个延时编码数据块输入第一合并器，p-1个延时编码数据块输入各自连接的下一第一延时器，包括：
k个第一延时器中的每个第一延时器对输入各自的依次排列的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将p个延时编码数据块中的第1个延时编码数据块输入第一合并器，第2至第p个延时编码数据块输入各自连接的下一第一延时器。
可选地，初始数据块中的数据为0。
可选地，信号传输系统还包括：编码器和第二译码器，编码器与卷积模块连接，第二译码器与第一译码器连接，该信号传输方法还包括：
编码器对输入自身的数据流进行编码，得到编码数据流；
第二译码器对译码数据流进行二次译码。
需要说明的是，本申请实施例提供的信号传输方法的具体实现过程在信号传输系统实施例中已经进行了详细描述，该信号传输方法的具体实现过程可以参考上述系统实施例，本实施例在此不再赘述。还需要说明的是，实际应用中，本申请提供的信号传输方法可以通过处理器执行程序来实现，此时，编码器、卷积模块和DAC可以为发送端设备的处理器 中的功能单元，发送端设备的处理器可以通过执行程序实现上述方法中编码器、卷积模块和DAC所对应的方法，相干接收器、ADC、均衡模块、反馈模块、第一译码器、第二译码器和判决器可以为接收端设备的处理器中的功能单元，接收端设备的处理器可以通过执行程序实现上述方法中相干接收器、ADC、均衡模块、反馈模块、第一译码器、第二译码器和判决器所对应的方法。
综上所述，本申请实施例提供的信号传输方法，由于均衡模块包括至少两个多符号检测器，至少两个多符号检测器根据反馈数据流对卷积数据流进行多符号检测处理，且反馈数据流是根据译码数据流确定的，因此，可以在第一译码器与至少两个多符号检测器之间对信号进行反馈传输，而无需设置多个译码器，并在译码器与多符号检测器进行多次迭代过程，解决了传输信号的复杂度较高的问题，有助于降低传输信号的复杂度。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种信号传输系统，其特征在于，所述信号传输系统包括：均衡模块、第一译码器和反馈模块，所述均衡模块和所述第一译码器连接，所述均衡模块包括至少两个多符号检测器，所述反馈模块分别与所述第一译码器和所述至少两个多符号检测器连接，
    所述均衡模块用于对卷积数据流进行均衡处理，得到均衡数据流，其中，在所述均衡模块对所述卷积数据流进行均衡处理的过程中，所述至少两个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理；
    所述第一译码器用于对所述均衡数据流进行译码，得到译码数据流；
    所述反馈模块用于根据所述译码数据流确定反馈数据流，并将所述反馈数据流反馈至所述均衡模块的至少两个多符号检测器；
    所述均衡模块还用于根据所述反馈数据流对所述卷积数据流进行均衡处理，其中，在所述均衡模块对所述卷积数据流进行均衡处理的过程中，所述至少两个多符号检测器中的每个多符号检测器用于根据所述反馈模块反馈的反馈数据流对输入各自的卷积数据流进行多符号检测处理。
  2. 根据权利要求1所述的信号传输系统，其特征在于，所述信号传输系统还包括：卷积模块，所述卷积模块、所述均衡模块和所述第一译码器依次连接，
    所述卷积模块用于对输入自身的编码数据流进行卷积处理，得到所述卷积数据流；
    所述编码数据流包括与连续的m个单位时间一一对应的m个编码码字，所述m个编码码字中的每个编码码字包括k+1个编码数据块，m>1，k>0，且m和k均为整数；
    所述卷积数据流包括与连续的w个单位时间一一对应的w个卷积码字，w＝m+n*k，所述w个卷积码字中的每个卷积码字包括k+1个卷积数据块，所述每个卷积码字包括所述m个编码码字中的至少一个编码码字中的1个编码数据块，n>0，且n为整数；
    所述均衡数据流包括与连续的g个单位时间一一对应的g个均衡码字，g＝m+2n*k，所述g个均衡码字中的每个均衡码字包括k+1个均衡数据块，所述g个均衡码字中，与连续的m个单位时间对应的m个均衡码字与所述m个编码码字一一对应，所述m个均衡码字中的每个均衡码字包括对相应的编码码字中的所有编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块；
    所述译码数据流包括与连续的g个单位时间一一对应的g个译码码字，所述g个译码码字是对所述g个均衡码字进行译码得到的，所述g个译码码字中的每个译码码字包括k+1个译码数据块。
  3. 根据权利要求2所述的信号传输系统，其特征在于，所述卷积模块包括：第一分块器、第一合并器和k个第一延时器，
    所述k个第一延时器依次串联，且所述第一分块器、所述k个第一延时器和所述第一合并器依次串联，所述k个第一延时器中每个第一延时器的输出端分别与所述第一合并器的输入端连接，所述k个第一延时器中的首个第一延时器的输入端与所述第一合并器的输入端连接，
    所述第一分块器用于将所述m个编码码字中的每个编码码字分成k+1个编码数据块，并将所述k+1个编码数据块中的1个编码数据块输入所述第一合并器，k个编码数据块输入所述首个第一延时器；
    所述k个第一延时器中的每个第一延时器用于对输入各自的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将所述p个延时编码数据块中的1个延时编码数据块输入所述第一合并器，p-1个延时编码数据块输入各自连接的下一第一延时器，1≤p≤k，且p为整数；
    所述第一合并器用于对输入自身的所述m个编码码字对应的编码数据块进行合并，得到所述卷积数据流。
  4. 根据权利要求3所述的信号传输系统，其特征在于，
    所述第一合并器用于按照时间顺序对输入自身的m个编码码字对应的编码数据块进行合并，得到所述卷积数据流，所述卷积数据流包括w个卷积码字；
    在所述w个卷积码字中：
    与所述w个单位时间中的前n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括i个第一卷积数据块和k+1-i个第二卷积数据块，其中，所述i个第一卷积数据块中的每个第一卷积数据块是与所述m个单位时间中的前n*i个单位时间对应的n*i个编码码字中的i个编码码字中的一个编码数据块，所述i个第一卷积数据块一一对应来自于所述i个编码码字，所述k+1-i个第二卷积数据块为初始数据块，k≥i>0，且i为整数；
    与所述w个单位时间中的后n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括k+1-j个第一卷积数据块和j个第二卷积数据块，其中，所述k+1-j个第一卷积数据块中的每个第一卷积数据块是与所述m个单位时间中的后n*j个单位时间对应的n*j个编码码字中的k+1-j个编码码字中的一个编码数据块，所述k+1-j个第一卷积数据块一一对应来自于所述k+1-j个编码码字，所述j个第二编码数据块为所述初始数据块，k≥j>0，且j为整数；
    中间单位时间中的每个单位时间对应的卷积码字包括k+1个第一卷积数据块，所述k+1个第一卷积数据块中的每个第一卷积数据块是所述m个编码码字中的k+1个编码码字中的一个编码数据块，所述k+1个第一卷积数据块一一对应来自于所述k+1个编码码字，所述中间单位时间为所述w个单位时间中，除所述前n*k个单位时间和所述后n*k个单位时间之外的单位时间。
  5. 根据权利要求4所述的信号传输系统，其特征在于，所述均衡模块包括：第二合并器、k个第二延时器、k+1个多符号检测器、k+1个第二分块器和k+1个第一数据提取器，
    所述k+1个多符号检测器的输出端与所述k+1个第二分块器的输入端一一对应连接，所述k+1个第二分块器的输出端与所述k+1个第一数据提取器的输入端一一对应连接，所述k+1个第一数据提取器中的每个第一数据提取器的输出端与所述第二合并器的输入端连接，所述k个第二延时器依次串联，且所述k个第二延时器的输出端与所述k+1个多符号检测器中的k个多符号检测器的输入端一一对应连接，所述k个第二延时器中的首个第二延时器的输入端 与所述k+1个多符号检测器除所述k个多符号检测器之外的多符号检测器的输入端连接，所述首个第二延时器的输入端还与所述卷积模块连接，
    所述卷积模块用于将所述卷积数据流分别输入所述首个第二延时器，以及与首个第二延时器的输入端连接的多符号检测器；
    所述k个第二延时器中的每个第二延时器用于对输入各自的卷积数据流延时n个单位时间，得到延时卷积数据流，并将所述延时卷积数据流分别输入各自连接的多符号检测器和下一第二延时器，每个延时卷积数据流包括与连续的w个单位时间一一对应的w个延时卷积码字；
    所述k+1个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，并将所述多符号检测卷积数据流输入各自连接的第二分块器，每个多符号检测卷积数据流包括与连续的w个单位时间一一对应的w个多符号检测卷积码字；
    所述k+1个第二分块器中的每个第二分块器用于将输入各自的多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流，并将所述k+1个卷积数据块流输入各自连接的第一数据提取器；
    所述k+1个第一数据提取器中的每个第一数据提取器用于从输入各自的k+1个卷积数据块流中，提取目标卷积数据块流，并将提取到的目标卷积数据块流输入所述第二合并器；
    所述第二合并器用于对输入自身的k+1个目标卷积数据块流进行合并，得到所述均衡数据流。
  6. 根据权利要求5所述的信号传输系统，其特征在于，
    所述第二合并器用于按照时间顺序对输入自身的k+1个目标卷积数据块流进行合并，得到所述均衡数据流，所述均衡数据流包括k+1个目标卷积数据块流，每个所述目标卷积数据块流包括所述g个均衡码字中的每个均衡码字中的1个均衡数据块；
    其中，在所述g个均衡码字中：
    与所述g个单位时间中的前n*k个单位时间和后n*k个单位时间中的每个单位时间对应的均衡码字包括k+1个初始数据块；
    与所述g个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的k+1个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，所述中间单位时间为所述g个单位时间中，除所述前n*k个单位时间和所述后n*k个单位时间之外的单位时间。
  7. 根据权利要求6所述的信号传输系统，其特征在于，所述反馈模块包括：k个第三延时器，
    所述k个第三延时器依次串联，所述第一译码器的输出端与所述k个第三延时器中的首个第三延时器的输入端连接，所述k个第三延时器中的第q个第三延时器的输出端与所述k+1个多符号检测器中的k+1-q个多符号检测器的输入端连接，所述k+1-q个多符号检测器为与所述k个第二延时器中的倒数k+1-q个第二延时器的输出端连接的多符号检测器，
    所述k个第三延时器中的每个第三延时器用于对输入各自的译码数据流延时n个单位时 间，得到延时译码数据流，并将所述延时译码数据流输入各自连接的多符号检测器和下一第三延时器；
    所述k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第三延时器反馈的延时译码数据流，对输入各自的卷积数据流进行多符号检测处理。
  8. 根据权利要求7所述的信号传输系统，其特征在于，所述译码数据流包括k+1个译码数据块流，所述k+1个译码数据块流是所述第一译码器对所述均衡数据流中的k+1个目标卷积数据块流进行译码处理得到的，
    所述反馈模块还包括：外信息计算器和k个第二数据提取器，
    所述外信息计算器的输入端分别与所述第一译码器的输出端和所述第一译码器的输入端连接，所述外信息计算器的输出端与所述k个第三延时器中的首个第三延时器连接，所述k个第三延时器中的每个第三延时器通过一个第二数据提取器与相应的多符号检测器的输入端连接，
    所述外信息计算器用于根据所述第一译码器输出的译码数据流和输入所述第一译码器的均衡数据流计算所述第一译码器的外信息流，所述外信息流包括k+1个外信息块流，所述k+1个外信息块流是所述外信息计算器根据所述k+1个译码数据块流和所述k+1个目标卷积数据块流计算得到的；
    所述k个第三延时器中的每个第三延时器用于对输入各自的外信息流延时n个单位时间，得到延时外信息流，并将所述延时外信息流输入各自连接的第二数据提取器和下一第三延时器，每个延时外信息流包括k+1个延时外信息块流；
    所述k个第二数据提取器中的每个第二数据提取器用于从输入各自的延时外信息流的k+1个延时外信息块流中提取目标延时外信息块流，并将提取到的目标延时外信息块流输入各自连接的多符号检测器；
    所述k+1个多符号检测器中的每个多符号检测器用于根据各自连接的第二数据提取器反馈的目标延时外信息块流，对输入各自的卷积数据流进行多符号检测处理。
  9. 根据权利要求3所述的信号传输系统，其特征在于，
    所述第一分块器具体用于：将所述m个编码码字中的每个编码码字分成依次排列的k+1个编码数据块，并将所述k+1个编码数据块中的第1个编码数据块输入所述第一合并器，第2至第k+1个编码数据块输入所述首个第一延时器；
    所述k个第一延时器中的每个第一延时器具体用于：对输入各自的依次排列的p个编码数据块延时n个单位时间，得到p个延时编码数据块，并将所述p个延时编码数据块中的第1个延时编码数据块输入所述第一合并器，第2至第p个延时编码数据块输入各自连接的下一第一延时器。
  10. 根据权利要求6所述的信号传输系统，其特征在于，所述初始数据块中的数据为0。
  11. 根据权利要求1至10任一所述的信号传输系统，其特征在于，所述信号传输系统还包括：编码器和第二译码器，所述编码器与所述卷积模块连接，所述第二译码器与所述第一 译码器连接，
    所述编码器用于对输入自身的数据流进行编码，得到所述编码数据流；
    所述第二译码器用于对所述译码数据流进行二次译码。
  12. 一种信号传输方法，其特征在于，所述信号传输方法包括：
    对卷积数据流进行均衡处理，得到均衡数据流，其中，在对所述卷积数据流进行均衡处理的过程中，至少两个多符号检测器中的每个多符号检测器用于对输入各自的卷积数据流进行多符号检测处理；
    对所述均衡数据流进行译码，得到译码数据流；
    根据所述译码数据流确定反馈数据流；
    根据所述反馈数据流对所述卷积数据流进行均衡处理，其中，在对所述卷积数据流进行均衡处理的过程中，所述至少两个多符号检测器中的每个多符号检测器用于根据所述反馈数据流对输入各自的卷积数据流进行多符号检测处理。
  13. 根据权利要求12所述的信号传输方法，其特征在于，所述信号传输方法还包括：
    对编码数据流进行卷积处理，得到所述卷积数据流；
    所述编码数据流包括与连续的m个单位时间一一对应的m个编码码字，所述m个编码码字中的每个编码码字包括k+1个编码数据块，m>1，k>0，且m和k均为整数；
    所述卷积数据流包括与连续的w个单位时间一一对应的w个卷积码字，w＝m+n*k，所述w个卷积码字中的每个卷积码字包括k+1个卷积数据块，所述每个卷积码字包括所述m个编码码字中的至少一个编码码字中的1个编码数据块，n>0，且n为整数；
    所述均衡数据流包括与连续的g个单位时间一一对应的g个均衡码字，g＝m+2n*k，所述g个均衡码字中的每个均衡码字包括k+1个均衡数据块，所述g个均衡码字中，与连续的m个单位时间对应的m个均衡码字与所述m个编码码字一一对应，所述m个均衡码字中的每个均衡码字包括对相应的编码码字中的所有编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块；
    所述译码数据流包括与连续的g个单位时间一一对应的g个译码码字，所述g个译码码字是对所述g个均衡码字进行译码得到的，所述g个译码码字中的每个译码码字包括k+1个译码数据块。
  14. 根据权利要求13所述的信号传输方法，其特征在于，所述对编码数据流进行卷积处理，得到所述卷积数据流，包括：
    将所述m个编码码字中的每个编码码字分成k+1个编码数据块；
    对p个编码数据块延时n个单位时间，得到p个延时编码数据块，1≤p≤k，且p为整数；
    对所述m个编码码字对应的编码数据块进行合并，得到所述卷积数据流。
  15. 根据权利要求14所述的信号传输方法，其特征在于，对所述m个编码码字对应的编码数据块进行合并，得到所述卷积数据流，包括：
    按照时间顺序对所述m个编码码字对应的编码数据块进行合并，得到所述卷积数据流， 所述卷积数据流包括w个卷积码字；
    在所述w个卷积码字中：
    与所述w个单位时间中的前n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括i个第一卷积数据块和k+1-i个第二卷积数据块，其中，所述i个第一卷积数据块中的每个第一卷积数据块是与所述m个单位时间中的前n*i个单位时间对应的n*i个编码码字中的i个编码码字中的一个编码数据块，所述i个第一卷积数据块一一对应来自于所述i个编码码字，所述k+1-i个第二卷积数据块为初始数据块，k≥i>0，且i为整数；
    与所述w个单位时间中的后n*k个单位时间对应的n*k卷积码字包括k个卷积码字组，每个卷积码字组包括n个卷积码字，每个卷积码字包括k+1-j个第一卷积数据块和j个第二卷积数据块，其中，所述k+1-j个第一卷积数据块中的每个第一卷积数据块是与所述m个单位时间中的后n*j个单位时间对应的n*j个编码码字中的k+1-j个编码码字中的一个编码数据块，所述k+1-j个第一卷积数据块一一对应来自于所述k+1-j个编码码字，所述j个第二编码数据块为所述初始数据块，k≥j>0，且j为整数；
    中间单位时间中的每个单位时间对应的卷积码字包括k+1个第一卷积数据块，所述k+1个第一卷积数据块中的每个第一卷积数据块是所述m个编码码字中的k+1个编码码字中的一个编码数据块，所述k+1个第一卷积数据块一一对应来自于所述k+1个编码码字，所述中间单位时间为所述w个单位时间中，除所述前n*k个单位时间和所述后n*k个单位时间之外的单位时间。
  16. 根据权利要求15所述的信号传输方法，其特征在于，所述对卷积数据流进行均衡处理，得到均衡数据流，包括：
    对所述卷积数据流延时n个单位时间，得到延时卷积数据流，每个延时卷积数据流包括与连续的w个单位时间一一对应的w个延时卷积码字；
    对所述卷积数据流进行多符号检测处理，得到多符号检测卷积数据流，每个多符号检测卷积数据流包括与连续的w个单位时间一一对应的w个多符号检测卷积码字；
    将所述多符号检测卷积数据流中的每个多符号卷积码字分成k+1个卷积数据块，得到k+1个卷积数据块流；
    从所述每个多符号卷积码字的k+1个卷积数据块流中，提取目标卷积数据块流；
    对所述目标卷积数据块流进行合并，得到所述均衡数据流。
  17. 根据权利要求16所述的信号传输方法，其特征在于，
    所述对所述目标卷积数据块流进行合并，得到所述均衡数据流，包括：
    按照时间顺序对k+1个目标卷积数据块流进行合并，得到所述均衡数据流，所述均衡数据流包括k+1个目标卷积数据块流，每个所述目标卷积数据块流包括所述g个均衡码字中的每个均衡码字中的1个均衡数据块；
    其中，在所述g个均衡码字中：
    与所述g个单位时间中的前n*k个单位时间和后n*k个单位时间中的每个单位时间对应的均衡码字包括k+1个初始数据块；
    与所述g个单位时间中的中间单位时间中的每个单位时间对应的均衡码字包括：对相应的编码码字中的k+1个编码数据块依次进行卷积处理和均衡处理之后得到的均衡数据块，所述中间单位时间为所述g个单位时间中，除所述前n*k个单位时间和所述后n*k个单位时间之外的单位时间。
  18. 根据权利要求17所述的信号传输方法，其特征在于，所述根据所述译码数据流确定反馈数据流，包括：
    对所述译码数据流延时n个单位时间，得到延时译码数据流；
    将所述延时译码数据流确定为所述反馈数据流。
  19. 根据权利要求18所述的信号传输方法，其特征在于，所述译码数据流包括k+1个译码数据块流，所述k+1个译码数据块流是对所述均衡数据流中的k+1个目标卷积数据块流进行译码处理得到的，
    所述根据所述译码数据流确定反馈数据流，包括：
    根据所述译码数据流和所述均衡数据流计算外信息流，所述外信息流包括k+1个外信息块流，所述k+1个外信息块流是根据所述k+1个译码数据块流和所述k+1个目标卷积数据块流计算得到的；
    对所述外信息流延时n个单位时间，得到延时外信息流；
    将所述延时外信息流确定为所述反馈数据流。
  20. 根据权利要求14所述的信号传输方法，其特征在于，
    所述将所述m个编码码字中的每个编码码字分成k+1个编码数据块，包括：
    将所述m个编码码字中的每个编码码字分成依次排列的k+1个编码数据块；
    所述对p个编码数据块延时n个单位时间，得到p个延时编码数据块，包括：
    对依次排列的p个编码数据块延时n个单位时间，得到p个延时编码数据块。
  21. 根据权利要求17所述的信号传输方法，其特征在于，所述初始数据块中的数据为0。
PCT/CN2017/097185 2017-08-11 2017-08-11 信号传输方法及系统 WO2019028868A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2017/097185 WO2019028868A1 (zh) 2017-08-11 2017-08-11 信号传输方法及系统
EP17920755.0A EP3657697B1 (en) 2017-08-11 2017-08-11 Signal transmission method and system
CN201780085583.4A CN110249554B (zh) 2017-08-11 2017-08-11 信号传输方法及系统
US16/786,566 US10958488B2 (en) 2017-08-11 2020-02-10 Signal transmission method and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/097185 WO2019028868A1 (zh) 2017-08-11 2017-08-11 信号传输方法及系统

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/786,566 Continuation US10958488B2 (en) 2017-08-11 2020-02-10 Signal transmission method and system

Publications (1)

Publication Number Publication Date
WO2019028868A1 true WO2019028868A1 (zh) 2019-02-14

Family

ID=65272889

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/097185 WO2019028868A1 (zh) 2017-08-11 2017-08-11 信号传输方法及系统

Country Status (4)

Country Link
US (1) US10958488B2 (zh)
EP (1) EP3657697B1 (zh)
CN (1) CN110249554B (zh)
WO (1) WO2019028868A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113055332B (zh) * 2021-03-17 2024-07-26 上海雷骥电子科技有限公司 一种pcm/fm和gmsk复用接收机

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004040789A2 (en) * 2002-10-29 2004-05-13 Axiocom Inc. Cascade filter receiver for ds-cdma communication systems
WO2006087283A1 (en) * 2005-02-18 2006-08-24 Nokia Siemens Networks Gmbh & Co. Kg Method & apparatus for demodulating an optical differential phase-shift keying signal
CN102394843A (zh) * 2011-06-30 2012-03-28 华为技术有限公司 一种纠错及反馈均衡控制方法和装置
CN103384975A (zh) * 2013-01-14 2013-11-06 华为技术有限公司 译码方法和装置
CN105610517A (zh) * 2014-11-14 2016-05-25 中兴通讯股份有限公司 相干光接收机的迭代后均衡

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7787522B2 (en) * 2003-04-11 2010-08-31 Telefonaktiebolaget Lm Ericsson (Publ) Joint multi-code detectors in CDMA communications system
US8006163B2 (en) * 2006-12-27 2011-08-23 Nec Laboratories America, Inc. Polarization mode dispersion compensation using BCJR equalizer and iterative LDPC decoding
US8611480B1 (en) * 2007-03-26 2013-12-17 Marvell International Ltd. Optimal decoding of transmit diversity code with varying channel characteristics
US8185796B2 (en) * 2008-08-20 2012-05-22 Nec Laboratories America, Inc. Mitigation of fiber nonlinearities in multilevel coded-modulation schemes
US8175466B2 (en) 2009-03-10 2012-05-08 Nec Laboratories America, Inc. Methods and systems for polarization multiplexed multilevel modulation for optical communication
KR20150097048A (ko) * 2014-02-17 2015-08-26 한국전자통신연구원 Ｆｔｎ 기반 신호 수신 장치 및 그의 신호 복호화 방법
US10257105B2 (en) * 2016-12-02 2019-04-09 At&T Intellectual Property I, L.P. Facilitation of physical layer design for 5G networks or other next generation networks

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004040789A2 (en) * 2002-10-29 2004-05-13 Axiocom Inc. Cascade filter receiver for ds-cdma communication systems
WO2006087283A1 (en) * 2005-02-18 2006-08-24 Nokia Siemens Networks Gmbh & Co. Kg Method & apparatus for demodulating an optical differential phase-shift keying signal
CN102394843A (zh) * 2011-06-30 2012-03-28 华为技术有限公司 一种纠错及反馈均衡控制方法和装置
CN103384975A (zh) * 2013-01-14 2013-11-06 华为技术有限公司 译码方法和装置
CN105610517A (zh) * 2014-11-14 2016-05-25 中兴通讯股份有限公司 相干光接收机的迭代后均衡

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3657697A4 *

Also Published As

Publication number Publication date
CN110249554A (zh) 2019-09-17
EP3657697A4 (en) 2020-09-02
US10958488B2 (en) 2021-03-23
EP3657697A1 (en) 2020-05-27
CN110249554B (zh) 2020-08-07
US20200186402A1 (en) 2020-06-11
EP3657697B1 (en) 2021-12-22

Similar Documents

Publication Publication Date Title
US10659192B2 (en) Apparatus and method for communicating data over an optical channel
US7331012B2 (en) System and method for iterative decoding of Reed-Muller codes
EP1645112A2 (en) Method and apparatus for delayed recursion decoder
JP2013150350A (ja) Ｈｄｔｖ受信器用連結等化器／トレリス復号器アーキテクチャ
EP3480960B1 (en) Error correction decoding device, and optical transmission/reception device
WO2019028868A1 (zh) 信号传输方法及系统
CN110808772B (zh) 用于近月空间通信的接收机的基带信号处理方法及装置
CN113055319B (zh) 一种信号均衡方法和装置
US10177876B2 (en) Sequence detector
KR100891676B1 (ko) 송/수신 시스템 및 데이터 처리 방법
US20110243213A1 (en) Receivers for Processing Vestigial Sideband Signals and Processing Methods Thereof
WO2018059057A1 (zh) 一种适用于OvXDM系统的软值提取方法、装置及OvXDM系统
KR100720593B1 (ko) 송/수신 시스템 및 데이터 처리 방법
KR100720561B1 (ko) 송/수신 시스템 및 데이터 처리 방법
KR100897811B1 (ko) 송/수신 시스템 및 데이터 처리 방법
KR100860036B1 (ko) 송/수신 시스템 및 데이터 처리 방법
KR100995052B1 (ko) 송/수신 시스템 및 데이터 처리 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17920755

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2017920755

Country of ref document: EP

Effective date: 20200220