WO2019023943A1 - 流道结构器件及其制造方法 - Google Patents

流道结构器件及其制造方法 Download PDF

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Publication number
WO2019023943A1
WO2019023943A1 PCT/CN2017/095498 CN2017095498W WO2019023943A1 WO 2019023943 A1 WO2019023943 A1 WO 2019023943A1 CN 2017095498 W CN2017095498 W CN 2017095498W WO 2019023943 A1 WO2019023943 A1 WO 2019023943A1
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Prior art keywords
layer
flow channel
material layer
substrate
sacrificial
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English (en)
French (fr)
Inventor
云全新
林建勋
董龙涛
汪天书
朱国丽
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BGI Shenzhen Co Ltd
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BGI Shenzhen Co Ltd
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Priority to CN201780090943.XA priority Critical patent/CN110770160B/zh
Priority to PCT/CN2017/095498 priority patent/WO2019023943A1/zh
Publication of WO2019023943A1 publication Critical patent/WO2019023943A1/zh
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate

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  • the present invention relates to the field of semiconductor technology, and in particular, to a flow channel structure device and a method of fabricating the same.
  • Micro-nano flow control analysis technology based on micro-nano flow channel is being studied and applied more and more in the fields of biochemical analysis and gene sequencing.
  • the combination of micro-nano channel devices and integrated circuits (ICs) will also help to improve the automation and miniaturization of micro-analysis systems and better expand their application space.
  • electrode materials need to be embedded in the micro-nano flow channels, and in some designs, nano-flow channels with high aspect ratios are required.
  • electron beam lithography or laser lithography may be employed, and an anisotropic etching process is combined to realize a nano flow channel.
  • direct electron beam or laser lithography methods are inefficient, have poor dimensional adjustability, and are difficult to achieve high aspect ratios on metallic materials, usually only about one.
  • the side wall method can also be used to implement the above micro-nano flow path structure.
  • the sidewall method must rely on the side wall support structure of the semiconductor material to achieve structural interconnection and signal extraction, which will bring more parasitic effects, and ultimately affect the quality of the detection signal, and the process thermal budget is high, which is not conducive to integration with CMOS chips.
  • most electrode extractions in the prior art rely on spliced metal interconnects (e.g., typically aluminum and copper) or semiconductor interconnects (e.g., typically polysilicon) to form an alloy structure with the electrode material.
  • the alloy structure has the following disadvantages: (1) The alloy process requires an additional heat treatment process, which will increase the process heat budget, which is not conducive to process integration on the IC chip.
  • a typical polysilicon interconnect process for example, a polysilicon deposition process is required (the temperature is usually high). At 600 ° C), ion implantation and activation (usually above 550 ° C) and metal semiconductor alloys (usually above 400 ° C) and other high thermal budget technology; (2) alloy body will introduce additional contact resistance, which Will reduce device performance.
  • the nanogap structure can also be realized by adjusting the metal sputtering angle.
  • the particle sputtering direction is at an angle to the surface of the substrate substrate, and the groove can be prepared in advance by adjusting the angle.
  • a dead angle of sputtering is generated at the bottom to obtain a nano-gap flow path structure, but process controllability and dimensional adjustability are poor.
  • the inventors of the present invention have found that there is a problem in the above prior art, and thus propose a new technical solution to at least one of the problems.
  • a method of fabricating a flow path structure device comprising: providing a substrate, the substrate comprising a first portion and a second portion abutting the first portion; on the substrate Forming a patterned first sacrificial layer, the first sacrificial layer covering the second portion and exposing the first portion; forming a first structural layer on the first portion of the substrate and the first sacrificial layer; After forming the first structural layer, performing a first polishing process to expose the first sacrificial layer; removing the first sacrificial layer to expose an upper surface of the second portion of the substrate and the first structure a side surface of the layer; a second sacrificial layer is formed on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer; Forming a second structural layer on the second portion, the second sacrificial layer and the first structural layer; after forming the second structural layer
  • the first structural layer and the second structural layer are also exposed; before the second sacrificial layer is removed by a selective etching process, the method also includes forming a cap layer on the second sacrificial layer, the first structural layer, and the second structural layer.
  • the forming the first structural layer includes: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers the first a side of a sacrificial layer; and forming a first support layer on the first material layer; wherein the first structural layer comprises: the first material layer and the first support layer;
  • the step of forming a structural layer includes: forming a second material layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer, the second material layer covering the second sacrificial layer Forming a second support layer on the second material layer; wherein the second structural layer comprises: the second material layer and the second support layer.
  • a side of the exposed first structural layer is a side of the first material layer;
  • the second sacrificial layer covers the exposed side of the first material layer.
  • the first material layer is further exposed, The first support layer, the second material layer, and the second support layer; before removing the second sacrificial layer by a selective etching process, the method further includes: at the second sacrificial layer a cap layer is formed on the first material layer, the first support layer, the second material layer, and the second support layer.
  • the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness ranging from 1 nanometer to 10 micrometers.
  • a selective etchant is implanted from an edge of the second sacrificial layer to remove the second sacrificial layer.
  • the method before removing the second sacrificial layer by a selective etch process, the method further includes: etching the capping layer to form through the capping layer and exposing the second sacrificial a via hole of the layer; wherein, in the step of removing the second sacrificial layer by a selective etching process, a selective etching liquid is injected from the via hole to remove the second sacrificial layer.
  • a portion of the first material layer is between the first support layer and the flow channel, and another portion of the first material layer is between the first support layer and the substrate Between the first portions of the second material layer between the second support layer and the flow channel, and another portion of the second material layer between the second support layer and the substrate Between the second part.
  • the material of the first material layer comprises: a metal material or a semiconductor material; the material of the second material layer comprises: a metal material or a semiconductor material; wherein the first material layer is in the a portion between the first support layer and the flow channel as a first electrode of the flow channel structure device; between the first support layer and the first portion of the substrate a portion as a first lead of the first electrode; a portion of the second material layer between the second support layer and the flow channel as a second electrode of the flow channel structure device; A portion of the two material layers between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
  • the material of the first material layer and the material of the second material layer respectively comprise: an insulating dielectric material.
  • the thickness of the first sacrificial layer is determined according to the height of the desired flow channel; the thickness of the first sacrificial layer ranges from 100 nanometers to 100 micrometers.
  • the thickness of the second sacrificial layer is determined according to the width of the desired flow channel; the thickness of the second sacrificial layer ranges from 0.1 nanometers to 1 micrometer.
  • the first material layer has a thickness ranging from 1 nanometer to 500 nanometers; the first branch The thickness of the interlayer ranges from 100 nanometers to 100 micrometers; the thickness of the second material layer ranges from 1 nanometer to 500 nanometers; and the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.
  • a patterned first sacrificial layer is formed on a substrate; a first structural layer is formed on the first portion of the substrate and the first sacrificial layer; a first polishing process is performed to expose the first sacrificial layer; a sacrificial layer to expose an upper surface of the second portion of the substrate and a side of the first structural layer; a second sacrificial layer formed on a portion of the upper surface of the second portion of the substrate; the second portion and the second portion of the substrate Forming a second structural layer on the sacrificial layer and the first structural layer; performing a second polishing process to expose the second sacrificial layer after forming the second structural layer; and removing the second sacrificial layer by a selective etching process to form Flow path.
  • the above manufacturing method of the present invention can form a flow path structure device having a vertical flow path, and the above manufacturing method can reduce the process heat budget and facilitate integration of the flow path structure device and the CMOS chip.
  • the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high aspect ratio flow path structure can be realized.
  • the first material layer may include the first electrode and the first lead
  • the second material layer may include the second electrode and the first
  • a flow path structure device comprising: a substrate comprising a first portion and a second portion abutting the first portion; a first structure on the substrate a layer and a second structural layer; wherein the first structural layer comprises: a first material layer on the first portion of the substrate and a first support layer on the first material layer, the second The structural layer includes: a second material layer on the second portion of the substrate and a second support layer on the second material layer; between the first material layer and the second material layer a flow channel; the first support layer and the second support layer are respectively on opposite sides of the flow channel; wherein a portion of the first material layer is in the first support layer and the flow channel Another portion of the first material layer between the first support layer and the first portion of the substrate; a portion of the second material layer between the second support layer and the flow channel Another portion of the second material layer between the second support layer and the second portion of the substrate Room.
  • the flow channel structure device further includes: a capping layer covering the first material layer, the first support layer, the second material layer, and the second support layer; The cap layer is covered in the Above the flow path.
  • the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness ranging from 1 nanometer to 10 micrometers.
  • the flow channel structure device further includes a through hole penetrating the cap layer and communicating to the flow channel.
  • the material of the first material layer comprises: a metal material or a semiconductor material; the material of the second material layer comprises: a metal material or a semiconductor material; wherein the first material layer is in the a portion between the first support layer and the flow channel as a first electrode of the flow channel structure device; between the first support layer and the first portion of the substrate a portion as a first lead of the first electrode; a portion of the second material layer between the second support layer and the flow channel as a second electrode of the flow channel structure device; A portion of the two material layers between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
  • the material of the first material layer and the material of the second material layer respectively comprise: an insulating dielectric material.
  • the flow channel has a height ranging from 100 nanometers to 100 micrometers; the flow channel has a width ranging from 0.1 nanometers to 1 micrometer.
  • the first material layer has a thickness ranging from 1 nanometer to 500 nanometers; the first support layer has a thickness ranging from 100 nanometers to 100 micrometers; and the second material layer has a thickness ranging from 1 nanometer to 1 nanometer. Up to 500 nm; the second support layer has a thickness ranging from 100 nm to 100 microns.
  • the flow path structure device of the above embodiment of the present invention has a vertical flow path, which can increase the manufacturing density of the flow path on the chip, reduce manufacturing and application costs, and the like.
  • the above-described flow path structure device can realize a flow structure of a high aspect ratio.
  • the first material layer may include the first electrode and the first lead
  • the second material layer may include the second electrode and the first
  • a flow path sensor comprising: a flow path structure device as described above.
  • a biochemical analysis apparatus comprising: a flow path structure device as described above.
  • a chip for molecular detection comprising: a flow path structure device, a signal collection unit, and a signal processing unit as described above; wherein a sample to be detected is added to the flow path In the flow channel of the structural device, in the case where the electrode of the flow channel structure device is electrically excited, the target molecule in the sample to be detected generates an electrical signal or an optical signal under electrical excitation; the signal collecting unit is used for Collecting the electrical signal or the optical signal and transmitting the electrical signal or the optical signal to the signal processing unit; the signal processing unit is configured to perform signal processing on the electrical signal or the optical signal Identifying information about the target molecule.
  • a method of molecular detection comprising: performing molecular detection using a chip as described above.
  • the step of performing molecular detection using the chip comprises: processing a sample to be detected; adding the sample to be detected to the chip; applying an electrode in a flow channel structure device in the chip Electrically exciting such that the target molecule in the sample to be detected generates an electrical signal or an optical signal under electrical excitation; and the signal processing unit of the chip obtains the electrical signal or the light through the signal collecting unit And signaling the electrical signal or the optical signal to identify information of the target molecule.
  • the application of molecular detection is realized by using a chip including the flow path structure device of the embodiment of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating a flow path structure device in accordance with one embodiment of the present invention.
  • FIGS 2 to 10 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • FIG. 11 is a view schematically showing a manufacturing process of a flow path structure device according to another embodiment of the present invention. A cross-sectional view of the structure of the stages.
  • Figure 12 is a plan view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 13 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • FIG 14 to 22 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 23 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 24 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention.
  • Figure 26 is a flow chart showing a molecular detection method in accordance with one embodiment of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating a flow path structure device in accordance with one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to an embodiment of the present invention. The manufacturing process of the flow path structure device according to an embodiment of the present invention will be described in detail below with reference to FIG. 1 and FIGS. 2 to 10.
  • step S101 a substrate is provided, the substrate including a first portion and a second portion adjacent to the first portion.
  • a substrate 21 is provided which may include a first portion 211 and a second portion 212 adjacent the first portion 211.
  • the substrate may include: a semiconductor substrate (e.g., silicon, germanium, etc.), an insulating substrate (e.g., quartz, silicon nitride, etc.), a wafer in which an IC circuit has been integrated, or any combination of these substrates.
  • FIG. 2 is only for convenience to show the first part and the second part, and the line does not necessarily exist in practice, and the following drawings are similar.
  • step S102 a patterned first sacrificial layer is formed on the substrate, the first sacrificial layer covering the second portion and exposing the first portion.
  • FIG. 3 is a cross-sectional view schematically showing the structure of the step S102 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a patterned first sacrificial layer 31 is formed on the substrate 21, and the first sacrificial layer 31 covers the second portion 212 and exposes the first portion 211.
  • the first sacrificial layer can serve as a defined layer of runner position.
  • the thickness of the first sacrificial layer can be determined according to the height of the desired flow channel. In one embodiment, the first sacrificial layer may have a thickness ranging from 100 nanometers to 100 micrometers.
  • the first sacrificial layer may have a thickness of 500 nm, 1 micron, 10 micron, or 50 micron, or the like.
  • the material of the first sacrificial layer may include: a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials), an insulating dielectric material (eg, silicon oxide, nitrogen) Silicon, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials) or a metal material (for example, aluminum, copper, or the like, or a combination of metal materials).
  • the step S102 may include forming a first sacrificial layer on the substrate, the first sacrificial layer covering the first portion and the second portion of the substrate.
  • the step S102 may further include: patterning the first sacrificial layer by a photolithography method, thereby removing a portion of the first sacrificial layer covering the first portion to expose the first portion.
  • the photolithography method may include pattern exposure, pattern development, pattern etching, and the like.
  • the method of pattern exposure may include: optical exposure, electron beam exposure, or nanoimprint.
  • the method of pattern etching may include: wet etching or dry etching.
  • step S103 a first structural layer is formed on the first portion of the substrate and the first sacrificial layer.
  • a first structural layer 41 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31, for example, by a deposition process.
  • the first structural layer 41 covers the side of the first sacrificial layer 31.
  • the thickness of the first structural layer is greater than or equal to the thickness of the first sacrificial layer, so that during the subsequent execution of the first polishing process, the portion of the first sacrificial layer may be polished and removed as little as possible, which is beneficial for control.
  • the height of the flow path obtained subsequently is not limited thereto.
  • the thickness of the first structural layer may also be smaller than the thickness of the first sacrificial layer.
  • the material of the first structural layer may include: a metal material (for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials), a semiconductor material (eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials, or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric materials).
  • a metal material for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials
  • a semiconductor material eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric
  • step S104 after forming the first structural layer, a first polishing process is performed to expose the first sacrificial layer.
  • FIG. 5 is a cross-sectional view schematically showing the structure of step S104 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a first polishing process for example, CMP (Chemical Mechanical Polishing)
  • CMP Chemical Mechanical Polishing
  • the polishing process can remove portions of the first structural layer on the top surface of the first sacrificial layer.
  • step S105 the first sacrificial layer is removed to expose the upper surface of the second portion of the substrate and the side of the first structural layer.
  • Fig. 6 is a cross-sectional view schematically showing the structure of the flow path structure device in the manufacturing process of step S105 according to an embodiment of the present invention.
  • the first sacrificial layer 31 is removed, for example, by a selective etching process, thereby exposing the upper surface of the second portion 212 of the substrate 21 and the side of the first structural layer 41.
  • the selective etching process may include: dry etching or wet etching.
  • a second sacrificial layer is formed on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer.
  • Fig. 7 is a cross-sectional view schematically showing the structure of the step S106 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • the first structural layer 41 is supported as the support on the substrate 21.
  • a second sacrificial layer 32 is formed on a portion of the upper surface of the second portion 212, wherein the second sacrificial layer 32 covers the exposed side of the first structural layer 41.
  • the step S106 may include: depositing a second sacrificial layer on the semiconductor structure shown in FIG. 6; then performing etch back on the second sacrificial layer to form the structure shown in FIG.
  • the thickness of the second sacrificial layer can be determined according to the width of the desired flow channel.
  • the second sacrificial layer may have a thickness ranging from 0.1 nanometers to 1 micrometer.
  • the thickness of the second sacrificial layer may be 1 nm, 10 nm, 100 nm or 500 nm or the like.
  • the material of the second sacrificial layer may include: a metal material (such as chromium, aluminum, titanium, etc. or a combination of metal materials), a semiconductor material (such as polysilicon, amorphous silicon, indium tin oxide, etc. or A combination of a plurality of semiconductor materials) or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials).
  • a metal material such as chromium, aluminum, titanium, etc. or a combination of metal materials
  • a semiconductor material such as polysilicon, amorphous silicon, indium tin oxide, etc. or A combination of a plurality of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials.
  • a second structural layer is formed on the second portion of the substrate, the second sacrificial layer, and the first structural layer.
  • Fig. 8 is a cross-sectional view schematically showing the structure of the step S107 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a second structural layer 42 is formed on the second portion 212 of the substrate 21, the second sacrificial layer 32, and the first structural layer 41, for example, by a deposition process.
  • the thickness of the second structural layer is greater than or equal to the height of the second sacrificial layer, so that during the subsequent performing of the second polishing process, the portion of the second sacrificial layer may be polished and removed as little as possible, which is beneficial for control.
  • the height of the flow path obtained subsequently is not limited thereto.
  • the thickness of the second structural layer may also be smaller than the height of the second sacrificial layer.
  • the material of the second structural layer may include: a metal material (for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials), a semiconductor material (eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials, or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric materials).
  • a metal material for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials
  • a semiconductor material eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric
  • step S108 after forming the second structural layer, a second polishing process is performed to expose the second sacrificial layer.
  • Figure 9 is a cross-sectional view schematically showing the structure of the flow path structure device in the manufacturing process of step S108 in accordance with one embodiment of the present invention.
  • a second polishing process e.g., CMP
  • CMP chemical vapor deposition
  • the first structural layer 41 and the second structural layer 42 may also be exposed, for example, exposing the top of the first structural layer 41.
  • the second polishing process may remove portions of the second structural layer on the top surfaces of the first structural layer and the second sacrificial layer.
  • step S109 the second sacrificial layer is removed using a selective etching process to form a flow path.
  • Figure 10 is a cross-sectional view schematically showing the structure of the step S109 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • the second sacrificial layer 32 is removed by a selective etching process to form the flow channel 50.
  • the height of the flow channel can range from 100 nanometers to 100 microns.
  • the flow channel may have a width ranging from 0.1 nanometers to 1 micrometer.
  • a method of manufacturing a flow path structure device has been provided.
  • a patterned first sacrificial layer is formed on a substrate; a first structural layer is formed on the first portion of the substrate and the first sacrificial layer; a first polishing process is performed to expose the first sacrificial layer; a sacrificial layer to expose an upper surface of the second portion of the substrate and a side of the first structural layer; a second sacrificial layer formed on a portion of the upper surface of the second portion of the substrate; the second portion and the second portion of the substrate Forming a second structural layer on the sacrificial layer and the first structural layer; performing a second polishing process to expose the second sacrificial layer after forming the second structural layer; and removing the second sacrificial layer by a selective etching process to form Flow path.
  • a flow path structure device having a vertical flow path i.e., the flow path is perpendicular to the surface of the substrate
  • the flow path may be an open space in a direction perpendicular to the substrate or a transparent material may be provided, so this does not affect the transmission of the optical signal.
  • the effective surface area of a single flow channel can be the cross-sectional area of the flow channel, which can greatly increase the manufacturing density of the flow channel on the chip, and reduce manufacturing and application costs.
  • the above manufacturing method of the embodiment of the present invention can reduce the process heat budget.
  • the process of the present invention involves relatively low process temperatures (temperatures ranging from room temperature to 350 ° C) and short heat treatment times, thereby reducing the process thermal budget to facilitate integration of the flow channel structure device with the CMOS chip.
  • the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high aspect ratio flow path structure can be realized.
  • a flow path structure having a width of 10 nm and an aspect ratio of 100:1 can be realized.
  • the aspect ratio of the flow channel structure achieved by the method of the embodiment of the present invention may range from 1:1 to 100,000:1.
  • the flow path structure device includes a substrate, a first structural layer and a second structural layer on the substrate, and a flow path between the first structural layer and the second structural layer.
  • first structural layer and the second structural layer are respectively insulating dielectric materials
  • an insulating medium flow path structure device may be formed, which may be applied to fluid formation and control, and the like.
  • the first structural layer and the second structural layer are respectively conductive materials
  • a metal material or a semiconductor material for example, a doped semiconductor material
  • it can be used as an electrode on both sides of the flow path, which can be used for fluid processing, biochemical detection, and the like.
  • FIGS. 11 and 13 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 12 is a plan view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention. The manufacturing process of the flow path structure device according to further embodiments of the present invention will be described in detail below with reference to FIGS. 11 through 13.
  • the manufacturing method may further include: as shown in FIG. 11, at the second sacrificial layer 32, the first structural layer 41, and A cap layer 60 is formed on the second structural layer 42.
  • the cap layer 60 may implement a closed flow path together with the first structural layer 41 and the second structural layer 42 (ie, the upper side of the flow path is closed), and the first structural layer 41 may be avoided. And the parasitic reaction that may occur with the upper surface of the second structural layer 42 in contact with the fluid.
  • the material of the capping layer 60 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or a semiconductor material. (for example, polysilicon or amorphous silicon, etc.).
  • the capping layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers.
  • the cap layer may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer or 5 micrometers, and the like.
  • a selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer, thereby forming a structure as shown in FIG.
  • the planarly extending second sacrificial layer is bordered, and the edge of the second sacrificial layer may be exposed, so that a selective etching solution is implanted at the edge of the second sacrificial layer (ie, at the boundary) to remove The second sacrificial layer forms a flow channel.
  • the manufacturing method may further include: etching the capping layer 60 to form a capping layer and exposing as shown in FIG. The through hole 61 of the second sacrificial layer.
  • the selective etching liquid may be injected from the via hole 61 to remove the second sacrificial layer, thereby forming the channel structure device as shown in FIG.
  • the number, shape or size of the through holes can be determined according to design requirements, and the scope of the present invention is not limited to the number, shape or size of the through holes shown in FIG.
  • the selective etching liquid is facilitated to pass through the via hole.
  • the corrosion rate can be increased.
  • the flow path structure device further includes: a cap layer 60 on the first structural layer 41 and the second structural layer 42.
  • the cap layer 60 covers the flow path.
  • the cap layer 60 can implement a closed flow path (ie, the upper side of the flow channel is closed) together with the first structural layer 41 and the second structural layer 42 and can also avoid the upper surface of the first structural layer 41 and the second structural layer 42. Parasitic reactions that may be caused by contact with fluids.
  • the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids.
  • the flow channel structure device may further include: a through hole penetrating the cap layer and communicating to the flow channel.
  • the forming the first structural layer may include: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers a side of the first sacrificial layer; A first support layer is formed on the first material layer.
  • the first structural layer may include: the first material layer and the first support layer.
  • the step of forming the second structural layer may include forming a second material layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer, the second material layer covering the second a side of the sacrificial layer; and a second support layer formed on the second material layer.
  • the second structural layer may include: the second material layer and the second support layer.
  • FIGS. 14 to 22 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • the following is an example in which the first structural layer includes the first material layer and the first support layer, and the second structural layer includes the second material layer and the second support layer, and is further described in detail with reference to FIGS. 14 to 22 according to another embodiment of the present invention.
  • the manufacturing process of the flow channel structure device is
  • a substrate is provided that includes a first portion and a second portion that is contiguous with the first portion. This step has been described in detail above with reference to FIG. 2 and will not be described again here.
  • a patterned first sacrificial layer is formed on the substrate, the first sacrificial layer covering the second portion and exposing the first portion. This step has been described in detail above with reference to FIG. 3 and will not be described again here.
  • a first material layer 411 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31, for example, by a deposition process, wherein the first material layer 411 covers the first sacrificial layer 31. The side.
  • the material of the first material layer 411 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials) or a semiconductor material (eg, polysilicon, Amorphous silicon, indium tin oxide, or the like, or a combination of a plurality of semiconductor materials).
  • the first material layer can be made of metal A conductive material such as a material or a semiconductor material (for example, a doped semiconductor material), such that the first material layer can be used as one of the embedded electrode layers of the subsequently formed flow channel, and can be applied to fluid processing or biochemical detection.
  • the material of the first material layer 411 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials).
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials.
  • the first material layer 411 may have a thickness ranging from 1 nanometer to 500 nanometers.
  • the thickness of the first material layer 411 may be 10 nm, 50 nm, 100 nm or 300 nm or the like.
  • a first support layer 412 is formed on the first material layer 411, for example, by a deposition process.
  • the first support layer 412 can serve as a support layer for the first material layer 411. So far, the first structural layer 41 is formed.
  • the first structural layer 41 may include a first material layer 411 on the first portion 211 of the substrate 21 and the first sacrificial layer 31 and a first support layer 412 on the first material layer 411.
  • the material of the first support layer 412 may include: a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials), an insulating dielectric material (eg, silicon oxide, nitrogen) Silicon, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials) or a conductive metal material (for example, aluminum, copper, titanium, titanium nitride, or the like, or a combination of a plurality of metal materials).
  • a semiconductor material eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, nitrogen
  • Silicon silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials
  • a conductive metal material for example, aluminum, copper, titanium, titanium nitride, or the like, or a
  • the first support layer has a thickness ranging from 100 nanometers to 100 micrometers.
  • the thickness of the first support layer may be 200 nanometers, 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.
  • a first polishing process (e.g., CMP) is performed on the first structural layer 41 (i.e., the first support layer 412 and the first material layer 411) to expose the first sacrificial layer 31.
  • the first polishing process may remove portions of the first support layer 412 and the first material layer 411 located on the top surface of the first sacrificial layer 31.
  • the first sacrificial layer 31 is removed, for example, by a selective etching process to expose the upper surface of the second portion 212 of the substrate 21 and the side of the first structural layer 41.
  • the exposed side surface of the first structural layer 41 is the side surface of the first material layer 411.
  • a second sacrificial layer 32 is formed on a portion of the upper surface of the second portion 212 of the substrate 21 with the first support layer 412 and the first material layer 411 as supports, wherein the second sacrifice Layer 32 covers the exposed side of first structural layer 41.
  • the second sacrificial layer 32 covers the exposed side of the first material layer 411.
  • the second sacrifice A second material layer 421 is formed on the layer 32 and the first structural layer 41 (ie, the first material layer 411 and the first support layer 412), and the second material layer 421 covers the side surface of the second sacrificial layer 32.
  • the material of the second material layer 421 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials) or a semiconductor material (eg, polysilicon, Amorphous silicon, indium tin oxide, or the like, or a combination of a plurality of semiconductor materials).
  • the second material layer may be a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material), such that the second material layer may serve as one of the embedded electrode layers of the subsequently formed flow channel. Used in fluid processing or biochemical testing.
  • the material of the second material layer 421 may include: an insulating dielectric material (for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials). This makes it possible to form a flow path formed of an insulating dielectric material in a subsequent step, which can be applied to fluid formation and control and the like.
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials.
  • the second material layer 421 may have a thickness ranging from 1 nanometer to 500 nanometers.
  • the thickness of the second material layer 421 may be 10 nm, 50 nm, 100 nm or 300 nm or the like.
  • a second support layer 422 is formed on the second material layer 421, for example, by a deposition process.
  • the second support layer 422 can serve as a support layer for the second material layer 421. So far, the second structural layer 42 is formed.
  • the second structural layer 42 may include a second material layer on the second portion 212 of the substrate 21, the second sacrificial layer 32, and the first structural layer 41 (ie, the first material layer 411 and the first support layer 412) 421 and a second support layer 422 on the second material layer 421.
  • the material of the second support layer 422 may include: a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials), an insulating dielectric material (eg, silicon oxide, Silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials) or a conductive metal material (for example, aluminum, copper, titanium, titanium nitride, or the like, or a combination of metal materials).
  • a semiconductor material eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, Silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials
  • a conductive metal material for example, aluminum, copper, titanium, titanium nitride, or the like, or
  • the second support layer 422 may have a thickness ranging from 100 nanometers to 100 micrometers.
  • the thickness of the second support layer may be 200 nm, 500 nm, 1 micron, 10 micron or 50 micron, or the like.
  • a second polishing process (e.g., CMP) is performed on the second structural layer 42 (i.e., the second support layer 422 and the second material layer 421) to expose the second sacrificial layer 32.
  • the second polishing process may also remove portions of the second material layer 421 and the second support layer 422 on the top surface of the first support layer 412.
  • the first material layer 411, the first support layer 412, the second material layer 421, and the second support layer 422 are also exposed.
  • the second sacrificial layer 32 is removed by a selective etching process to form the flow channel 50.
  • the first structural layer may include: a first material layer and a first support layer, wherein a portion of the first material layer is between the first support layer and the flow channel, Another portion of the first material layer is between the first support layer and the first portion of the substrate;
  • the second structural layer can include: a second material layer and a second support layer, wherein a portion of the second material layer is Between the second support layer and the flow channel, another portion of the second material layer is between the second support layer and the second portion of the substrate.
  • the material of the first material layer comprises a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • a portion of the first material layer between the first support layer and the flow channel may serve as the flow
  • a first electrode of the track structure device, a portion of the first material layer between the first support layer and the first portion of the substrate may serve as a first lead of the first electrode.
  • the material of the second material layer comprises a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • a portion of the second material layer between the second support layer and the flow channel may serve as the flow
  • a second electrode of the track structure device, a portion of the second material layer between the second support layer and the second portion of the substrate may serve as a second lead of the second electrode. Since the first material layer and the second material layer are integrally formed by, for example, a deposition process, the contact resistance can be reduced between the first electrode and the first lead, and the second electrode is compared with the prior art. The contact resistance can also be reduced between the second leads, thereby improving device performance.
  • the above manufacturing method of the embodiment of the present invention can reduce the process heat budget.
  • the process of the present invention involves relatively low process temperatures (temperatures ranging from room temperature to 350 ° C) and short heat treatment times, thereby reducing the process thermal budget to facilitate integration of the flow channel structure device with the CMOS chip.
  • the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high aspect ratio flow path structure can be realized.
  • the flow path structure device may include a substrate 21, which may include a first portion 211 and a second portion 212 adjacent to the first portion 211.
  • the flow path structure device may further include: a first structural layer 41 and a second structural layer 42 on the substrate 21.
  • the first structural layer 41 may include: a first material layer 411 on the first portion 211 of the substrate 21 and a first support layer 412 on the first material layer 411
  • the second structural layer 42 may include : a second material layer 421 on the second portion 212 of the substrate 21 and a second support layer 422 on the second material layer 421.
  • the runner structure device may further include a flow passage 50 between the first material layer 411 and the second material layer 421.
  • the first support layer 421 and the second support layer 422 are respectively on both sides of the flow channel 50.
  • the first material A portion of the material layer 411 is between the first support layer 412 and the flow channel 50, and another portion of the first material layer 411 is between the first support layer 412 and the first portion 211 of the substrate 21;
  • a portion of the material layer 421 is between the second support layer 422 and the flow channel 50, and another portion of the second material layer 421 is between the second support layer 422 and the second portion 212 of the substrate 21.
  • the flow path structure device of the above embodiment of the present invention has a vertical flow path, for example, the flow path may be an open space in a direction perpendicular to the substrate or may be provided with a transparent material, so that this does not affect the transmission of the optical signal.
  • the effective surface area of a single flow channel is the cross-sectional area of the flow channel, which can greatly increase the manufacturing density of the flow channel on the chip, and can increase the application flux (ie, the number of flow channels per unit area). And reduce manufacturing and application costs.
  • the height of the flow channel 50 can range from 100 nanometers to 100 microns.
  • the height of the flow channel may be 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.
  • the flow channel 50 may have a width ranging from 0.1 nanometers to 1 micrometer.
  • the width of the flow channel may be 1 nm, 10 nm, 14 nm, 100 nm or 500 nm, and the like.
  • the flow channel structure device can realize a high aspect ratio flow path structure after selecting a suitable flow path height and width.
  • the first material layer 411 may have a thickness ranging from 1 nanometer to 500 nanometers. In one embodiment, the first support layer 412 may have a thickness ranging from 100 nanometers to 100 micrometers. In one embodiment, the second material layer 421 may have a thickness ranging from 1 nanometer to 500 nanometers. In one embodiment, the second support layer 422 may have a thickness ranging from 100 nanometers to 100 micrometers.
  • the material of the first material layer 411 may include a metal material or a semiconductor material (eg, a doped semiconductor material). Wherein the portion of the first material layer 411 between the first support layer 412 and the flow channel 50 may serve as a first electrode of the flow channel structure device; the first material layer 411 at the first support layer 412 and the base A portion between the first portions 211 of the sheets 21 may serve as a first lead of the first electrode.
  • the material of the second material layer 412 may include a metal material or a semiconductor material (eg, a doped semiconductor material).
  • the portion of the second material layer 412 between the second support layer 422 and the flow channel 50 can serve as a second electrode of the flow channel structure device; the second material layer 421 is at the second support layer 422 and the base A portion between the second portions 212 of the sheets 21 can serve as a second lead of the second electrode.
  • the contact resistance can be reduced between the first electrode and the first lead, and the second electrode and the second electrode are compared with the prior art. Contact resistance can also be reduced between leads to improve device performance.
  • the flow channel structure device may have a mosaic electrode structure and may have different lifetimes. Analysis and fluid handling functions. For example, by applying electrical excitation through an electrode, an electrical or electrochemical reaction can occur in the flow channel, an electrical signal or an optical signal can be generated, and a specific molecular species can be identified by the acquired electrical signal or optical signal; further, by identifying multiple Different molecular species can perform functions such as gene sequencing.
  • the materials of the first material layer 411 and the second material layer 421 may respectively include: an insulating dielectric material (for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials). combination).
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials. combination).
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials. combination).
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials.
  • Such a flow path formed of an insulating dielectric material can be applied to formation and control of fluids and the like.
  • the flow channel structure device can be applied to some cases where it is not necessary to
  • FIGS. 23 and 24 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention. Next, a manufacturing process of a flow path structure device according to another embodiment of the present invention will be described in detail with reference to FIGS. 23 and 24.
  • the manufacturing method may further include: at the second sacrificial layer 32, the first material layer 411, the first A cap layer 60 is formed on a support layer 412, a second material layer 421, and a second support layer 422.
  • the cap layer may be combined with the first structural layer (which may include the first material layer and the first support layer) and the second structural layer (which may include the second material layer and the second support layer) Achieving a closed flow channel structure can also avoid parasitic reactions that may be caused by contact of the first material layer with the top of the second material layer with the fluid.
  • the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids.
  • the selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer.
  • a flow path structure device as shown in Fig. 24 is formed.
  • the planarly extending second sacrificial layer is bordered, and the edge of the second sacrificial layer may be exposed, so that a selective etching solution is implanted at the edge of the second sacrificial layer (ie, at the boundary) to remove The second sacrificial layer forms a flow channel.
  • the manufacturing method may further include: etching the cap layer to form the cap layer and exposing the cap layer
  • the through holes of the two sacrificial layers (not shown in FIG. 24, reference may be made to the through holes 61 in FIG. 12).
  • the use of selective engraving In the step of removing the second sacrificial layer by the etching process, a selective etching liquid may be injected from the via hole to remove the second sacrificial layer, thereby forming a channel structure device as shown in FIG.
  • the selective etching liquid is facilitated to remove the second sacrificial layer through the via hole, and the etching rate can be accelerated.
  • the flow path structure device may include the same or similar structure as that of FIG. 22, and may include, for example, a substrate 21, a first material layer 411, a first support layer 412, a second material layer 421, and a second. Support layer 422 and flow channel 50 are not described in detail herein.
  • the flow channel structure device may further include: a cap layer covering the first material layer 411, the first support layer 412, the second material layer 421, and the second support layer 422. 60.
  • the cap layer 60 covers the flow channel 50.
  • the capping layer 60 can be closed with the first structural layer 41 (which can include the first material layer 411 and the first support layer 412) and the second structural layer 42 (which can include the second material layer 421 and the second support layer 422)
  • the flow channel i.e., the upper portion of the flow channel is closed
  • the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids.
  • the material of the capping layer 60 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or a semiconductor material. (for example, polysilicon or amorphous silicon, etc.).
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.
  • a semiconductor material for example, polysilicon or amorphous silicon, etc.
  • the capping layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers.
  • the cap layer may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer or 5 micrometers, and the like.
  • the flow channel structure device may further include: a through hole penetrating the cap layer and communicating to the flow channel.
  • the flow path of the embodiment of the present invention may be a nano flow channel.
  • the invention has the following advantages: (1) a nano-channel structure with high aspect ratio can be realized, and the size controllability is good; (2) an all-metal conductive electrode mosaic structure can be realized; (3) the nano-channel structure can be effectively improved; Manufacturability, reducing the manufacturing cost of nanochannel structure; (4) has a relatively low thermal budget and is compatible with integrated circuit processes. Further, the flow path structure device of the embodiment of the present invention can be applied to molecular detection, liquid formation, or fluid transportation control.
  • a flow channel sensor can also be provided.
  • the flow path sensor can include: A flow path structure device as previously described (for example, a flow path structure device as shown in FIG. 22 or as shown in FIG. 24).
  • a biochemical analysis device can also be provided.
  • the biochemical analysis device may comprise: a flow channel structure device as previously described (eg, a flow channel structure device as shown in FIG. 22 or as shown in FIG. 24).
  • FIG. 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention.
  • the chip 250 may include a flow path structure device 2501, a signal collection unit 2502, and a signal processing unit 2503.
  • the flow channel structure device 2501 includes electrodes (eg, a first electrode and a second electrode).
  • the flow path structure device may be a flow path structure device as shown in FIG. 22 or as shown in FIG. Wherein the sample to be detected is added to the flow channel of the flow channel structure device, and the target molecule in the sample to be detected is applied when the electrodes of the channel structure device (for example, the first electrode and the second electrode) are electrically excited. An electrical or optical signal is generated under electrical excitation.
  • the signal collecting unit 2502 can be configured to collect the electrical signal or the optical signal and transmit the electrical signal or the optical signal to the signal processing unit 2503.
  • the signal processing unit 2503 can be configured to perform signal processing on the electrical signal or the optical signal to identify information of the target molecule.
  • a molecular detection method is also provided.
  • the method can include performing molecular detection using a chip as described above (eg, a chip as shown in FIG. 25).
  • Figure 26 is a flow chart showing a molecular detection method in accordance with one embodiment of the present invention. The step of performing molecular detection using a chip will be described below with reference to FIG.
  • step S2601 the sample to be tested is processed.
  • the test sample can be subjected to chemical treatment or other treatment.
  • step S2602 the sample to be detected is added to the chip.
  • a sample to be tested is added to the flow path of the flow channel structure device of the chip.
  • step S2603 electrical excitation is applied to electrodes (eg, the first electrode and the second electrode) in the flow channel structure device in the chip such that the target molecules in the sample to be detected generate an electrical signal or an optical signal under electrical excitation.
  • electrodes eg, the first electrode and the second electrode
  • step S2604 the signal processing unit of the chip obtains an electrical signal or an optical signal through the signal collecting unit, and performs signal processing on the electrical signal or the optical signal to identify the information of the target molecule.
  • the application of molecular detection is realized by using a chip including the flow path structure device of the embodiment of the present invention.

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Abstract

一种流道结构器件及其制造方法，该方法包括：提供基片（21），其包括第一部分（211）和与第一部分（211）邻接的第二部分（212）；在基片（21）上形成图形化的第一牺牲层（31），该第一牺牲层（31）覆盖第二部分（212）且露出第一部分（211）；在基片（21）的第一部分（211）和第一牺牲层（31）上形成第一结构层（41）；执行第一抛光处理以露出第一牺牲层（31）；去除第一牺牲层（31）以露出基片（21）的第二部分（212）的上表面和第一结构层（41）的侧面；在基片（21）的第二部分（212）的部分上表面上形成第二牺牲层（32），其中第二牺牲层（32）覆盖第一结构层（41）的侧面；在基片（21）的第二部分（212）、第二牺牲层（32）和第一结构层（41）上形成第二结构层（42）；执行第二抛光处理以露出第二牺牲层（32）；以及利用选择性刻蚀工艺去除第二牺牲层（32）以形成流道（50）；该方法可以实现具有垂直流道的流道结构器件。

Description

流道结构器件及其制造方法 技术领域
本发明涉及半导体技术领域，特别涉及一种流道结构器件及其制造方法。
背景技术
基于微纳流道的微纳流控分析技术，在生化分析、基因测序等领域，正受到越来越多的研究和应用。微纳流道器件与集成电路(Integrated Circuit，简称为IC)的结合，也将有助于提升微分析系统的自动化和小型化，更好地拓展其应用空间。在某些应用中，需要在微纳流道中嵌入电极材料，在某些设计中，需要具有高深宽比的纳米流道。
传统方法中，可以采用电子束光刻或者激光光刻，并结合各向异性刻蚀工艺实现纳米流道。但是直接电子束或激光光刻方法的效率低、尺寸可调性差，且在金属材料上很难实现高深宽比，通常只有1左右。
现有技术中也可以采用侧墙法实现上述微纳流道结构。但是侧墙法必须依赖半导体材料侧墙支撑结构实现结构互联与信号引出，这会带来更多寄生效应，并最终会影响检测信号的质量，且工艺热预算高，不利于与CMOS芯片的集成。例如，现有技术中大部分电极引出需要依赖拼接的金属互联线(例如典型材料是铝和铜)或半导体互连线(例如典型材料是多晶硅)与电极材料形成合金结构引出。但是合金结构存在以下缺点：(1)合金过程需要额外热处理工艺，将增加工艺热预算，不利于在IC芯片上实施工艺集成，以典型的多晶硅互联工艺为例，需要多晶硅沉积工艺(温度通常高于600℃)、离子注入与激活(通常需要550℃以上)以及金属半导体合金(通常需要400℃以上)等热预算比较高的工艺技术；(2)合金体将会引入额外的接触电阻，这将会降低器件性能。此外，现有技术中还存在金属引线的横向流道结构，但是这样的横向流道结构中，金属电极分别在流道的上下两侧相对分布，会影响其应用范围，比如，其无法用于包含发光的应用，因为光信号将被上下电极挡住。而且，这样的横向流道结构还限制了在芯片上的制造密度。
现有技术中还可以通过调节金属溅射角度实现纳米间隙结构。在该溅射工艺中，粒子溅射方向与衬底基片表面存在一定角度，通过调整角度，可以在预先制备的沟槽 底部产生溅射的死角，从而获得纳米间隙流道结构，但工艺可控性和尺寸可调性差。
发明内容
本发明的发明人发现上述现有技术中存在问题，并因此针对所述问题中的至少一个问题提出了一种新的技术方案。
根据本发明的第一方面，提供了一种流道结构器件的制造方法，包括：提供基片，所述基片包括第一部分和与所述第一部分邻接的第二部分；在所述基片上形成图形化的第一牺牲层，所述第一牺牲层覆盖所述第二部分且露出所述第一部分；在所述基片的第一部分和所述第一牺牲层上形成第一结构层；在形成所述第一结构层之后，执行第一抛光处理以露出所述第一牺牲层；去除所述第一牺牲层以露出所述基片的第二部分的上表面和所述第一结构层的侧面；在所述基片的第二部分的部分上表面上形成第二牺牲层，其中所述第二牺牲层覆盖所述第一结构层的被露出的侧面；在所述基片的第二部分、所述第二牺牲层和所述第一结构层上形成第二结构层；在形成所述第二结构层之后，执行第二抛光处理以露出所述第二牺牲层；以及利用选择性刻蚀工艺去除所述第二牺牲层以形成流道。
在一个实施例中，在执行所述第二抛光处理的步骤中，还露出所述第一结构层和所述第二结构层；在利用选择性刻蚀工艺去除所述第二牺牲层之前，所述方法还包括：在所述第二牺牲层、所述第一结构层和所述第二结构层上形成盖帽层。
在一个实施例中，所述形成第一结构层的步骤包括：在所述基片的第一部分和所述第一牺牲层上形成第一材料层，其中所述第一材料层覆盖所述第一牺牲层的侧面；以及在所述第一材料层上形成第一支撑层；其中，所述第一结构层包括：所述第一材料层和所述第一支撑层；所述形成第二结构层的步骤包括：在所述基片的第二部分、所述第二牺牲层和所述第一结构层上形成第二材料层，所述第二材料层覆盖所述第二牺牲层的侧面；以及在所述第二材料层上形成第二支撑层；其中，所述第二结构层包括：所述第二材料层和所述第二支撑层。
在一个实施例中，在去除所述第一牺牲层以露出所述第一结构层的侧面的步骤中，所露出的所述第一结构层的侧面为所述第一材料层的侧面；在形成第二牺牲层的步骤中，所述第二牺牲层覆盖所述第一材料层的被露出的侧面。
在一个实施例中，在执行所述第二抛光处理的步骤中，还露出所述第一材料层、 所述第一支撑层、所述第二材料层和所述第二支撑层；在利用选择性刻蚀工艺去除所述第二牺牲层之前，所述方法还包括：在所述第二牺牲层、所述第一材料层、所述第一支撑层、所述第二材料层和所述第二支撑层上形成盖帽层。
在一个实施例中，所述盖帽层的材料包括：绝缘介质材料或半导体材料；所述盖帽层的厚度范围为1纳米至10微米。
在一个实施例中，在利用选择性刻蚀工艺去除所述第二牺牲层的步骤中，从所述第二牺牲层的边缘注入选择性刻蚀液以去除所述第二牺牲层。
在一个实施例中，在利用选择性刻蚀工艺去除所述第二牺牲层之前，所述方法还包括：对所述盖帽层进行刻蚀以形成贯穿所述盖帽层且露出所述第二牺牲层的通孔；其中，在利用选择性刻蚀工艺去除所述第二牺牲层的步骤中，从所述通孔注入选择性刻蚀液以去除所述第二牺牲层。
在一个实施例中，所述第一材料层的一部分在所述第一支撑层与所述流道之间，所述第一材料层的另一部分在所述第一支撑层与所述基片的第一部分之间；所述第二材料层的一部分在所述第二支撑层与所述流道之间，所述第二材料层的另一部分在所述第二支撑层与所述基片的第二部分之间。
在一个实施例中，所述第一材料层的材料包括：金属材料或半导体材料；所述第二材料层的材料包括：金属材料或半导体材料；其中，所述第一材料层的在所述第一支撑层与所述流道之间的部分作为所述流道结构器件的第一电极；所述第一材料层的在所述第一支撑层与所述基片的第一部分之间的部分作为所述第一电极的第一引线；所述第二材料层的在所述第二支撑层与所述流道之间的部分作为所述流道结构器件的第二电极；所述第二材料层的在所述第二支撑层与所述基片的第二部分之间的部分作为所述第二电极的第二引线。
在一个实施例中，所述第一材料层的材料和所述第二材料层的材料分别包括：绝缘介质材料。
在一个实施例中，所述第一牺牲层的厚度根据所需要的流道的高度来确定；所述第一牺牲层的厚度范围为100纳米至100微米。
在一个实施例中，所述第二牺牲层的厚度根据所需要的流道的宽度来确定；所述第二牺牲层的厚度范围为0.1纳米至1微米。
在一个实施例中，所述第一材料层的厚度范围为1纳米至500纳米；所述第一支 撑层的厚度范围为100纳米至100微米；所述第二材料层的厚度范围为1纳米至500纳米；所述第二支撑层的厚度范围为100纳米至100微米。
在上述制造方法中，在基片上形成图形化的第一牺牲层；在基片的第一部分和第一牺牲层上形成第一结构层；执行第一抛光处理以露出第一牺牲层；去除第一牺牲层以露出基片的第二部分的上表面和第一结构层的侧面；在基片的第二部分的部分上表面上形成第二牺牲层；在基片的第二部分、第二牺牲层和第一结构层上形成第二结构层；在形成第二结构层之后，执行第二抛光处理以露出第二牺牲层；以及利用选择性刻蚀工艺去除所述第二牺牲层以形成流道。本发明的上述制造方法可以形成具有垂直流道的流道结构器件，而且上述制造方法能够降低工艺热预算，便于流道结构器件与CMOS芯片的集成。
进一步地，由于上述制造方法中，第一牺牲层的厚度和第二牺牲层的厚度可以根据设计需要来确定，因此可以实现高深宽比的流道结构。
进一步地，在第一材料层和第二材料层分别采用金属或半导体等导电材料的情况下，第一材料层可以包括第一电极和第一引线，第二材料层可以包括第二电极和第二引线，由于第一材料层和第二材料层分别整体地形成，因此，相比现有技术，第一电极与第一引线之间可以减小接触电阻，第二电极与第二引线之间也可以减小接触电阻，从而可以提高器件性能。
根据本发明的第二方面，提供了一种流道结构器件，包括：基片，所述基片包括第一部分和与所述第一部分邻接的第二部分；在所述基片上的第一结构层和第二结构层；其中，所述第一结构层包括：在所述基片的第一部分上的第一材料层和在所述第一材料层上的第一支撑层，所述第二结构层包括：在所述基片的第二部分上的第二材料层和在所述第二材料层上的第二支撑层；在所述第一材料层与所述第二材料层之间的流道；所述第一支撑层和所述第二支撑层分别在所述流道的两侧；其中，所述第一材料层的一部分在所述第一支撑层与所述流道之间，所述第一材料层的另一部分在所述第一支撑层与所述基片的第一部分之间；所述第二材料层的一部分在所述第二支撑层与所述流道之间，所述第二材料层的另一部分在所述第二支撑层与所述基片的第二部分之间。
在一个实施例中，所述流道结构器件还包括：覆盖在所述第一材料层、所述第一支撑层、所述第二材料层和所述第二支撑层上的盖帽层；其中，所述盖帽层覆盖在所 述流道之上。
在一个实施例中，所述盖帽层的材料包括：绝缘介质材料或半导体材料；所述盖帽层的厚度范围为1纳米至10微米。
在一个实施例中，所述流道结构器件还包括：贯穿所述盖帽层且连通到所述流道的通孔。
在一个实施例中，所述第一材料层的材料包括：金属材料或半导体材料；所述第二材料层的材料包括：金属材料或半导体材料；其中，所述第一材料层的在所述第一支撑层与所述流道之间的部分作为所述流道结构器件的第一电极；所述第一材料层的在所述第一支撑层与所述基片的第一部分之间的部分作为所述第一电极的第一引线；所述第二材料层的在所述第二支撑层与所述流道之间的部分作为所述流道结构器件的第二电极；所述第二材料层的在所述第二支撑层与所述基片的第二部分之间的部分作为所述第二电极的第二引线。
在一个实施例中，所述第一材料层的材料和所述第二材料层的材料分别包括：绝缘介质材料。
在一个实施例中，所述流道的高度范围为100纳米至100微米；所述流道的宽度范围为0.1纳米至1微米。
在一个实施例中，所述第一材料层的厚度范围为1纳米至500纳米；所述第一支撑层的厚度范围为100纳米至100微米；所述第二材料层的厚度范围为1纳米至500纳米；所述第二支撑层的厚度范围为100纳米至100微米。
本发明上述实施例的流道结构器件具有垂直流道，这可以提高在芯片上的流道的制造密度，降低制造和应用成本等。
进一步地，上述流道结构器件可以实现高深宽比的流道结构。
进一步地，在第一材料层和第二材料层分别采用金属或半导体等导电材料的情况下，第一材料层可以包括第一电极和第一引线，第二材料层可以包括第二电极和第二引线，由于第一材料层和第二材料层分别整体地形成，因此，相比现有技术，第一电极与第一引线之间可以减小接触电阻，第二电极与第二引线之间也可以减小接触电阻，从而可以提高器件性能。
根据本发明的第三方面，提供了一种流道传感器，包括：如前所述的流道结构器件。
根据本发明的第四方面，提供了一种生物化学分析设备，包括：如前所述的流道结构器件。
根据本发明的第五方面，提供了一种用于分子检测的芯片，包括：如前所述流道结构器件、信号收集单元和信号处理单元；其中，待检测样品被加入到所述流道结构器件的流道中，在所述流道结构器件的电极被施加电激励情况下，所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；所述信号收集单元用于收集所述电信号或所述光信号，并将所述电信号或所述光信号传输到所述信号处理单元；所述信号处理单元用于对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
根据本发明的第六方面，提供了一种分子检测方法，包括：使用如前所述的芯片进行分子检测。
在一个实施例中，使用所述芯片进行分子检测的步骤包括：对待检测样品进行处理；将所述待检测样品加入到所述芯片中；对所述芯片中的流道结构器件中的电极施加电激励，使得所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；以及所述芯片的所述信号处理单元通过所述信号收集单元获得所述电信号或所述光信号，并对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
在上述实施例中，通过使用包含本发明实施例的流道结构器件的芯片实现了分子检测的应用。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是示出根据本发明一个实施例的流道结构器件的制造方法的流程图。
图2至图10是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。
图11是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一 个阶段的结构的横截面图。
图12是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的俯视图。
图13是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图14至图22是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。
图23是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图24是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图25是示意性地示出根据本发明一个实施例的用于分子检测的芯片的结构图。
图26是示出根据本发明一个实施例的分子检测方法的流程图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图1是示出根据本发明一个实施例的流道结构器件的制造方法的流程图。图2 至图10是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。下面结合图1以及图2至图10详细描述根据本发明一个实施例的流道结构器件的制造过程。
如图1所示，在步骤S101，提供基片，该基片包括第一部分和与该第一部分邻接的第二部分。
图2是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S101的结构的横截面图。如图2所示，提供基片21，该基片21可以包括第一部分211和与该第一部分211邻接的第二部分212。例如该基片可以包括：半导体衬底(例如硅、锗等)、绝缘衬底(例如石英、氮化硅等)、已集成了IC电路的晶圆或者这些衬底的任意组合。
需要说明的是，图2中的虚线仅是为了方便示出第一部分和第二部分，实际中并不一定存在该线，以下附图类似。
回到图1，在步骤S102，在基片上形成图形化的第一牺牲层，该第一牺牲层覆盖第二部分且露出第一部分。
图3是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S102的结构的横截面图。如图3所示，在基片21上形成图形化的第一牺牲层31，该第一牺牲层31覆盖第二部分212且露出第一部分211。该第一牺牲层可以作为流道位置的定义层。该第一牺牲层的厚度可以根据所需要的流道的高度来确定。在一个实施例中，该第一牺牲层的厚度范围可以为100纳米至100微米。例如，该第一牺牲层的厚度可以为500纳米、1微米、10微米或50微米等。在一个实施例中，该第一牺牲层的材料可以包括：半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)、绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)或者金属材料(例如，铝、铜等或多种金属材料的组合)。
可选地，该步骤S102可以包括：在基片上形成第一牺牲层，该第一牺牲层覆盖基片的第一部分和第二部分。可选地，该步骤S102还可以包括：利用光刻方法对该第一牺牲层进行图形化，从而去除该第一牺牲层的覆盖在第一部分上的部分以露出该第一部分。例如该光刻方法可以包括图形曝光、图形显影和图形刻蚀等。例如，该图形曝光的方法可以包括：光学曝光、电子束曝光或纳米压印等。例如，该图形刻蚀的方法可以包括：湿法腐蚀或干法刻蚀等。
回到图1，在步骤S103，在基片的第一部分和第一牺牲层上形成第一结构层。
图4是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S103的结构的横截面图。如图4所示，例如通过淀积工艺在基片21的第一部分211和第一牺牲层31上形成第一结构层41。该第一结构层41覆盖第一牺牲层31的侧面。优选地，该第一结构层的厚度大于或等于该第一牺牲层的厚度，这样在后续执行第一抛光处理的过程中，可以尽量少地抛光去除第一牺牲层的部分，有利于控制好后续所获得的流道的高度。当然，本发明的范围并不仅限于此，例如该第一结构层的厚度也可以小于该第一牺牲层的厚度。
在一个实施例中，该第一结构层的材料可以包括：金属材料(例如，金、铂、银、钛、氮化钛等或多种金属材料的组合)、半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)或者绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)。
回到图1，在步骤S104，在形成第一结构层之后，执行第一抛光处理以露出第一牺牲层。
图5是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S104的结构的横截面图。如图5所示，例如对图4所示的半导体结构执行第一抛光处理(例如CMP(Chemical Mechanical Polishing，化学机械抛光))，从而露出第一牺牲层31的顶表面。该抛光处理可以去除位于第一牺牲层顶表面上的第一结构层的部分。
回到图1，在步骤S105，去除第一牺牲层以露出基片的第二部分的上表面和第一结构层的侧面。
图6是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S105的结构的横截面图。如图6所示，例如通过选择性刻蚀工艺去除第一牺牲层31，从而露出基片21的第二部分212的上表面和第一结构层41的侧面。例如，该选择性刻蚀工艺可以包括：干法刻蚀或湿法刻蚀等。
回到图1，在步骤S106，在基片的第二部分的部分上表面上形成第二牺牲层，其中该第二牺牲层覆盖第一结构层的被露出的侧面。
图7是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S106的结构的横截面图。如图7所示，以第一结构层41作为支撑，在基片21的 第二部分212的部分上表面上形成第二牺牲层32，其中该第二牺牲层32覆盖第一结构层41的被露出的侧面。例如，该步骤S106可以包括：在图6所示的半导体结构上淀积第二牺牲层；然后对该第二牺牲层执行回蚀刻，从而形成图7所示的结构。该第二牺牲层的厚度可以根据所需要的流道的宽度来确定。在一个实施例中，该第二牺牲层的厚度范围可以为0.1纳米至1微米。例如，该第二牺牲层的厚度可以为1纳米、10纳米、100纳米或500纳米等。
在一个实施例中，该第二牺牲层的材料可以包括：金属材料(例如铬、铝、钛等或多种金属材料的组合)、半导体材料(例如多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)或绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)。
回到图1，在步骤S107，在基片的第二部分、第二牺牲层和第一结构层上形成第二结构层。
图8是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S107的结构的横截面图。如图8所示，例如通过淀积工艺在基片21的第二部分212、第二牺牲层32和第一结构层41上形成第二结构层42。优选地，该第二结构层的厚度大于或等于该第二牺牲层的高度，这样在后续执行第二抛光处理的过程中，可以尽量少地抛光去除第二牺牲层的部分，有利于控制好后续所获得的流道的高度。当然，本发明的范围并不仅限于此，例如该第二结构层的厚度也可以小于该第二牺牲层的高度。
在一个实施例中，该第二结构层的材料可以包括：金属材料(例如，金、铂、银、钛、氮化钛等或多种金属材料的组合)、半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)或者绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)。
回到图1，在步骤S108，在形成第二结构层之后，执行第二抛光处理以露出第二牺牲层。
图9是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S108的结构的横截面图。如图9所示，例如对图8所示的半导体结构执行第二抛光处理(例如CMP)，从而露出第二牺牲层32的顶表面。在该执行第二抛光处理的步骤中，还可以露出第一结构层41和第二结构层42，例如露出第一结构层41的顶 表面和第二结构层42的顶表面。该第二抛光处理可以去除位于第一结构层和第二牺牲层的顶表面上的第二结构层的部分。
回到图1，在步骤S109，利用选择性刻蚀工艺去除第二牺牲层以形成流道。
图10是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S109的结构的横截面图。如图10所示，利用选择性刻蚀工艺去除第二牺牲层32以形成流道50。在一个实施例中，该流道的高度范围可以为100纳米至100微米。在一个实施例中，该流道的宽度范围可以为0.1纳米至1微米。
至此，提供了根据本发明一个实施例的流道结构器件的制造方法。在该制造方法中，在基片上形成图形化的第一牺牲层；在基片的第一部分和第一牺牲层上形成第一结构层；执行第一抛光处理以露出第一牺牲层；去除第一牺牲层以露出基片的第二部分的上表面和第一结构层的侧面；在基片的第二部分的部分上表面上形成第二牺牲层；在基片的第二部分、第二牺牲层和第一结构层上形成第二结构层；在形成第二结构层之后，执行第二抛光处理以露出第二牺牲层；以及利用选择性刻蚀工艺去除所述第二牺牲层以形成流道。通过上述制造方法，可以形成具有垂直流道(即该流道垂直于基片的表面)的流道结构器件。例如，该流道在垂直于基片的方向上可以为开放空间或可以设置透明材料，因此这不会影响光信号的传输。此外，采用垂直流道，可以使得单个流道的有效表面积是流道的截面积，可以大大提高在芯片上的流道的制造密度，降低制造和应用成本等。
本发明实施例的上述制造方法能够降低工艺热预算。例如，本发明的方法所涉及的工艺温度比较低(温度范围在室温至350℃之间)，而且热处理过程时间短，因此降低了工艺热预算，以便于流道结构器件与CMOS芯片的集成。
进一步地，由于上述制造方法中，第一牺牲层的厚度和第二牺牲层的厚度可以根据设计需要来确定，因此可以实现高深宽比的流道结构。例如可以实现宽度10nm、深宽比为100：1的流道结构。本发明实施例的方法所实现的流道结构的深宽比的范围可以为1:1至100000:1。
通过上述制造方法，形成了一种流道结构器件。该流道结构器件包括：基片，在基片上的第一结构层和第二结构层，以及在第一结构层与第二结构层之间的流道。在第一结构层和第二结构层分别为绝缘介质材料的情况下，可以形成绝缘介质流道结构器件，这可以应用于流体形成与控制等。在第一结构层和第二结构层分别为导电材料 (例如金属材料或半导体材料(例如掺杂的半导体材料))的情况下，可以作为在流道两侧的电极，这可以用于流体处理、生化检测等应用。
图11和图13是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。图12是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的俯视图。下面结合图11至图13详细描述根据本发明另一些实施例的流道结构器件的制造过程。
在本发明的一个实施例中，在利用选择性刻蚀工艺去除第二牺牲层之前，所述制造方法还可以包括：如图11所示，在第二牺牲层32、第一结构层41和第二结构层42上形成盖帽层60。在后续形成流道的步骤中，该盖帽层60可以与第一结构层41和第二结构层42一起实现封闭性流道(即流道的上方被封闭)，还可以避免第一结构层41和第二结构层42的上表面与流体接触所可能带来的寄生反应。此外，对于一些需要流体(例如液体)在流道中流动的应用，该实施例的覆盖有盖帽层的流道更容易控制这些流体的流动。在一个实施例中，该盖帽层60的材料可以包括：绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅、硼磷硅玻璃、氧化铝、氧化钛或氧化钽等)或半导体材料(例如，多晶硅或非晶硅等)。在一个实施例中，该盖帽层60的厚度范围可以为1纳米至10微米。例如，该盖帽层的厚度可以为10纳米、100纳米、500纳米、1微米或5微米等。
在一个实施例中，在利用选择性刻蚀工艺去除第二牺牲层的步骤中，可以从第二牺牲层的边缘注入选择性刻蚀液以去除该第二牺牲层，从而形成如图13所示的流道结构器件。在实际平面结构中，平面延伸的第二牺牲层是有边界的，该第二牺牲层的边缘可以被暴露，因此在第二牺牲层的边缘(即边界处)注入选择性刻蚀液以去除第二牺牲层，从而形成流道。
在另一个实施例中，在利用选择性刻蚀工艺去除第二牺牲层之前，所述制造方法还可以包括：如图12所示，对盖帽层60进行刻蚀以形成贯穿该盖帽层且露出第二牺牲层的通孔61。其中，在利用选择性刻蚀工艺去除第二牺牲层的步骤中，可以从该通孔61注入选择性刻蚀液以去除第二牺牲层，从而形成如图13所示的流道结构器件。本领域技术人员应该理解，该通孔的数量、形状或大小等均可以根据设计需要来确定，本发明的范围并不仅限于图12所示的通孔的数量、形状或大小等。在该实施例中通过在盖帽层60上形成通孔，从而在选择性刻蚀工艺中，有利于选择性刻蚀液经过该通孔 来去除第二牺牲层，可以加快腐蚀速率。
在图13所示的流道结构器件中，除了具有与图10相同或相似的结构之外，该流道结构器件还包括：在第一结构层41和第二结构层42上的盖帽层60，该盖帽层60覆盖在流道之上。该盖帽层60可以与第一结构层41和第二结构层42一起实现封闭性流道(即流道的上方被封闭)，还可以避免第一结构层41和第二结构层42的上表面与流体接触所可能带来的寄生反应。此外，对于一些需要流体(例如液体)在流道中流动的应用，该实施例的覆盖有盖帽层的流道更容易控制这些流体的流动。可选地，该流道结构器件还可以包括：贯穿盖帽层且连通到流道的通孔。
在一个实施例中，形成第一结构层的步骤可以包括：在基片的第一部分和第一牺牲层上形成第一材料层，其中该第一材料层覆盖该第一牺牲层的侧面；以及在该第一材料层上形成第一支撑层。其中，该第一结构层可以包括：该第一材料层和该第一支撑层。
在另一个实施例中，形成第二结构层的步骤可以包括：在基片的第二部分、第二牺牲层和第一结构层上形成第二材料层，该第二材料层覆盖该第二牺牲层的侧面；以及在该第二材料层上形成第二支撑层。其中，该第二结构层可以包括：该第二材料层和该第二支撑层。
图14至图22是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。下面以第一结构层包括第一材料层和第一支撑层、第二结构层包括第二材料层和第二支撑层为例，并结合图14至图22详细描述根据本发明另一个实施例的流道结构器件的制造过程。
首先，提供基片，该基片包括第一部分和与该第一部分邻接的第二部分。该步骤在前面已经结合图2详细描述，这里不再赘述。
接下来，在基片上形成图形化的第一牺牲层，该第一牺牲层覆盖第二部分且露出第一部分。该步骤在前面已经结合图3详细描述，这里不再赘述。
接下来，如图14所示，例如通过淀积工艺在基片21的第一部分211和第一牺牲层31上形成第一材料层411，其中该第一材料层411覆盖该第一牺牲层31的侧面。
在一个实施例中，该第一材料层411的材料可以包括：金属材料(例如，金、铂、银、钛、氮化钛等或多种金属材料的组合)或半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)。在该实施例中，第一材料层可以采用金属材 料或半导体材料(例如掺杂的半导体材料)等导电材料，这样该第一材料层可以作为后续形成的流道的嵌入电极层之一，可应用于流体的处理或生化检测等。
在另一个实施例中，该第一材料层411的材料可以包括：绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)。这样可以在后续步骤中可以形成由绝缘介质材料形成的流道，可应用于流体的形成与控制等。
在一个实施例中，该第一材料层411的厚度范围可以为1纳米至500纳米。例如该第一材料层411的厚度可以为10纳米、50纳米、100纳米或300纳米等。
接下来，如图15所示，例如通过淀积工艺在该第一材料层411上形成第一支撑层412。该第一支撑层412可以作为第一材料层411的支撑层。至此，形成了第一结构层41。该第一结构层41可以包括：在基片21的第一部分211和第一牺牲层31上的第一材料层411和在该第一材料层411上的第一支撑层412。
在一个实施例中，该第一支撑层412的材料可以包括：半导体材料(例如多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)、绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)或者导电金属材料(例如，铝、铜、钛、氮化钛等或多种金属材料的组合)。
在一个实施例中，该第一支撑层的厚度范围为100纳米至100微米。例如，该第一支撑层的厚度可以为200纳米、500纳米、1微米、10微米或50微米等。
接下来，如图16所示，对第一结构层41(即第一支撑层412和第一材料层411)执行第一抛光处理(例如CMP)以露出第一牺牲层31。该第一抛光处理可以去除位于第一牺牲层31的顶表面上的第一支撑层412和第一材料层411的部分。当然，也可以进一步抛光去除一部分第一牺牲层。
接下来，如图17所示，例如通过选择性刻蚀工艺去除第一牺牲层31以露出基片21的第二部分212的上表面和第一结构层41的侧面。在该步骤中，如图17所示，所露出的第一结构层41的侧面为第一材料层411的侧面。
接下来，如图18所示，以第一支撑层412和第一材料层411作为支撑，在基片21的第二部分212的部分上表面上形成第二牺牲层32，其中该第二牺牲层32覆盖第一结构层41的被露出的侧面。在该步骤中，该第二牺牲层32覆盖该第一材料层411的被露出的侧面。
接下来，如图19所示，例如通过淀积工艺在基片21的第二部分212、第二牺牲 层32和第一结构层41(即第一材料层411和第一支撑层412)上形成第二材料层421，该第二材料层421覆盖该第二牺牲层32的侧面。
在一个实施例中，该第二材料层421的材料可以包括：金属材料(例如，金、铂、银、钛、氮化钛等或多种金属材料的组合)或半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)。在该实施例中，第二材料层可以采用金属材料或半导体材料(例如掺杂的半导体材料)等导电材料，这样该第二材料层可以作为后续形成的流道的嵌入电极层之一，可应用于流体处理或生化检测等。
在另一个实施例中，该第二材料层421的材料可以包括：绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)。这样可以在后续步骤中可以形成由绝缘介质材料形成的流道，可应用于流体形成与控制等。
在一个实施例中，该第二材料层421的厚度范围可以为1纳米至500纳米。例如该第二材料层421的厚度可以为10纳米、50纳米、100纳米或300纳米等。
接下来，如图20所示，例如通过淀积工艺在该第二材料层421上形成第二支撑层422。该第二支撑层422可以作为第二材料层421的支撑层。至此，形成了第二结构层42。该第二结构层42可以包括：在基片21的第二部分212、第二牺牲层32和第一结构层41(即第一材料层411和第一支撑层412)上的第二材料层421和在该第二材料层421上的第二支撑层422。
在一个实施例中，该第二支撑层422的材料可以包括：半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)、绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)或导电金属材料(例如，铝、铜、钛、氮化钛等或多种金属材料的组合)。
在一个实施例中，该第二支撑层422的厚度范围可以为100纳米至100微米。例如，该第二支撑层的厚度可以为200纳米、500纳米、1微米、10微米或50微米等。
接下来，如图21所示，对第二结构层42(即第二支撑层422和第二材料层421)执行第二抛光处理(例如CMP)以露出第二牺牲层32。此外，该第二抛光处理还可以去除第一支撑层412的顶表面上的第二材料层421和第二支撑层422的部分。如图21所示，在执行该第二抛光处理的步骤中，还露出第一材料层411、第一支撑层412、第二材料层421和第二支撑层422。
接下来，如图22所示，利用选择性刻蚀工艺去除第二牺牲层32以形成流道50。
至此，提供了根据本发明另一个实施例的流道结构器件的制造方法。通过上述制造方法所形成的流道结构器件中，第一结构层可以包括：第一材料层和第一支撑层，其中该第一材料层的一部分在该第一支撑层与流道之间，该第一材料层的另一部分在该第一支撑层与基片的第一部分之间；第二结构层可以包括：第二材料层和第二支撑层，其中，该第二材料层的一部分在该第二支撑层与该流道之间，该第二材料层的另一部分在该第二支撑层与基片的第二部分之间。
在第一材料层的材料包括金属材料或半导体材料(例如掺杂的半导体材料)等导电材料的情况下，该第一材料层的在第一支撑层与流道之间的部分可以作为该流道结构器件的第一电极，该第一材料层的在该第一支撑层与基片的第一部分之间的部分可以作为该第一电极的第一引线。在第二材料层的材料包括金属材料或半导体材料(例如掺杂的半导体材料)等导电材料的情况下，该第二材料层的在第二支撑层与流道之间的部分可以作为该流道结构器件的第二电极，该第二材料层的在该第二支撑层与基片的第二部分之间的部分可以作为该第二电极的第二引线。由于第一材料层和第二材料层分别是通过例如淀积工艺而整体地形成的，因此，相比现有技术，第一电极与第一引线之间可以减小接触电阻，第二电极与第二引线之间也可以减小接触电阻，从而可以提高器件性能。
此外，本发明实施例的上述制造方法能够降低工艺热预算。例如，本发明的方法所涉及的工艺温度比较低(温度范围在室温至350℃之间)，而且热处理过程时间短，因此降低了工艺热预算，以便于流道结构器件与CMOS芯片的集成。
进一步地，由于上述制造方法中，第一牺牲层的厚度和第二牺牲层的厚度可以根据设计需要来确定，因此可以实现高深宽比的流道结构。
由上述制造方法，还形成了一种流道结构器件。如图22所示，该流道结构器件可以包括基片21，该基片21可以包括第一部分211和与该第一部分211邻接的第二部分212。该流道结构器件还可以包括：在基片21上的第一结构层41和第二结构层42。其中，该第一结构层41可以包括：在基片21的第一部分211上的第一材料层411和在该第一材料层411上的第一支撑层412，该第二结构层42可以包括：在基片21的第二部分212上的第二材料层421和在该第二材料层421上的第二支撑层422。该流道结构器件还可以包括：在该第一材料层411与该第二材料层421之间的流道50。该第一支撑层421和该第二支撑层422分别在流道50的两侧。如图22所示，该第一材 料层411的一部分在该第一支撑层412与流道50之间，该第一材料层411的另一部分在该第一支撑层412与该基片21的第一部分211之间；该第二材料层421的一部分在该第二支撑层422与流道50之间，该第二材料层421的另一部分在该第二支撑层422与该基片21的第二部分212之间。
本发明上述实施例的流道结构器件具有垂直流道，例如该流道在垂直于基片的方向上可以为开放空间或可以设置透明材料，因此这不会影响光信号的传输。此外，采用垂直流道，可以使得单个流道的有效表面积是流道的截面积，可以大大提高在芯片上的流道的制造密度，可以提高应用通量(即单位面积的流道数量)，以及降低制造和应用成本等。
在一个实施例中，该流道50的高度范围可以为100纳米至100微米。例如该流道的高度可以为500纳米、1微米、10微米或50微米等。在一个实施例中，该流道50的宽度范围可以为0.1纳米至1微米。例如，该流道的宽度可以为1纳米、10纳米、14纳米、100纳米或500纳米等。在选择合适的流道高度和宽度后，该流道结构器件可以实现高深宽比的流道结构。
在一个实施例中，该第一材料层411的厚度范围可以为1纳米至500纳米。在一个实施例中，该第一支撑层412的厚度范围可以为100纳米至100微米。在一个实施例中，该第二材料层421的厚度范围可以为1纳米至500纳米。在一个实施例中，该第二支撑层422的厚度范围可以为100纳米至100微米。
在一个实施例中，该第一材料层411的材料可以包括：金属材料或半导体材料(例如掺杂的半导体材料)。其中，该第一材料层411的在第一支撑层412与流道50之间的部分可以作为流道结构器件的第一电极；该第一材料层411的在该第一支撑层412与基片21的第一部分211之间的部分可以作为该第一电极的第一引线。在一个实施例中，该第二材料层412的材料可以包括：金属材料或半导体材料(例如掺杂的半导体材料)。其中，该第二材料层412的在第二支撑层422与流道50之间的部分可以作为流道结构器件的第二电极；该第二材料层421的在该第二支撑层422与基片21的第二部分212之间的部分可以作为该第二电极的第二引线。在该实施例中，由于第一材料层和第二材料层分别整体地形成，因此，相比现有技术，第一电极与第一引线之间可以减小接触电阻，第二电极与第二引线之间也可以减小接触电阻，从而可以提高器件性能。
在上述实施例中，上述流道结构器件可以具有镶嵌电极结构，可以具有不同的生 化分析与流体处理功能。比如，通过电极施加电激励，流道中可以发生电的或电化学的反应，可以产生电信号或光信号，可以通过获取的电信号或者光信号识别特定的分子种类；再进一步，通过识别多种不同分子种类，可以实现诸如基因测序等功能。
在另一个实施例中，该第一材料层411和该第二材料层421的材料可以分别包括：绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅等或多种绝缘介质材料的组合)。这样由绝缘介质材料形成的流道可应用于流体的形成与控制等。例如，利用绝缘介质材料作为第一材料层和第二材料层，可以将流道结构器件应用到某些不需要在流道中施加电极的情况，例如在一些情况下，需要用特定的绝缘介质材料作为材料层来修饰流道表面以获得某些特定效果，比如获得疏水表面或亲水表面等，从而有利于流体的形成和控制。
图23和图24是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。下面结合图23和图24详细描述根据本发明另一个实施例的流道结构器件的制造过程。
在一个实施例中，在利用选择性刻蚀工艺去除第二牺牲层之前以及在执行第二抛光处理之后，所述制造方法还可以包括：在第二牺牲层32、第一材料层411、第一支撑层412、第二材料层421和第二支撑层422上形成盖帽层60。在后续形成流道的步骤中，该盖帽层可以与第一结构层(可以包括第一材料层和第一支撑层)和第二结构层(可以包括第二材料层和第二支撑层)一起实现封闭性流道结构，还可以避免第一材料层与第二材料层顶部与流体的接触而可能带来的寄生反应。此外，对于一些需要流体(例如液体)在流道中流动的应用，该实施例的覆盖有盖帽层的流道更容易控制这些流体的流动。
在一个实施例中，与前面所述类似，在利用选择性刻蚀工艺去除第二牺牲层的步骤中，可以从第二牺牲层的边缘注入选择性刻蚀液以去除该第二牺牲层，从而形成如图24所示的流道结构器件。在实际平面结构中，平面延伸的第二牺牲层是有边界的，该第二牺牲层的边缘可以被暴露，因此在第二牺牲层的边缘(即边界处)注入选择性刻蚀液以去除第二牺牲层，从而形成流道。
在另一个实施例中，与前面所述类似，在利用选择性刻蚀工艺去除第二牺牲层之前，所述制造方法还可以包括：对盖帽层进行刻蚀以形成贯穿该盖帽层且露出第二牺牲层的通孔(图24中未示出，可以参考图12中的通孔61)。其中，在利用选择性刻 蚀工艺去除第二牺牲层的步骤中，可以从该通孔注入选择性刻蚀液以去除第二牺牲层，从而形成如图24所示的流道结构器件。在该实施例中通过在盖帽层上形成通孔，从而在选择性刻蚀工艺中，有利于选择性刻蚀液经过该通孔来去除第二牺牲层，可以加快腐蚀速率。
由上述制造方法，还形成了根据本发明另一个实施例的流道结构器件。如图24所示，该流道结构器件可以包括与图22相同或相似的结构，例如可以包括：基片21、第一材料层411、第一支撑层412、第二材料层421、第二支撑层422和流道50，这里不再详细描述。
在一个实施例中，如图24所示，该流道结构器件还可以包括：覆盖在第一材料层411、第一支撑层412、第二材料层421和第二支撑层422上的盖帽层60。其中，该盖帽层60覆盖在流道50之上。该盖帽层60可以与第一结构层41(可以包括第一材料层411和第一支撑层412)和第二结构层42(可以包括第二材料层421和第二支撑层422)一起实现封闭性流道(即流道的上方被封闭)，还可以避免第一结构层41和第二结构层42的上表面与流体接触所可能带来的寄生反应。此外，对于一些需要流体(例如液体)在流道中流动的应用，该实施例的覆盖有盖帽层的流道更容易控制这些流体的流动。
在一个实施例中，该盖帽层60的材料可以包括：绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅、硼磷硅玻璃、氧化铝、氧化钛或氧化钽等)或半导体材料(例如，多晶硅或非晶硅等)。
在一个实施例中，该盖帽层60的厚度范围可以为1纳米至10微米。例如，该盖帽层的厚度可以为10纳米、100纳米、500纳米、1微米或5微米等。
在一个实施例中，该流道结构器件还可以包括：贯穿盖帽层且连通到流道的通孔。
至此，提供了根据本发明一些实施例的制造方法和由这些制造方法所形成的流道结构器件。本发明实施例的流道可以是纳米流道。本发明具有以下优点：(1)可以实现高深宽比的纳米流道结构，尺寸可控性好；(2)可以实现全金属导电电极镶嵌结构；(3)可以有效提升纳米流道结构的可制造性，降低纳米流道结构制造成本；(4)具有比较低的热预算，可以与集成电路工艺兼容。此外，本发明实施例的流道结构器件可以实现在分子检测、液体形成或者流体运输控制等方面的应用。
在本发明的一个实施例中，还可以提供一种流道传感器。该流道传感器可以包括： 如前所述的流道结构器件(例如，如图22或如图24所示的流道结构器件)。
在本发明的一个实施例中，还可以提供一种生物化学分析设备。该生物化学分析设备可以包括：如前所述的流道结构器件(例如，如图22或如图24所示的流道结构器件)。
图25是示意性地示出根据本发明一个实施例的用于分子检测的芯片的结构图。如图25所示，该芯片250可以包括：流道结构器件2501、信号收集单元2502和信号处理单元2503。该流道结构器件2501包括电极(例如第一电极和第二电极)。例如该流道结构器件可以为如图22或如图24所示的流道结构器件。其中，待检测样品被加入到该流道结构器件的流道中，在该流道结构器件的电极(例如第一电极和第二电极)被施加电激励情况下，该待检测样品中的目标分子在电激励作用下产生电信号或光信号。
该信号收集单元2502可以用于收集该电信号或该光信号，并将该电信号或该光信号传输到该信号处理单元2503。
该信号处理单元2503可以用于对该电信号或该光信号进行信号处理，识别出目标分子的信息。
在本发明的实施例中，还提供了一种分子检测方法。该方法可以包括：使用如前所述的芯片(例如如图25所示的芯片)进行分子检测。
图26是示出根据本发明一个实施例的分子检测方法的流程图。下面结合图26来描述使用芯片进行分子检测的步骤。
在步骤S2601，对待检测样品进行处理。例如可以对待检测样品进行化学处理或其他处理。
在步骤S2602，将待检测样品加入到芯片中。例如将待检测样品加入到该芯片的流道结构器件的流道中。
在步骤S2603，对芯片中的流道结构器件中的电极(例如第一电极和第二电极)施加电激励，使得待检测样品中的目标分子在电激励作用下产生电信号或光信号。
在步骤S2604，芯片的信号处理单元通过信号收集单元获得电信号或光信号，并对该电信号或该光信号进行信号处理，识别出目标分子的信息。
在上述实施例中，通过使用包含本发明实施例的流道结构器件的芯片实现了分子检测的应用。
至此，已经详细描述了本发明。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (27)

  1. 一种流道结构器件的制造方法，其特征在于，包括：
    提供基片，所述基片包括第一部分和与所述第一部分邻接的第二部分；
    在所述基片上形成图形化的第一牺牲层，所述第一牺牲层覆盖所述第二部分且露出所述第一部分；
    在所述基片的第一部分和所述第一牺牲层上形成第一结构层；
    在形成所述第一结构层之后，执行第一抛光处理以露出所述第一牺牲层；
    去除所述第一牺牲层以露出所述基片的第二部分的上表面和所述第一结构层的侧面；
    在所述基片的第二部分的部分上表面上形成第二牺牲层，其中所述第二牺牲层覆盖所述第一结构层的被露出的侧面；
    在所述基片的第二部分、所述第二牺牲层和所述第一结构层上形成第二结构层；
    在形成所述第二结构层之后，执行第二抛光处理以露出所述第二牺牲层；以及
    利用选择性刻蚀工艺去除所述第二牺牲层以形成流道。
  2. 根据权利要求1所述的方法，其特征在于，
    在执行所述第二抛光处理的步骤中，还露出所述第一结构层和所述第二结构层；
    在利用选择性刻蚀工艺去除所述第二牺牲层之前，所述方法还包括：在所述第二牺牲层、所述第一结构层和所述第二结构层上形成盖帽层。
  3. 根据权利要求1所述的方法，其特征在于，
    所述形成第一结构层的步骤包括：在所述基片的第一部分和所述第一牺牲层上形成第一材料层，其中所述第一材料层覆盖所述第一牺牲层的侧面；以及在所述第一材料层上形成第一支撑层；其中，所述第一结构层包括：所述第一材料层和所述第一支撑层；
    所述形成第二结构层的步骤包括：在所述基片的第二部分、所述第二牺牲层和所述第一结构层上形成第二材料层，所述第二材料层覆盖所述第二牺牲层的侧面；以及在所述第二材料层上形成第二支撑层；其中，所述第二结构层包括：所述第二材料层 和所述第二支撑层。
  4. 根据权利要求3所述的方法，其特征在于，
    在去除所述第一牺牲层以露出所述第一结构层的侧面的步骤中，所露出的所述第一结构层的侧面为所述第一材料层的侧面；
    在形成第二牺牲层的步骤中，所述第二牺牲层覆盖所述第一材料层的被露出的侧面。
  5. 根据权利要求3所述的方法，其特征在于，
    在执行所述第二抛光处理的步骤中，还露出所述第一材料层、所述第一支撑层、所述第二材料层和所述第二支撑层；
    在利用选择性刻蚀工艺去除所述第二牺牲层之前，所述方法还包括：在所述第二牺牲层、所述第一材料层、所述第一支撑层、所述第二材料层和所述第二支撑层上形成盖帽层。
  6. 根据权利要求2或5所述的方法，其特征在于，
    所述盖帽层的材料包括：绝缘介质材料或半导体材料；
    所述盖帽层的厚度范围为1纳米至10微米。
  7. 根据权利要求2或5所述的方法，其特征在于，
    在利用选择性刻蚀工艺去除所述第二牺牲层的步骤中，从所述第二牺牲层的边缘注入选择性刻蚀液以去除所述第二牺牲层。
  8. 根据权利要求2或5所述的方法，其特征在于，
    在利用选择性刻蚀工艺去除所述第二牺牲层之前，所述方法还包括：对所述盖帽层进行刻蚀以形成贯穿所述盖帽层且露出所述第二牺牲层的通孔；
    其中，在利用选择性刻蚀工艺去除所述第二牺牲层的步骤中，从所述通孔注入选择性刻蚀液以去除所述第二牺牲层。
  9. 根据权利要求3所述的方法，其特征在于，
    所述第一材料层的一部分在所述第一支撑层与所述流道之间，所述第一材料层的另一部分在所述第一支撑层与所述基片的第一部分之间；
    所述第二材料层的一部分在所述第二支撑层与所述流道之间，所述第二材料层的另一部分在所述第二支撑层与所述基片的第二部分之间。
  10. 根据权利要求9所述的方法，其特征在于，
    所述第一材料层的材料包括：金属材料或半导体材料；
    所述第二材料层的材料包括：金属材料或半导体材料；
    其中，所述第一材料层的在所述第一支撑层与所述流道之间的部分作为所述流道结构器件的第一电极；所述第一材料层的在所述第一支撑层与所述基片的第一部分之间的部分作为所述第一电极的第一引线；所述第二材料层的在所述第二支撑层与所述流道之间的部分作为所述流道结构器件的第二电极；所述第二材料层的在所述第二支撑层与所述基片的第二部分之间的部分作为所述第二电极的第二引线。
  11. 根据权利要求3所述的方法，其特征在于，
    所述第一材料层的材料和所述第二材料层的材料分别包括：绝缘介质材料。
  12. 根据权利要求1所述的方法，其特征在于，
    所述第一牺牲层的厚度根据所需要的流道的高度来确定；
    所述第一牺牲层的厚度范围为100纳米至100微米。
  13. 根据权利要求1所述的方法，其特征在于，
    所述第二牺牲层的厚度根据所需要的流道的宽度来确定；
    所述第二牺牲层的厚度范围为0.1纳米至1微米。
  14. 根据权利要求3所述的方法，其特征在于，
    所述第一材料层的厚度范围为1纳米至500纳米；
    所述第一支撑层的厚度范围为100纳米至100微米；
    所述第二材料层的厚度范围为1纳米至500纳米；
    所述第二支撑层的厚度范围为100纳米至100微米。
  15. 一种流道结构器件，其特征在于，包括：
    基片，所述基片包括第一部分和与所述第一部分邻接的第二部分；
    在所述基片上的第一结构层和第二结构层；其中，所述第一结构层包括：在所述基片的第一部分上的第一材料层和在所述第一材料层上的第一支撑层，所述第二结构层包括：在所述基片的第二部分上的第二材料层和在所述第二材料层上的第二支撑层；
    在所述第一材料层与所述第二材料层之间的流道；所述第一支撑层和所述第二支撑层分别在所述流道的两侧；
    其中，所述第一材料层的一部分在所述第一支撑层与所述流道之间，所述第一材料层的另一部分在所述第一支撑层与所述基片的第一部分之间；所述第二材料层的一部分在所述第二支撑层与所述流道之间，所述第二材料层的另一部分在所述第二支撑层与所述基片的第二部分之间。
  16. 根据权利要求15所述的流道结构器件，其特征在于，还包括：
    覆盖在所述第一材料层、所述第一支撑层、所述第二材料层和所述第二支撑层上的盖帽层；其中，所述盖帽层覆盖在所述流道之上。
  17. 根据权利要求16所述的流道结构器件，其特征在于，
    所述盖帽层的材料包括：绝缘介质材料或半导体材料；
    所述盖帽层的厚度范围为1纳米至10微米。
  18. 根据权利要求16所述的流道结构器件，其特征在于，还包括：
    贯穿所述盖帽层且连通到所述流道的通孔。
  19. 根据权利要求15所述的流道结构器件，其特征在于，
    所述第一材料层的材料包括：金属材料或半导体材料；
    所述第二材料层的材料包括：金属材料或半导体材料；
    其中，所述第一材料层的在所述第一支撑层与所述流道之间的部分作为所述流道结构器件的第一电极；所述第一材料层的在所述第一支撑层与所述基片的第一部分之间的部分作为所述第一电极的第一引线；所述第二材料层的在所述第二支撑层与所述流道之间的部分作为所述流道结构器件的第二电极；所述第二材料层的在所述第二支撑层与所述基片的第二部分之间的部分作为所述第二电极的第二引线。
  20. 根据权利要求15所述的流道结构器件，其特征在于，
    所述第一材料层的材料和所述第二材料层的材料分别包括：绝缘介质材料。
  21. 根据权利要求15所述的流道结构器件，其特征在于，
    所述流道的高度范围为100纳米至100微米；
    所述流道的宽度范围为0.1纳米至1微米。
  22. 根据权利要求15所述的流道结构器件，其特征在于，
    所述第一材料层的厚度范围为1纳米至500纳米；
    所述第一支撑层的厚度范围为100纳米至100微米；
    所述第二材料层的厚度范围为1纳米至500纳米；
    所述第二支撑层的厚度范围为100纳米至100微米。
  23. 一种流道传感器，其特征在于，包括：如权利要求15至22任意一项所述的流道结构器件。
  24. 一种生物化学分析设备，其特征在于，包括：如权利要求15至22任意一项所述的流道结构器件。
  25. 一种用于分子检测的芯片，其特征在于，包括：如权利要求19所述流道结构器件、信号收集单元和信号处理单元；
    其中，待检测样品被加入到所述流道结构器件的流道中，在所述流道结构器件的电极被施加电激励情况下，所述待检测样品中的目标分子在电激励作用下产生电信号 或光信号；
    所述信号收集单元用于收集所述电信号或所述光信号，并将所述电信号或所述光信号传输到所述信号处理单元；
    所述信号处理单元用于对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
  26. 一种分子检测方法，其特征在于，包括：使用如权利要求25所述的芯片进行分子检测。
  27. 根据权利要求26所述的分子检测方法，其特征在于，使用所述芯片进行分子检测的步骤包括：
    对待检测样品进行处理；
    将所述待检测样品加入到所述芯片中；
    对所述芯片中的流道结构器件中的电极施加电激励，使得所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；以及
    所述芯片的所述信号处理单元通过所述信号收集单元获得所述电信号或所述光信号，并对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
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