WO2019023943A1 - Dispositif de structure de canal fluidique et procédé de fabrication associé - Google Patents

Dispositif de structure de canal fluidique et procédé de fabrication associé Download PDF

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Publication number
WO2019023943A1
WO2019023943A1 PCT/CN2017/095498 CN2017095498W WO2019023943A1 WO 2019023943 A1 WO2019023943 A1 WO 2019023943A1 CN 2017095498 W CN2017095498 W CN 2017095498W WO 2019023943 A1 WO2019023943 A1 WO 2019023943A1
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layer
flow channel
material layer
substrate
sacrificial
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PCT/CN2017/095498
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English (en)
Chinese (zh)
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云全新
林建勋
董龙涛
汪天书
朱国丽
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深圳华大基因研究院
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Priority to PCT/CN2017/095498 priority Critical patent/WO2019023943A1/fr
Priority to CN201780090943.XA priority patent/CN110770160B/zh
Publication of WO2019023943A1 publication Critical patent/WO2019023943A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate

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  • the present invention relates to the field of semiconductor technology, and in particular, to a flow channel structure device and a method of fabricating the same.
  • Micro-nano flow control analysis technology based on micro-nano flow channel is being studied and applied more and more in the fields of biochemical analysis and gene sequencing.
  • the combination of micro-nano channel devices and integrated circuits (ICs) will also help to improve the automation and miniaturization of micro-analysis systems and better expand their application space.
  • electrode materials need to be embedded in the micro-nano flow channels, and in some designs, nano-flow channels with high aspect ratios are required.
  • electron beam lithography or laser lithography may be employed, and an anisotropic etching process is combined to realize a nano flow channel.
  • direct electron beam or laser lithography methods are inefficient, have poor dimensional adjustability, and are difficult to achieve high aspect ratios on metallic materials, usually only about one.
  • the side wall method can also be used to implement the above micro-nano flow path structure.
  • the sidewall method must rely on the side wall support structure of the semiconductor material to achieve structural interconnection and signal extraction, which will bring more parasitic effects, and ultimately affect the quality of the detection signal, and the process thermal budget is high, which is not conducive to integration with CMOS chips.
  • most electrode extractions in the prior art rely on spliced metal interconnects (e.g., typically aluminum and copper) or semiconductor interconnects (e.g., typically polysilicon) to form an alloy structure with the electrode material.
  • the alloy structure has the following disadvantages: (1) The alloy process requires an additional heat treatment process, which will increase the process heat budget, which is not conducive to process integration on the IC chip.
  • a typical polysilicon interconnect process for example, a polysilicon deposition process is required (the temperature is usually high). At 600 ° C), ion implantation and activation (usually above 550 ° C) and metal semiconductor alloys (usually above 400 ° C) and other high thermal budget technology; (2) alloy body will introduce additional contact resistance, which Will reduce device performance.
  • the nanogap structure can also be realized by adjusting the metal sputtering angle.
  • the particle sputtering direction is at an angle to the surface of the substrate substrate, and the groove can be prepared in advance by adjusting the angle.
  • a dead angle of sputtering is generated at the bottom to obtain a nano-gap flow path structure, but process controllability and dimensional adjustability are poor.
  • the inventors of the present invention have found that there is a problem in the above prior art, and thus propose a new technical solution to at least one of the problems.
  • a method of fabricating a flow path structure device comprising: providing a substrate, the substrate comprising a first portion and a second portion abutting the first portion; on the substrate Forming a patterned first sacrificial layer, the first sacrificial layer covering the second portion and exposing the first portion; forming a first structural layer on the first portion of the substrate and the first sacrificial layer; After forming the first structural layer, performing a first polishing process to expose the first sacrificial layer; removing the first sacrificial layer to expose an upper surface of the second portion of the substrate and the first structure a side surface of the layer; a second sacrificial layer is formed on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer; Forming a second structural layer on the second portion, the second sacrificial layer and the first structural layer; after forming the second structural layer
  • the first structural layer and the second structural layer are also exposed; before the second sacrificial layer is removed by a selective etching process, the method also includes forming a cap layer on the second sacrificial layer, the first structural layer, and the second structural layer.
  • the forming the first structural layer includes: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers the first a side of a sacrificial layer; and forming a first support layer on the first material layer; wherein the first structural layer comprises: the first material layer and the first support layer;
  • the step of forming a structural layer includes: forming a second material layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer, the second material layer covering the second sacrificial layer Forming a second support layer on the second material layer; wherein the second structural layer comprises: the second material layer and the second support layer.
  • a side of the exposed first structural layer is a side of the first material layer;
  • the second sacrificial layer covers the exposed side of the first material layer.
  • the first material layer is further exposed, The first support layer, the second material layer, and the second support layer; before removing the second sacrificial layer by a selective etching process, the method further includes: at the second sacrificial layer a cap layer is formed on the first material layer, the first support layer, the second material layer, and the second support layer.
  • the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness ranging from 1 nanometer to 10 micrometers.
  • a selective etchant is implanted from an edge of the second sacrificial layer to remove the second sacrificial layer.
  • the method before removing the second sacrificial layer by a selective etch process, the method further includes: etching the capping layer to form through the capping layer and exposing the second sacrificial a via hole of the layer; wherein, in the step of removing the second sacrificial layer by a selective etching process, a selective etching liquid is injected from the via hole to remove the second sacrificial layer.
  • a portion of the first material layer is between the first support layer and the flow channel, and another portion of the first material layer is between the first support layer and the substrate Between the first portions of the second material layer between the second support layer and the flow channel, and another portion of the second material layer between the second support layer and the substrate Between the second part.
  • the material of the first material layer comprises: a metal material or a semiconductor material; the material of the second material layer comprises: a metal material or a semiconductor material; wherein the first material layer is in the a portion between the first support layer and the flow channel as a first electrode of the flow channel structure device; between the first support layer and the first portion of the substrate a portion as a first lead of the first electrode; a portion of the second material layer between the second support layer and the flow channel as a second electrode of the flow channel structure device; A portion of the two material layers between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
  • the material of the first material layer and the material of the second material layer respectively comprise: an insulating dielectric material.
  • the thickness of the first sacrificial layer is determined according to the height of the desired flow channel; the thickness of the first sacrificial layer ranges from 100 nanometers to 100 micrometers.
  • the thickness of the second sacrificial layer is determined according to the width of the desired flow channel; the thickness of the second sacrificial layer ranges from 0.1 nanometers to 1 micrometer.
  • the first material layer has a thickness ranging from 1 nanometer to 500 nanometers; the first branch The thickness of the interlayer ranges from 100 nanometers to 100 micrometers; the thickness of the second material layer ranges from 1 nanometer to 500 nanometers; and the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.
  • a patterned first sacrificial layer is formed on a substrate; a first structural layer is formed on the first portion of the substrate and the first sacrificial layer; a first polishing process is performed to expose the first sacrificial layer; a sacrificial layer to expose an upper surface of the second portion of the substrate and a side of the first structural layer; a second sacrificial layer formed on a portion of the upper surface of the second portion of the substrate; the second portion and the second portion of the substrate Forming a second structural layer on the sacrificial layer and the first structural layer; performing a second polishing process to expose the second sacrificial layer after forming the second structural layer; and removing the second sacrificial layer by a selective etching process to form Flow path.
  • the above manufacturing method of the present invention can form a flow path structure device having a vertical flow path, and the above manufacturing method can reduce the process heat budget and facilitate integration of the flow path structure device and the CMOS chip.
  • the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high aspect ratio flow path structure can be realized.
  • the first material layer may include the first electrode and the first lead
  • the second material layer may include the second electrode and the first
  • a flow path structure device comprising: a substrate comprising a first portion and a second portion abutting the first portion; a first structure on the substrate a layer and a second structural layer; wherein the first structural layer comprises: a first material layer on the first portion of the substrate and a first support layer on the first material layer, the second The structural layer includes: a second material layer on the second portion of the substrate and a second support layer on the second material layer; between the first material layer and the second material layer a flow channel; the first support layer and the second support layer are respectively on opposite sides of the flow channel; wherein a portion of the first material layer is in the first support layer and the flow channel Another portion of the first material layer between the first support layer and the first portion of the substrate; a portion of the second material layer between the second support layer and the flow channel Another portion of the second material layer between the second support layer and the second portion of the substrate Room.
  • the flow channel structure device further includes: a capping layer covering the first material layer, the first support layer, the second material layer, and the second support layer; The cap layer is covered in the Above the flow path.
  • the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness ranging from 1 nanometer to 10 micrometers.
  • the flow channel structure device further includes a through hole penetrating the cap layer and communicating to the flow channel.
  • the material of the first material layer comprises: a metal material or a semiconductor material; the material of the second material layer comprises: a metal material or a semiconductor material; wherein the first material layer is in the a portion between the first support layer and the flow channel as a first electrode of the flow channel structure device; between the first support layer and the first portion of the substrate a portion as a first lead of the first electrode; a portion of the second material layer between the second support layer and the flow channel as a second electrode of the flow channel structure device; A portion of the two material layers between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
  • the material of the first material layer and the material of the second material layer respectively comprise: an insulating dielectric material.
  • the flow channel has a height ranging from 100 nanometers to 100 micrometers; the flow channel has a width ranging from 0.1 nanometers to 1 micrometer.
  • the first material layer has a thickness ranging from 1 nanometer to 500 nanometers; the first support layer has a thickness ranging from 100 nanometers to 100 micrometers; and the second material layer has a thickness ranging from 1 nanometer to 1 nanometer. Up to 500 nm; the second support layer has a thickness ranging from 100 nm to 100 microns.
  • the flow path structure device of the above embodiment of the present invention has a vertical flow path, which can increase the manufacturing density of the flow path on the chip, reduce manufacturing and application costs, and the like.
  • the above-described flow path structure device can realize a flow structure of a high aspect ratio.
  • the first material layer may include the first electrode and the first lead
  • the second material layer may include the second electrode and the first
  • a flow path sensor comprising: a flow path structure device as described above.
  • a biochemical analysis apparatus comprising: a flow path structure device as described above.
  • a chip for molecular detection comprising: a flow path structure device, a signal collection unit, and a signal processing unit as described above; wherein a sample to be detected is added to the flow path In the flow channel of the structural device, in the case where the electrode of the flow channel structure device is electrically excited, the target molecule in the sample to be detected generates an electrical signal or an optical signal under electrical excitation; the signal collecting unit is used for Collecting the electrical signal or the optical signal and transmitting the electrical signal or the optical signal to the signal processing unit; the signal processing unit is configured to perform signal processing on the electrical signal or the optical signal Identifying information about the target molecule.
  • a method of molecular detection comprising: performing molecular detection using a chip as described above.
  • the step of performing molecular detection using the chip comprises: processing a sample to be detected; adding the sample to be detected to the chip; applying an electrode in a flow channel structure device in the chip Electrically exciting such that the target molecule in the sample to be detected generates an electrical signal or an optical signal under electrical excitation; and the signal processing unit of the chip obtains the electrical signal or the light through the signal collecting unit And signaling the electrical signal or the optical signal to identify information of the target molecule.
  • the application of molecular detection is realized by using a chip including the flow path structure device of the embodiment of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating a flow path structure device in accordance with one embodiment of the present invention.
  • FIGS 2 to 10 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • FIG. 11 is a view schematically showing a manufacturing process of a flow path structure device according to another embodiment of the present invention. A cross-sectional view of the structure of the stages.
  • Figure 12 is a plan view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 13 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • FIG 14 to 22 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 23 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 24 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention.
  • Figure 26 is a flow chart showing a molecular detection method in accordance with one embodiment of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating a flow path structure device in accordance with one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to an embodiment of the present invention. The manufacturing process of the flow path structure device according to an embodiment of the present invention will be described in detail below with reference to FIG. 1 and FIGS. 2 to 10.
  • step S101 a substrate is provided, the substrate including a first portion and a second portion adjacent to the first portion.
  • a substrate 21 is provided which may include a first portion 211 and a second portion 212 adjacent the first portion 211.
  • the substrate may include: a semiconductor substrate (e.g., silicon, germanium, etc.), an insulating substrate (e.g., quartz, silicon nitride, etc.), a wafer in which an IC circuit has been integrated, or any combination of these substrates.
  • FIG. 2 is only for convenience to show the first part and the second part, and the line does not necessarily exist in practice, and the following drawings are similar.
  • step S102 a patterned first sacrificial layer is formed on the substrate, the first sacrificial layer covering the second portion and exposing the first portion.
  • FIG. 3 is a cross-sectional view schematically showing the structure of the step S102 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a patterned first sacrificial layer 31 is formed on the substrate 21, and the first sacrificial layer 31 covers the second portion 212 and exposes the first portion 211.
  • the first sacrificial layer can serve as a defined layer of runner position.
  • the thickness of the first sacrificial layer can be determined according to the height of the desired flow channel. In one embodiment, the first sacrificial layer may have a thickness ranging from 100 nanometers to 100 micrometers.
  • the first sacrificial layer may have a thickness of 500 nm, 1 micron, 10 micron, or 50 micron, or the like.
  • the material of the first sacrificial layer may include: a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials), an insulating dielectric material (eg, silicon oxide, nitrogen) Silicon, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials) or a metal material (for example, aluminum, copper, or the like, or a combination of metal materials).
  • the step S102 may include forming a first sacrificial layer on the substrate, the first sacrificial layer covering the first portion and the second portion of the substrate.
  • the step S102 may further include: patterning the first sacrificial layer by a photolithography method, thereby removing a portion of the first sacrificial layer covering the first portion to expose the first portion.
  • the photolithography method may include pattern exposure, pattern development, pattern etching, and the like.
  • the method of pattern exposure may include: optical exposure, electron beam exposure, or nanoimprint.
  • the method of pattern etching may include: wet etching or dry etching.
  • step S103 a first structural layer is formed on the first portion of the substrate and the first sacrificial layer.
  • a first structural layer 41 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31, for example, by a deposition process.
  • the first structural layer 41 covers the side of the first sacrificial layer 31.
  • the thickness of the first structural layer is greater than or equal to the thickness of the first sacrificial layer, so that during the subsequent execution of the first polishing process, the portion of the first sacrificial layer may be polished and removed as little as possible, which is beneficial for control.
  • the height of the flow path obtained subsequently is not limited thereto.
  • the thickness of the first structural layer may also be smaller than the thickness of the first sacrificial layer.
  • the material of the first structural layer may include: a metal material (for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials), a semiconductor material (eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials, or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric materials).
  • a metal material for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials
  • a semiconductor material eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric
  • step S104 after forming the first structural layer, a first polishing process is performed to expose the first sacrificial layer.
  • FIG. 5 is a cross-sectional view schematically showing the structure of step S104 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a first polishing process for example, CMP (Chemical Mechanical Polishing)
  • CMP Chemical Mechanical Polishing
  • the polishing process can remove portions of the first structural layer on the top surface of the first sacrificial layer.
  • step S105 the first sacrificial layer is removed to expose the upper surface of the second portion of the substrate and the side of the first structural layer.
  • Fig. 6 is a cross-sectional view schematically showing the structure of the flow path structure device in the manufacturing process of step S105 according to an embodiment of the present invention.
  • the first sacrificial layer 31 is removed, for example, by a selective etching process, thereby exposing the upper surface of the second portion 212 of the substrate 21 and the side of the first structural layer 41.
  • the selective etching process may include: dry etching or wet etching.
  • a second sacrificial layer is formed on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer.
  • Fig. 7 is a cross-sectional view schematically showing the structure of the step S106 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • the first structural layer 41 is supported as the support on the substrate 21.
  • a second sacrificial layer 32 is formed on a portion of the upper surface of the second portion 212, wherein the second sacrificial layer 32 covers the exposed side of the first structural layer 41.
  • the step S106 may include: depositing a second sacrificial layer on the semiconductor structure shown in FIG. 6; then performing etch back on the second sacrificial layer to form the structure shown in FIG.
  • the thickness of the second sacrificial layer can be determined according to the width of the desired flow channel.
  • the second sacrificial layer may have a thickness ranging from 0.1 nanometers to 1 micrometer.
  • the thickness of the second sacrificial layer may be 1 nm, 10 nm, 100 nm or 500 nm or the like.
  • the material of the second sacrificial layer may include: a metal material (such as chromium, aluminum, titanium, etc. or a combination of metal materials), a semiconductor material (such as polysilicon, amorphous silicon, indium tin oxide, etc. or A combination of a plurality of semiconductor materials) or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials).
  • a metal material such as chromium, aluminum, titanium, etc. or a combination of metal materials
  • a semiconductor material such as polysilicon, amorphous silicon, indium tin oxide, etc. or A combination of a plurality of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials.
  • a second structural layer is formed on the second portion of the substrate, the second sacrificial layer, and the first structural layer.
  • Fig. 8 is a cross-sectional view schematically showing the structure of the step S107 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a second structural layer 42 is formed on the second portion 212 of the substrate 21, the second sacrificial layer 32, and the first structural layer 41, for example, by a deposition process.
  • the thickness of the second structural layer is greater than or equal to the height of the second sacrificial layer, so that during the subsequent performing of the second polishing process, the portion of the second sacrificial layer may be polished and removed as little as possible, which is beneficial for control.
  • the height of the flow path obtained subsequently is not limited thereto.
  • the thickness of the second structural layer may also be smaller than the height of the second sacrificial layer.
  • the material of the second structural layer may include: a metal material (for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials), a semiconductor material (eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials, or an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric materials).
  • a metal material for example, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials
  • a semiconductor material eg, polysilicon, non- A combination of crystalline silicon, indium tin oxide, or the like, or a plurality of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of insulating dielectric
  • step S108 after forming the second structural layer, a second polishing process is performed to expose the second sacrificial layer.
  • Figure 9 is a cross-sectional view schematically showing the structure of the flow path structure device in the manufacturing process of step S108 in accordance with one embodiment of the present invention.
  • a second polishing process e.g., CMP
  • CMP chemical vapor deposition
  • the first structural layer 41 and the second structural layer 42 may also be exposed, for example, exposing the top of the first structural layer 41.
  • the second polishing process may remove portions of the second structural layer on the top surfaces of the first structural layer and the second sacrificial layer.
  • step S109 the second sacrificial layer is removed using a selective etching process to form a flow path.
  • Figure 10 is a cross-sectional view schematically showing the structure of the step S109 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • the second sacrificial layer 32 is removed by a selective etching process to form the flow channel 50.
  • the height of the flow channel can range from 100 nanometers to 100 microns.
  • the flow channel may have a width ranging from 0.1 nanometers to 1 micrometer.
  • a method of manufacturing a flow path structure device has been provided.
  • a patterned first sacrificial layer is formed on a substrate; a first structural layer is formed on the first portion of the substrate and the first sacrificial layer; a first polishing process is performed to expose the first sacrificial layer; a sacrificial layer to expose an upper surface of the second portion of the substrate and a side of the first structural layer; a second sacrificial layer formed on a portion of the upper surface of the second portion of the substrate; the second portion and the second portion of the substrate Forming a second structural layer on the sacrificial layer and the first structural layer; performing a second polishing process to expose the second sacrificial layer after forming the second structural layer; and removing the second sacrificial layer by a selective etching process to form Flow path.
  • a flow path structure device having a vertical flow path i.e., the flow path is perpendicular to the surface of the substrate
  • the flow path may be an open space in a direction perpendicular to the substrate or a transparent material may be provided, so this does not affect the transmission of the optical signal.
  • the effective surface area of a single flow channel can be the cross-sectional area of the flow channel, which can greatly increase the manufacturing density of the flow channel on the chip, and reduce manufacturing and application costs.
  • the above manufacturing method of the embodiment of the present invention can reduce the process heat budget.
  • the process of the present invention involves relatively low process temperatures (temperatures ranging from room temperature to 350 ° C) and short heat treatment times, thereby reducing the process thermal budget to facilitate integration of the flow channel structure device with the CMOS chip.
  • the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high aspect ratio flow path structure can be realized.
  • a flow path structure having a width of 10 nm and an aspect ratio of 100:1 can be realized.
  • the aspect ratio of the flow channel structure achieved by the method of the embodiment of the present invention may range from 1:1 to 100,000:1.
  • the flow path structure device includes a substrate, a first structural layer and a second structural layer on the substrate, and a flow path between the first structural layer and the second structural layer.
  • first structural layer and the second structural layer are respectively insulating dielectric materials
  • an insulating medium flow path structure device may be formed, which may be applied to fluid formation and control, and the like.
  • the first structural layer and the second structural layer are respectively conductive materials
  • a metal material or a semiconductor material for example, a doped semiconductor material
  • it can be used as an electrode on both sides of the flow path, which can be used for fluid processing, biochemical detection, and the like.
  • FIGS. 11 and 13 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 12 is a plan view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention. The manufacturing process of the flow path structure device according to further embodiments of the present invention will be described in detail below with reference to FIGS. 11 through 13.
  • the manufacturing method may further include: as shown in FIG. 11, at the second sacrificial layer 32, the first structural layer 41, and A cap layer 60 is formed on the second structural layer 42.
  • the cap layer 60 may implement a closed flow path together with the first structural layer 41 and the second structural layer 42 (ie, the upper side of the flow path is closed), and the first structural layer 41 may be avoided. And the parasitic reaction that may occur with the upper surface of the second structural layer 42 in contact with the fluid.
  • the material of the capping layer 60 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or a semiconductor material. (for example, polysilicon or amorphous silicon, etc.).
  • the capping layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers.
  • the cap layer may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer or 5 micrometers, and the like.
  • a selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer, thereby forming a structure as shown in FIG.
  • the planarly extending second sacrificial layer is bordered, and the edge of the second sacrificial layer may be exposed, so that a selective etching solution is implanted at the edge of the second sacrificial layer (ie, at the boundary) to remove The second sacrificial layer forms a flow channel.
  • the manufacturing method may further include: etching the capping layer 60 to form a capping layer and exposing as shown in FIG. The through hole 61 of the second sacrificial layer.
  • the selective etching liquid may be injected from the via hole 61 to remove the second sacrificial layer, thereby forming the channel structure device as shown in FIG.
  • the number, shape or size of the through holes can be determined according to design requirements, and the scope of the present invention is not limited to the number, shape or size of the through holes shown in FIG.
  • the selective etching liquid is facilitated to pass through the via hole.
  • the corrosion rate can be increased.
  • the flow path structure device further includes: a cap layer 60 on the first structural layer 41 and the second structural layer 42.
  • the cap layer 60 covers the flow path.
  • the cap layer 60 can implement a closed flow path (ie, the upper side of the flow channel is closed) together with the first structural layer 41 and the second structural layer 42 and can also avoid the upper surface of the first structural layer 41 and the second structural layer 42. Parasitic reactions that may be caused by contact with fluids.
  • the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids.
  • the flow channel structure device may further include: a through hole penetrating the cap layer and communicating to the flow channel.
  • the forming the first structural layer may include: forming a first material layer on the first portion of the substrate and the first sacrificial layer, wherein the first material layer covers a side of the first sacrificial layer; A first support layer is formed on the first material layer.
  • the first structural layer may include: the first material layer and the first support layer.
  • the step of forming the second structural layer may include forming a second material layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer, the second material layer covering the second a side of the sacrificial layer; and a second support layer formed on the second material layer.
  • the second structural layer may include: the second material layer and the second support layer.
  • FIGS. 14 to 22 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • the following is an example in which the first structural layer includes the first material layer and the first support layer, and the second structural layer includes the second material layer and the second support layer, and is further described in detail with reference to FIGS. 14 to 22 according to another embodiment of the present invention.
  • the manufacturing process of the flow channel structure device is
  • a substrate is provided that includes a first portion and a second portion that is contiguous with the first portion. This step has been described in detail above with reference to FIG. 2 and will not be described again here.
  • a patterned first sacrificial layer is formed on the substrate, the first sacrificial layer covering the second portion and exposing the first portion. This step has been described in detail above with reference to FIG. 3 and will not be described again here.
  • a first material layer 411 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31, for example, by a deposition process, wherein the first material layer 411 covers the first sacrificial layer 31. The side.
  • the material of the first material layer 411 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials) or a semiconductor material (eg, polysilicon, Amorphous silicon, indium tin oxide, or the like, or a combination of a plurality of semiconductor materials).
  • the first material layer can be made of metal A conductive material such as a material or a semiconductor material (for example, a doped semiconductor material), such that the first material layer can be used as one of the embedded electrode layers of the subsequently formed flow channel, and can be applied to fluid processing or biochemical detection.
  • the material of the first material layer 411 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials).
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials.
  • the first material layer 411 may have a thickness ranging from 1 nanometer to 500 nanometers.
  • the thickness of the first material layer 411 may be 10 nm, 50 nm, 100 nm or 300 nm or the like.
  • a first support layer 412 is formed on the first material layer 411, for example, by a deposition process.
  • the first support layer 412 can serve as a support layer for the first material layer 411. So far, the first structural layer 41 is formed.
  • the first structural layer 41 may include a first material layer 411 on the first portion 211 of the substrate 21 and the first sacrificial layer 31 and a first support layer 412 on the first material layer 411.
  • the material of the first support layer 412 may include: a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials), an insulating dielectric material (eg, silicon oxide, nitrogen) Silicon, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials) or a conductive metal material (for example, aluminum, copper, titanium, titanium nitride, or the like, or a combination of a plurality of metal materials).
  • a semiconductor material eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, nitrogen
  • Silicon silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials
  • a conductive metal material for example, aluminum, copper, titanium, titanium nitride, or the like, or a
  • the first support layer has a thickness ranging from 100 nanometers to 100 micrometers.
  • the thickness of the first support layer may be 200 nanometers, 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.
  • a first polishing process (e.g., CMP) is performed on the first structural layer 41 (i.e., the first support layer 412 and the first material layer 411) to expose the first sacrificial layer 31.
  • the first polishing process may remove portions of the first support layer 412 and the first material layer 411 located on the top surface of the first sacrificial layer 31.
  • the first sacrificial layer 31 is removed, for example, by a selective etching process to expose the upper surface of the second portion 212 of the substrate 21 and the side of the first structural layer 41.
  • the exposed side surface of the first structural layer 41 is the side surface of the first material layer 411.
  • a second sacrificial layer 32 is formed on a portion of the upper surface of the second portion 212 of the substrate 21 with the first support layer 412 and the first material layer 411 as supports, wherein the second sacrifice Layer 32 covers the exposed side of first structural layer 41.
  • the second sacrificial layer 32 covers the exposed side of the first material layer 411.
  • the second sacrifice A second material layer 421 is formed on the layer 32 and the first structural layer 41 (ie, the first material layer 411 and the first support layer 412), and the second material layer 421 covers the side surface of the second sacrificial layer 32.
  • the material of the second material layer 421 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metal materials) or a semiconductor material (eg, polysilicon, Amorphous silicon, indium tin oxide, or the like, or a combination of a plurality of semiconductor materials).
  • the second material layer may be a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material), such that the second material layer may serve as one of the embedded electrode layers of the subsequently formed flow channel. Used in fluid processing or biochemical testing.
  • the material of the second material layer 421 may include: an insulating dielectric material (for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials). This makes it possible to form a flow path formed of an insulating dielectric material in a subsequent step, which can be applied to fluid formation and control and the like.
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials.
  • the second material layer 421 may have a thickness ranging from 1 nanometer to 500 nanometers.
  • the thickness of the second material layer 421 may be 10 nm, 50 nm, 100 nm or 300 nm or the like.
  • a second support layer 422 is formed on the second material layer 421, for example, by a deposition process.
  • the second support layer 422 can serve as a support layer for the second material layer 421. So far, the second structural layer 42 is formed.
  • the second structural layer 42 may include a second material layer on the second portion 212 of the substrate 21, the second sacrificial layer 32, and the first structural layer 41 (ie, the first material layer 411 and the first support layer 412) 421 and a second support layer 422 on the second material layer 421.
  • the material of the second support layer 422 may include: a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials), an insulating dielectric material (eg, silicon oxide, Silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials) or a conductive metal material (for example, aluminum, copper, titanium, titanium nitride, or the like, or a combination of metal materials).
  • a semiconductor material eg, polysilicon, amorphous silicon, indium tin oxide, or the like, or a combination of semiconductor materials
  • an insulating dielectric material eg, silicon oxide, Silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials
  • a conductive metal material for example, aluminum, copper, titanium, titanium nitride, or the like, or
  • the second support layer 422 may have a thickness ranging from 100 nanometers to 100 micrometers.
  • the thickness of the second support layer may be 200 nm, 500 nm, 1 micron, 10 micron or 50 micron, or the like.
  • a second polishing process (e.g., CMP) is performed on the second structural layer 42 (i.e., the second support layer 422 and the second material layer 421) to expose the second sacrificial layer 32.
  • the second polishing process may also remove portions of the second material layer 421 and the second support layer 422 on the top surface of the first support layer 412.
  • the first material layer 411, the first support layer 412, the second material layer 421, and the second support layer 422 are also exposed.
  • the second sacrificial layer 32 is removed by a selective etching process to form the flow channel 50.
  • the first structural layer may include: a first material layer and a first support layer, wherein a portion of the first material layer is between the first support layer and the flow channel, Another portion of the first material layer is between the first support layer and the first portion of the substrate;
  • the second structural layer can include: a second material layer and a second support layer, wherein a portion of the second material layer is Between the second support layer and the flow channel, another portion of the second material layer is between the second support layer and the second portion of the substrate.
  • the material of the first material layer comprises a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • a portion of the first material layer between the first support layer and the flow channel may serve as the flow
  • a first electrode of the track structure device, a portion of the first material layer between the first support layer and the first portion of the substrate may serve as a first lead of the first electrode.
  • the material of the second material layer comprises a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • a portion of the second material layer between the second support layer and the flow channel may serve as the flow
  • a second electrode of the track structure device, a portion of the second material layer between the second support layer and the second portion of the substrate may serve as a second lead of the second electrode. Since the first material layer and the second material layer are integrally formed by, for example, a deposition process, the contact resistance can be reduced between the first electrode and the first lead, and the second electrode is compared with the prior art. The contact resistance can also be reduced between the second leads, thereby improving device performance.
  • the above manufacturing method of the embodiment of the present invention can reduce the process heat budget.
  • the process of the present invention involves relatively low process temperatures (temperatures ranging from room temperature to 350 ° C) and short heat treatment times, thereby reducing the process thermal budget to facilitate integration of the flow channel structure device with the CMOS chip.
  • the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high aspect ratio flow path structure can be realized.
  • the flow path structure device may include a substrate 21, which may include a first portion 211 and a second portion 212 adjacent to the first portion 211.
  • the flow path structure device may further include: a first structural layer 41 and a second structural layer 42 on the substrate 21.
  • the first structural layer 41 may include: a first material layer 411 on the first portion 211 of the substrate 21 and a first support layer 412 on the first material layer 411
  • the second structural layer 42 may include : a second material layer 421 on the second portion 212 of the substrate 21 and a second support layer 422 on the second material layer 421.
  • the runner structure device may further include a flow passage 50 between the first material layer 411 and the second material layer 421.
  • the first support layer 421 and the second support layer 422 are respectively on both sides of the flow channel 50.
  • the first material A portion of the material layer 411 is between the first support layer 412 and the flow channel 50, and another portion of the first material layer 411 is between the first support layer 412 and the first portion 211 of the substrate 21;
  • a portion of the material layer 421 is between the second support layer 422 and the flow channel 50, and another portion of the second material layer 421 is between the second support layer 422 and the second portion 212 of the substrate 21.
  • the flow path structure device of the above embodiment of the present invention has a vertical flow path, for example, the flow path may be an open space in a direction perpendicular to the substrate or may be provided with a transparent material, so that this does not affect the transmission of the optical signal.
  • the effective surface area of a single flow channel is the cross-sectional area of the flow channel, which can greatly increase the manufacturing density of the flow channel on the chip, and can increase the application flux (ie, the number of flow channels per unit area). And reduce manufacturing and application costs.
  • the height of the flow channel 50 can range from 100 nanometers to 100 microns.
  • the height of the flow channel may be 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.
  • the flow channel 50 may have a width ranging from 0.1 nanometers to 1 micrometer.
  • the width of the flow channel may be 1 nm, 10 nm, 14 nm, 100 nm or 500 nm, and the like.
  • the flow channel structure device can realize a high aspect ratio flow path structure after selecting a suitable flow path height and width.
  • the first material layer 411 may have a thickness ranging from 1 nanometer to 500 nanometers. In one embodiment, the first support layer 412 may have a thickness ranging from 100 nanometers to 100 micrometers. In one embodiment, the second material layer 421 may have a thickness ranging from 1 nanometer to 500 nanometers. In one embodiment, the second support layer 422 may have a thickness ranging from 100 nanometers to 100 micrometers.
  • the material of the first material layer 411 may include a metal material or a semiconductor material (eg, a doped semiconductor material). Wherein the portion of the first material layer 411 between the first support layer 412 and the flow channel 50 may serve as a first electrode of the flow channel structure device; the first material layer 411 at the first support layer 412 and the base A portion between the first portions 211 of the sheets 21 may serve as a first lead of the first electrode.
  • the material of the second material layer 412 may include a metal material or a semiconductor material (eg, a doped semiconductor material).
  • the portion of the second material layer 412 between the second support layer 422 and the flow channel 50 can serve as a second electrode of the flow channel structure device; the second material layer 421 is at the second support layer 422 and the base A portion between the second portions 212 of the sheets 21 can serve as a second lead of the second electrode.
  • the contact resistance can be reduced between the first electrode and the first lead, and the second electrode and the second electrode are compared with the prior art. Contact resistance can also be reduced between leads to improve device performance.
  • the flow channel structure device may have a mosaic electrode structure and may have different lifetimes. Analysis and fluid handling functions. For example, by applying electrical excitation through an electrode, an electrical or electrochemical reaction can occur in the flow channel, an electrical signal or an optical signal can be generated, and a specific molecular species can be identified by the acquired electrical signal or optical signal; further, by identifying multiple Different molecular species can perform functions such as gene sequencing.
  • the materials of the first material layer 411 and the second material layer 421 may respectively include: an insulating dielectric material (for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials). combination).
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials. combination).
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials. combination).
  • an insulating dielectric material for example, silicon oxide, silicon nitride, silicon oxynitride, etc. or a plurality of insulating dielectric materials.
  • Such a flow path formed of an insulating dielectric material can be applied to formation and control of fluids and the like.
  • the flow channel structure device can be applied to some cases where it is not necessary to
  • FIGS. 23 and 24 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to another embodiment of the present invention. Next, a manufacturing process of a flow path structure device according to another embodiment of the present invention will be described in detail with reference to FIGS. 23 and 24.
  • the manufacturing method may further include: at the second sacrificial layer 32, the first material layer 411, the first A cap layer 60 is formed on a support layer 412, a second material layer 421, and a second support layer 422.
  • the cap layer may be combined with the first structural layer (which may include the first material layer and the first support layer) and the second structural layer (which may include the second material layer and the second support layer) Achieving a closed flow channel structure can also avoid parasitic reactions that may be caused by contact of the first material layer with the top of the second material layer with the fluid.
  • the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids.
  • the selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer.
  • a flow path structure device as shown in Fig. 24 is formed.
  • the planarly extending second sacrificial layer is bordered, and the edge of the second sacrificial layer may be exposed, so that a selective etching solution is implanted at the edge of the second sacrificial layer (ie, at the boundary) to remove The second sacrificial layer forms a flow channel.
  • the manufacturing method may further include: etching the cap layer to form the cap layer and exposing the cap layer
  • the through holes of the two sacrificial layers (not shown in FIG. 24, reference may be made to the through holes 61 in FIG. 12).
  • the use of selective engraving In the step of removing the second sacrificial layer by the etching process, a selective etching liquid may be injected from the via hole to remove the second sacrificial layer, thereby forming a channel structure device as shown in FIG.
  • the selective etching liquid is facilitated to remove the second sacrificial layer through the via hole, and the etching rate can be accelerated.
  • the flow path structure device may include the same or similar structure as that of FIG. 22, and may include, for example, a substrate 21, a first material layer 411, a first support layer 412, a second material layer 421, and a second. Support layer 422 and flow channel 50 are not described in detail herein.
  • the flow channel structure device may further include: a cap layer covering the first material layer 411, the first support layer 412, the second material layer 421, and the second support layer 422. 60.
  • the cap layer 60 covers the flow channel 50.
  • the capping layer 60 can be closed with the first structural layer 41 (which can include the first material layer 411 and the first support layer 412) and the second structural layer 42 (which can include the second material layer 421 and the second support layer 422)
  • the flow channel i.e., the upper portion of the flow channel is closed
  • the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids.
  • the material of the capping layer 60 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or a semiconductor material. (for example, polysilicon or amorphous silicon, etc.).
  • an insulating dielectric material eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.
  • a semiconductor material for example, polysilicon or amorphous silicon, etc.
  • the capping layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers.
  • the cap layer may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer or 5 micrometers, and the like.
  • the flow channel structure device may further include: a through hole penetrating the cap layer and communicating to the flow channel.
  • the flow path of the embodiment of the present invention may be a nano flow channel.
  • the invention has the following advantages: (1) a nano-channel structure with high aspect ratio can be realized, and the size controllability is good; (2) an all-metal conductive electrode mosaic structure can be realized; (3) the nano-channel structure can be effectively improved; Manufacturability, reducing the manufacturing cost of nanochannel structure; (4) has a relatively low thermal budget and is compatible with integrated circuit processes. Further, the flow path structure device of the embodiment of the present invention can be applied to molecular detection, liquid formation, or fluid transportation control.
  • a flow channel sensor can also be provided.
  • the flow path sensor can include: A flow path structure device as previously described (for example, a flow path structure device as shown in FIG. 22 or as shown in FIG. 24).
  • a biochemical analysis device can also be provided.
  • the biochemical analysis device may comprise: a flow channel structure device as previously described (eg, a flow channel structure device as shown in FIG. 22 or as shown in FIG. 24).
  • FIG. 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention.
  • the chip 250 may include a flow path structure device 2501, a signal collection unit 2502, and a signal processing unit 2503.
  • the flow channel structure device 2501 includes electrodes (eg, a first electrode and a second electrode).
  • the flow path structure device may be a flow path structure device as shown in FIG. 22 or as shown in FIG. Wherein the sample to be detected is added to the flow channel of the flow channel structure device, and the target molecule in the sample to be detected is applied when the electrodes of the channel structure device (for example, the first electrode and the second electrode) are electrically excited. An electrical or optical signal is generated under electrical excitation.
  • the signal collecting unit 2502 can be configured to collect the electrical signal or the optical signal and transmit the electrical signal or the optical signal to the signal processing unit 2503.
  • the signal processing unit 2503 can be configured to perform signal processing on the electrical signal or the optical signal to identify information of the target molecule.
  • a molecular detection method is also provided.
  • the method can include performing molecular detection using a chip as described above (eg, a chip as shown in FIG. 25).
  • Figure 26 is a flow chart showing a molecular detection method in accordance with one embodiment of the present invention. The step of performing molecular detection using a chip will be described below with reference to FIG.
  • step S2601 the sample to be tested is processed.
  • the test sample can be subjected to chemical treatment or other treatment.
  • step S2602 the sample to be detected is added to the chip.
  • a sample to be tested is added to the flow path of the flow channel structure device of the chip.
  • step S2603 electrical excitation is applied to electrodes (eg, the first electrode and the second electrode) in the flow channel structure device in the chip such that the target molecules in the sample to be detected generate an electrical signal or an optical signal under electrical excitation.
  • electrodes eg, the first electrode and the second electrode
  • step S2604 the signal processing unit of the chip obtains an electrical signal or an optical signal through the signal collecting unit, and performs signal processing on the electrical signal or the optical signal to identify the information of the target molecule.
  • the application of molecular detection is realized by using a chip including the flow path structure device of the embodiment of the present invention.

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Abstract

La présente invention concerne un dispositif de structure de canal fluidique et un procédé de fabrication associé. Le procédé comprend : la fourniture d'un substrat (21) comprenant une première partie (211) et une seconde partie (212) adjacente à la première partie (211) ; la formation d'une première couche sacrificielle à motifs (31) sur le substrat (21), la première couche sacrificielle (31) recouvrant la seconde partie (212), et la première partie (211) étant exposée ; la formation d'une première couche de structure (41) sur la première partie (211) du substrat (21) et la première couche sacrificielle (31) ; la réalisation d'un premier traitement de polissage pour exposer la première couche sacrificielle (31) ; le retrait de la première couche sacrificielle (31) pour exposer une surface supérieure de la seconde partie (212) du substrat (21) et une surface latérale de la première couche de structure (41) ; la formation d'une seconde couche sacrificielle (32) sur une partie de la surface supérieure de la seconde partie (212) du substrat (21), la seconde couche sacrificielle (32) recouvrant la surface latérale de la première couche de structure (41) ; la formation d'une seconde couche de structure (42) sur la seconde partie (212) du substrat (21), la seconde couche sacrificielle (32) et la première couche de structure (41) ; la réalisation d'un second traitement de polissage pour exposer la seconde couche sacrificielle (32) ; et le retrait de la seconde couche sacrificielle (32) au moyen d'un processus de gravure sélective de manière à former un canal fluidique (50). Le procédé peut réaliser un dispositif de structure de canal fluidique comprenant un canal fluidique vertical.
PCT/CN2017/095498 2017-08-01 2017-08-01 Dispositif de structure de canal fluidique et procédé de fabrication associé WO2019023943A1 (fr)

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