TW201423101A - 生物場效電晶體裝置與生物場效電晶體的製造方法 - Google Patents
生物場效電晶體裝置與生物場效電晶體的製造方法 Download PDFInfo
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- TW201423101A TW201423101A TW102142589A TW102142589A TW201423101A TW 201423101 A TW201423101 A TW 201423101A TW 102142589 A TW102142589 A TW 102142589A TW 102142589 A TW102142589 A TW 102142589A TW 201423101 A TW201423101 A TW 201423101A
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Classifications
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- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
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- G—PHYSICS
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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Abstract
本發明提供一種生物場效電晶體裝置,以及生物場效電晶體與生物場效電晶體裝置的製造方法,包括使用一或多道相容於或典型的互補式金氧半導體(CMOS)製程的步驟。生物場效電晶體裝置包括一閘結構,設置於一基底之一第一表面上;以及一界面層,形成於基底之一第二表面。在形成界面層之前,薄化基底之第二表面以暴露出一通道區。
Description
本發明係有關於生物感測器(biosensors)及其製造方法,特別係有關於生物場效電晶體(biological field-effect-transistors,BioFETs)及其製造方法。
生物感測器(biosensors)係用以感測與偵測生物分子(biomolecules)並以於電子、電化學、光學、與機械偵測原理的基礎運作。生物感測器包括電晶體,其作為感測器以電性感測(electrically sense)生物體(bio-entity)或生物分子的電荷、光子、以及機械特性。此偵測可藉由直接偵測生物體或生物分子而執行,或透過特定的反應劑與生物體/生物分子之間的相互作用(interaction)或反應(reaction)而執行。可使用半導體製程製造生物感測器,如此一來,可使生物感測器快速地轉換電子訊號,且可使生物感測器易於應用在積體電路與微機電系統(Micro Electro Mechanical Systems,MEMS)上。
生物場效電晶體(生物感測性場效電晶體(biologically sensitive field-effect-transostors)、或生物有機場效電晶體(bio-organic field-effect transistor),BioFETs)是一種
生物感測器,其包括用以感測生物分子或生物體的電晶體。儘管生物場效電晶體在許多方面係有利的,然而,製作及/或操作生物場效電晶體的困難度逐漸增加,舉例來說,因為半導體製程的相容性問題、生物應用、半導體製程的限制、電子訊號與生物應用的整合、及/或其他來自於執行大型積體電路(large scale integration,LSI)製程所面臨的問題。
本發明一實施例提供一種生物場效電晶體(biological field-effect transistor,BioFET)的製造方法,包括:形成一場效電晶體(FET)裝置於一半導體基底上,其中該場效電晶體裝置包括一閘結構,形成於半導體基底的一第一表面上、以及一通道區;形成一開口,其從半導體基底的一第二表面暴露出通道區,其中通道區的一表面藉由一非電漿蝕刻而暴露出;以及形成一感測膜於開口中的半導體基底之第二表面的通道區上。
本發明另一實施例提供一種生物場效電晶體的製造方法,包括:形成一場效電晶體(FET)裝置於一半導體基底上,其中場效電晶體裝置包括一閘結構,形成於半導體基底的一第一表面上、以及一通道區,於半導體基底中且於閘結構下方;將半導體基底之第一表面接附於一載體基底;藉由移除部份的半導體基底而形成一開口,開口從半導體基底的一第二表面暴露出通道區;形成一感測膜於開口中的半導體基底之第二表面的通道區上;以及形成一微流體(microfluidic)通道或一微流體井於感測膜上方。
本發明又一實施例提供一種生物場效電晶體裝置,包括:一載體基底;一第一BioFET裝置,接附於載體基底,BioFET裝置包括:一閘結構,於一半導體基底之一第一側;一源極區與一汲極區,於半導體基底中且相鄰於閘結構;一通道區,插入於源極區與汲極區之間,且位於閘結構下方;以及一感測膜,直接地位於且覆蓋於半導體基底之一第二側上的通道區之至少一部份;以及一微流體通道或一微流體井,設置於感測膜上方。
100‧‧‧方法
201‧‧‧第一半導體層
203‧‧‧埋入氧化層
205‧‧‧第二半導體層
207‧‧‧第一側
209‧‧‧背側
210‧‧‧場效電晶體
211、213‧‧‧源極/汲極區
215‧‧‧介電層
217‧‧‧電極
219‧‧‧通道區
301‧‧‧載體基底
303‧‧‧多層內連線結構
400、501‧‧‧晶圓
503‧‧‧介電層
505‧‧‧溝槽
507、509‧‧‧表面
601、701‧‧‧感測膜
702‧‧‧鈍化層
801‧‧‧生物相容性材料
803‧‧‧微流體結構
804‧‧‧鈍化/阻擋層
901‧‧‧微流體井
1001‧‧‧微流體井結構
1003‧‧‧微流體通道結構
第1A~1C圖為根據本發明一或多種面向繪示出不同實施例的BioFET裝置之製造方法的流程圖。
第2~4、5A、5B、6A、6B、7A、7B、8A、8B、8C、8D、9A、9B、9C圖為根據第1A~1C圖的方法之一或多個步驟所繪示出的BioFET裝置半成品的剖面示意圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本發明。此外,若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方,即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例,亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間,而使
上述第一特徵與上述第二特徵可能未直接接觸的實施例。再者,在空間上的相關用語,例如“頂部”、“前”、“底部”、及“後”係用以容易表達出本說明書中的特徵與額外特徵的關係。為了簡化與清晰,不同特徵可任意的案不同比例繪製。
在一個生物場效電晶體(biological field-effect-transistor,BioFET)中,係以生物(bio-)或生物化學(biochemical-)相容層、或以作為表面受體(receptor)的固定化探針(probe)分子之生物機能(biofunctionalized)層取代金氧半場效電晶體(MOSFET)的閘極(其控制半導體源極與汲極接點之間的傳導)。事實上,BioFET為一個帶有半導體傳感器的場效生物感測器。BioFET的一個明確的優點為其操作上不需任何標定物(label-free)。具體來說,BioFET能夠免於昂貴且費時的標定操作(labeling operation),例如,以螢光或放射性探針分析的標定。
BioFET的一個典型的偵測機制為將生物分子或生物體標的連結至BioFET的感測表面或連結至固定化於BioFET之感測表面的受體(receptor)分子而引發傳感器的傳導調節(conductance modulation)。當生物分子或生物體標的連結至感測表面或固定化受體,感測表面的位能改變了BioFET的汲極電流。汲極電流的改變可被測定,並可鑑定(identify)受體與生物分子或生物體標的的連結。可使用各式各樣的生物分子與生物體以機能化BioFET的感測表面,例如,離子、酵素(enzymes)、抗體、配體(ligands)、受體、縮氨酸(peptides)、寡核苷酸(oligonucleotides)、器官的細胞、有機體(organisms)、
組織碎片。舉例來說,為了偵測單鏈去氧核醣核酸(single-stranded deoxyribonucleic acid,ssDNA),可使用固定化的互補ssDNA鏈機能化BioFET的感測表面。同樣地,為了偵測各種蛋白質,例如,腫瘤標誌(tumor markers),可使用單株抗體(monoclonal antibodies)機能化BioFET的感測表面。
浮動閘(floating gate)的一頂部連接至BioFET的閘極為具有感測表面的生物感測器之一範例。浮動閘係透過含有多個金屬內連線(interconnection lines)與導孔(vias)(或多層內連線(multi-layer interconnect,MLI))的堆疊而連接至BioFET的閘極結構。因形成MLI過程中的天線效應(antenna effect),閘極上方的多個金屬層亦會造成破壞。在這樣的BioFET中,位能調節係發生於最終(頂部)金屬層之外表面或形成於MLI之上的介電表面,且位能調節不是由BioFET直接感測。此為不理想的實施例,然而,在其中,裝置的感測度(sensitivity)因伴隨著MLI的寄生電容(parasitic capacitance)而降低。如此一來,通常會指定出感測板的一最小尺寸,以充足地進行位能調節反應之感測。然而,感測板的最小尺寸會限制BioFET之密度。
在另一範例中,生物分子直接地或透過受體連結於BioFET的閘極或閘介電層上。這種“直接感測(directly sensing)”BioFET不需透過伴隨著MLI的寄生電容而直接地感測生物分子標的。此BioFET的製作必須移除BioFET上方的MLI材料以形成感測井(well),並將閘電極及或閘介電層暴露於產生表面位能調節反應的流體環境。這種BioFET相較於
浮動閘型更具有感測度,但因數種原因而使製作更困難。蝕刻出的感測井具有高長寬比(aspect ratio),例如,30或更高,因此通常係以高能量電漿蝕刻製作。感測井的高長寬比亦限制蝕刻出的感測井之輪廓。高能量電漿蝕刻會因電荷引起的損害(charge-induced damage)而對閘電極造成傷害。如果嘗試降低感測井之長寬比以使蝕刻容易進行,則會限制金屬層的數量,減少至一或兩層金屬層。金屬層的減少會限制裝置的內連線路徑(interconnect routing)與整合選擇性(integration option),舉例來說,用以控制BioFET的電路之數量與種類。此製程亦對對準(alignment)非常敏感,這是因為不準確的對準(misalignment)可能會暴露出圍繞著感測井的MLI中的金屬、或造成感測表面的面積小於設計的大小。
在又一範例中,生物分子被置於靠近基底背側的閘極處。在此範例中,感測表面係透過基底的背側而形成於電晶體閘極的背側上。此範例可免於必須以蝕刻穿透內連線之多層(multiple layers)的困難,並且可置放生物分子於夠接近閘極處,以使感測度遠高於浮動閘生物感測器。第1圖繪示出製作生物有機場效電晶體(bio-organic field-effect transistor,BioFET)的方法100。方法100可包括使用一或多道相容於或典型的互補式金氧半導體(CMOS)製程的步驟。應理解的是,在此方法額外的實施例中,可在方法100之前、期間、與之後提供額外的步驟,且以下一些步驟可被取代或省略。再者,應理解的是,方法100包括具有典型CMOS技術製造流程之特徵的步驟,因此,僅在此作簡單敘述。
方法100由步驟102開始,提供一基底。基底可為半導體基底。半導體基底可為矽基底。或者,基底可包括其他元素(elementary)半導體,例如,鍺、化合物半導體(其包括碳化矽)、合金半導體(包括矽鍺合金)、或前述之組合。一些實施例中,基底為半導體覆絕緣體(semiconductor on insulator,SOI)基底。如第2圖所示,SOI基底可包括埋入氧化(buried oxide,BOX)層203,其係由如一製程所形成,例如,氧佈植隔離(separation by implated oxygen,SIMOX)、及/或其他合適製程。SOI基底亦包括在BOX層203兩側的第一半導體層201與第二半導體層205。SOI基底的第一表面或第一側207為裝置側(device side),其是場效電晶體(FET)的閘極形成處。SOI基底之第二表面或第二側為背側,其會在隨後的作業中被薄化。基底可包括摻雜區域,例如p井與n井。在本發明中,晶圓(wafer)為一工作件(workpiece),其包括半導體基底以及各種形成於半導體基底之中、之上、以及連接至半導體基底的元件。晶圓可用於製程的不同階段中,且晶圓係利用CMOS製程加工。在完成製程的不同階段後,晶圓被切割成封裝至一積體晶片的獨立晶粒。
請參照第1A圖,方法100進行至步驟104,在基底的第一側207上形成一場效電晶體(FET)210。FET 210可包括一閘結構(其包括介電層215與電極217)、一源極區(211或213)、一汲極區(211或213)、以及插入源極與汲極區(211與213)之間的一通道(channel)區219。源極、汲極、及/或通道區係形成於半導體基底的主動區上。主動區為半導體層201的一
部份。FET 210可為n型FET(nFET)、或p型FET(pFET)。舉例來說,依據FET的配置,源/汲極區可包括n型摻質或p型摻質。閘結構可包括閘介電層215、閘電極層217、及/或其他合適的層。一實施例中,閘電極217為多晶矽(polysilicon)。其他範例的閘電極包括金屬閘電極(例如,Cu、W、Ti、Ta、Cr、Pt、Ag、Au)、合適的金屬化合物(例如,TiN、TaN、NiSi、CoSi)、前述之組合、或其他合適的導電材料。一實施例中,閘介電層為氧化矽。其它範例的閘介電層包括氮化矽、氮氧化矽、高介電常數材料、及/或上述之組合。高介電材料的例子包括矽酸鉿(hafnium silicate)、氧化鉿、氧化鋯、氧化鋁、五氧化鉭、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、或前述之組合。可使用典型的CMOS製程形成FET,例如,微影(photolithography)、離子佈植(ion implantation)、擴散(diffusion)、沉積(其包括物理氣相沉積(physical vapor deposition,PVD)、金屬汽化(metal vaporation)或濺鍍(sputtering)、化學氣相沉積(chemical vapor deposition,CVD)、電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)、大氣壓化學氣相沉積(atmospheric pressure CVD,APCVD)、低壓化學氣相沉積(low pressure CVD,LPCVD)、高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)、原子層化學氣相沉積(atomic layer CVD,ALCVD)、旋轉塗佈(spin on coating))、蝕刻(其包括濕蝕刻、乾蝕刻、電漿蝕刻)、及/或其他合適的CMOS製程。
方法100可包括在FET上形成額外的層,包括金
屬內連線層、介電層、鈍化(passivation)層、連接金屬(bonding metal)層、及其他完成一半導體裝置的典型材料層。在第3圖中,層303置於FET上方且位於FET與載體(carrier)基底301之間。層303可包括多層內連線(multi-layer interconnect,MLI)結構。MLI結構可包括導電線(conductive lines)、導孔(conductive vias)、及/或插入性(interposing)介電層(例如,層間介電層(interlayer dielectric,ILD))。MLI結構可在源極與汲極區211與213以及閘電極217處提供物理性與電性連接給FET。導電線可包括銅、鋁、鎢、鉭、鈦、鎳、鈷、金屬矽化物、金屬氮化物、多晶矽、前述之組合、及/或其他可能包括一或多個層或內襯(linings)的材料。插入性或層間介電層(例如ILD層)可包括二氧化矽、氟化矽玻璃(fluorinated silicon glass,FSG)、SILK(密西根陶氏化學公司(Dow Chemical of Michigan)之產品)、BLACK DIAMOND(加州聖克拉拉應用材料公司(Applied Materials of Santa Clara,California)之產品)、及/或其他絕緣材料。可藉由適用於製作典型CMOS的製程形成MLI,例如,CVD、PVD、ALD、電鍍、旋轉塗佈、及/或其他製程。
若使用載體基底301,可不影響半導體基底之結構完整性(structural integrity)地容許在半導體基底的背側209上進行各種後續作業。載體基底301係藉由接合製程(bonding)接附於半導體基底。在一些實施例中,載體基底係接合至最終MLI層。一實施例中,載體基底係接合至形成於基底之MLI及/或ILD層上的鈍化層。可使用融合(fusion)、擴散(diffusion)、共晶(eutectic)、及/或其他合適的接合方法將載體
基體接附於裝置基底。載體基底的範例組成包括矽、玻璃、與石英(quartz)。一些實施例中,載體基底301可包括其他功能性(functionality),例如,內連線元件、接合位置(bonding sites)、定義的腔體(defined cavities)、及/或其他合適的元件。可在隨後的製程中移除載體基底(例如,薄化之後)。
方法100接著進行至步驟106,從基底的背側暴露出FET的主動區。根據基底的種類,可使用不同的方法以暴露出主動區,主動區通常包括FET的通道區。根據不同實施例,基底係從背側被薄化。第一薄化製程可由濕蝕刻、乾蝕刻、電漿蝕刻、及/或其他合適的製程而完成。為了防止隨著FET之主動區上的殘留電荷產生的電漿造成之損害(plasma-induced damage),此作業中係使用非電漿蝕刻,或至少在最後的薄化製程中使用非電漿蝕刻。因此,在一些實施例中,係使用濕蝕刻或非電漿乾蝕刻以將基底從背側薄化至主動區。在其他實施例中,先進行第一薄化製程,其可包括電漿蝕刻,以降低基底的厚度,並使用非電漿蝕刻作為最後蝕刻作業以在基底的背側暴露出主動區域。
第1B圖係根據本發明不同實施例繪示出當基底為矽覆絕緣層(silicon-on-insulator,SOI)基底時,方法100之步驟106的流程圖。SOI基底在兩個半導體層之間具有內在(intrinsic)介電層,其亦稱為埋入氧化(buried oxide,BOX)層。FET係形成於第一半導體層中,第一半導體層通常薄於內位於介電層之另一側的第二半導體層。移除第二半導體層。第1B圖的步驟152中,從SOI基底上移除第二半導體層。被移除的
半導體層是相對於步驟104所製作的FET的半導體層。可藉由機械或化學方法執行移除製程。舉例來說,機械方法包括拋光(polishing)或研磨(grinding),例如,化學機械拋光(chemical mechanical polishing,CMP)。化學方法包括濕蝕刻(例如使用HNA或TMAH)、或乾時刻(其包括電漿與非電漿蝕刻)。第4圖顯示出移除第3圖之半導體層205後的晶圓400。晶圓400包括在FET 210兩側的內在(intrinsic)介電層203與載體基底301。
在第1B圖的步驟154中,內在介電層被薄化。內在介電層可為介於極小奈米至數百奈米的氧化矽層。一些實施例中,係藉由使用濕蝕刻(例如,緩衝氧化物蝕刻(buffered oxide etch))、或非電漿乾蝕刻以薄化內在介電層。內在介電層可部份地被移除,例如,第5A圖所示的內在介電層503,或者,內在介電層可完全地被移除,例如第5B圖所示的實施例。若內在介電層僅需部份地被移除,則可使用電漿蝕刻以薄化。一些實施例中,內在介電層被薄化至2000埃或更薄。
根據不同實施例,在步驟154中的剩餘之內在介電層上形成光阻圖案。光阻圖案可保護部份的內在介電層免於被隨後步驟158中用以暴露出主動區的非電漿蝕刻損害。非電漿蝕刻可為濕蝕刻或不包含電漿的乾蝕刻。非電漿製程產生升出溝槽(trench)505,溝槽505具有暴露出FET210之通道區219的底部。使用非電漿蝕刻係為了在通道區219之暴露的表面509上防止電漿造成的損害(plasma-induced damage)。藉由先將內在介電層203薄化,溝槽509具有一低長寬比,舉例來說,
小於5,甚至約為1或更小。低長寬比在蝕刻期間提供良好的輪廓控制(fine profile control),並免於形成阻礙感測膜均勻性(sensing film uniformity)的尖銳邊角(sharp corners)。一些實施例中,溝槽505的側壁輪廓大抵上是筆直的。
根據一些實施例,如第5B圖所示,內在介電層203完全地被移除且第一半導體層201係暴露於表面507。可在一或多道作業中完整移除內在介電層,例如,第1B圖的步驟154與158。然而,暴露出表面507的最後作業不能包含電漿蝕刻,以防止對表面507造成電漿產生的損害(plasma-induced damage,PID)。
若在步驟156形成有光阻圖案,光阻圖案則在步驟160中被移除。可使用不會有電漿產生的損害(PID-less)之移除步驟,例如,剝除(stripping)與臭氧灰化(ozone ashing)。因為溝槽505之暴露表面509與第一半導體層201之暴露表面207易受電漿產生的損害(PID)的影響,不可使用某些電漿灰化製程移除光阻圖案。
請參照第1A圖,步驟108中,在開口中形成界面層。第1C圖為根據本發明不同實施例顯示出方法100之步驟108的流程圖。在第1C圖的步驟182中,在晶圓上方沉積感測膜。可在溝槽505之暴露表面509與第一半導體層201之暴露表面507上形成感測膜。感測膜在此亦稱為界面層,界面層相容於(合適於)連接生物分子或生物體。感測膜可包括介電材料、導電材料、及/或其他適用於乘載受體的材料。範例界面材料可包括高介電常數材料層、金屬氧化物、介電質、及/或
其他合適的材料。進一步的例子中,範例界面材料可包括HfO2、Ta2O5、Pt、Au、W、Ti、Al、Cu、前述金屬之氧化物、SiO2、Si3N4、Al2O3、TiO2、TiN、ZrO2、SnO、SnO2、及/或其他合適材料。可使用CMOS製程形成感測膜,例如,PVD、濺鍍、CVD、PECVD、APCVD、LPCVD、HDPCVD、或ALCVD。在實施例中,感測膜包括多個層。
第6A圖與第6B圖顯示出在溝槽505之暴露表面509上(第6A圖)與在第一半導體層201之暴露表面上(第6B圖)形成感測膜。在第6A圖中,感測膜係沉積於晶圓上方且位於剩餘的內在介電層503之上的場區(field area)、以及溝槽505之側壁與底部上。在第6B圖中,感測膜係沉積於晶圓上方且位於半導體層之上的整個表面507之上。
請參照第1C圖,在步驟184中,在感測膜上形成光阻圖案以保護部份的感測膜。位於通道區上方的部份反測膜受光阻圖案保護。在步驟186中,未被保護的部分感測膜以蝕刻製程移除。蝕刻製程可包含任何習知的蝕刻製程,因為容易受電漿產生的損害(PID)影響的部份已被保護,因此蝕刻製程可包括電漿蝕刻。第7A圖與第7B圖顯示出各自殘留於表面的感測膜701。在第7A圖中,顯示出感測膜701僅殘留於溝槽505的底部。然而,在一些實施例中,溝槽505之側壁亦有感測膜包覆於其上。感測膜701完全覆蓋通道區219,並部份地覆蓋源極與汲極區211與213。可以FET的設計與感測膜701所需的面積為基礎而調整源極與汲極區的部份覆蓋範圍。在第7B圖中,感測膜701完全覆蓋通道區219,並部份地覆蓋源極
與汲極區211與213。為了防止生物分子不必要地連結至感測膜以外的其他表面,可沉積阻擋(blocking)層或鈍化層702。鈍化層702可為氮化矽、氧化矽、或其它固態介電材料。阻擋劑(blocking agent)702可為固體或液體,其中生物分子無法連結至其上、或生物分子與阻擋劑702間具有低親和力(affinity)。阻擋劑的一例子為六甲基二矽氧烷(hexamethyldisiloxane)。在其他例子中,係使用如牛血清蛋白(Bovine Serum Albumin,BSA)的蛋白質作為阻擋劑。阻擋層/鈍化層702可厚於或薄於感測膜701。
在經過蝕刻與視情況而定地加入鈍化或阻擋劑後,在步驟188中以不會有電漿產生的損害(PID-less)之移除步驟將光阻圖案移除。一些實施例中,感測膜601未經過圖案化及蝕刻而殘留於FET的相應表面上。
請參照第1A圖,在步驟110中,薄膜處理(film treatment)或受體提供於或連結至界面層/感測膜上,以提供申物分子標的的感測,舉例來說,受體可為,酵素(enzymes)、抗體、配體(ligands)、縮氨酸(peptides)、核苷酸(nucleotides)、器官的細胞、有機體(organisms)、組織碎片等。。舉例來說,為了偵測單鏈去氧核醣核酸(single-stranded deoxyribonucleic acid,ssDNA),可使用固定化的互補ssDNA鏈機能化BioFET的感測表面。同樣地,為了偵測各種蛋白質,例如,腫瘤標誌(tumor markers),可使用單株抗體(monoclonal antibodies)機能化BioFET的感測表面。受體可為分子的自動組合單層(self-assembled monolayer,SAM)之一部份。SAM之頭部基
(head group)可為矽烷基(silane groups)、矽基(silyl groups)、矽醇基(silianol groups)、膦酸酯基(phosphonate groups)、胺基(amine groups)、硫醇基(thiol groups)、烷基(alkyl groups)、烯基(alkene groups)、疊氮基(azido groups)、或環氧基(epoxy groups)。受體係接附於SAM之頭部基。
一些實施例中,以塗層(coating)或化學品對感測膜處理(treat)或改質以影響感測膜的化學功能起作用。舉例來說,可處理感測膜以使其具有親水性(hydrophilic)或疏水性(hydrophobic)的表面。一些範例中,可將感測膜改質使其具有一些傳導性或磁性。膜加工或受體的製作可為對溶液的吸附作用,溶液可來自反應槽(wet tank)或沖壓(stamping),或是以某些種類的沉積製作膜加工或受體,例如濺鍍或氣相沉積。可圖案化受體,例如,藉由使用微觸印刷法(micro-contact printing)、沾筆式奈米微影(dip-pen nanolithography)、或藉由在接附受體後選擇性地(selectively)移除受體。當接附至受體時,可以BioFET偵測感測膜上的生物材料,這是因為生物材料的呈現改變了通道區的電性特性。
請參照第1A圖,在步驟112中,在感測膜上方形成微流體(microfluidic)通道或微流體井。可根據使用的材料或膜加工/受體的種類而在第1A圖之方法100的步驟110之前或之後執行步驟112。舉例來說,在形成微流體通道或微流體井結構期間,某些受體可能會受到損害。一些實施例中,係在感測井上方沉積及塑型(shape)微流體通道或井。第8A/8B圖與第9A/9B圖為形成於感測膜上的微流體井之剖面示意圖。第8A
圖為溝槽505形成於感測膜601上的範例。第8B圖為完全移除內在介電層且未形成溝槽505的範例。在這兩個例子中,在晶圓上方沉積生物相容性(biocompatible)材料以形成大抵上平坦的表面。在不同的例子中,生物相容性材料為生物相容性光阻。因光阻容易藉由微影而塑型且不會對感測膜之表面產生影響,因此,可使用光阻。一例子為環氧基(epoxy-based)負型光阻(negative photoresist)SU-8TM。光阻可為透明的,且這種微流體結構的一特徵係在於其可在作業期間從外部觀測(externally observed)。如第9A圖與9B圖所示,光阻可藉由使用旋塗工具(spin-on tool)沉積、使用曝光(exposure)以圖案化、以及使用顯影以移除井。第9A圖與第9B圖包括形成於生物相容性材料801之中的微流體井901。如圖所示,微流體井901在作業期間將感測膜601(以及感測膜601上的任何塗層或受體)暴露至生物流體物質。
在一些實施例中,生物相容性材料不是光阻。生物相容性材料可為環氧樹酯、矽膠(例如,聚二甲基矽氧烷(polydimethylsiloxane,PDMS))、或其他有機聚合物(例如,聚乙二醇(polyethylene glycol,PEG))。可大量地沉積生物相容性材料於BioFET上,並將生物相容性材料塑型。亦可透過塑型製程(molding)將生物相容性材料依特定的形狀沉積於BioFET上,例如,藉由壓模(compressing molding)製程與隨後的固化(curing)製程,或透過模具執行注入成型(injection molding)。所選之生物相容性材料801對部份的感測膜601及多個相鄰的BioFETs之間的半導體層之表面具有良好的接附性。
在又一實施例中,微流體通道或井係個別地從BioFET形成,且在獨立的作業中被接附。第8C與8D圖為包括預先形成的微流體結構803之剖面示意圖,微流體結構803接著接附於感測膜與鈍化/組擋層804上的晶圓。微流體結構803可在BioFET被切割之前,個別且獨自地接附置晶圓。微流體結構803亦可作為一對一(one to one)映到(mapped to)晶圓上之BioFET裝置的封裝基板而形成。可藉由陽極接合(anodic bonding)或黏著劑接合(adhesive bonding)接附微流體結構803。微流體結構803可包括輸入口/輸出口、井、通道、以及可存放流體的儲水槽。微流體結構803可進一步包括有助於引導生物物質流動與傳導分析的材料。舉例來說,微流體結構803可包括微微型泵(micropumps)與閥(valves)以及作為磁泳(magnetophoresis)的磁性(magnetic)或鐵磁性(ferromagnetic)材料、作為電泳(electrophoresis)的金屬、或作為介電泳(dielectrophoresis)的特定介電材料。
可使用CMOS製程以外的製程製作微流體結構803、及/或將微流體結構803連接至或接合至BioFET裝置,例如,可使用非典型的CMOS製程製作微流體結構803、及/或將微流體結構803連接至或接合至裝置。個別地形成微流體結構容許使用更多種類的材料,且當微流體結構803不是形成於易受損害(easily-damaged)的BioFET上時,個別地形成微流體結構亦提供較大的製程窗(process window)。因光阻基的微流體結構較能適應表面變化,用以接附微流體結構的BioFET之表面均勻度變的更重要。
在又一實施例中,可使用多種作業的組合製作微流體結構。第9C圖具有兩部份的微流體結構之BioFET的剖面示意圖。微流體井結構1001藉由沉積與圖案化製程形成於感測膜上方,以及微流體通道結構1003接附至微流體井結構1001。
以上概略敘述許多實施例的特徵,使所屬技術領域中具有通常知識者能夠清楚理解以下的說明。任何所屬技術領域中具有通常知識者能夠理解到本說明書可輕易作為其它結構或製程的變更或設計基礎,以進行相同於本發明實施例的目的及/或獲得相同的的優點。任何所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。
203‧‧‧埋入氧化層
205‧‧‧第二半導體層
207‧‧‧第一側
209‧‧‧背側
210‧‧‧場效電晶體
211、213‧‧‧源極/汲極區
215‧‧‧介電層
217‧‧‧電極
219‧‧‧通道區
Claims (10)
- 一種生物場效電晶體(biological field-effect transistor,BioFET)的製造方法,包括:形成一場效電晶體(FET)裝置於一半導體基底上,其中該場效電晶體裝置包括一閘結構,形成於該半導體基底的一第一表面上、以及一通道區;形成一開口,其從該半導體基底的一第二表面暴露出該通道區,其中該通道區的一表面藉由一非電漿蝕刻而暴露出;以及形成一感測膜於該開口中的半導體基底之該第二表面的該通道區上。
- 如申請專利範圍第1項所述之生物場效電晶體的製造方法,更包括:形成一受體(receptor)於該感測膜上,其中該受體包括酵素(enzymes)、抗體、配體(ligands)、縮氨酸(peptides)、核苷酸(nucleotides)、或自動組合單層分子(self-assembled monolayer molecules)。
- 如申請專利範圍第1項所述之生物場效電晶體的製造方法,更包括:以親水性(hydrophilic)或疏水性(hydrophobic)塗層塗佈該感測膜。
- 如申請專利範圍第1項所述之生物場效電晶體的製造方法,其中該感測膜包括Si3N4、Al2O3、TiO2、HfO2、Ta2O5、SnO、SnO2、BaxSr1-xTiO3、或前述之組合。
- 一種生物場效電晶體的製造方法,包括:形成一場效電晶體(FET)裝置於一半導體基底上,其中該場效電晶體裝置包括一閘結構,形成於該半導體基底的一第一表面上、以及一通道區,於該半導體基底中且於該閘結構下方;將該半導體基底之該第一表面接附於一載體基底;藉由移除部份的該半導體基底而形成一開口,該開口從該半導體基底的一第二表面暴露出該通道區;形成一感測膜於該開口中的半導體基底之該第二表面的該通道區上;以及形成一微流體(microfluidic)通道或一微流體井於該感測膜上方,其中該半導體基底為一矽覆絕緣層(silicon-on-insulator,SOI)基底,且其中該矽覆絕緣層基底包括一絕緣層插入一第一半導體層與一第二半導體層之間,其中暴露該通道區的步驟包括:薄化該矽覆絕緣層基底以移除上方形成有該場效電晶體之半導體層的相反半導體層;以及蝕刻該絕緣層以暴露出該通道區域,其中係使用濕蝕刻或非電漿乾蝕刻製程。
- 一種生物場效電晶體裝置,包括:一載體基底;一第一BioFET裝置,接附於該載體基底,該BioFET裝置包括:一閘結構,於一半導體基底之一第一側; 一源極區與一汲極區,於該半導體基底中且相鄰於該閘結構;一通道區,插入於該源極區與該汲極區之間,且位於該閘結構下方;一感測膜,直接地位於且覆蓋於該半導體基底之一第二側上的通道區之至少一部份;以及一微流體通道或一微流體井,設置於該感測膜上方。
- 如申請專利範圍第6項所述之生物場效電晶體裝置,更包括:一內在(intrinsic)介電層,位於該第一BioFET裝置與一微流體結構之間且圍繞著至少一部份的該通道區,該微流體結構包括該微流體通道或該微流體井。
- 如申請專利範圍第6項所述之生物場效電晶體裝置,其中該內在介電層之側壁具有一筆直的輪廓。
- 如申請專利範圍第6項所述之生物場效電晶體裝置,更包括一塗層,用以將生物分子黏合於該感測膜上。
- 如申請專利範圍第6項所述之生物場效電晶體裝置,更包括:一第二BioFET,藉由該微流體通道連接至該第一BioFET;以及一第三BioFET與一第四BioFET,連接至一第二微流體通道,其中該第一、第二、第三、與第四BioFETs被設置為一陣列配置(array configuration)。
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