WO2019021590A1 - Circuit d'attaque destiné à un élément semi-conducteur de puissance - Google Patents

Circuit d'attaque destiné à un élément semi-conducteur de puissance Download PDF

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Publication number
WO2019021590A1
WO2019021590A1 PCT/JP2018/019024 JP2018019024W WO2019021590A1 WO 2019021590 A1 WO2019021590 A1 WO 2019021590A1 JP 2018019024 W JP2018019024 W JP 2018019024W WO 2019021590 A1 WO2019021590 A1 WO 2019021590A1
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Prior art keywords
gate
gate voltage
power semiconductor
semiconductor device
value
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PCT/JP2018/019024
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English (en)
Japanese (ja)
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康滋 椋木
貴志 益原
堀口　剛司
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112018003834.3T priority Critical patent/DE112018003834T5/de
Priority to JP2018540894A priority patent/JP6425864B1/ja
Priority to CN201880048828.0A priority patent/CN110945789B/zh
Priority to US16/620,092 priority patent/US10790813B2/en
Publication of WO2019021590A1 publication Critical patent/WO2019021590A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08128—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in composite switches
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2608—Circuits therefor for testing bipolar transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/18—Modifications for indicating state of switch
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch

Definitions

  • the present disclosure relates to a drive circuit of a power semiconductor device, and more particularly to a drive circuit having a function of detecting and protecting a short circuit state of the power semiconductor device.
  • Patent Document 1 As a drive circuit having a function of detecting and protecting a short-circuited state of a power semiconductor device, for example, in Japanese Patent Laid-Open No. 2015-53749 (Patent Document 1), a turn-on command is output to the power semiconductor device The amount of charge supplied to the gate terminal of the semiconductor device and the gate voltage applied to the gate terminal are detected, and based on the detected amount of charge and the gate voltage, whether or not the power semiconductor device is in a short circuit state The configuration to judge is described.
  • the drive circuit described in Patent Document 1 adopts a configuration in which the short-circuited state of the power semiconductor device is determined based on the charge amount and the detected value of the gate voltage, thereby detecting the collector voltage of the power semiconductor device. As compared with the prior art in which the determination operation is performed based on the above, it is possible to detect the short-circuit state of the power semiconductor element more quickly.
  • the drive circuit described in Patent Document 1 it is necessary to include a gate voltage detection unit for detecting a gate voltage and a charge amount detection unit for detecting a charge amount.
  • the charge amount detection unit is configured to calculate the charge amount by detecting a gate current flowing into the gate terminal or a voltage corresponding to the gate current. Therefore, there is a problem that the configuration of the entire drive circuit becomes complicated, the device becomes large, and the cost becomes high.
  • the present invention has been made to solve such problems, and an object thereof is to provide a drive circuit for a power semiconductor device capable of quickly detecting a short circuit state of a power semiconductor device with a simple configuration. It is to provide.
  • FIG. 6 is a diagram showing waveforms of gate voltages at the time of turn-on operation in the IGBT for each of a normal time and an arm short circuit time. It is a figure which shows the relationship between the gate voltage at the time of the turn-on operation
  • FIG. 7 is a diagram showing waveforms of gate voltages at turn-on operation in the SiC-MOSFET in each of a normal state and an arm short circuit state.
  • FIG. 1 is a diagram showing a configuration of a power semiconductor device and a drive circuit thereof according to a first embodiment of the present invention.
  • FIG. 1 exemplifies an IGBT as the power semiconductor element 101, it is not necessarily limited to the IGBT, and may be a self arc extinguishing semiconductor element such as a MOSFET.
  • the power semiconductor element 101 is included in a power converter such as a reverse converter that converts DC power to AC power, and a forward converter that converts AC power to DC power.
  • the power semiconductor element 101 has a collector terminal 101c, an emitter terminal 101e and a gate terminal 101g.
  • the collector terminal 101c corresponds to an embodiment of the "first terminal” in the present invention
  • the emitter terminal 101e corresponds to an embodiment of the "second terminal”.
  • a voltage higher than that of the emitter terminal 101e is applied to the collector terminal 101c.
  • drive circuit 100 is a circuit for driving power semiconductor element 101, and includes control command unit 102, gate voltage detection unit 103, differentiator 104, first reference value generation circuit 105, A second reference value generation circuit 106, a first comparator 107, a third reference value generation circuit 108, a second comparator 109, and a short circuit determination unit 110.
  • the control command unit 102 When the control command unit 102 receives an on command from the outside, the power command semiconductor device 101 is switched to a conductive state (on state) (hereinafter referred to as “turn on”) as a gate command (turn on command). It outputs to the gate terminal 101g of 101. As a result, the power semiconductor element 101 is turned on and becomes conductive.
  • the control command unit 102 transmits a gate command (turn-off command) to the power semiconductor element to cause the power semiconductor element 101 to transition to a cutoff state (off state) (hereinafter referred to as “turn off”) when an off command is input from the outside. It outputs to the gate terminal 101g of 101. As a result, the power semiconductor element 101 is turned off to be in the cutoff state.
  • the gate voltage detection unit 103 detects a gate voltage applied to the gate terminal 101 g of the power semiconductor element 101 after receiving a turn-on command from the control command unit 102.
  • the gate voltage detection unit 103 outputs a signal indicating the detected gate voltage E.
  • the first reference value generation circuit 105 generates a first reference value REF1 (unit [V]).
  • the second reference value generation circuit 106 generates a second reference value REF2 (unit [V]).
  • the second reference value REF2 is higher than the first reference value REF1 (REF1 ⁇ REF2).
  • the first comparator 107 compares the gate voltage E detected by the gate voltage detection unit 103 with the first reference value REF1 and the second reference value REF2, and outputs a signal S1 representing the comparison result. .
  • the signal S1 becomes “H (logic high)” level.
  • the gate voltage E is lower than the first reference value REF1 (ie, when E ⁇ REF1), or when the gate voltage E is higher than the second reference value REF2 (ie, when E ⁇ REF2), the signal S1 is at the "L (logic low)" level.
  • the differentiator 104 time-differentiates the gate voltage E detected by the gate voltage detection unit 103 and outputs a differential value D.
  • the third reference value generation circuit 108 generates a third reference value REF3 (unit [V / s]).
  • the second comparator 109 compares the differential value D by the differentiator 104 with the third reference value REF3 and outputs a signal S2 representing the comparison result.
  • the signal S2 is at the “H” level.
  • the differential value D is smaller than or equal to the third reference value REF3 (ie, when D ⁇ REF3), the signal S2 is at the “L” level.
  • the short circuit determination unit 110 calculates the logical product of the signal S1 output from the first comparator 107 and the signal S2 output from the second comparator 109, whereby the power semiconductor device 101 It is determined whether or not there is a short circuit condition.
  • the short circuit determination unit 110 outputs a signal SS indicating the determination result to the control command unit 102.
  • Signal SS attains an "H” level indicating that power semiconductor element 101 is in a short-circuited state when signals S1 and S2 are both at an "H” level. That is, when the gate voltage E is higher than the first reference value REF1 and lower than the second reference value REF2 (REF1 ⁇ E ⁇ REF2), the differential value D is higher than the third reference value REF3. When the signal SS is also large (D> REF3), the signal SS is at the “H” level. On the other hand, when one of the signals S1 and S2 is at the "L” level, the signal SS is at the "L” level indicating that the power semiconductor element 101 is normal.
  • control command unit 102 When control command unit 102 receives signal SS at "H" level from short circuit determination unit 110, control command unit 102 outputs a turn-off command to power semiconductor device 101 in order to shut off power semiconductor device 101.
  • the gate voltage E decreases.
  • the signal S1 output from the first comparator 107 changes to the “L” level, and as a result, the logic between the signal S1 and the signal S2
  • the product signal SS also changes to the "L" level.
  • the short circuit determination unit 110 erroneously determines that the power semiconductor element 101 is not in the short circuit state.
  • the control command unit 102 receives the signal SS at the “L” level from the short circuit determination unit 110 and outputs the turn-on command again, the interruption of the power semiconductor element 101 is prevented.
  • the control command unit 102 has a function of holding the signal SS when the signal SS at the “H” level is received from the short circuit determination unit 110. According to this, even when the power semiconductor device 101 is determined to be in the short-circuit state, the power semiconductor device 101 is cut off according to the turn-off command, and the gate voltage E falls below the first reference value REF1. The control command unit 102 continues to output the turn-off command. Therefore, arm short circuit protection can be reliably performed without interruption operation for protecting the power semiconductor element 101 being disturbed.
  • drive circuit 100 determines the short-circuited state of power semiconductor element 101 based on gate voltage E and its differential value D at the time of turn-on operation of power semiconductor element 101. Is configured as. Such a configuration is realized by using a point where the relationship between the gate voltage at turn-on operation and its differential value differs between the normal state of the power semiconductor device 101 and the arm short circuit as described below. can do.
  • FIG. 2 is a diagram showing waveforms of the gate voltage V GE at the time of turn-on operation in the IGBT for each of the normal state and the arm short circuit state.
  • the solid line L1 in the figure shows a waveform of the gate voltage V GE during the turn-on operation in the normal
  • dashed L2 in the figure shows a waveform of the gate voltage V GE during turn-on operation at the time of arm short.
  • the gate voltage V GE rises.
  • a capacitance generated with reference to a gate terminal is generated between a gate terminal and an emitter terminal and a parasitic capacitance component (hereinafter referred to as “gate-collector capacitance C GC ”) generated between the gate terminal and the collector terminal.
  • gate-collector capacitance C GC a parasitic capacitance component generated between the gate terminal and the collector terminal.
  • gate-emitter capacitance C GE parasitic capacitance component
  • the gate-collector capacitance C GC corresponds to the feedback capacitance in the IGBT.
  • the gate-collector capacitance C GC and the gate-emitter capacitance C GE are connected in parallel with reference to the gate terminal.
  • the IGBT starts to turn on.
  • the IGBT is turned on, current starts to flow and the voltage at the collector terminal starts to fall. Since most of the gate current flows through the gate-collector capacitance C GC during the period from time t1 to t2 and no current flows through the gate-emitter capacitance C GE , the gate voltage V GE does not increase, and a constant state is obtained. maintain.
  • the length of the mirror period is determined by the gate-collector capacitance C GC . That is, when the gate-collector capacitance C GC becomes smaller, the mirror period becomes shorter, and when the gate-collector capacitance C GC becomes larger, the mirror period becomes longer.
  • the gate voltage V GE rises to the gate drive power supply voltage while charging the gate-emitter capacitance C GE .
  • the period from time t2 to t3 corresponds to the charging period of the gate-emitter capacitance C.sub.GE.
  • the collector-emitter voltage V CE hardly changes in the high voltage state, and the feedback capacitance (gate-collector capacitance C GC ) remains substantially constant.
  • the gate-collector capacitance C GC the feedback capacitance
  • FIG. 3 is a diagram showing the relationship between the gate voltage V GE at turn-on operation of the IGBT and its differential value (dV GE / dt) in each of the normal state and the arm short circuit state.
  • the solid line k1 in the figure shows the relationship between the gate voltage V GE in the normal state and the derivative thereof (gate voltage-differential value curve), and the broken line k2 in the figure is the gate voltage V GE at the arm short circuit and its derivative The relationship with the value (gate voltage-differential value curve) is shown.
  • the relationship shown by the solid line k1 is derived using a derivative value obtained by time-differentiating the waveform of the gate voltage V GE of the solid line L1 in FIG.
  • This mirror voltage V m is based on that varies depending on the value of the current flowing through the IGBT. When the current value is relatively small, the mirror voltage Vm is relatively low, and when the current value is relatively large, the mirror voltage Vm is relatively high.
  • the gate voltage V GE is the mirror voltage
  • the differential value when it is V m is a value close to zero.
  • the relationship shown by the broken line k2 is derived using a derivative value obtained by time-differentiating the waveform of the gate voltage V GE of the broken line L2 in FIG. Since the gate voltage V GE during arm short rises straight to the gate drive power supply voltage, the relationship shown in broken lines k2, the differential value with respect to the gate voltage V GE is maintained substantially constant.
  • FIG. 4 is a diagram showing the waveform of the gate voltage V GS at turn-on operation in the SiC-MOSFET in each of the normal state and the arm short circuit state.
  • the solid line L3 in the figure shows a waveform of the gate voltage V GS at the time of normal
  • the dashed line L4 in the figure shows a waveform of the gate voltage V GS at the time of turn-on operation at the time of arm short.
  • the gate voltage V GS rises.
  • the capacitance generated with reference to the gate terminal is a parasitic capacitance component (hereinafter referred to as “gate-drain capacitance C GD ”) generated between the gate terminal and the drain terminal, and between the gate terminal and the source terminal.
  • gate-source capacitance C GS parasitic capacitance component
  • the gate-drain capacitance C.sub.GD and the gate-source capacitance C.sub.GS are connected in parallel as viewed from the gate terminal.
  • the gate-source capacitance C GS When a voltage is applied to the gate terminal at time t0, the gate-source capacitance C GS is charged first, and the gate voltage V GS gradually rises.
  • the period from time t0 to t11 corresponds to the charging period of the gate-source capacitance C GS .
  • the SiC-MOSFET starts to turn on.
  • the SiC-MOSFET is turned on, current starts to flow and the voltage at the drain terminal starts to fall.
  • To charge the gate-drain capacitance C GD current starts flowing towards the gate-drain capacitance C GD.
  • the period from time t11 to t12 corresponds to the gate current propagation period of the gate-drain capacitance CGD .
  • the gate-source capacitance C GS is also charged in parallel with the charging of the gate-drain capacitance C GD , and as a result, the gate voltage V GS is gradually increased.
  • a period in which the gate voltage V GS gently rises from the mirror voltage V m11 to the mirror voltage V m12 as in the period from time t11 to t12 in FIG. 4 is referred to as a mirror period of the SiC-MOSFET.
  • the drain-source voltage V DS hardly changes with the high voltage state.
  • the mirror period does not appear, and the gate voltage V GS rises rapidly to the gate drive power supply voltage.
  • FIG. 5 is a diagram showing the relationship between the gate voltage V GS at turn-on operation and its differential value (dV GS / dt) in the SiC-MOSFET for each of the normal state and the arm short circuit state.
  • the solid line k3 in the figure shows the relationship between the gate voltage V GS in the normal state and its derivative value
  • the broken line k4 in the figure shows the relationship between the gate voltage V GS and its derivative value at the time of arm short circuit.
  • the relationship shown by the solid line k3 is derived using a derivative value obtained by time-differentiating the waveform of the gate voltage V GS of the solid line L3 in FIG.
  • the gate voltage V GS gradually increases in the mirror period. Therefore, in the relationship shown by the solid line k3, the differential value becomes a value near the positive value X2 before and after the mirror period, and the differential value becomes a positive value X3 smaller than the differential value before and after the mirror period in the mirror period.
  • the relationship shown by the broken line k4 is derived using a derivative value obtained by time-differentiating the waveform of the gate voltage V GS of the broken line L4 in FIG.
  • the gate voltage V GS rises at once to the gate drive power supply voltage, so the differential value with respect to the gate voltage V GS maintains a substantially constant state in the relationship shown by the broken line k4.
  • a first reference value REF1 which is used to determine a short-circuited state of the power semiconductor device 101 based on the gate voltage E at the turn-on operation of the power semiconductor device 101 and its differential value D.
  • the second reference value REF2 and the third reference value REF3 will be described.
  • first reference value REF1 and second reference value REF2 are based on the relationship between gate voltage V GE and its differential value dV GE / dt shown in FIG. 3. And a third reference value REF3 can be set.
  • the gate voltage-differential value curve (corresponding to the solid line k1 in the figure) in the normal state and the gate voltage in the arm short circuit
  • the reference values REF1, REF2, and REF3 are set to be included in the area surrounded by the derivative value curve (corresponding to the broken line k2 in the figure).
  • FIG. 3 shows a trapezoidal region RGN1 surrounded by the gate voltage-differential value curve (solid line k1) in the normal state and the gate voltage-differential value curve (broken line k2) in the arm short circuit state. It is done. It is set such that reference values REF1, REF2 and REF3 are included in this region RGN1. It is desirable that reference values REF1, REF2, and REF3 have a constant margin with respect to the boundary of region RGN1 in consideration of detection errors and the like. For example, to set the first reference value REF1 to a value greater than the minimum value V m1 mirror voltage V m, it sets the second reference value REF2 to a value smaller than the maximum value V m2 of the mirror voltage V m. The third reference value REF3 is set to a value larger than zero in the region RGN1.
  • a region RGN2 surrounded by the reference values REF1, REF2 and REF3 is set in the region RGN1.
  • output signal SS of short circuit determining portion 110 attains "H” level, and power semiconductor element 101 (IGBT) is in a short circuit state. It can be determined that there is.
  • output signal SS of short circuit determination unit 110 attains the “L” level, and it can be determined that power semiconductor element 101 is normal.
  • the first reference value REF 1 based on the relationship between the gate voltage V GS and its differential value dV GS / dt shown in FIG.
  • a second reference value REF2 and a third reference value REF3 can be set.
  • the gate voltage-differential value curve (corresponding to solid line k3 in the figure) under normal conditions and the gate voltage during arm short circuit
  • the reference values REF1, REF2, and REF3 are set to be included in the area surrounded by the derivative value curve (corresponding to the broken line k4 in the figure).
  • FIG. 5 shows a trapezoidal region RGN3 surrounded by the gate voltage-differential value curve (solid line k3) at normal time and the gate voltage-differential value curve (broken line k4) at arm short circuited. It is done. It is set such that reference values REF1, REF2 and REF3 are included in this region RGN3. It is desirable that reference values REF1, REF2, and REF3 have a constant margin with respect to the boundary of region RGN3 in consideration of detection errors and the like. For example, to set the first reference value REF1 to a value greater than the mirror voltage V m11, it sets the second reference value REF2 to a value smaller than the mirror voltage V m12. Third reference value REF3 is set to a value larger than positive value X3 in region RGN3.
  • a region RGN4 surrounded by the reference values REF1, REF2 and REF3 is set in the region RGN3.
  • output signal SS of short determination unit 110 attains the “H” level, and power semiconductor element 101 (SiC-MOSFET) is shorted. It can be determined that On the other hand, when the gate voltage V GS and a differential value is out of this region RGN4 can output signal SS of the short-circuit determination unit 110 becomes the "L" level, it is determined that the power semiconductor element 101 is normal.
  • FIG. 6 is a flowchart for explaining the processing procedure of the determination operation of the short-circuited state of the power semiconductor element 101.
  • the flowchart of FIG. 6 is executed by the drive circuit 100 in a fixed cycle by hardware or software processing.
  • gate voltage detection unit 103 is first applied to gate terminal 101g of power semiconductor element 101 after receiving a turn-on command from control command unit 102 in step S01. The gate voltage E is detected.
  • step S 02 the differentiator 104 temporally differentiates the gate voltage E detected by the gate voltage detection unit 103 to calculate a differential value D.
  • the first comparator 107 compares the gate voltage E with the first reference value REF1 and the second reference value REF2, and outputs a signal S1 representing the comparison result.
  • the second comparator 109 compares the differential value D with the third reference value REF3 and outputs a signal S2 representing the comparison result.
  • the short circuit determination unit 110 calculates the logical product of the signal S1 output from the first comparator 107 and the signal S2 output from the second comparator 109, whereby the power semiconductor device 101 is in a short circuit state. It determines whether or not it is, and outputs a signal SS indicating the determination result to the control command unit 102.
  • the short circuit determination unit 110 determines in step S04 that the power semiconductor element 101 is in the short circuit state, and outputs the signal SS of the “H” level.
  • the short circuit determination unit 110 holds the signal SS at the “H” level in step S06.
  • control command unit 102 When control command unit 102 receives signal SS at "H" level from short circuit determination unit 110 at step S07, control command unit 102 outputs a turn-off command to power semiconductor device 101 to cut off power semiconductor device 101. .
  • the short circuit determination unit 110 determines that the power semiconductor element 101 is normal at step S08, and outputs the signal SS of the “L” level.
  • short-circuited state of power semiconductor device based on gate voltage E of power semiconductor device and its differential value D at turn-on operation. Can be determined. According to this, since the determination operation can be performed by detecting only the gate voltage E of the power semiconductor element, the short circuit state of the power semiconductor element can be detected with a simple configuration.
  • the determination operation can be performed during the period until the gate voltage rises to the gate drive power supply voltage after the turn-on operation command, so the short-circuited state of the power semiconductor element Can be detected and protected quickly.
  • the reference values REF1, REF2, and REF3 can be easily set even when the power semiconductor device is a device such as a SiC-MOSFET in which the gate voltage in the mirror period is not constant. Since the setting can be made (see FIG. 5), the short-circuited state of the power semiconductor element can be detected quickly with a simple configuration.
  • the power semiconductor device is not limited to the SiC-MOSFET, and the present invention is also applied to a power semiconductor device composed of a wide band gap semiconductor material such as gallium nitride, gallium oxide, or diamond, for example. It is possible.
  • the gate voltage may be detected with high accuracy. is important.
  • configuration examples of the gate voltage detection unit for detecting the gate voltage with high accuracy will be described.
  • FIG. 7 is a diagram showing the configuration of a drive circuit 100A for a power semiconductor device according to a second embodiment of the present invention.
  • the drive circuit 100A according to the second embodiment is different from the drive circuit 100 shown in FIG. 1 in that a gate voltage detection unit 402 is provided instead of the gate voltage detection unit 103. .
  • the configuration of other portions of drive circuit 100A is the same as that of drive circuit 100 of FIG. 1, and therefore detailed description will not be repeated.
  • the gate voltage detection unit 402 includes a current detector 403 and an integrator 404.
  • the current detector 403 detects the gate current ig flowing into the gate terminal 101 g of the power semiconductor element 101.
  • the current detector 403 outputs a signal ig indicating the detected gate current.
  • the integrator 404 integrates the gate current ig detected by the current detector 403 in time.
  • C is shows a parasitic capacitance component generated between the gate terminal 101g and an emitter terminal 101e of the power semiconductor element 101 (i.e., the gate-emitter capacitance C GE).
  • the integrator 404 can calculate the gate voltage E based on an integral value obtained by time-integrating the gate current ig by using the above equation (1).
  • the gate-emitter capacitance C GE has a characteristic dependent on the gate-emitter voltage V GE . Therefore, the gate voltage E is calculated by setting the gate-emitter capacitance C GE in the equation (1) to an arbitrary constant between the maximum value and the minimum value of the function of the gate-emitter voltage V GE. be able to. Furthermore, the calculation accuracy of the gate voltage E can be improved by treating the gate-emitter capacitance C GE in the equation (1) as a function of the gate-emitter voltage V GE .
  • gate voltage detection unit 402 performs a gate based on an integral value obtained by time-integrating gate current ig detected by current detector 403. By detecting the voltage E, the gate voltage E can be detected with high accuracy.
  • the voltage generated by the parasitic inductance L of the power semiconductor element 101 is superimposed on the detection value of the voltmeter.
  • the parasitic inductance is an inductance component of a wire mainly connected to the emitter terminal 101 e of the power semiconductor element 101.
  • di / dt represents the time derivative of the current flowing through the parasitic inductance L. Since the voltmeter can not be installed avoiding the parasitic inductance L, it detects a voltage in which the voltage generated in the parasitic inductance L is superimposed on the gate voltage directly applied to the gate terminal 101g. Therefore, the detection value of the voltmeter has an error with respect to the gate voltage.
  • the parasitic inductance L Therefore, the voltage error due to V.sub.2 can be eliminated, and as a result, the accuracy of the gate voltage E can be improved. Therefore, the gate voltage E can be detected with high accuracy even when the power semiconductor element 101 is switched at high speed or operated with a large current. As a result, in the configuration in which the short-circuited state of the power semiconductor element 101 is determined based on the gate voltage E and its differential value D, it is possible to improve the determination accuracy of the shorted state.
  • FIG. 8 is a diagram showing the configuration of a drive circuit 100B for a power semiconductor element according to a third embodiment of the present invention.
  • drive circuit 100B according to the third embodiment is different from drive circuit 100 shown in FIG. 1 in that a gate voltage detection unit 502 is provided instead of gate voltage detection unit 103. .
  • the configuration of other portions of drive circuit 100B is the same as that of drive circuit 100 of FIG. 1, and therefore detailed description will not be repeated.
  • the gate voltage detection unit 502 includes a voltage detector 5100, a current detector 5201, an integrator 5202 and a gate voltage calculation unit 5300.
  • the voltage detector 5100 detects a gate voltage applied to the gate terminal 101 g of the power semiconductor element 101.
  • a general voltmeter can be used as the voltage detector 5100.
  • the voltage detector 5100 outputs a signal E1 indicating the detected gate voltage.
  • the current detector 5201 detects a gate current flowing into the gate terminal 101 g of the power semiconductor element 101.
  • the current detector 5201 outputs a signal ig indicating the detected gate current.
  • the integrator 5202 integrates the gate current ig detected by the current detector 5201 in time.
  • the integrator 5202 calculates the gate voltage based on the integral value obtained by time-integrating the gate current ig by using the above-mentioned equation (1).
  • the integrator 5202 outputs a signal E2 indicating the calculated gate voltage.
  • the gate voltage calculation unit 5300 applies the voltage to the gate terminal 101g of the power semiconductor element 101 by performing calculation using the gate voltage E1 detected by the voltage detector 5100 and the gate voltage E2 calculated by the integrator 5202. Calculate the gate voltage.
  • the gate voltage calculator 5300 outputs a signal E3 indicating the calculated gate voltage.
  • the gate voltage calculator 5300 calculates the gate voltage E3 by calculating the average value of the gate voltage E1 and the gate voltage E2. According to this, the gate voltage detection unit 502 can output the gate voltage E3 having high accuracy.
  • the gate voltage E when the gate voltage E is directly detected using the voltage detector 5100 (voltmeter), a voltage V generated by the parasitic inductance L of the power semiconductor element 101 is detected in the detected value. (2) see Fig. 2). Therefore, the gate voltage E1 detected by the voltage detector 5100 has a value larger than the gate voltage applied to the gate terminal 101g, and has an excessive error corresponding to the voltage V generated in the parasitic inductance L.
  • the gate current ig flowing into 101g gate terminal charges the gate-emitter capacitance C GE flows into the gate-emitter capacitance C GE.
  • the current for charging the gate-emitter capacitance C GE has two systems of a gate current ig flowing from the gate terminal 101g and a collector current ic flowing between the collector terminal 101c and the emitter terminal 101e.
  • the current detector 5201 can detect the gate current ig, it can not detect the collector current ic. Therefore, the value detected by the current detector 5201 is smaller than the current which actually charges the gate-emitter capacitance C.sub.GE.
  • the gate voltage E2 obtained by time-integrating the detected value of the gate current ig becomes a smaller value than the original gate voltage. That is, the gate voltage E2 has an undererror corresponding to the charging voltage by the collector current ic.
  • the gate voltage calculation unit 5300 substantially cancels out the excessive error and the excessive error by calculating the average value of the gate voltage E1 having the excessive error and the gate voltage E2 having the too small error. As a result, it is possible to obtain the gate voltage E3 with high accuracy in which both errors are reduced.
  • the gate voltage E1 and the gate voltage E2 may be simply averaged or weighted averaged.
  • the weight given to each of the gate voltages E1 and E2 can be adjusted for each of the power semiconductor elements, so that the accuracy of the gate voltage E3 can be further enhanced.
  • gate voltage E1 detected by voltage detector 5100 and the integral value of gate current ig detected by current detector 5201 are used.
  • the gate voltage E3 By calculating the gate voltage E3 by averaging the calculated gate voltage E2, the gate voltage can be detected with high accuracy.
  • the configuration in which the short-circuited state of the power semiconductor element 101 is determined based on the gate voltage E3 and its differential value D it is possible to improve the determination accuracy of the shorted state.
  • FIG. 9 is a diagram showing a configuration of a drive circuit 100C for a power semiconductor element according to a fourth embodiment of the present invention.
  • drive circuit 100C according to the fourth embodiment is different from drive circuit 100 shown in FIG. 1 in that gate voltage detection portion 602 is provided instead of gate voltage detection portion 103. .
  • the configuration of other portions of drive circuit 100C is the same as that of drive circuit 100 of FIG. 1, and therefore detailed description will not be repeated.
  • the gate voltage detection unit 602 includes a voltage detector 6101, a current detector 6201, a voltage drop calculation unit 6202, a correction gate voltage calculation unit 6102, an integrator 6203, and a gate voltage calculation unit 6300.
  • the voltage detector 6101 detects a gate voltage applied to the gate terminal 101 g of the power semiconductor element 101.
  • a common voltmeter can be used as the voltage detector 6101.
  • the voltage detector 6101 outputs a signal E1 indicating the detected gate voltage.
  • the current detector 6201 detects a gate current flowing into the gate terminal 101 g of the power semiconductor element 101.
  • the current detector 6201 outputs a signal ig indicating the detected gate current.
  • the gate voltage calculation unit 6300 performs the calculation using the gate voltage E11 calculated by the correction gate voltage calculation unit 6102 and the gate voltage E2 calculated by the integrator 6203 to obtain the gate terminal 101g of the power semiconductor element 101. Calculate the gate voltage applied to the The gate voltage calculator 6300 outputs a signal E3 indicating the calculated gate voltage.
  • the gate voltage calculation unit 6300 corresponds to an example of the “third calculation unit” in the present invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Conversion In General (AREA)

Abstract

La présente invention concerne un circuit d'attaque (100) destiné à un élément semi-conducteur de puissance, comprenant : une unité d'instruction de commande (102) qui émet une instruction de mise sous tension destinée à l'élément semi-conducteur de puissance (101) ; une unité de détection de tension de grille (103) qui détecte une tension de grille appliquée à une borne de grille (101g) après émission de l'instruction de mise sous tension par l'unité d'instruction de commande (102) ; un différenciateur (104) qui différencie temporellement la tension de grille détectée par l'unité de détection de tension de grille (103) ; et une unité de détermination (110) qui détermine, sur la base de la tension de grille détectée par l'unité de détection de tension de grille (103) et d'une valeur différentielle obtenue par le différenciateur (104), si l'élément semi-conducteur de puissance (101) est dans un état court-circuité ou non.
PCT/JP2018/019024 2017-07-28 2018-05-17 Circuit d'attaque destiné à un élément semi-conducteur de puissance WO2019021590A1 (fr)

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DE112018003834.3T DE112018003834T5 (de) 2017-07-28 2018-05-17 Treiberschaltung für ein leistungshalbleiterelement
JP2018540894A JP6425864B1 (ja) 2017-07-28 2018-05-17 電力用半導体素子の駆動回路
CN201880048828.0A CN110945789B (zh) 2017-07-28 2018-05-17 功率用半导体元件的驱动电路
US16/620,092 US10790813B2 (en) 2017-07-28 2018-05-17 Drive circuit for power semiconductor element

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JP2017-146886 2017-07-28

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WO2022049772A1 (fr) * 2020-09-07 2022-03-10 三菱電機株式会社 Dispositif de commande d'élément semi-conducteur, dispositif à semi-conducteurs et dispositif de conversion de puissance
CN114217201A (zh) * 2021-12-15 2022-03-22 中南大学 Igbt在线结温测量电路及其测量方法
WO2022091264A1 (fr) * 2020-10-28 2022-05-05 三菱電機株式会社 Circuit d'attaque d'élément semi-conducteur de puissance, appareil à semi-conducteur et appareil de conversion de puissance

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EP4160899A4 (fr) * 2020-05-27 2024-06-05 Hitachi, Ltd. Dispositif de détection de défaut et son procédé
CN111474460B (zh) * 2020-05-29 2022-03-22 中煤科工集团重庆研究院有限公司 Igbt栅极电阻故障检测系统
US20230074777A1 (en) * 2021-09-08 2023-03-09 Abb Schweiz Ag Sensor-less overcurrent fault detection using high electron mobility transistors
US11545969B1 (en) * 2021-09-20 2023-01-03 Infineon Technologies Ag Gate-to-source monitoring of power switches during runtime
FR3128995B1 (fr) * 2021-11-08 2023-10-27 Thales Sa Détection et protection de court-circuit d’un composant à grille isolée par monitoring et contrôle de la tension de grille.
US20230344332A1 (en) * 2022-04-21 2023-10-26 General Electric Company System and method for detecting igbt failure in a multi-level converter using gate-emitter voltage sensing
CN115754656A (zh) * 2022-11-23 2023-03-07 东莞光亚智能科技有限公司 场效应管损坏检测系统

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JP7334674B2 (ja) 2020-05-14 2023-08-29 株式会社デンソー スイッチの駆動回路
WO2022049772A1 (fr) * 2020-09-07 2022-03-10 三菱電機株式会社 Dispositif de commande d'élément semi-conducteur, dispositif à semi-conducteurs et dispositif de conversion de puissance
WO2022091264A1 (fr) * 2020-10-28 2022-05-05 三菱電機株式会社 Circuit d'attaque d'élément semi-conducteur de puissance, appareil à semi-conducteur et appareil de conversion de puissance
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CN114217201A (zh) * 2021-12-15 2022-03-22 中南大学 Igbt在线结温测量电路及其测量方法
CN114217201B (zh) * 2021-12-15 2022-10-18 中南大学 Igbt在线结温测量电路及其测量方法

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US20200212906A1 (en) 2020-07-02
CN110945789A (zh) 2020-03-31

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