WO2019010754A1 - Goa电路及其驱动方法、显示面板 - Google Patents

Goa电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2019010754A1
WO2019010754A1 PCT/CN2017/098258 CN2017098258W WO2019010754A1 WO 2019010754 A1 WO2019010754 A1 WO 2019010754A1 CN 2017098258 W CN2017098258 W CN 2017098258W WO 2019010754 A1 WO2019010754 A1 WO 2019010754A1
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Prior art keywords
pull
circuit
display panel
control
down switch
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PCT/CN2017/098258
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English (en)
French (fr)
Inventor
吕晓文
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/558,547 priority Critical patent/US10403220B2/en
Publication of WO2019010754A1 publication Critical patent/WO2019010754A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of driving technologies, and in particular, to a GOA (Gate Driver on Array) circuit, a driving method thereof, and a display panel.
  • GOA Gate Driver on Array
  • the GOA technology manufactures the driving circuit of the scanning line on the substrate around the display area of the liquid crystal display panel, so as to replace the external IC (Integrated Circuit) to complete the driving of each scanning line.
  • the GOA technology not only reduces the bonding process of the external IC, but also facilitates the narrow bezel or borderless design of the liquid crystal display panel.
  • the GOA circuit mainly includes a pull-up circuit, a pull-up control circuit, and a pull-down circuit, wherein a node capable of accessing a reference voltage, that is, a Q node, is provided between the pull-up control circuit and the pull-up circuit.
  • a node capable of accessing a reference voltage that is, a Q node
  • the GOA circuit needs to completely release the charge of the Q node at the abnormal shutdown moment.
  • the prior art generally pulls up the reference voltage when the liquid crystal display panel is turned off, for example, pulls up VSS (Voltage Series, common ground voltage) to completely discharge the entire GOA circuit.
  • VSS Voltage Series, common ground voltage
  • the reference voltage is low, and it takes time to pull it high to the high level.
  • the required time needs to be specially designed according to the entire driving system of the liquid crystal display panel, which is not only difficult to operate, but some driving systems may not support the technology, resulting in It is difficult to achieve complete discharge.
  • the present invention provides a GOA circuit, a driving method thereof, and a display panel capable of completely discharging a GOA circuit in a simpler manner.
  • a GOA circuit of a display panel includes a pull-up control circuit, a pull-up circuit and a reset circuit, and a node having a reference voltage accessible between the pull-up control circuit and the pull-up circuit, and an input terminal of the reset circuit The node is connected, the output end of the reset circuit is used to access the reference voltage, and the control end of the reset circuit is used to access the start signal STV at the moment of shutdown of the display panel to lower the potential of the node.
  • the GOA circuit includes a pull-up control circuit and a pull-up
  • the circuit and the reset circuit, the pull-up control circuit and the pull-up circuit have a node that can access the reference voltage, the input end of the reset circuit is connected to the node, and the output end of the reset circuit is used to access the reference voltage, and the reset circuit is
  • the control terminal is configured to access the start signal STV at the moment of shutdown of the display panel to lower the potential of the node.
  • a driving method of a GOA circuit of a display panel includes a pull-up control circuit and a pull-up circuit, and a node having a reference voltage between the pull-up control circuit and the pull-up circuit,
  • the driving methods include:
  • the output end of the reset circuit is connected to the reference voltage, and the control end of the reset circuit is connected to the start signal STV at the moment of shutdown of the display panel to pull down the potential of the node.
  • the present invention is designed to connect the start signal STV to the reset circuit at the moment of shutdown of the display panel. Since the start signal STV is originally a high level signal, the time required to pull up the reference voltage VSS can be eliminated in a simpler manner.
  • the GOA circuit is completely discharged to prevent the Q node from having signal residual and causing incomplete discharge, thereby avoiding abnormal startup.
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a GOA circuit according to an embodiment of the present invention.
  • Figure 3 is a timing diagram of various signals of the present invention.
  • FIG. 4 is a flow chart showing a driving method of a GOA circuit according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • the display panel 10 is provided with a GOA circuit 20 outside its display area (Active Area), which may be formed on the array substrate or the color film substrate of the display panel 10, and due to the display panel 10 GOA driving circuit structure of each line are the same, therefore the present embodiment to drive the n-th stage of the scanning line G n GOA circuit 20 are described as an example.
  • the GOA circuit 20 includes a pull-up control circuit 21, a pull-up circuit 22, and a reset circuit 23.
  • a node (ie, Q node) 24 between the pull-up control circuit 21 and the pull-up circuit 22, and the node 24 can access a reference voltage, such as VSS.
  • the input terminal of the reset circuit 23 is connected to the node 24, the output terminal of the reset circuit 23 is used to access the reference voltage VSS, and the control terminal of the reset circuit 23 can be connected to the IC formed outside the display area of the display panel 10.
  • the pull-up control circuit 21 may include a first switching transistor T 1
  • the pull-up circuit 22 may include a second switching transistor T 2 .
  • the control terminal (gate) of the first switching transistor T 1 is for receiving an ST signal (cycle start input signal), and the input terminal (source) of the first switching transistor T 1 is used for scanning from the upper stage (or the front stage) receives the output signal line, the output terminal of the first switch transistor T 1 (drain) and the control terminal of the second switching transistor T 2 is connected to the input terminal of the second switching transistor T 2 for receiving a CK signal (clock signal), the The output of the second switch T 2 is used to output a drive signal to the scan line G n of the present stage.
  • the output of the second switch T 2 is the output of the GOA circuit 20, and the output of the GOA circuit 20 outputs a drive signal.
  • the node 24 can be located between the output of the first switching transistor T 1 and the control terminal of the second switching transistor T 2 .
  • the ST signal of the pull-up control circuit 21 and the CK signal of the pull-up circuit 22 are both low, that is, the IC stops the pull-up control circuit 21 to input the ST signal and stops the pull-up circuit 22 to input the CK signal.
  • the first switch tube T 1 and the second switch tube T 2 are both turned off, and the IC applies a start signal STV to the control terminal of the reset circuit 23, which is equivalent to the conduction between the node 24 and the reference voltage VSS through the reset circuit 23.
  • the node 24 since the reference voltage VSS is a low level signal, the node 24 still has a high level signal at the moment of shutdown, so the charge of the node 24 will move to the reference voltage VSS, thereby achieving complete discharge of the GOA circuit 20, preventing the node 24 There is a residual signal, which causes the discharge to be incomplete, thereby preventing the display panel 10 from being turned on abnormally.
  • the start signal STV is used as the start signal of the scan line, it is originally a high level signal. Therefore, compared with the prior art, the full discharge is achieved by pulling the reference voltage VSS high. For example, it is not necessary to calculate the time required to pull up the reference voltage VSS, not only to completely discharge the GOA circuit 20 in a simpler manner, but also to adapt to the display panel 10 of various drive systems.
  • the start signal STV (served as the first start signal STV) applied to the reset circuit 23 by the IC at the moment of the shutdown of the display panel 10 and the start signal STV applied to the GOA circuit 20 when the display panel 10 is normally displayed ( It is considered that the second start signal STV) may be different.
  • the level of the first enable signal STV is higher than the level of the second enable signal STV, that is, the enable signal STV is pulled up, so that the charge of the node 24 can be released more quickly.
  • the time during which the first start signal STV is applied in the present embodiment is smaller than the time at which the second start signal STV is applied.
  • the purpose of the present invention is to access the enable signal STV to the reset circuit 23 at the moment of shutdown of the display panel 10 to achieve full discharge of the Q node 24.
  • the GOA circuit 20 to which the present invention is applied is not limited to the above.
  • the GOA circuit 20 may further include a pull-down circuit 25, which may include a first pull-down control circuit 251, a second pull-down control circuit 252, and a first
  • the pull-down switch component T 3 and the second pull-down switch component T 4 , the first pull-down switch component T 3 and the second pull-down switch component T 4 may both be thin film transistors, wherein the first pull-down switch component T 3 is first a source terminal, a first control terminal of the pull-down switching element T 3 is a gate, a first terminal of the third pull-down switching element T 3 as a drain; a second end of the first pull-down switching element T 4 as a source the control terminal of the second pull-down switching element T for the gate 4, the second end of the second pull-down switch element T 4 as a drain.
  • the first pull-down switch element T 3 is connected to the first gate of pull-down control circuit 251, a first pull-down switch element T 3 is the source electrode connected to the output terminal of the GOA circuit 20, the first pull-down switch element T 3
  • the drain is used to access the reference voltage VSS
  • the gate of the second pull-down switch T 4 is connected to the second pull-down control circuit 252
  • the source of the second pull-down switch T 4 is connected to the output of the GOA circuit 20
  • the second The drain of the pull-down switch T 4 is used to access the reference voltage VSS.
  • the present invention may be a control circuit 251 and a second pull-down control circuit 252 controls the first pull-down switch and the second member.
  • the reset circuit 23 can also perform corresponding structural design as needed.
  • the reset circuit 23 can include a thin film transistor.
  • the control terminal, the input terminal, and the output terminal of the reset circuit 23 are respectively the gate, the source, and the drain of the thin film transistor. pole.
  • the present invention also provides a driving method of a GOA circuit, which is applicable to a GOA circuit having a pull-up control circuit and a pull-up circuit, and the pull-up control circuit and the pull-up circuit have A node that can access the reference voltage.
  • the driving method of the GOA circuit of this embodiment may include the following steps S41 and S42.
  • S41 Form a reset circuit, and an input end of the reset circuit is connected to the node.
  • S42 Connect the output end of the reset circuit to the reference voltage, and connect the control end of the reset circuit to the start signal STV at the moment of shutdown of the display panel to lower the potential of the node.
  • the reset circuit of this embodiment may have the same structural design as the reset circuit 23 shown in FIG. 2.
  • the principle and process of the GOA test method can be referred to the above description, so the driving method has the same beneficial effects.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路（20）及其驱动方法、显示面板（10），GOA电路（20）的上拉控制电路（21）和上拉电路（22）之间具有可接入参考电压（VSS）的节点（24），复位电路（23）的输入端与节点（24）连接，复位电路（23）的输出端用于接入参考电压（VSS），复位电路（23）的控制端用于在显示面板（10）的关机瞬间接入启动信号（STV），以拉低节点（24）的电位。

Description

GOA电路及其驱动方法、显示面板 【技术领域】
本发明涉及驱动技术领域，具体涉及一种GOA(Gate Driver on Array，阵列基板行驱动)电路及其驱动方法、显示面板。
【背景技术】
GOA技术将扫描线的驱动电路制作在液晶显示面板的显示区周围的基板上，使之替代外接IC(Integrated Circuit，集成电路)来完成各级扫描线的驱动。GOA技术不仅能够减少外接IC的焊接(bonding)工序，而且有利于液晶显示面板的窄边框或无边框设计。
当前，GOA电路主要包括上拉电路、上拉控制电路以及下拉电路，其中上拉控制电路和上拉电路之间具有可接入参考电压的节点，即Q节点。并且，为了确保液晶显示面板在异常关机后能够正常开机，GOA电路需要在异常关机瞬间将Q节点的电荷完全释放。现有技术一般是在液晶显示面板关机瞬间拉高参考电压，例如拉高VSS(Voltage Series，公共接地端电压)，来对整个GOA电路进行完全放电。但是参考电压为低电平，将其拉高至高电平需要时间，所需时间需要根据液晶显示面板的整个驱动系统进行特别设计，不仅操作困难，而且某些驱动系统可能无法支持该技术，导致难以实现完全放电。
【发明内容】
鉴于此，本发明提供一种GOA电路及其驱动方法、显示面板，能够以更加简单的方式对GOA电路进行完全放电。
本发明一实施例的显示面板的GOA电路，包括上拉控制电路、上拉电路以及复位电路，上拉控制电路和上拉电路之间具有可接入参考电压的节点，复位电路的输入端与所述节点连接，复位电路的输出端用于接入参考电压，复位电路的控制端用于在显示面板的关机瞬间接入启动信号STV，以拉低所述节点的电位。
本发明一实施例的显示面板，其GOA电路包括上拉控制电路、上拉电 路以及复位电路，上拉控制电路和上拉电路之间具有可接入参考电压的节点，复位电路的输入端与所述节点连接，复位电路的输出端用于接入参考电压，复位电路的控制端用于在显示面板的关机瞬间接入启动信号STV，以拉低所述节点的电位。
本发明一实施例的显示面板的GOA电路的驱动方法，所述GOA电路包括上拉控制电路和上拉电路，上拉控制电路和上拉电路之间具有可接入参考电压的节点，所述驱动方法包括：
形成复位电路，且复位电路的输入端与所述节点连接；
将复位电路的输出端接入参考电压，并在显示面板的关机瞬间将复位电路的控制端接入启动信号STV，以拉低所述节点的电位。
有益效果：本发明设计在显示面板的关机瞬间为复位电路接入启动信号STV，由于启动信号STV原本就是高电平信号，因此无需拉高参考电压VSS所需的时间，能够以更加简单的方式对GOA电路进行完全放电，防止Q节点有信号残留而导致放电不完全，从而避免开机异常。
【附图说明】
图1是本发明一实施例显示面板的结构示意图；
图2是本发明一实施例的GOA电路的示意图；
图3是本发明的各个信号的时序图；
图4是本发明一实施例的GOA电路的驱动方法的流程示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的各个示例性的实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述各个实施例以及实施例中的特征可以相互组合。
图1是本发明一实施例显示面板的结构示意图。如图1所示，显示面板10在其显示区(Active Area)之外设置有GOA电路20，该GOA电路20可以形成于显示面板10的阵列基板或者彩膜基板上，并且由于显示面板10中驱动每一扫描线的GOA电路的结构均相同，因此本实施例以驱动第n级扫描线Gn的GOA电路20为例进行介绍。
图2是本发明一实施例的GOA电路的示意图。如图2所示，GOA电路20包括上拉控制电路21、上拉电路22以及复位电路23。其中，上拉控制电路21和上拉电路22之间具有节点(即Q节点)24，该节点24可接入参考电压，例如VSS。复位电路23的输入端与节点24连接，复位电路23的输出端用于接入参考电压VSS，复位电路23的控制端可以与形成于显示面板10的显示区之外的IC连接。
具体地，上拉控制电路21可以包括第一开关管T1，上拉电路22可以包括第二开关管T2。第一开关管T1的控制端(栅极)用于接收ST信号(循环启动输入信号)，第一开关管T1的输入端(源极)用于从上一级(或前级)扫描线接收输出信号，第一开关管T1的输出端(漏极)与第二开关管T2的控制端连接，第二开关管T2的输入端用于接收CK信号(时钟信号)，第二开关管T2的输出端用于向本级扫描线Gn输出驱动信号，其中第二开关管T2的输出端为GOA电路20的输出端，GOA电路20的输出端输出驱动信号。所述节点24可位于第一开关管T1的输出端和第二开关管T2的控制端之间。
结合图3所示，在显示面板10正常显示一帧画面时，形成于显示面板10的显示区之外的IC向第一开关管T1的控制端输入ST信号以及向第二开关管T2的输入端输入CK信号，ST信号和CK信号均为高电平。此时，第一开关管T1导通，第二开关管T2导通，上拉电路22根据CK信号向扫描线Gn输出驱动信号。
在显示面板10的关机瞬间，上拉控制电路21的ST信号以及上拉电路22的CK信号均为低电平，即IC停止向上拉控制电路21输入ST信号以及停止向上拉电路22输入CK信号，此时，第一开关管T1和第二开关管T2均断开，IC向复位电路23的控制端施加启动信号STV，相当于通过复位电路23导通节点24和参考电压VSS之间的连接，由于参考电压VSS为低电平信号、节点24在关机瞬间仍具有高电平信号，因此节点24的电荷会向参考电压VSS移动，从而实现对GOA电路20的完全放电，防止节点24有信号残留而导致放电不完全，进而避免显示面板10开机异常。
由于启动信号STV作为扫描线的启动信号，其原本就是高电平信号，因此，相比较于现有技术中通过拉高参考电压VSS实现完全放电，本实施 例无需计算拉高参考电压VSS所需的时间，不仅能够以更加简单的方式对GOA电路20进行完全放电，而且能够适应各种驱动系统的显示面板10。
在本实施例中，在显示面板10关机瞬间IC施加给复位电路23的启动信号STV(视为第一启动信号STV)和IC在显示面板10正常显示时施加给GOA电路20的启动信号STV(视为第二启动信号STV)可以不相同。具体地，第一启动信号STV的电平高于第二启动信号STV的电平，即拉高启动信号STV，从而能够更快的将节点24的电荷释放完。另外，基于节点24的放电时间小于一帧画面的显示时间，本实施例施加第一启动信号STV的时间小于施加第二启动信号STV的时间。
应该理解到，本发明的目的是在显示面板10的关机瞬间为复位电路23接入启动信号STV，以实现Q节点24的完全放电。基于此，本发明所适用的GOA电路20并不限于上述，例如GOA电路20还可以包括下拉电路25，该下拉电路25可以包括第一下拉控制电路251、第二下拉控制电路252、第一下拉开关件T3和第二下拉开关件T4，第一下拉开关件T3和第二下拉开关件T4可以均为薄膜晶体管，其中，第一下拉开关件T3的第一端为源极，第一下拉开关件T3的控制端为栅极，第一下拉开关件T3的第三端为漏极；第二下拉开关件T4的第一端为源极，第二下拉开关件T4的控制端为栅极，第二下拉开关件T4的第二端为漏极。第一下拉开关件T3的栅极连接于第一下拉控制电路251，第一下拉开关件T3的源极与GOA电路20的输出端连接，第一下拉开关件T3的漏极用于接入参考电压VSS，第二下拉开关件T4的栅极连接于第二下拉控制电路252，第二下拉开关件T4的源极与GOA电路20的输出端连接，第二下拉开关件T4的漏极用于接入参考电压VSS。在显示面板10的关机瞬间为复位电路23接入STV时，本发明可以通过第一下拉控制电路251和第二下拉控制电路252控制第一下拉开关件T3和第二下拉开关件T4导通，使得GOA电路20的输出端接入参考电压VSS，从而拉低驱动信号的电位。另外，复位电路23也可以根据需要进行相应的结构设计，例如复位电路23可以包括薄膜晶体管，复位电路23的控制端、输入端和输出端分别为所述薄膜晶体管的栅极、源极和漏极。
本发明还提供一种GOA电路的驱动方法，该驱动方法适用于具有上拉控制电路和上拉电路的GOA电路，所述上拉控制电路和上拉电路之间具有 可接入参考电压的节点。如图4所示，本实施例的GOA电路的驱动方法可以包括如下步骤S41和S42。
S41：形成复位电路，且复位电路的输入端与所述节点连接。
S42：将复位电路的输出端接入参考电压，并在显示面板的关机瞬间将复位电路的控制端接入启动信号STV，以拉低所述节点的电位。
其中，本实施例的复位电路可具有与图2所示复位电路23相同的结构设计。所述GOA测试方法的原理及过程可参阅上述描述，因此该驱动方法具有与其相同的有益效果。
再次说明，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种显示面板的阵列基板行驱动GOA电路，其中，所述GOA电路至少包括上拉控制电路、上拉电路以及复位电路，所述上拉控制电路和所述上拉电路之间具有可接入参考电压的节点，所述复位电路的输入端与所述节点连接，所述复位电路的输出端用于接入所述参考电压，所述复位电路的控制端用于在所述显示面板的关机瞬间接入启动信号STV，以拉低所述节点的电位。
  2. 根据权利要求1所述的GOA电路，其中，所述启动信号STV的电平高于所述显示面板在正常显示时施加给所述GOA电路的启动信号STV的电平。
  3. 根据权利要求1所述的GOA电路，其中，所述复位电路的控制端接入启动信号STV的时间小于所述显示面板正常显示一帧画面时施加给所述GOA电路的启动信号STV的时间。
  4. 根据权利要求1所述的GOA电路，其中，所述复位电路至少包括薄膜晶体管，所述复位电路的控制端、输入端和输出端分别为所述薄膜晶体管的栅极、源极和漏极。
  5. 根据权利要求1所述的GOA电路，其中，所述GOA电路的输出端输出驱动信号，所述GOA电路还包括第一下拉控制电路、第二下拉控制电路、第一下拉开关件和第二下拉开关件，所述第一下拉开关件的第一端和所述第二下拉开关件的第一端与所述输出端连接，所述第一下拉开关件的控制端连接所述第一下拉控制电路，所述第二下拉开关件的控制端连接所述第二下拉控制电路，所述第一下拉开关件的第二端和所述第二下拉开关件的第二端均接入参考电压。
  6. 根据权利要求1所述的GOA电路，其中，所述参考电压包括公共接地端电压VSS。
  7. 一种显示面板，其中，所述显示面板的GOA电路至少包括上拉控制电路、上拉电路以及复位电路，所述上拉控制电路和所述上拉电路之间具有可接入参考电压的节点，所述复位电路的输入端与所述节点连接，所述复位电路的输出端用于接入所述参考电压，所述复位电路的控制端用于 在所述显示面板的关机瞬间接入启动信号STV，以拉低所述节点的电位。
  8. 根据权利要求7所述的显示面板，其中，所述启动信号STV的电平高于所述显示面板在正常显示时施加给所述GOA电路的启动信号STV的电平。
  9. 根据权利要求7所述的显示面板，其中，所述复位电路的控制端接入启动信号STV的时间小于所述显示面板正常显示一帧画面时施加给所述GOA电路的启动信号STV的时间。
  10. 根据权利要求7所述的显示面板，其中，所述复位电路至少包括薄膜晶体管，所述复位电路的控制端、输入端和输出端分别为所述薄膜晶体管的栅极、源极和漏极。
  11. 根据权利要求7所述的显示面板，其中，所述GOA电路的输出端输出驱动信号，所述GOA电路还包括第一下拉控制电路、第二下拉控制电路、第一下拉开关件和第二下拉开关件，所述第一下拉开关件的第一端和所述第二下拉开关件的第一端与所述输出端连接，所述第一下拉开关件的控制端连接所述第一下拉控制电路，所述第二下拉开关件的控制端连接所述第二下拉控制电路，所述第一下拉开关件的第二端和所述第二下拉开关件的第二端均接入参考电压。
  12. 根据权利要求7所述的显示面板，其中，所述参考电压包括公共接地端电压VSS。
  13. 一种显示面板的阵列基板行驱动GOA电路的驱动方法，所述GOA电路包括上拉控制电路和上拉电路，所述上拉控制电路和所述上拉电路之间具有可接入参考电压的节点，其中，所述驱动方法包括：
    形成复位电路，且所述复位电路的输入端与所述节点连接；
    将所述复位电路的输出端接入参考电压，并在所述显示面板的关机瞬间将所述复位电路的控制端接入启动信号STV，以拉低所述节点的电位。
  14. 根据权利要求13所述的驱动方法，其中，所述启动信号STV的电平高于所述显示面板在正常显示时施加给所述GOA电路的启动信号STV的电平。
  15. 根据权利要求13所述的驱动方法，其中，所述复位电路的控制端接入启动信号STV的时间小于所述显示面板正常显示一帧画面时施加给所 述GOA电路的启动信号STV的时间。
  16. 根据权利要求13所述的驱动方法，其中，所述复位电路至少包括薄膜晶体管，所述复位电路的控制端、输入端和输出端分别为所述薄膜晶体管的栅极、源极和漏极。
  17. 根据权利要求13所述的驱动方法，其中，所述GOA电路的输出端输出驱动信号，所述GOA电路还包括第一下拉控制电路、第二下拉控制电路、第一下拉开关件和第二下拉开关件，所述第一下拉开关件的第一端和所述第二下拉开关件的第一端与所述输出端连接，所述第一下拉开关件的控制端连接所述第一下拉控制电路，所述第二下拉开关件的控制端连接所述第二下拉控制电路，所述第一下拉开关件的第二端和所述第二下拉开关件的第二端均接入参考电压。
  18. 根据权利要求13所述的驱动方法，其中，所述参考电压包括公共接地端电压VSS。
PCT/CN2017/098258 2017-07-12 2017-08-21 Goa电路及其驱动方法、显示面板 Ceased WO2019010754A1 (zh)

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