WO2019007310A1 - 共模电压产生装置及逐次逼近寄存器型模数转换器 - Google Patents

共模电压产生装置及逐次逼近寄存器型模数转换器 Download PDF

Info

Publication number
WO2019007310A1
WO2019007310A1 PCT/CN2018/094185 CN2018094185W WO2019007310A1 WO 2019007310 A1 WO2019007310 A1 WO 2019007310A1 CN 2018094185 W CN2018094185 W CN 2018094185W WO 2019007310 A1 WO2019007310 A1 WO 2019007310A1
Authority
WO
WIPO (PCT)
Prior art keywords
common mode
circuit
mode voltage
resistor
voltage generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/094185
Other languages
English (en)
French (fr)
Inventor
李有慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Publication of WO2019007310A1 publication Critical patent/WO2019007310A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Definitions

  • the present invention relates to the field of analog-to-digital conversion technology, and in particular, to a common mode voltage generating device and a successive approximation register type analog to digital converter.
  • the successive approximation register analog to digital converter has the advantages of low power consumption, high precision, large working bandwidth and simple circuit design, and is widely used in various portable devices. .
  • the SAR ADC works by converting the analog voltage to digital bits using a series of stages, each of which compares an analog voltage to a reference voltage to produce a digital bit.
  • the comparator is one of the key modules in the SAR ADC, and its performance determines the performance of the entire ADC.
  • the comparator compares the analog input signal outputted by the sample-and-hold circuit with a reference voltage provided by a digital to analog converter (DAC) to obtain a corresponding high level or low level, and sends it to successive approximation. register.
  • DAC digital to analog converter
  • the comparator needs a common mode voltage (VCM) to work normally.
  • VCM common mode voltage
  • the common mode voltage is used to set the static operating point of each stage of the amplifier circuit, so that the amplifier circuits inside the comparator have no input signal. Before the best working condition.
  • a common mode voltage generating device for outputting a common mode voltage to a comparator in a successive approximation register type analog to digital converter
  • the first end of the switching circuit is connected to a power source; the second end of the switching circuit is configured to receive the successive approximation register type analog-to-digital converter for controlling the sampling and holding circuit in a sampling state and a holding state a control signal for switching between; and
  • a common mode voltage generating circuit an input end of the common mode voltage generating circuit is connected to a third end of the switch circuit, and an output end of the common mode voltage generating circuit is used to connect the comparator;
  • the switch circuit is configured to turn on the power supply circuit of the power supply to the common mode voltage generating circuit when the control signal is to control the sampling and holding circuit to switch to a command corresponding to the sampling state;
  • the circuit is configured to: when the control signal is to be controlled to switch the sampling and holding circuit to a command corresponding to the hold state, disconnect the power supply circuit of the common mode voltage generating circuit; and the common mode voltage generating circuit
  • the common mode voltage is output to the comparator.
  • a successive approximation register type analog-to-digital converter including a common mode voltage generating device for outputting a total of comparators in the successive approximation register type analog to digital converter a mode voltage;
  • the common mode voltage generating device includes:
  • the first end of the switching circuit is connected to a power source; the second end of the switching circuit is configured to receive the successive approximation register type analog-to-digital converter for controlling the sampling and holding circuit in a sampling state and a holding state a control signal for switching between; and
  • a common mode voltage generating circuit an input end of the common mode voltage generating circuit is connected to a third end of the switch circuit, and an output end of the common mode voltage generating circuit is used to connect the comparator;
  • the switch circuit is configured to turn on the power supply circuit of the power supply to the common mode voltage generating circuit when the control signal is to control the sampling and holding circuit to switch to a command corresponding to the sampling state;
  • the circuit is configured to: when the control signal is to be controlled to switch the sampling and holding circuit to a command corresponding to the hold state, disconnect the power supply circuit of the common mode voltage generating circuit; and the common mode voltage generating circuit
  • the common mode voltage is output to the comparator.
  • FIG. 1 is a block diagram showing the composition of a common mode voltage generating device provided in an embodiment
  • FIG. 2 is a block diagram showing a composition of a successive approximation register type analog-to-digital converter in an embodiment
  • FIG. 3 is a specific circuit diagram of a common mode voltage generating device in the embodiment shown in FIG. 1.
  • the bandgap reference voltage generating circuit is usually used to generate a highly accurate bandgap voltage, which is then supplied to the comparator through an amplifier or a buffer.
  • the bandgap reference voltage generating circuit is usually complicated, and sometimes requires trimming technology, which occupies a large area and consumes a large amount of power.
  • the bandgap voltage is generally a high-impedance output, there is almost no driving capability, and the required common-mode voltage cannot be directly supplied to the comparator in the SAR ADC, so an amplifier or a buffer is indispensable.
  • the common-mode voltage requirements are also high: First, the common-mode voltage is stable, otherwise the performance of the SAR ADC will deteriorate; secondly, The common mode voltage must have a sufficiently fast response speed, and the common mode voltage must be sufficiently stable before the comparator begins to compare; again, the common mode voltage should have less noise. Based on these characteristics of the common mode voltage, high demands are placed on the above amplifiers or buffers, that is, stable, low noise, high gain, and large bandwidth are required, and amplifiers or buffers having these characteristics generally consume power. Large, large chip area and high cost. Therefore, the conventional SAR ADC common-mode voltage processing method has the defects of large power consumption, large chip area, and high cost.
  • an embodiment provides a common mode voltage generating device for outputting a common mode voltage to a comparator 200 in a successive approximation register type analog-to-digital converter (SAR ADC).
  • the common mode voltage is used to set the static operating point of each stage of the amplifying circuit in the comparator 200, so that the level amplifying circuits inside the comparator 200 are in an optimal working state before the input signal is received.
  • the successive approximation register type analog to digital converter generally includes a sample and hold circuit 300, a comparator 200, a successive approximation register 400, a digital/analog converter 500, and a logic control unit 600. Please refer to FIG.
  • the output of the sample and hold circuit 300 is coupled to the non-inverting input of the comparator 200.
  • the output of comparator 200 is coupled to successive approximation register 400.
  • the successive approximation register 400 is also coupled to the digital to analog converter 500 and the logic control unit 600, respectively.
  • the output of the digital to analog converter 500 is coupled to the inverting input of the comparator 200.
  • the analog input voltage V IN is held by the sample and hold circuit 300.
  • logic control unit 600 To implement the binary search algorithm, logic control unit 600 first controls the most significant bit of successive approximation register 400 to be "1" level, while the remaining bits are all “0" levels. At this time, the output voltage V DAC of the digital-to-analog converter 500 is V REF /2, where V REF is the reference voltage.
  • the comparison between V IN and V DAC if V IN >V DAC , the comparator 200 outputs a "1" level, and the most significant bit of the successive approximation register 400 remains “1”level; otherwise, if V IN ⁇ V For the DAC , the comparator 200 outputs a "0" level, and the most significant bit of the successive approximation register 400 is set to the "0" level.
  • the logic control unit 600 controls the successive approximation register 400 to move to the next bit, and sets the bit to the "1" level for the next comparison until the least significant bit comparison is completed. After the end of the process, an analog to digital conversion is completed and the conversion result is stored in the successive approximation register 400.
  • the common mode voltage generating device includes a switching circuit 110 and a common mode voltage generating circuit 120 .
  • the first end (1) of the switching circuit 110 is connected to a power supply (VDD).
  • the second terminal (2) of the switching circuit 110 is operative to receive a control signal in the successive approximation register type analog to digital converter for controlling the sampling and holding circuit 300 to switch between the sampling state and the holding state.
  • the output signal of the sample and hold circuit 300 changes in accordance with the change of the input signal; when in the hold state, the output signal of the sample and hold circuit 300 remains the input signal level value at the moment of receiving the hold command.
  • the third terminal (3) of the switching circuit 110 is connected to the input terminal of the common mode voltage generating circuit 120.
  • the output of the common mode voltage generating circuit 120 is used to connect the comparator 200.
  • the common mode voltage generating circuit 120 outputs a common mode voltage to the comparator 200 after the power is turned on through the switching circuit 110. Therefore, the common mode voltage generating circuit 120 can generate a common mode voltage after the power is turned on. For example, the power supply voltage can be converted into a common mode voltage by voltage conversion.
  • the switch circuit 110 has two states of disconnection and conduction.
  • the switch circuit 110 turns on the power supply (VDD) to the power supply circuit of the common mode voltage generating circuit 120 when the control signal is to control the sampling and holding circuit 300 to switch to the command corresponding to the sampling state.
  • the switch circuit 110 turns off the power supply (VDD) to the power supply circuit of the common mode voltage generating circuit 120 when the control signal is a command to switch the sample hold circuit 300 to the hold state.
  • control signal is simultaneously input to two ports: one port is the control terminal of the sample-and-hold circuit 300, and the other port is the second terminal of the switch circuit 110.
  • control signal can be output by the logic control unit 600 or other type of controller.
  • the switch circuit 110 switches between the off state and the on state according to different states of the control signal, so that the common mode voltage generating circuit 120 is not always in the working state. Specifically, after the control signal output by the controller is a command corresponding to the sampling state, the sample and hold circuit 300 will switch to the sampling state, and the comparator 200 will reset and require a common mode voltage to enter the comparison state, and at the same time, In the common mode voltage generating device, the switching circuit 110 is turned on, so that the power supply can supply the common mode voltage generating circuit 120, so that the common mode voltage generating circuit 120 outputs the common mode voltage to the comparator 200 to ensure that the comparator 200 is Before the comparison is in an optimal working state; after the control signal output by the controller is the command corresponding to the hold state, the sample and hold circuit 300 will switch to the hold state, and at this time, the comparator 200 has been compared and the common mode is not required. At the same time, in the common mode voltage generating device, the switching circuit 110 is turned on, so that the power supply can supply
  • the common mode voltage generating circuit 120 operates normally only when the comparator 200 requires a common mode voltage, and stops when the comparator 200 does not require a common mode voltage. Moreover, since the sampling time accounts for only a small portion of the entire operating time during the entire operation of the successive approximation register type analog-to-digital converter, power consumption can be effectively reduced.
  • the sample and hold circuit 300 when the control signal is at a low level, the sample and hold circuit 300 will switch to the sampling state; and when the control signal is at a high level, the sample and hold circuit 300 will switch to the hold state.
  • the sample and hold circuit 300 can be composed of an analog switch, a storage element, and a buffer amplifier.
  • the control signal applied to the analog switch is low, at which point the analog switch is turned on, causing the voltage across the storage element to vary with the sampled signal.
  • the control signal goes high.
  • the analog switch is turned off, and the voltage across the storage element remains unchanged at the moment of disconnection.
  • the switch circuit 110 turns on the power supply circuit to the common mode voltage generating circuit 120 when the control signal is at the first level. Further, the switch circuit 110 turns off the power supply circuit to the common mode voltage generating circuit 120 when the control signal is at the second level.
  • the voltage level corresponding to the first level is lower than the voltage value corresponding to the second level, and the first level is less than the second level.
  • the first level is a low level and the second level is a high level.
  • the voltage value corresponding to the low level is lower than the voltage value corresponding to the high level.
  • the voltage value corresponding to the low level may be 0V
  • the voltage value corresponding to the high level may be 5V.
  • the operation mode of the switch circuit 110 is not limited to the above case. If the control signal is replaced by the control mode, the operation mode of the switch circuit 110 will change correspondingly according to the control signal. For example, if the control signal is high, the sample and hold circuit 300 will switch to the hold state; and when the control signal is low, the sample and hold circuit 300 will switch to the sampling state, then at this time, the switch circuit 110 is at the control signal. When the level is high, the power supply circuit for the common mode voltage generating circuit 120 is turned on. When the control signal is low, the switch circuit 110 turns off the power supply circuit for the common mode voltage generating circuit 120.
  • the switch circuit 110 includes a PMOS transistor. Further, the source, the gate and the drain of the PMOS transistor are a first end, a second end, and a third end, respectively. Therefore, when the control signal is low, the voltage applied to the gate of the PMOS transistor is low, and the PMOS transistor is turned on; when the control signal is high, the voltage applied to the gate of the PMOS transistor is high. At this time, the PMOS tube is disconnected.
  • the common mode voltage generating circuit 120 is a voltage dividing circuit. Among them, the voltage dividing circuit obtains the common mode voltage through the principle of resistance division. At this time, after the common mode voltage generating circuit 120 is connected to the power source through the switch circuit 110, the power source is divided to obtain a common mode voltage, and the common mode voltage is output to the comparator 200. In addition, by adjusting the voltage division ratio of the voltage dividing circuit, the common mode voltage can be applied to the different types of comparators 200, thereby expanding the application range of the common mode voltage generating device.
  • the voltage dividing circuit includes a first resistor R1 and a second resistor R2.
  • One end of the first resistor R1 is connected to the third end of the switch circuit 110.
  • the switch circuit 110 is a PMOS transistor
  • one end of the resistor R1 is connected to the drain of the PMOS transistor.
  • the other end of the first resistor R1 is grounded through the second resistor R2.
  • the common terminal of the first resistor R1 and the second resistor R2 is an output terminal of the common mode voltage generating circuit 120, that is, used for connection with the comparator 200.
  • the resistance values of the first resistor R1 and the second resistor R2 are both greater than the resistance values after the switch circuit 110 is turned on.
  • the resistance of the first resistor R1 and the second resistor R2 may be between 2000 ohms and 5000 ohms.
  • the switching circuit 110 is a PMOS transistor
  • the resistance of the PMOS transistor is small after being turned on, usually on the order of several tens of ohms. Therefore, the value of the common mode voltage (referred to as VCM) and the value of the power supply voltage (VDD).
  • the above-mentioned common mode voltage generating device provided by the embodiment of the present invention can directly apply the common mode voltage of the output to the comparator 200 by selecting an appropriate resistor, without separately setting an amplifier, thereby eliminating the traditional complicated.
  • the bandgap reference voltage generating circuit and the more complicated common mode voltage buffer circuit have simple circuit structure, are easy to implement, have small chip area, low cost, and further reduce low power consumption.
  • a successive approximation register type analog to digital converter including a common mode voltage generating device.
  • the common mode voltage generating means is operative to output a common mode voltage to a comparator in the successive approximation register type analog to digital converter.
  • the common mode voltage generating device includes a switching circuit and a common mode voltage generating circuit. The first end of the switch circuit is connected to a power source. The second end of the switching circuit is configured to receive a control signal in the successive approximation register type analog-to-digital converter for controlling the sampling and holding circuit to switch between a sampling state and a holding state. The third end of the switching circuit is coupled to an input of the common mode voltage generating circuit. An output of the common mode voltage generating circuit is used to connect the comparator.
  • the switching circuit turns on the power supply circuit of the common mode voltage generating circuit when the control signal is a command to switch the sampling and holding circuit to a sampling state. Moreover, the switch circuit turns off the power supply circuit to the common mode voltage generating circuit when the control signal is a command corresponding to switching the sample hold circuit to the hold state.
  • the common mode voltage generating circuit outputs the common mode voltage to the comparator after the power is applied through the switching circuit.
  • the switching circuit turns on the power supply circuit of the common mode voltage generating circuit when the control signal is low level; and the switching circuit is in the control signal When the level is high, the power supply circuit of the common mode voltage generating circuit is turned off; wherein the voltage value corresponding to the low level is lower than the voltage value corresponding to the high level.
  • the switching circuit includes a PMOS transistor; the source, the gate, and the drain of the PMOS transistor are the first end, the second end, and the third end, respectively.
  • the common mode voltage generating circuit is a voltage dividing circuit; and the common mode voltage generating circuit divides the power source after the power is connected through the switching circuit. The common mode voltage is applied and the common mode voltage is output to the comparator.
  • the voltage dividing circuit includes a first resistor and a second resistor; one end of the first resistor is connected to a third end of the switch circuit, and the other end of the first resistor passes the Two resistors are grounded; a common end of the first resistor and the second resistor is used for connecting with the comparator; and, the resistances of the first resistor and the second resistor are both greater than the switch circuit The resistance after the pass.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

一种共模电压产生装置，用于向逐次逼近寄存器型模数转换器内的比较器(200)输出共模电压；包括：开关电路(110)，所述开关电路(110)的第一端接入电源；所述开关电路(110)的第二端用于接收所述逐次逼近寄存器型模数转换器内用于控制采样保持电路(300)在采样状态和保持状态之间进行切换的控制信号；及共模电压产生电路(120)，所述共模电压产生电路(120)的输入端连接所述开关电路(110)的第三端，所述共模电压产生电路(120)的输出端用于连接所述比较器(200)；其中，所述开关电路(110)用于在所述控制信号为将要控制所述采样保持电路(300)切换至采样状态对应的命令时，接通所述电源对所述共模电压产生电路(120)的供电电路；所述开关电路(110)用于在所述控制信号为将要控制所述采样保持电路(300)切换至保持状态对应的命令时，断开所述电源对所述共模电压产生电路(120)的供电电路；所述共模电压产生电路(120)用于向所述比较器(200)输出所述共模电压。

Description

共模电压产生装置及逐次逼近寄存器型模数转换器 技术领域
本发明涉及模数转换技术领域，特别是涉及一种共模电压产生装置及逐次逼近寄存器型模数转换器。
背景技术
逐次逼近寄存器型模数转换器(Successive Approximation Register Analog to Digital Converter，简称SAR ADC)具有低功耗，高精度、较大的工作带宽及电路设计简单等优点，被广泛应用于各种便携设备中。SAR ADC的工作原理为：使用一系列阶段将模拟电压转换成数字比特，其中每个阶段将一个模拟电压和一个参考电压进行比较，以产生一个数字比特。
其中，比较器是SAR ADC中的关键模块之一，它的性能决定着整个ADC的性能。比较器将采样保持电路输出的模拟输入信号与数/模转换器(Digital to analog converter，简称DAC)提供的参考电压进行比较，得出相应的高电平或低电平，并发送至逐次逼近寄存器。并且，比较器需要一个共模电压(VCM)方能正常工作，该共模电压用于设置比较器内各级放大电路的静态工作点，从而使比较器内部的各级放大电路在没有输入信号前处于最佳的工作状态。
发明内容
基于此，有必要提供一种共模电压产生装置及逐次逼近寄存器型模数转换器。
一种共模电压产生装置，用于向逐次逼近寄存器型模数转换器内的比较器输出共模电压；包括：
开关电路，所述开关电路的第一端接入电源；所述开关电路的第二端用 于接收所述逐次逼近寄存器型模数转换器内用于控制采样保持电路在采样状态和保持状态之间进行切换的控制信号；及
共模电压产生电路，所述共模电压产生电路的输入端连接所述开关电路的第三端，所述共模电压产生电路的输出端用于连接所述比较器；
其中，所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至采样状态对应的命令时，接通所述电源对所述共模电压产生电路的供电电路；所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至保持状态对应的命令时，断开所述电源对所述共模电压产生电路的供电电路；所述共模电压产生电路用于向所述比较器输出所述共模电压。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
另一方面，还提供一种逐次逼近寄存器型模数转换器，包括共模电压产生装置；所述共模电压产生装置用于向所述逐次逼近寄存器型模数转换器内的比较器输出共模电压；所述共模电压产生装置包括：
开关电路，所述开关电路的第一端接入电源；所述开关电路的第二端用于接收所述逐次逼近寄存器型模数转换器内用于控制采样保持电路在采样状态和保持状态之间进行切换的控制信号；及
共模电压产生电路，所述共模电压产生电路的输入端连接所述开关电路的第三端，所述共模电压产生电路的输出端用于连接所述比较器；
其中，所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至采样状态对应的命令时，接通所述电源对所述共模电压产生电路的供电电路；所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至保持状态对应的命令时，断开所述电源对所述共模电压产生电路的供电电路；所述共模电压产生电路用于向所述比较器输出所述共模电压。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中提供的共模电压产生装置的组成框图；
图2为一实施例中逐次逼近寄存器型模数转换器的一种组成框图；
图3为图1所示实施例中的共模电压产生装置的其中一种具体电路图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在传统的SAR ADC共模电压的处理方法中，通常要利用带隙基准电压产生电路产生一个高精准的带隙电压，并经过放大器或者缓冲器后再提供至比较器使用。其中，带隙基准电压产生电路通常比较复杂，有时还需要用到微调(trimming)技术，占用面积比较大，功耗较大。另外，由于带隙电压一般是高阻输出，几乎没有任何驱动能力，不能直接为SAR ADC内的比较器提供所需的共模电压，因此放大器或缓冲器是必不可少的。而且，由于比较器的性能对整个SAR ADC来说都是至关重要的，因此，对共模电压的要求也较高：首先，共模电压要稳定，否则会恶化SAR ADC的性能；其次，共模电压要有足够快的响应速度，并且，共模电压必须在比较器开始进行比较前足够稳定；再次，共模电压要有较小的噪声。基于共模电压的这些特点， 对于上述放大器或者缓冲器也提出了较高的要求，即需要具备稳定、低噪声、高增益和大带宽等特点，而具备这些特点的放大器或者缓冲器通常功耗大，芯片面积大，成本较高。因此，传统的SAR ADC共模电压的处理方法具有功耗大、芯片面积大、成本较高等缺陷。
请参考图1和图2，一实施例提供了一种共模电压产生装置，用来向逐次逼近寄存器型模数转换器(SAR ADC)内的比较器200输出共模电压。其中，共模电压用于设置比较器200内各级放大电路的静态工作点，从而使比较器200内部的各级放大电路在没有输入信号前处于最佳的工作状态。
逐次逼近寄存器型模数转换器通常包括采样保持电路300、比较器200、逐次逼近寄存器400、数/模转换器500及逻辑控制单元600，请参考图2。采样保持电路300的输出端连接比较器200的同相输入端。比较器200的输出端连接逐次逼近寄存器400。逐次逼近寄存器400还分别与数/模转换器500、逻辑控制单元600连接。数/模转换器500的输出端连接比较器200的反相输入端。
其中，模拟输入电压V IN由采样保持电路300保持。为实现二进制搜索算法，逻辑控制单元600首先控制逐次逼近寄存器400的最高有效位为“1”电平，而其余位均为“0”电平。此时，数/模转换器500的输出电压V DAC为V REF/2，其中，V REF是基准电压。然后，比较判断V IN与V DAC，若V IN>V DAC，则比较器200输出“1”电平，逐次逼近寄存器400的最高有效位保持“1”电平；反之，若V IN<V DAC，则比较器200输出“0”电平，逐次逼近寄存器400的最高有效位被置为“0”电平。随后，逻辑控制单元600控制逐次逼近寄存器400移至下一位，并将该位设置为“1”电平，进行下一次比较，直至最低有效位比较完毕。整个过程结束后，即完成了一次模拟量到数字量的转换，转换结果储存在逐次逼近寄存器400内。
本发明实施例中，请继续参考图1，共模电压产生装置包括开关电路110及共模电压产生电路120。开关电路110的第一端(1)接入电源(VDD)。开关电路110的第二端(2)用于接收逐次逼近寄存器型模数转换器内用于控 制采样保持电路300在采样状态和保持状态之间进行切换的控制信号。其中，当处于采样状态时，采样保持电路300的输出信号跟随输入信号变化而变化；当处于保持状态时，采样保持电路300的输出信号保持为接到保持命令的瞬间的输入信号电平值。另外，开关电路110的第三端(3)连接共模电压产生电路120的输入端。共模电压产生电路120的输出端用于连接比较器200。
共模电压产生电路120在通过开关电路110接入电源后向比较器200输出共模电压。因此，共模电压产生电路120在接入电源后能够产生共模电压，例如可以通过电压转换的方式将电源电压转换为共模电压。
开关电路110具有断开和导通两种状态。本发明实施例中，开关电路110在控制信号为将要控制采样保持电路300切换至采样状态对应的命令时，接通电源(VDD)对共模电压产生电路120的供电电路。并且，开关电路110在控制信号为将要控制采样保持电路300切换至保持状态对应的命令时，断开电源(VDD)对共模电压产生电路120的供电电路。
换言之，在逐次逼近寄存器型模数转换器内，控制信号同时输入至两个端口：一个端口为采样保持电路300的控制端，另一个端口为开关电路110的第二端。并且，控制信号可以由逻辑控制单元600或其他类型的控制器输出。
因此，本发明实施例中，开关电路110根据控制信号的不同状态而相应在断开状态和导通状态之间进行切换，使得共模电压产生电路120不是一直都处于工作状态的。具体为：当控制器输出的控制信号为采样状态对应的命令之后，采样保持电路300将会切换至采样状态，比较器200将会进行复位并需要共模电压以进入比较状态，与此同时，在共模电压产生装置内，开关电路110导通，使得电源能够对共模电压产生电路120进行供电，从而使得共模电压产生电路120向比较器200输出共模电压，以保证比较器200在进行比较前处于最佳的工作状态；当控制器输出的控制信号为保持状态对应的命令之后，采样保持电路300将会切换至保持状态，并且这时比较器200已经比较完毕将无需使用共模电压，与此同时，在共模电压产生装置内，开关 电路110断开，这时电源无法对共模电压产生电路120进行供电，共模电压产生电路120则停止运行。
综上所述，本发明实施例中，共模电压产生电路120只有在比较器200需要共模电压时才正常运行，而在比较器200不需要共模电压时则停止运行。并且，由于在逐次逼近寄存器型模数转换器的整个运行期间，采样时间只占整个工作时间的较少部分，因此可以有效降低功耗。
具体地，控制信号为低电平时，采样保持电路300将切换至采样状态；而控制信号为高电平时，采样保持电路300将切换至保持状态。例如：采样保持电路300可以由模拟开关、存储元件和缓冲放大器组成。在采样时刻，加到模拟开关上的控制信号为低电平，此时模拟开关被接通，使存储元件两端的电压随着采样信号变化。当采样间隔终止时，控制信号则变为高电平，这时模拟开关断开，存储元件两端的电压则保持在断开瞬间的值不变。
基于控制信号的上述控制方式，开关电路110在控制信号为第一电平时，接通电源对共模电压产生电路120的供电电路。并且，开关电路110在控制信号为第二电平时，断开电源对共模电压产生电路120的供电电路。第一电平对应的电压值低于第二电平对应的电压值，第一电平小于第二电平。在一个实施例中，第一电平是低电平，第二电平是高电平。其中，低电平对应的电压值低于高电平对应的电压值。例如：低电平对应的电压值可以为0V，高电平对应的电压值可以为5V。
可以理解的是，开关电路110的运行方式不限于上述情况，如果控制信号更换了控制方式后，开关电路110的运行方式将会根据控制信号而发生相应的变化。例如：如果控制信号为高电平时，采样保持电路300将切换至保持状态；而控制信号为低电平时，采样保持电路300将切换至采样状态，那么此时，开关电路110则在控制信号为高电平时，接通电源对共模电压产生电路120的供电电路，在控制信号为低电平时，开关电路110断开电源对共模电压产生电路120的供电电路。
具体地，请参考图3，开关电路110包括PMOS管。并且，PMOS管的 源极、栅极、漏极分别为第一端、第二端、第三端。因此，当控制信号为低电平时，加在PMOS管栅极的电压为低电平，这时PMOS管导通；当控制信号为高电平时，加在PMOS管栅极的电压为高电平，这时PMOS管断开。
另外，共模电压产生电路120为分压电路。其中，分压电路通过电阻分压原理得到共模电压。此时，共模电压产生电路120在通过开关电路110接入电源后，对电源进行分压得到共模电压，并向比较器200输出共模电压。另外，通过调节分压电路的分压比例，可以使得共模电压适用于不同型号的比较器200，从而扩大了该共模电压产生装置的应用范围。
具体地，请参考图3，上述分压电路包括第一电阻R1和第二电阻R2。第一电阻R1的一端连接开关电路110的第三端，具体地，当开关电路110为PMOS管时，电阻R1的一端连接PMOS管的漏极。第一电阻R1的另一端通过第二电阻R2接地。第一电阻R1与第二电阻R2的公共端为共模电压产生电路120的输出端，即用于与比较器200连接。并且，第一电阻R1和第二电阻R2的阻值均大于开关电路110导通后的阻值。
在一个实施例中，第一电阻R1和第二电阻R2的阻值可以介于2000欧姆至5000欧姆之间。这时，若开关电路110为PMOS管，PMOS管导通后其电阻较小，通常在几十欧姆的量级，因此，共模电压的值(记为VCM)和电源电压的值(VDD)之间具有如下关系：
VCM/VDD≈R2/(R1+R2)
这时只要改变第一电阻R1和第二电阻R2的阻值，就可以得到不同的共模电压，从而适用于多种型号的比较器200。
因此，本发明实施例提供的上述共模电压产生装置，通过选择合适的电阻，即可使得输出的共模电压能够直接应用到比较器200，而无需另外设置放大器，从而省去了传统复杂的带隙基准电压产生电路以及更为复杂的共模电压缓冲电路，电路结构简单，易于实现，芯片面积小，成本低，同时进一步降低了功耗低。
在另一实施例中，提供了一种逐次逼近寄存器型模数转换器，包括共模 电压产生装置。所述共模电压产生装置用来向所述逐次逼近寄存器型模数转换器内的比较器输出共模电压。所述共模电压产生装置包括：开关电路及共模电压产生电路。所述开关电路的第一端接入电源。所述开关电路的第二端用于接收所述逐次逼近寄存器型模数转换器内用于控制采样保持电路在采样状态和保持状态之间进行切换的控制信号。所述开关电路的第三端连接所述共模电压产生电路的输入端。所述共模电压产生电路的输出端用于连接所述比较器。
所述开关电路在所述控制信号为将要控制所述采样保持电路切换至采样状态对应的命令时，接通所述电源对所述共模电压产生电路的供电电路。并且，所述开关电路在所述控制信号为将要控制所述采样保持电路切换至保持状态对应的命令时，断开所述电源对所述共模电压产生电路的供电电路。所述共模电压产生电路在通过所述开关电路接入所述电源后向所述比较器输出所述共模电压。
在其中一个实施例中，所述开关电路在所述控制信号为低电平时，接通所述电源对所述共模电压产生电路的供电电路；并且，所述开关电路在所述控制信号为高电平时，断开所述电源对所述共模电压产生电路的供电电路；其中，所述低电平对应的电压值低于所述高电平对应的电压值。
在其中一个实施例中，所述开关电路包括PMOS管；所述PMOS管的源极、栅极、漏极分别为所述第一端、所述第二端、所述第三端。
在其中一个实施例中，所述共模电压产生电路为分压电路；并且，所述共模电压产生电路在通过所述开关电路接入所述电源后，对所述电源进行分压得到所述共模电压，并向所述比较器输出所述共模电压。
在其中一个实施例中，所述分压电路包括第一电阻和第二电阻；所述第一电阻的一端连接所述开关电路的第三端，所述第一电阻的另一端通过所述第二电阻接地；所述第一电阻与所述第二电阻的公共端用于与所述比较器连接；并且，所述第一电阻和所述第二电阻的阻值均大于所述开关电路导通后的阻值。
需要说明的是，上述逐次逼近寄存器型模数转换器的具体原理与上述实施例提供的共模电压产生装置相应结构的原理相同，这里就不再赘述。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种共模电压产生装置，用于向逐次逼近寄存器型模数转换器内的比较器输出共模电压；包括：
    开关电路，所述开关电路的第一端接入电源；所述开关电路的第二端用于接收所述逐次逼近寄存器型模数转换器内用于控制采样保持电路在采样状态和保持状态之间进行切换的控制信号；及
    共模电压产生电路，所述共模电压产生电路的输入端连接所述开关电路的第三端，所述共模电压产生电路的输出端用于连接所述比较器；
    其中，所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至采样状态对应的命令时，接通所述电源对所述共模电压产生电路的供电电路；所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至保持状态对应的命令时，断开所述电源对所述共模电压产生电路的供电电路；所述共模电压产生电路用于向所述比较器输出所述共模电压。
  2. 根据权利要求1所述的共模电压产生装置，其特征在于，所述开关电路在所述控制信号为第一电平时，接通所述电源对所述共模电压产生电路的供电电路；所述开关电路在所述控制信号为第二电平时，断开所述电源对所述共模电压产生电路的供电电路；其中，所述第一电平对应的电压值低于所述第二电平对应的电压值，所述第一电平小于所述第二电平。
  3. 根据权利要求2所述的共模电压产生装置，其特征在于，所述开关电路包括PMOS管；所述PMOS管的源极、栅极、漏极分别为所述第一端、所述第二端、所述第三端。
  4. 根据权利要求1所述的共模电压产生装置，其特征在于，所述共模电压产生电路为分压电路；所述共模电压产生电路在通过所述开关电路接入所述电源后，对所述电源进行分压得到所述共模电压，并向所述比较器输出所述共模电压。
  5. 根据权利要求4所述的共模电压产生装置，其特征在于，所述分压电 路包括第一电阻和第二电阻；所述第一电阻的一端连接所述开关电路的第三端，所述第一电阻的另一端通过所述第二电阻接地；所述第一电阻与所述第二电阻的公共端用于与所述比较器连接；并且，所述第一电阻和所述第二电阻的阻值均大于所述开关电路导通后的阻值。
  6. 根据权利要求5所述的共模电压产生装置，其特征在于，所述共模电压产生电路输出的所述共模电压和所述电源的电压比值为所述第二电阻的阻值与所述第一电阻和第二电阻的阻值之和的比值，从而可以通过调节所述第一电阻和第二电阻的阻值来调节所述共模电压。
  7. 根据权利要求5所述的共模电压产生装置，其特征在于，所述第一电阻和第二电阻的阻值介于2000欧姆至5000欧姆之间。
  8. 一种逐次逼近寄存器型模数转换器，包括共模电压产生装置；所述共模电压产生装置用于向所述逐次逼近寄存器型模数转换器内的比较器输出共模电压；所述共模电压产生装置包括：
    开关电路，所述开关电路的第一端接入电源；所述开关电路的第二端用于接收所述逐次逼近寄存器型模数转换器内用于控制采样保持电路在采样状态和保持状态之间进行切换的控制信号；及
    共模电压产生电路，所述共模电压产生电路的输入端连接所述开关电路的第三端，所述共模电压产生电路的输出端用于连接所述比较器；
    其中，所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至采样状态对应的命令时，接通所述电源对所述共模电压产生电路的供电电路；所述开关电路用于在所述控制信号为将要控制所述采样保持电路切换至保持状态对应的命令时，断开所述电源对所述共模电压产生电路的供电电路；所述共模电压产生电路用于向所述比较器输出所述共模电压。
  9. 根据权利要求8所述的逐次逼近寄存器型模数转换器，其特征在于，所述开关电路在所述控制信号为第一电平时，接通所述电源对所述共模电压产生电路的供电电路；所述开关电路在所述控制信号为第二电平时，断开所述电源对所述共模电压产生电路的供电电路；其中，所述低电平对应的电压 值低于所述高电平对应的电压值，所述第一电平小于所述第二电平。
  10. 根据权利要求9所述的逐次逼近寄存器型模数转换器，其特征在于，所述开关电路包括PMOS管；所述PMOS管的源极、栅极、漏极分别为所述第一端、所述第二端、所述第三端。
  11. 根据权利要求8所述的逐次逼近寄存器型模数转换器，其特征在于，所述共模电压产生电路为分压电路；所述共模电压产生电路在通过所述开关电路接入所述电源后，对所述电源进行分压得到所述共模电压，并向所述比较器输出所述共模电压。
  12. 根据权利要求11所述的逐次逼近寄存器型模数转换器，其特征在于，所述分压电路包括第一电阻和第二电阻；所述第一电阻的一端连接所述开关电路的第三端，所述第一电阻的另一端通过所述第二电阻接地；所述第一电阻与所述第二电阻的公共端用于与所述比较器连接；并且，所述第一电阻和所述第二电阻的阻值均大于所述开关电路导通后的阻值。
  13. 根据权利要求12所述的逐次逼近寄存器型模数转换器，其特征在于，所述共模电压产生电路输出的所述共模电压和所述电源的电压比值为所述第二电阻的阻值与所述第一电阻和第二电阻的阻值之和的比值，从而可以通过调节所述第一电阻和第二电阻的阻值来调节所述共模电压。
  14. 根据权利要求12所述的逐次逼近寄存器型模数转换器，其特征在于，所述第一电阻和第二电阻的阻值介于2000欧姆至5000欧姆之间。
PCT/CN2018/094185 2017-07-03 2018-07-03 共模电压产生装置及逐次逼近寄存器型模数转换器 Ceased WO2019007310A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710533735.4 2017-07-03
CN201710533735.4A CN109217873B (zh) 2017-07-03 2017-07-03 共模电压产生装置及逐次逼近寄存器型模数转换器

Publications (1)

Publication Number Publication Date
WO2019007310A1 true WO2019007310A1 (zh) 2019-01-10

Family

ID=64950575

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/094185 Ceased WO2019007310A1 (zh) 2017-07-03 2018-07-03 共模电压产生装置及逐次逼近寄存器型模数转换器

Country Status (2)

Country Link
CN (1) CN109217873B (zh)
WO (1) WO2019007310A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113452371B (zh) * 2020-03-25 2023-07-04 智原微电子(苏州)有限公司 连续逼近暂存式模拟数字转换器与相关的控制方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070115159A1 (en) * 2005-11-18 2007-05-24 Fujitsu Limited Analog-to-digital converter
CN101325401A (zh) * 2007-06-12 2008-12-17 上海沙丘微电子有限公司 全差分音频功率放大器开关机噪声抑制电路
CN102006075A (zh) * 2010-12-23 2011-04-06 复旦大学 一种能量节省型电容阵列的逐次逼近型模数转换器
CN103166644A (zh) * 2013-04-11 2013-06-19 东南大学 一种低功耗逐次逼近型模数转换器及其转换方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2388483B (en) * 2002-05-10 2005-08-24 Wolfson Ltd Audio transient suppression circuits and methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070115159A1 (en) * 2005-11-18 2007-05-24 Fujitsu Limited Analog-to-digital converter
CN101325401A (zh) * 2007-06-12 2008-12-17 上海沙丘微电子有限公司 全差分音频功率放大器开关机噪声抑制电路
CN102006075A (zh) * 2010-12-23 2011-04-06 复旦大学 一种能量节省型电容阵列的逐次逼近型模数转换器
CN103166644A (zh) * 2013-04-11 2013-06-19 东南大学 一种低功耗逐次逼近型模数转换器及其转换方法

Also Published As

Publication number Publication date
CN109217873A (zh) 2019-01-15
CN109217873B (zh) 2020-02-11

Similar Documents

Publication Publication Date Title
US6967611B2 (en) Optimized reference voltage generation using switched capacitor scaling for data converters
JP4381993B2 (ja) 校正可能なアナログ／デジタル変換器及び関連方法
US9479190B2 (en) Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling
CN107017883B (zh) 模拟数字转换器及用于模拟数字转换器的输入缓冲器
US9106239B1 (en) Data converter with redundancy for error correction
JP2006517765A (ja) 臨界的な連続時間用途における自動ゼロ化
US8410820B2 (en) High speed latch comparators
CN110012677B (zh) 电容式逐次逼近模数转换器
US8004446B2 (en) A/D converter and A/D conversion method
US7382305B1 (en) Reference generators for enhanced signal converter accuracy
WO2019007310A1 (zh) 共模电压产生装置及逐次逼近寄存器型模数转换器
Singh et al. Power efficient SAR ADC designed in 90 nm CMOS technology
US4862171A (en) Architecture for high speed analog to digital converters
TWI446726B (zh) 連續逼近暫存式類比數位轉換器
CN108449076B (zh) 动态比较器、模数转换器、模数转换系统以及校准方法
JPH0877789A (ja) サンプルホールド回路
CN118487600A (zh) 一种单端输入的精度可配置的sar-adc及其芯片
JP2001326327A (ja) 半導体集積回路
KR102259734B1 (ko) 와이드 샘플링 레이트를 위한 순차접근 방식의 아날로그-디지털 컨버터
JP2004080238A (ja) Ｄ／ａコンバータ及び自動補正方法
KR20010021082A (ko) 전류모드 비동기식 결정 ａ/ｄ 변환기
US6646584B2 (en) Circuit design technique for increasing the bandwidth of sample-and-hold circuits in flash ADCs
US8410968B2 (en) Track and hold circuit
JPH07202700A (ja) Ａ／ｄ変換装置
JP3637936B2 (ja) 比較器及びａ／ｄコンバータ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18828878

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18828878

Country of ref document: EP

Kind code of ref document: A1