WO2018236651A1 - Gravure au plasma pour la formation de motifs en cuivre - Google Patents

Gravure au plasma pour la formation de motifs en cuivre Download PDF

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Publication number
WO2018236651A1
WO2018236651A1 PCT/US2018/037396 US2018037396W WO2018236651A1 WO 2018236651 A1 WO2018236651 A1 WO 2018236651A1 US 2018037396 W US2018037396 W US 2018037396W WO 2018236651 A1 WO2018236651 A1 WO 2018236651A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper
exposed portion
hard mask
interconnect
radiation
Prior art date
Application number
PCT/US2018/037396
Other languages
English (en)
Inventor
Peter Nunan
Xuena Zhang
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to CN201880041196.5A priority Critical patent/CN110770881B/zh
Priority to KR1020207000988A priority patent/KR102355416B1/ko
Publication of WO2018236651A1 publication Critical patent/WO2018236651A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70008—Production of exposure light, i.e. light sources
    • G03F7/70033—Production of exposure light, i.e. light sources by plasma extreme ultraviolet [EUV] sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Definitions

  • Embodiments described herein generally relate to methods for forming flat panel displays, and more particularly to methods for forming high pixel density flat panel displays.
  • Display devices have been widely used for a wide range of electronic applications, such as television, monitors, mobile phone, MPS players, e-book readers, personal digital assistants (PDAs) and the like.
  • display devices As the resolution requirement for display devices becomes increasingly challenging, e.g., display resolution greater than 2,000 pixels per inch (PPi) or 450 PPi in mobile displays, display devices have a limited area for forming conductance electrodes that do not interfere with the illumination of the pixels and device performance. Maintaining the semiconductor integrated circuits formed in the display devices in a confined location with a relatively small area has become a focus. Low resistance materials such as copper enable higher currents to flow through a given area mitigating electromigration and allowing for further display scaling.
  • the low resistance materials such as copper
  • the low resistance materials need to be either a short, wide line or a tail, thin line.
  • a mask first patterns the copper and then a wet isotropic etch is utilized to make short, wide lines.
  • devices with short, wide interconnections interfere with the illumination of the pixels as the PPi increases. Utilizing wet etching to manufacture a tali, thick line results in etching underneath the mask which over-etches the copper and negatively affects device performance.
  • a method of etching includes depositing a copper layer on a substrate, depositing a hard mask on the copper layer, patterning the hard mask to expose a first portion of the copper layer, and removing the exposed portion of the copper to form an interconnect. Removing the exposed portion of the copper includes dry etching the exposed portion of the copper and continuously exposing the exposed portion of the copper to UV radiation.
  • a method of etching includes depositing a copper layer on a substrate, depositing a hard mask on the copper layer, patterning the hard mask to expose a first portion of the copper layer, and removing the exposed portion of the copper to form an interconnect. Removing the exposed portion of the copper includes dry etching the exposed portion of the copper and exposing the exposed portion of the copper to pulsed UV radiation.
  • a method of etching includes depositing a copper layer on a substrate, depositing a hard mask on the copper layer, patterning the hard mask to expose a first portion of the copper layer, and removing the exposed portion of the copper to form an interconnect. Removing the exposed portion of the copper includes wet and dry etching the exposed portion of the copper and exposing the exposed portion of the copper to UV radiation.
  • Figures 2A-2D show stages of fabrication of a device structure in accordance with the method of Figure 1.
  • Embodiments described herein generally relate to methods for forming flat panel displays, and more particularly to methods for forming high pixel density fiat panel displays.
  • a dry etch process with UV radiation exposure, copper voiafizes at low temperatures without driving the copper into other device components, which can destroy functionality of the device.
  • high aspect ratio copper interconnects can be formed.
  • Figure 1 shows a flow diagram summarizing a method 100 for forming low resistivity, high aspect ratio copper interconnects.
  • Figures 2A-2D depict stages of fabrication of a device 200 in accordance with the method 100 of Figure 1. The method 100 is described below in accordance with stages of formation of the copper interconnects as seen in Figures 2A-2D.
  • a copper layer 204 is deposited on a substrate 202.
  • the substrate 202 may include a silicon-containing material and the surface may include a material, such as silicon (Si), germanium (Ge) or silicon germanium alloys (SiGe).
  • the substrate may further include germanium (Ge), carbon (C), boron (B), phosphorous (P), or other known elements that may be co-grown, doped and/or associated with silicon materials.
  • the Si, Ge, or SiGe surface may have an oxide layer, such as native oxide layer, disposed thereon.
  • the substrate 202 may be a semiconductor substrate with devices formed thereon.
  • the copper layer 204 may be pure copper or a copper alloy formed with such materials as tin, zinc, silver, nickel, aluminum, and other metals. Any suitable process that deposits copper onto a substrate may be used. Suitable processes for depositing a copper layer 204 include physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, or combinations thereof.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • electroplating or combinations thereof.
  • a hard mask layer 206 is deposited on the copper layer 204.
  • the hard mask layer 206 may be deposited by any suitable deposition method, such as CVD process, which may be plasma enhanced, atomic layer deposition, spin coating, or any other suitable deposition method.
  • the hard mask layer 206 may be silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), titanium oxide (TiO), tungsten oxide (WO), Zirconium dioxide (Zr02), and other metal oxides.
  • the hard mask layer 206 is patterned to expose a first portion of the copper layer 212.
  • the hard mask layer 206 is patterned using photolithography. Patterning the hard mask layer includes depositing a photoresist layer 208 over the hard mask layer 206 by, in one example, spin coating, then exposing the photoresist layer 208 to radiation. The photoresist layer 208 is then developed using an aqueous base, and the photoresist layer 208 and hard mask layer 206 are etched to expose a first portion of the copper layer 212. A resist strip is then applied to the photoresist layer 208 to remove the patterned photoresist layer 208, resulting in a patterned hard mask 210.
  • Figure 2B illustrates the device 200 having a patterned hard mask 210 thereon, in such an example, the hard mask layer 206 is patterned to form the patterned hard mask 210.
  • the patterned hard mask 210 is in contact with an upper surface of the copper layer 204.
  • the copper layer 204 has an exposed upper surface 212 adjacent the patterned hard mask 210.
  • the exposed portion of the copper 212 is removed to form an interconnect 214.
  • the exposed portion of the copper layer 212 is etched to expose the substrate 202.
  • the copper interconnect 214 is about the same width as the patterned hard mask 210. in one implementation, the copper interconnect has an aspect ratio of about 5: 1 to about 8.1.
  • Suitable methods of etching the copper layer 212 include anisotropic dry etching in combination with radiation exposure.
  • the portion of the copper layer 212 that is not covered by the hard mask 210 is removed by utilizing a plasma dry etch processes in combination with a UV radiation exposure.
  • the etching process gas may include one or more etchants.
  • the etchants may be excited by a RF power to generate radicals of the etchant gas in order to facilitate etching of the exposed copper layer 212.
  • Exemplary cleaning processes include NF3/NH3 plasma-based processes, such as inductively coupled plasma processes, or remote plasma processes.
  • the etchant includes a halogen-containing gas, optionally a hydrogen-containing gas, and optionally an inert gas.
  • the halogen-containing gas is chlorine and/or fluorine gas
  • the hydrogen- containing gas is hydrogen gas
  • the optional inert gas is argon, helium, or both.
  • Exemplary chlorine-containing gases include diatomic chlorine (CI2) gas.
  • the inert gas may include at least one of argon, helium, hydrogen, neon, xenon, diatomic nitrogen and the like.
  • the plasma etch process is a remote plasma assisted dry etch process which involves the simultaneous exposure of a substrate to NF3 and NH3 plasma by-products
  • the plasma etch process includes exposing the copper layer 212 to nitrogen trifiuoride (NF 3 ) remote plasma at room temperature.
  • the plasma etch process may be an inductively couple plasma (ICP) process.
  • the plasma etch process may be performed in a SiCoNiTM chamber that is available from Applied Materials, Inc. of Santa Clara, California.
  • the device 200 is heated with or otherwise exposed to UV radiation.
  • the chemistry of the remote plasma etch may be chosen such at that etch process is selective towards silicon oxide layers, and thus does not readily etch silicon regardless of whether the silicon is amorphous, crystalline or polycrystaliine.
  • aspects of the present disclosure utilize UV radiation in addition to the disclosed etchant chemistries.
  • Etch processes associated with embodiments provided herein may be performed at temperatures between about 30°C and about 50°C. UV radiation facilitates voiatization of copper at lower temperatures than conventional processes, and therefore, device performance is not destroyed. Thus, high aspect ratio copper interconnects can be formed.
  • the device 200 is exposed to UV radiation generated by one or my UV bulbs, or other sources of radiation.
  • the UV radiation is a wavelength of about 10 nm to about 400 nm.
  • the device 200 is simultaneously exposed to the UV radiation while being dry etched.
  • the UV radiation is pulsed while the device 200 is being dry etched, in other words, the while the device 200 is being dry etched, there are periods of time where the UV radiation is on and periods of time where the UV radiation is turned off.
  • the device 200 may be alternately (e.g., cyclically) exposed to etchant chemistry and the UV radiation, or the device 200 may be exposed to a constant etchant chemistry while the UV radiation is pulsed.
  • the device 200 is exposed to UV radiation for between 0 min. to 10 hours. By combining the dry etch process with UV radiation exposure the copper will volatize at low temperatures without driving the copper into the substrate or other device components.
  • other methods of etching may be used to etch the copper layer 204. in one implementation, an optional wet etch may be used.
  • the device 200 is first dry etched and exposed to UV radiation and then wet etched. In other words, a UV assisted dry etch is performed followed by a wet etch, in another implementation, dry etching and wet etching are both performed in the presence of UV radiation.
  • the device 200 may continuously be exposed to UV radiation during both the dry etching and wet etching.
  • the UV radiation may be pulsed during the dry etching and wet etching.
  • the hard mask 210 may optionally be removed using the wet etching.
  • the hard mask 210 may optionally remain on the copper interconnect 214 if a wet etch is not employed.
  • the device 200 may undergo further processing after the interconnect 214 is formed, as seen in Figure 2D.
  • a dielectric layer 216 may be deposited over the interconnect 214.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne des procédés de formation d'écrans plats, et plus particulièrement des procédés de formation d'écrans plats à haute densité de pixels. Un procédé de gravure peut comprendre les étapes consistant à déposer une couche de cuivre sur un substrat, déposer un masque dur sur la couche de cuivre, appliquer un motif sur le masque dur pour exposer une première partie de la couche de cuivre, et retirer la partie exposée du cuivre pour former une interconnexion. L'étape consistant à retirer la partie exposée du cuivre comprend l'étape consistant à graver à sec la partie exposée du cuivre et l'étape consistant à exposer la partie exposée du cuivre à un rayonnement UV.
PCT/US2018/037396 2017-06-22 2018-06-13 Gravure au plasma pour la formation de motifs en cuivre WO2018236651A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880041196.5A CN110770881B (zh) 2017-06-22 2018-06-13 用于铜的图案化的等离子体蚀刻
KR1020207000988A KR102355416B1 (ko) 2017-06-22 2018-06-13 구리 패터닝을 위한 플라즈마 에칭

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762523443P 2017-06-22 2017-06-22
US62/523,443 2017-06-22

Publications (1)

Publication Number Publication Date
WO2018236651A1 true WO2018236651A1 (fr) 2018-12-27

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PCT/US2018/037396 WO2018236651A1 (fr) 2017-06-22 2018-06-13 Gravure au plasma pour la formation de motifs en cuivre

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KR (1) KR102355416B1 (fr)
CN (1) CN110770881B (fr)
TW (1) TWI834614B (fr)
WO (1) WO2018236651A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022256515A1 (fr) * 2021-06-04 2022-12-08 Tokyo Electron Limited Gravure de métal pendant le traitement d'une structure semi-conductrice

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339029B1 (en) * 2000-01-19 2002-01-15 Taiwan Semiconductor Manufacturing Company Method to form copper interconnects
US20020048952A1 (en) * 1999-05-25 2002-04-25 Tesauro Mark Richard Hard Mask for copper plasma etch
US20030098292A1 (en) * 2001-10-31 2003-05-29 Nagraj Kulkarni Process for low temperature, dry etching, and dry planarization of copper
US20170011887A1 (en) * 2013-03-13 2017-01-12 Applied Materials, Inc. Uv-assisted reactive ion etch for copper
WO2017075162A1 (fr) * 2015-10-27 2017-05-04 Applied Materials, Inc. Procédés de réduction du surplomb de cuivre dans un élément d'un substrat

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414950B1 (ko) * 1996-12-28 2004-03-24 주식회사 하이닉스반도체 반도체소자의구리배선형성방법
US8202783B2 (en) * 2009-09-29 2012-06-19 International Business Machines Corporation Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication
US8652940B2 (en) * 2012-04-10 2014-02-18 Applied Materials, Inc. Wafer dicing used hybrid multi-step laser scribing process with plasma etch
US9290848B2 (en) * 2014-06-30 2016-03-22 Tokyo Electron Limited Anisotropic etch of copper using passivation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020048952A1 (en) * 1999-05-25 2002-04-25 Tesauro Mark Richard Hard Mask for copper plasma etch
US6339029B1 (en) * 2000-01-19 2002-01-15 Taiwan Semiconductor Manufacturing Company Method to form copper interconnects
US20030098292A1 (en) * 2001-10-31 2003-05-29 Nagraj Kulkarni Process for low temperature, dry etching, and dry planarization of copper
US20170011887A1 (en) * 2013-03-13 2017-01-12 Applied Materials, Inc. Uv-assisted reactive ion etch for copper
WO2017075162A1 (fr) * 2015-10-27 2017-05-04 Applied Materials, Inc. Procédés de réduction du surplomb de cuivre dans un élément d'un substrat

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022256515A1 (fr) * 2021-06-04 2022-12-08 Tokyo Electron Limited Gravure de métal pendant le traitement d'une structure semi-conductrice

Also Published As

Publication number Publication date
CN110770881A (zh) 2020-02-07
KR20200008030A (ko) 2020-01-22
TW201921492A (zh) 2019-06-01
CN110770881B (zh) 2023-09-26
KR102355416B1 (ko) 2022-01-24
TWI834614B (zh) 2024-03-11

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