WO2018233555A1 - 偏磁抑制方法及装置 - Google Patents

偏磁抑制方法及装置 Download PDF

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Publication number
WO2018233555A1
WO2018233555A1 PCT/CN2018/091429 CN2018091429W WO2018233555A1 WO 2018233555 A1 WO2018233555 A1 WO 2018233555A1 CN 2018091429 W CN2018091429 W CN 2018091429W WO 2018233555 A1 WO2018233555 A1 WO 2018233555A1
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Prior art keywords
compensation amount
converter
bridge circuit
main
transformer
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PCT/CN2018/091429
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English (en)
French (fr)
Inventor
胡永辉
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中兴通讯股份有限公司
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Publication of WO2018233555A1 publication Critical patent/WO2018233555A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer

Definitions

  • the present disclosure relates to, but is not limited to, the field of power electronics, and in particular, a method and apparatus for suppressing bias.
  • the isolated BUCK-BOOST (buck-boost) circuit shown in Figure 1 has a wider input voltage range than the BUCK (buck) + full-bridge circuit. Or the BOOST + full-bridge circuit maintains high efficiency over the entire input voltage range.
  • long-term operation may cause the transformer to be biased in the circuit as shown in Fig. 1, as shown in Fig. 2a. , 2b, 2c are shown.
  • Eliminating the transformer bias can be done by adding a DC blocking capacitor to the topology of the circuit. As shown in Figure 3, the DC blocking capacitor is placed in series with the transformer winding to block the DC component.
  • Embodiments of the present disclosure provide a method and apparatus for suppressing a bias to avoid eliminating a bias phenomenon of a transformer in a circuit by adding a DC blocking capacitor in a circuit of the converter, resulting in high circuit complexity and large volume of the converter. High cost.
  • Embodiments of the present disclosure provide a bias suppression method including: detecting a voltage value U1 of a resistor R1 for detecting a secondary full-bridge circuit current in a converter and a voltage of a resistor R2 for detecting a secondary full-bridge circuit current Value U2; suppressing the bias of the transformer in the converter according to the U1 and the U2.
  • suppressing the bias of the transformer in the converter according to the U1 and the U2 includes: acquiring a main edge of the converter according to the U1 and the U2 The amount of compensation required for the duty cycle signal of each of the switching tubes of the full bridge circuit; superimposing the obtained compensation amount of each of the switching tubes with the corresponding duty ratio information of each of the switching tubes The way to suppress the bias of the transformer in the converter.
  • acquiring a compensation amount required for a duty cycle signal of each of the main-bridge full-bridge circuits in the converter includes: acquiring the U1 And a voltage difference of the U2; obtaining a first compensation amount according to the voltage difference; and obtaining, by determining the first compensation amount, each switch of the main-side full-bridge circuit in the converter The amount of compensation required for the duty cycle signal.
  • acquiring the first compensation amount according to the voltage difference value comprises: acquiring the first compensation amount by performing filtering processing on the voltage difference value; or The voltage difference is subjected to a clipping process to obtain the first compensation amount.
  • the compensation amount required to acquire the duty cycle signal of each of the main-bridge full-bridge circuits in the converter by determining the first compensation amount includes: When the first compensation amount is greater than zero, the compensation amount of the transformer forward excitation direction switching tubes Q1 and Q4 of the main-side full-bridge circuit is the first compensation amount, and the main-side full-bridge circuit transformer The compensation amount of the negative excitation direction switching tubes Q2 and Q3 is zero; in the case where the first compensation amount is less than zero, the compensation amount of the switching tubes Q1 and Q4 of the main side full bridge circuit is zero, the main The compensation amount of the switching tubes Q2 and Q3 of the full-bridge circuit is the absolute value of the first compensation amount.
  • the embodiment of the present disclosure further provides a bias suppression device, comprising: a detection module configured to: detect a voltage value U1 of a resistor R1 for detecting a secondary full-bridge circuit current in the converter, and detect a secondary bridge of the secondary side The voltage value U2 of the resistor R2 of the circuit current; the suppression module is configured to suppress the bias of the transformer in the converter according to the U1 and the U2.
  • the suppression module is further configured to: acquire, according to the U1 and the U2, a duty signal required for each duty cycle of each of the main-bridge full-bridge circuits in the converter a compensation amount; and suppressing a bias of the transformer in the converter by superimposing the obtained compensation amount of each of the switching tubes with the duty ratio information of the respective switching tubes.
  • the suppression module is further configured to: acquire a voltage difference between the U1 and the U2; acquire a first compensation amount according to the voltage difference; and pass the first compensation The quantity is judged in such a manner as to obtain the compensation amount required for the duty cycle signal of each of the main-bridge full-bridge circuits in the converter.
  • the suppression module is further configured to: acquire the first compensation amount by filtering the voltage difference; or, by limiting the voltage difference In the manner of processing, the first compensation amount is obtained.
  • the suppression module is further configured to: compensate the transformer forward excitation direction switch tubes Q1, Q4 of the main-side full-bridge circuit in a case where the first compensation amount is greater than zero
  • the amount of compensation is the first compensation amount, and the compensation amount of the transformer negative-direction excitation direction switching tubes Q2 and Q3 of the main-side full-bridge circuit is zero; if the first compensation amount is less than zero, the main side is The compensation amount of the switching tubes Q1 and Q4 of the full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
  • the embodiment of the present disclosure further provides a storage medium, the storage medium comprising a stored program, wherein the program is executed to perform the method of any of the above.
  • An embodiment of the present disclosure further provides a processor configured to execute a program, wherein the program is executed to perform the method of any of the above.
  • the embodiment of the present disclosure further provides a computer readable storage medium storing computer executable instructions that implement the above-described bias suppression method when the computer executable instructions are executed.
  • the voltage value U1 of the resistor R1 for detecting the secondary full-bridge circuit current in the converter and the voltage value U2 of the resistor R2 for detecting the secondary full-bridge circuit current are detected; according to U1 and U2,
  • the bias of the transformer in the converter is suppressed.
  • the voltage value U1 of the resistor R1 for detecting the secondary full-bridge circuit current in the original circuit of the transformer and the voltage value U2 of the resistor R2 for detecting the secondary full-bridge circuit current in the original circuit of the transformer can be realized in the converter.
  • the biasing of the transformer is suppressed, so that the biasing of the transformer can be effectively suppressed without adding any additional components.
  • FIG. 1 is a schematic diagram of an isolated BUCK-BOOST circuit in the related art
  • FIG. 2a is a schematic diagram of the entire process of transformer biasing in the related art
  • 2b is a schematic diagram showing a gradual process of initial biasing of a transformer excitation current in the related art
  • 2c is a schematic diagram of a transformer biasing stability in the related art
  • FIG. 3 is a schematic diagram of an isolated BUCK-BOOST circuit with a DC blocking capacitor added in the related art
  • 4a is a schematic diagram showing the waveforms of the voltage U1 of the detecting resistor R1 and the voltage U2 of the resistor R2 when the transformer is not biased in the related art;
  • 4b is a schematic diagram showing the waveform of the voltage U1 of the detecting resistor R1 and the voltage U2 of the resistor R2 when the transformer is biased in the related art;
  • FIG. 5 is a block diagram showing a hardware structure of a mobile terminal of a method for suppressing a bias magnetic field according to an embodiment of the present disclosure
  • FIG. 6 is a flow chart of a method of bias suppression according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic flow chart of a method for suppressing a bias voltage of an isolated BUCK-BOOST circuit according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of an isolated BUCK-BOOST circuit biasing suppression device according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram showing the connection of an isolated BUCK-BOOST circuit bias suppression device and a BUCK-BOOST circuit according to an embodiment of the present disclosure
  • FIG. 10 is a schematic diagram of a transformer excitation current of an isolated BUCK-BOOST circuit according to an embodiment of the present disclosure
  • FIG. 11 is a block diagram showing the structure of a bias magnetization suppressing apparatus according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of an isolated BUCK-BOOST circuit in the related art.
  • the detailed embodiment of the circuit may be a metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) with Vin being an input voltage source and Q1, Q2, Q3, Q4, Q5, and Q6 being 100V.
  • MOSFET Metal-oxide semiconductor field effect transistor
  • L1 is 3uH
  • transformer T1 turns ratio is 4:1
  • SR1, SR2, SR3, SR4 are 25V synchronous rectifier
  • current sampling resistor R1, R2 is 0.5mR
  • Vout is the output voltage.
  • FIG. 2b is a schematic diagram of a gradual process of initial biasing of the excitation current of the transformer in the related art, and the excitation current of the transformer is unidirectionally biased from 0.
  • Fig. 2c is a schematic diagram of the transformer biasing stability in the related art. As shown in Fig. 2c, the transformer biasing is finally stabilized at a transformer excitation current swing of 10-12A.
  • FIG. 3 is a schematic diagram of an isolated BUCK-BOOST circuit with a DC blocking capacitor added in the related art.
  • the circuit has a DC blocking capacitor C1 added to the circuit shown in FIG. 1, and the bias voltage suppression using the DC blocking capacitor C1 is a well-known technique, and will not be described in detail herein.
  • this scheme is simple, the addition of a DC blocking capacitor increases the complexity of the circuit, and in the case of a large current, the selection of the DC blocking capacitor is very difficult, and the size and cost of the converter are increased.
  • FIG. 4a and FIG. 4b and 4b are schematic diagrams of the voltage U1 of the isolated BUCK-BOOST circuit current detecting resistor R1 and the voltage U2 of the resistor R2 based on the related art of FIG. 4a is a waveform diagram of the voltage U1 of the detecting resistor R1 and the voltage U2 of the resistor R2 when the transformer is not biased in the related art.
  • FIG. 4a is a waveform diagram of the voltage U1 of the detecting resistor R1 and the voltage U2 of the resistor R2 when the transformer is not biased in the related art.
  • FIG. 4a the voltages U1 and U2 have the same amplitude, both being -75 mV;
  • FIG. 4b is related
  • the voltage U1 of the resistor R1 and the voltage U2 of the resistor R2 are waveform diagrams.
  • the voltages U1 and U2 have different amplitudes, U1 is about -60 mV, and U2 is about -90 mV.
  • FIG. 5 is a hardware structural block diagram of a mobile terminal of a bias suppression method according to an embodiment of the present disclosure.
  • mobile terminal 50 may include one or more (only one shown) processor 502 (processor 502 may include, but is not limited to, a Micro Controller Unit (MCU) or A processing device such as a programmable logic device FPGA (Field Programmable Gate Array), a memory 504 provided to store data, and a transmission device 506 provided as a communication function.
  • MCU Micro Controller Unit
  • FPGA Field Programmable Gate Array
  • memory 504 provided to store data
  • a transmission device 506 provided as a communication function.
  • FIG. 5 is merely illustrative, and the schematic structure does not limit the structure of the above electronic device.
  • mobile terminal 50 may also include more or fewer components than shown in FIG. 5, or have a different configuration than that shown in FIG.
  • the memory 504 can be configured as: a software program and a module for storing application software, such as a program instruction/module corresponding to the bias suppression method in the embodiment of the present disclosure, the processor 502 running the software program and the module stored in the memory 504, thereby The above methods are implemented by performing various functional applications and data processing.
  • Memory 504 can include high speed random access memory and can also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory.
  • memory 504 can also include memory remotely located relative to processor 502, which can be connected to mobile terminal 50 over a network. Examples of such networks may include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • Transmission device 506 can be configured to receive or transmit data via a network.
  • the network optional examples described above may include a wireless network provided by a communication provider of the mobile terminal 50.
  • transmission device 506 can include a Network Interface Controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet.
  • NIC Network Interface Controller
  • the transmission device 506 can be a radio frequency (RF) module configured to communicate with the Internet wirelessly.
  • RF radio frequency
  • FIG. 6 is a flowchart of a method for suppressing the biasing according to an embodiment of the present disclosure. As shown in FIG. 6, the flow may include the following steps:
  • Step S602 detecting a voltage value U1 of the resistor R1 for detecting the secondary full-bridge circuit current in the converter and a voltage value U2 of the resistor R2 for detecting the secondary full-bridge circuit current;
  • Step S604 according to U1 and U2, suppressing the bias of the transformer in the converter
  • the transformation can be realized.
  • the biasing of the transformer in the device is suppressed, so that the biasing of the transformer can be effectively suppressed without adding any accessory components. Therefore, it is possible to avoid the transformer bias in the circuit by adding a DC blocking capacitor in the circuit of the converter.
  • the phenomenon mode leads to high complexity of the circuit and large volume and high cost of the converter, which reduces the complexity of the circuit and reduces the volume and cost of the converter.
  • suppressing the bias of the transformer in the converter according to U1 and U2 comprises: obtaining compensation required for the duty cycle signal of each of the main-bridge full-bridge circuits in the converter according to U1 and U2 The amount of bias of the transformer in the converter is suppressed by superimposing the obtained compensation amount of each switch tube with the corresponding duty ratio information of each switch tube.
  • obtaining a compensation amount required for a duty cycle signal of each of the main-bridge full-bridge circuits in the converter includes: obtaining a voltage difference between U1 and U2; acquiring according to the voltage difference The first compensation amount; the compensation amount required for the duty signal of each of the main-bridge full-bridge circuits in the converter is obtained by judging the first compensation amount.
  • the acquiring the first compensation amount according to the voltage difference includes: obtaining a first compensation amount by performing a filtering process on the voltage difference; or acquiring the first by performing a limiting process on the voltage difference The amount of compensation.
  • the compensation amount required to obtain the duty cycle signal of each of the main-bridge full-bridge circuits in the converter by determining the first compensation amount includes: when the first compensation amount is greater than zero
  • the compensation amount of the forward-direction excitation direction switch tubes Q1 and Q4 of the main-side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative-direction excitation direction switch tubes Q2 and Q3 of the main-side full-bridge circuit is zero;
  • the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
  • isolation BUCK-BOOST circuit is taken as an example for description.
  • This embodiment proposes a method for effectively suppressing the bias of the isolated BUCK-BOOST circuit transformer without adding additional components and without increasing the volume of the converter.
  • FIG. 7 is a flow chart showing a method of suppressing a bias of a BUCK-BOOST circuit according to an embodiment of the present disclosure. As shown in FIG. 7, the process may include the following steps:
  • Step 1 The voltage value U1 of the resistor R1 for detecting the current of the transformer full-bridge circuit in the sampling converter and the voltage value U2 of the resistor R2 for detecting the current of the transformer full-bridge circuit.
  • the second step calculating the voltage difference ⁇ U between R1 and R2, and processing the voltage difference ⁇ U to obtain a compensation amount ⁇ d (corresponding to the first compensation amount described above).
  • the processing includes filtering the voltage difference ⁇ U or performing a limiting process on the voltage difference ⁇ U.
  • the filtering includes averaging the ⁇ U calculated multiple times; the clipping process includes a ⁇ U maximum or minimum limit, for example, selecting a ⁇ U maximum or minimum calculated multiple times.
  • the third step logically judge according to the obtained compensation amount ⁇ d, and determine the compensation amount required for each switch tube duty ratio signal in the full-bridge circuit of the transformer main side.
  • ⁇ d is greater than 0, the compensation amount of D(Q1, Q4) is ⁇ d, the compensation amount of D2 (Q2, Q3) is 0; when ⁇ d is less than 0, the compensation amount of D1 is 0, and the compensation amount of D2 is ⁇ d. Absolute value.
  • the fourth step superimposing the obtained compensation amount and the duty signal of the corresponding switch tube to suppress the DC bias of the transformer.
  • D1 (Q1, Q4) D (Q1, Q4) + ⁇ d
  • D (Q2, Q3) D (Q2, Q3) + 0.
  • the device may include: a voltage acquisition unit; a calculation unit; a logic processing unit; and a bias suppression unit.
  • the voltage obtaining unit is configured to acquire a voltage U1 of a resistor R1 for detecting a secondary full-bridge circuit current in the converter, and a voltage U2 of the resistor R2 for detecting a secondary full-bridge circuit current in the converter.
  • the processing may include filtering the voltage difference ⁇ U or performing a clipping process on the voltage difference ⁇ U.
  • the filtering includes averaging the ⁇ U calculated multiple times; the clipping process may include a ⁇ U maximum or minimum limit, for example, selecting a ⁇ U maximum or minimum calculated multiple times.
  • the above logic processing unit is configured to determine a compensation amount required for each switch tube duty cycle signal in the main side full bridge circuit.
  • the compensation amount of D(Q1, Q4) may be ⁇ d
  • the compensation amount of D2 (Q2, Q3) is 0 (denoted as ⁇ d/0 in Fig. 8);
  • the compensation of D1 The amount can be 0, and the compensation amount of D2 is the absolute value of ⁇ d (shown as 0/
  • the above-mentioned bias suppression unit is arranged to superimpose the compensation amount and each switch tube loop output duty signal D in the main-side full-bridge circuit to suppress the DC bias of the transformer.
  • FIG. 9 is a schematic diagram showing the connection of an isolated BUCK-BOOST circuit bias suppression device and a BUCK-BOOST circuit in accordance with an embodiment of the present disclosure.
  • the main power circuit can adopt the circuit shown in FIG. 1.
  • the circuit device parameters shown in FIG. 1 have been described above and are not repeated; the bias magnetic suppression device shown in FIG. 9 can be used as shown in FIG.
  • the magnetic bias suppression device shown in FIG. 8 has been described above and will not be described again.
  • the input of the voltage sampling unit can be the sampling voltages U1 and U2 of R1 and R2.
  • FIG. 10 is a schematic diagram of a transformer excitation current of an isolated BUCK-BOOST circuit in accordance with an embodiment of the present disclosure.
  • the switching speed difference between the switch tubes Q1, Q2, Q3 and Q4 is 80 ns.
  • the excitation current of the transformer is symmetrical based on the positive and negative amplitudes of 0 points, and the amplitude is plus or minus 1A, compared with Fig. 2a, 2b, 2c
  • the excitation current of the transformer is between 10-12 A, and the transformer excitation current is effectively suppressed by the method of the present disclosure.
  • the above technical solution provided by the present disclosure avoids the case where the BUCK-BOOST circuit known in the art is biased for a long time, and does not need to add any device, and does not bring volume and cost. Increase.
  • the optical disc includes a plurality of instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method described in the embodiments of the present disclosure.
  • a terminal device which may be a mobile phone, a computer, a server, or a network device, etc.
  • a biasing suppression device is further provided, which is configured to implement the above-mentioned embodiments and optional embodiments, and has not been described again.
  • the term “module” may implement software of a predetermined function, or hardware, or a combination of software and hardware.
  • the devices described in the following embodiments may be implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • the apparatus may include:
  • the detecting module 112 (corresponding to the voltage acquiring unit described above) is configured to: detect a voltage value U1 of the resistor R1 for detecting a secondary full-bridge circuit current in the converter, and a voltage of the resistor R2 for detecting a secondary full-bridge circuit current Value U2;
  • the suppression module 114 is configured to be connected to the detection module 112 to suppress the bias of the transformer in the converter according to U1 and U2.
  • the suppression module 114 is further configured to: obtain, according to U1 and U2, a compensation amount required for a duty cycle signal of each switch tube of the main-side full-bridge circuit in the converter; and pass each of the acquired switch tubes The amount of compensation is superimposed with the corresponding duty ratio information of each of the switching tubes to suppress the bias of the transformer in the converter.
  • the suppression module 114 is further configured to: obtain a voltage difference between U1 and U2; obtain a first compensation amount according to the voltage difference; and obtain a main-side full-bridge circuit in the converter by determining the first compensation amount The amount of compensation required for the duty cycle signal of each switch.
  • the suppression module 114 is further configured to: obtain a first compensation amount by performing a filtering process on the voltage difference; or obtain a first compensation amount by performing a limiting process on the voltage difference.
  • the suppression module 114 is further configured to: when the first compensation amount is greater than zero, the compensation amount of the transformer forward excitation direction switching tubes Q1 and Q4 of the main-side full-bridge circuit is the first compensation amount, and the main side is full In the bridge circuit, the compensation amount of the negative excitation direction switching tubes Q2 and Q3 is zero; when the first compensation amount is less than zero, the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the main side is full.
  • the compensation amount of the switching transistors Q2 and Q3 of the bridge circuit is the absolute value of the first compensation amount.
  • modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the above modules are all located in the same processor; or the above modules are in any combination. They are located in different processors.
  • Embodiments of the present disclosure also provide a storage medium including a stored program, wherein the program described above executes the method of any of the above.
  • the foregoing storage medium may be configured to store program code for performing the following steps:
  • the storage medium is further arranged to store program code for performing the steps of: suppressing the biasing of the transformer in the converter according to U1 and U2 comprises:
  • the storage medium is further arranged to store program code for performing the following steps: according to U1 and U2, the compensation amount required to acquire the duty cycle signal of each of the main-bridge full-bridge circuits in the converter includes :
  • the storage medium is further configured to store program code for performing the following steps: obtaining a duty cycle signal of each of the main-bridge full-bridge circuits in the converter by determining the first compensation amount
  • the amount of compensation required includes:
  • the compensation amount of the transformer positive excitation direction switching tubes Q1, Q4 of the main-side full-bridge circuit is the first compensation amount, and the transformer negative-direction excitation direction switch of the main-side full-bridge circuit
  • the compensation amount of the tubes Q2 and Q3 is zero;
  • the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the first compensation amount. Absolute value.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), and a Random Access Memory (RAM).
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • Embodiments of the present disclosure also provide a processor configured to execute a program, wherein the program, when executed, performs the steps of any of the above methods.
  • the foregoing program is used to perform the following steps:
  • the foregoing program is used to perform the following steps:
  • the foregoing program is configured to perform the following steps: suppressing the bias of the transformer in the converter according to U1 and U2 includes:
  • the foregoing program is configured to perform the following steps: according to U1 and U2, obtaining a compensation amount required for a duty cycle signal of each of the main-bridge full-bridge circuits in the converter includes:
  • acquiring the first compensation amount according to the voltage difference value includes:
  • the foregoing program is configured to perform the following steps: acquiring, by determining the first compensation amount, a duty signal required for each switch tube of the main-side full-bridge circuit in the converter
  • the amount of compensation includes:
  • the compensation amount of the transformer positive excitation direction switching tubes Q1, Q4 of the main-side full-bridge circuit is the first compensation amount, and the transformer negative-direction excitation direction switch of the main-side full-bridge circuit
  • the compensation amount of the tubes Q2 and Q3 is zero;
  • the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the first compensation amount. Absolute value.
  • the embodiment of the present disclosure further provides a computer readable storage medium storing computer executable instructions that implement the above-described bias suppression method when the computer executable instructions are executed.
  • modules or steps of the present disclosure may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices, optionally They may be implemented by program code executable by the computing device such that they may be stored in the storage device for execution by the computing device and, in some cases, may be performed in a different order than that illustrated herein. Or the steps described, either as separate circuit modules, or as a single integrated circuit module. As such, the disclosure is not limited to any specific combination of hardware and software.
  • the term computer storage medium includes volatile and nonvolatile, implemented in any method or technology for storing information, such as computer readable instructions, data structures, program modules or other data. Sex, removable and non-removable media.
  • the computer storage medium includes, but is not limited to, Random Access Memory (RAM), Read-Only Memory (ROM), and Electrically Erasable Programmable Read-only Memory (EEPROM). Flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or Any other medium used to store the desired information and that can be accessed by the computer.
  • communication media typically includes computer readable instructions, data structures, program modules or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and can include any information delivery media. .
  • the voltage value U1 of the resistor R1 for detecting the secondary full-bridge circuit current in the converter and the voltage value U2 of the resistor R2 for detecting the secondary full-bridge circuit current are detected; according to U1 and U2,
  • the bias of the transformer in the converter is suppressed.
  • the voltage value U1 of the resistor R1 for detecting the secondary full-bridge circuit current in the original circuit of the transformer and the voltage value U2 of the resistor R2 for detecting the secondary full-bridge circuit current in the original circuit of the transformer can be realized in the converter.
  • the biasing of the transformer is suppressed, so that the biasing of the transformer can be effectively suppressed without adding any additional components.

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Abstract

一种偏磁抑制方法包括：检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；根据U1和U2，对变换器中的变压器的偏磁进行抑制。

Description

偏磁抑制方法及装置 技术领域
本公开涉及但不限于电力电子技术领域，尤其是一种偏磁抑制方法及装置。
背景技术
在电力电子技术领域，特别是直流/直流变换器，如图1所示的隔离型BUCK-BOOST(升降压)电路在较宽的输入电压范围内相比BUCK(降压)+全桥电路或者BOOST(升压)+全桥电路在整个输入电压范围内都能维持较高的效率。但是，在实际应用时由于开关管开关速度差异、驱动信号延迟的差异，驱动信号脉冲宽度的差异等原因，长时间工作会造成如图1所述的电路中变压器出现偏磁现象，如图2a、2b、2c所示。
消除变压器偏磁可以有如下方式：在电路的拓扑结构中加入隔直电容，如图3所示，将隔直电容与变压器绕组串联，来阻断直流分量。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
隔直电容的加入增加了电路的复杂程度，而且大电流场合隔直电容的选取非常困难，同时增加了变换器的体积和成本。
因此，通过在变换器的电路中加入隔直电容来消除电路中变压器偏磁现象方式，导致电路的复杂度增高以及变换器的体积增大、成本增高。
本公开实施例提供了一种偏磁抑制方法及装置，以避免通过在变换器的电路中加入隔直电容来消除电路中变压器偏磁现象方式，导致电路的复杂度高以及变换器的体积大、成本高的情况。
本公开实施例提供了一种偏磁抑制方法，包括：检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电 阻R2的电压值U2；根据所述U1和所述U2，对所述变换器中的变压器的偏磁进行抑制。
在一种示例性实施方式中，根据所述U1和所述U2，对所述变换器中的变压器的偏磁进行抑制包括：根据所述U1和所述U2，获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；通过将获取的所述每个开关管的所述补偿量与相应的所述每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
在一种示例性实施方式中，根据所述U1和所述U2，获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：获取所述U1和所述U2的电压差值；根据所述电压差值，获取第一补偿量；通过对所述第一补偿量进行判断的方式获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
在一种示例性实施方式中，根据所述电压差值，获取第一补偿量包括：通过对所述电压差值进行滤波处理的方式，获取所述第一补偿量；或者，通过对所述电压差值进行限幅处理的方式，获取所述第一补偿量。
在一种示例性实施方式中，通过对所述第一补偿量进行判断的方式获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：在所述第一补偿量大于零的情况下，所述主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为所述第一补偿量，所述主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；在所述第一补偿量小于零的情况下，所述主边全桥电路的开关管Q1、Q4的补偿量为零，所述主边全桥电路的开关管Q2、Q3的补偿量为所述第一补偿量的绝对值。
本公开实施例还提供了一种偏磁抑制装置，包括：检测模块，设置为：检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；抑制模块，设置为：根据所述U1和所述U2，对所述变换器中的变压器的偏磁进行抑制。
在一种示例性实施方式中，所述抑制模块还设置为：根据所述U1和所述U2，获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；以及通过将获取的所述每个开关管的所述补偿量与相应的所述每个开 关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
在一种示例性实施方式中，所述抑制模块还设置为：获取所述U1和所述U2的电压差值；根据所述电压差值，获取第一补偿量；通过对所述第一补偿量进行判断的方式获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
在一种示例性实施方式中，所述抑制模块还设置为：通过对所述电压差值进行滤波处理的方式，获取所述第一补偿量；或者，通过对所述电压差值进行限幅处理的方式，获取所述第一补偿量。
在一种示例性实施方式中，所述抑制模块还设置为：在所述第一补偿量大于零的情况下，所述主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为所述第一补偿量，所述主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；在所述第一补偿量小于零的情况下，所述主边全桥电路的开关管Q1、Q4的补偿量为零，所述主边全桥电路的开关管Q2、Q3的补偿量为所述第一补偿量的绝对值。
本公开实施例还提供了一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述任一项所述的方法。
本公开实施例还提供了一种处理器，所述处理器设置为运行程序，其中，所述程序运行时执行上述任一项所述的方法。
本公开实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现上述偏磁抑制方法。
通过本公开实施例，检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；根据U1和U2，对变换器中的变压器的偏磁进行抑制。由于根据变压器原有电路中检测副边全桥电路电流的电阻R1的电压值U1和变压器原有电路中检测副边全桥电路电流的电阻R2的电压值U2，即可实现对变换器中的变压器的偏磁进行抑制，使得无需添加任何附加的元件，就可有效地抑制变压器的偏磁，因此，可以避免通过在变换器的电路中加入隔直电容来消除电路中变压器偏磁现象方式，导致电路的复杂度高以及变换器的体积大、成本高的情况，达到降低电路复杂度，减小变换器体积和成本效果。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1是相关技术中一种隔离BUCK-BOOST电路示意图；
图2a是相关技术中变压器偏磁的整个过程示意图；
图2b是相关技术中变压器励磁电流初始偏磁的渐变过程示意图；
图2c是相关技术中变压器偏磁稳定示意图；
图3是相关技术中增加了隔直电容的隔离BUCK-BOOST电路示意图；
图4a是相关技术中变压器无偏磁时检测电阻R1的电压U1、电阻R2的电压U2的波形示意图；
图4b是相关技术中变压器有偏磁时检测电阻R1的电压U1、电阻R2的电压U2的波形示意图；
图5是本公开实施例的一种偏磁抑制方法的移动终端的硬件结构框图；
图6是根据本公开实施例的偏磁抑制方法的流程图；
图7是根据本公开实施例的一种隔离BUCK-BOOST电路偏磁抑制方法的流程示意图；
图8是本公开实施例的一种隔离BUCK-BOOST电路偏磁抑制装置的结构示意图；
图9是根据本公开实施例的隔离BUCK-BOOST电路偏磁抑制装置与BUCK-BOOST电路连接示意图；
图10是根据本公开实施例的一种隔离BUCK-BOOST电路变压器励磁电流示意图；
图11是根据本公开实施例的偏磁抑制装置的结构框图。
本公开的较佳实施方式
下面结合附图对本公开的实施方式进行描述。
可以说明的是，本文中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
图1是相关技术中一种隔离BUCK-BOOST电路示意图。如图1所示，电路详细实施例可以为Vin为输入电压源，Q1、Q2、Q3、Q4、Q5、Q6为100V的金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)，L1为3uH，变压器T1匝比为4:1，SR1、SR2、SR3、SR4为25V同步整流管，电流采样电阻R1、R2为0.5mR，Vout为输出电压。在实际应用时由于开关管Q1、Q2、Q3、Q4开关速度差异、驱动信号延迟的差异，驱动信号脉冲宽度的差异等原因，长时间工作可造成如图1所示的电路中变压器T1出现偏磁现象。当开关管Q1、Q2、Q3、Q4开关速度差异为80ns时，变压器T1的励磁电流如图2a、2b、2c所示。参考图2a、2b、2c可知，变压器励磁电流单向偏磁。图2a是相关技术中变压器偏磁的整个过程示意图，如图2a所示，变压器励磁电流从0逐渐上升到最大幅值12A。图2b是相关技术中变压器励磁电流初始偏磁的渐变过程示意图，变压器励磁电流从0开始单方向偏磁。图2c是相关技术中变压器偏磁稳定示意图，如图2c所示，变压器偏磁最终稳定在变压器励磁电流摆幅在10-12A摆动。
图3是相关技术中增加了隔直电容的隔离BUCK-BOOST电路示意图。如图3所示，电路在如图1所示的电路基础上增加了隔直电容C1，利用隔直电容C1实现偏磁抑制为公知技术，在这里就不做详细描述。这种方案虽然简单，但是，隔直电容的加入增加了电路的复杂程度，而且大电流场合，隔直电容的选取非常困难，同时增加了变换器的体积和成本。
相关技术中隔直电容的隔离BUCK-BOOST电路中用于检测副边全桥电路电流的电阻R1的电压U1、用于检测副边全桥电路电流的电阻R2的电压U2，如图4a和图4b所示，图4a和图4b是基于图1相关技术的一种隔离BUCK-BOOST电路电流检测电阻R1的电压U1、电阻R2的电压U2的示意图。图4a是相关技术中变压器无偏磁时检测电阻R1的电压U1、电阻R2的电压U2的波形示意图，如图4a所示，电压U1以及U2幅值相同，都为-75mV；图4b是相关技术中变压器有偏磁时检测电阻R1的电压U1、电阻R2的电压U2的波形示意图，如图4b所示，电压U1以及U2幅值不同，U1约为-60mV，U2约为-90mV。从图4a和图4b的对比可知，如果根据U1以及U2的检测 值判断并调整使U1＝U2，则变压器可以无偏磁。
第一实施例
本公开实施例所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。以运行在移动终端上为例，图5是本公开实施例的一种偏磁抑制方法的移动终端的硬件结构框图。如图5所示，移动终端50可以包括一个或多个(图中仅示出一个)处理器502(处理器502可以包括但不限于微处理器MCU(Micro Controller Unit，微控制器单元)或可编程逻辑器件FPGA(Field Programmable Gate Array，现场可编程门阵列)等的处理装置)、设置为存储数据的存储器504、以及设置为通信功能的传输装置506。本领域普通技术人员可以理解，图5所示的结构仅为示意，该示意的结构并不对上述电子装置的结构造成限定。例如，移动终端50还可包括比图5中所示更多或者更少的组件，或者具有与图5所示不同的配置。
存储器504可设置为：存储应用软件的软件程序以及模块，如本公开实施例中的偏磁抑制方法对应的程序指令/模块，处理器502通过运行存储在存储器504内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器504可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器504还可包括相对于处理器502远程设置的存储器，这些远程存储器可以通过网络连接至移动终端50。上述网络的实例可包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置506可设置为：经由一个网络接收或者发送数据。上述的网络可选实例可包括移动终端50的通信供应商提供的无线网络。在一个实例中，传输装置506可包括一个网络适配器(Network Interface Controller，NIC)，该网络适配器可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置506可以为射频(Radio Frequency，RF)模块，该RF模块设置为：通过无线方式与互联网进行通讯。
在本实施例中提供了一种运行于上述移动终端的偏磁抑制方法，图6是根据本公开实施例的偏磁抑制方法的流程图，如图6所示，该流程可包括如下步骤：
步骤S602，检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；
步骤S604，根据U1和U2，对变换器中的变压器的偏磁进行抑制；
通过上述步骤，根据变压器原有电路中检测副边全桥电路电流的电阻R1的电压值U1和变压器原有电路中检测副边全桥电路电流的电阻R2的电压值U2，即可实现对变换器中的变压器的偏磁进行抑制，使得无需添加任何附件的元件，就可有效的抑制变压器的偏磁，因此，可以避免通过在变换器的电路中加入隔直电容来消除电路中变压器偏磁现象方式，导致电路的复杂度高以及变换器的体积大、成本高的情况，达到降低电路复杂度，减小变换器体积和成本效果。
可选地，根据U1和U2，对变换器中的变压器的偏磁进行抑制包括：根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；通过将获取的每个开关管的补偿量与相应的每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
可选地，根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：获取U1和U2的电压差值；根据电压差值，获取第一补偿量；通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
可选地，根据电压差值，获取第一补偿量包括：通过对电压差值进行滤波处理的方式，获取第一补偿量；或者，通过对电压差值进行限幅处理的方式，获取第一补偿量。
可选地，通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：在第一补偿量大于零的情况下，主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为第一补偿量，主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；在第一补偿量小于零的情况下，主边全桥电路的开关管Q1、Q4的补偿量为零，主边全桥电路的开关管Q2、Q3的补偿量为第一补偿量的绝对值。
为了方便理解上述实施例，以隔离BUCK-BOOST电路为例进行说明。
本实施例提出了在不添加附加元件和不增加变换器体积的情况下可以有效抑制隔离BUCK-BOOST电路变压器偏磁的方法。
图7是根据本公开实施例的一种隔离BUCK-BOOST电路偏磁抑制方法的流程示意图。如图7所示，该流程可包括如下步骤：
第一步：采样变换器中用于检测变压器副边全桥电路电流的电阻R1的电压值U1和用于检测变压器副边全桥电路电流的电阻R2的电压值U2。
第二步：计算R1和R2的电压差值ΔU，对电压差值ΔU进行处理获得补偿量Δd(相当于上述第一补偿量)。所述处理包括：将电压差值ΔU进行滤波或者将电压差值ΔU进行限幅处理。所述滤波包括将多次计算得到的ΔU进行平均值处理；所述限幅处理包括ΔU最大或最小值限制，例如，选择多次计算得到的ΔU最大值或者最小值。
第三步：根据得到的补偿量Δd进行逻辑判断，确定变压器主边全桥电路中每个开关管占空比信号所需要的补偿量。当Δd大于0时，D(Q1、Q4)的补偿量为Δd，D2(Q2、Q3)的补偿量为0；当Δd小于0时，D1的补偿量为0，D2的补偿量为Δd的绝对值。
第四步：将得到的补偿量和与相应的开关管的占空比信号叠加，以对变压器的直流偏磁进行抑制。例如，补偿后D1(Q1、Q4)＝D(Q1、Q4)+Δd，D(Q2、Q3)的补偿量为0，补偿后D2(Q2、Q3)＝D(Q2、Q3)+0。
图8是本公开实施例的一种隔离BUCK-BOOST电路偏磁抑制装置的结构示意图，如图8所示，该装置可包括：电压获取单元；计算单元；逻辑处理单元；偏磁抑制单元。
上述电压获取单元：设置为获取变换器中用于检测副边全桥电路电流的电阻R1的电压U1、变换器中用于检测副边全桥电路电流的电阻R2的电压U2。
上述计算单元：计算电阻R1和R2的电压差值ΔU，对电压差值ΔU进行处理获得补偿量Δd(图8中表示为Δd＝f(ΔU))。所述处理可包括：将电压差值ΔU进行滤波或者将电压差值ΔU进行限幅处理。所述滤波包括将多次计算得到的ΔU进行平均值处理；所述限幅处理可包括ΔU最大或最小值 限制，例如，选择多次计算得到的ΔU最大值或者最小值。
上述逻辑处理单元：设置为确定主边全桥电路中每个开关管占空比信号需要的补偿量。当Δd大于0时，D(Q1、Q4)的补偿量可为Δd，D2(Q2、Q3)的补偿量为0(图8中表示为Δd/0)；当Δd小于0时，D1的补偿量可为0，D2的补偿量为Δd的绝对值(图8中表示为0/|Δd|)。
上述偏磁抑制单元：设置为将补偿量和主边全桥电路中每个开关管环路输出占空比信号D叠加，以对变压器的直流偏磁进行抑制。
图9是根据本公开实施例的隔离BUCK-BOOST电路偏磁抑制装置与BUCK-BOOST电路连接示意图。如图9所示，主功率电路可采用如图1所示电路，图1所示电路器件参数前文已有描述，不再重复；如图9所示的偏磁抑制装置可采用如图8所示偏磁抑制装置，图8所示偏磁抑制装置前文已有描述，不再赘述。电压采样单元的输入可为R1以及R2的采样电压U1以及U2。
图10是根据本公开实施例的一种隔离BUCK-BOOST电路变压器励磁电流示意图。此时开关管Q1、Q2、Q3、Q4开关速度差异为80ns，如图10所述，变压器的励磁电流基于0点正负幅值对称，幅值为正负1A，相比图2a、2b、2c未采用本公开时变压器的励磁电流在10-12A之间，采用本公开方法后变压器励磁电流得到有效抑制。
综上所述，采用上述技术方案，本公开所提供的上述技术方案避免了本领域已知的BUCK-BOOST电路长时间工作偏磁的情况，且无需添加任何器件，不会带来体积和成本的增加。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，本公开的技术方案本质上或者说对本领域已知技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本公开实施例所述的方法。
第二实施例
在本实施例中还提供了一种偏磁抑制装置，该装置设置为实现上述实施例及可选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件、或硬件、或软件和硬件的组合。尽管以下实施例所描述的装置可以以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图11是根据本公开实施例的偏磁抑制装置的结构框图，如图11所示，该装置可包括：
检测模块112(相当于上述电压获取单元)，设置为：检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；
抑制模块114，设置为：连接至上述检测模块112，根据U1和U2，对变换器中的变压器的偏磁进行抑制。
可选地，抑制模块114还设置为：根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；以及通过将获取的每个开关管的补偿量与相应的每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
可选地，抑制模块114还设置为：获取U1和U2的电压差值；根据电压差值，获取第一补偿量；通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
可选地，抑制模块114还设置为：通过对电压差值进行滤波处理的方式，获取第一补偿量；或者，通过对电压差值进行限幅处理的方式，获取第一补偿量。
可选地，抑制模块114还设置为：在第一补偿量大于零的情况下，主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为第一补偿量，主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；在第一补偿量小于零的情况下，主边全桥电路的开关管Q1、Q4的补偿量为零，主边全桥电路的开关管Q2、Q3的补偿量为第一补偿量的绝对值。
可以说明的是，上述模块是可以通过软件或硬件来实现的，对于后者， 可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述模块以任意组合的形式分别位于不同的处理器中。
第三实施例
本公开的实施例还提供了一种存储介质，该存储介质包括存储的程序，其中，上述程序运行时执行上述任一项所述的方法。
可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的程序代码：
S1，检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；
S2，根据U1和U2，对变换器中的变压器的偏磁进行抑制。
可选地，存储介质还被设置为存储用于执行以下步骤的程序代码：根据U1和U2，对变换器中的变压器的偏磁进行抑制包括：
S1，根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；
S2，通过将获取的每个开关管的补偿量与相应的每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
可选地，存储介质还被设置为存储用于执行以下步骤的程序代码：根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：
S1，获取U1和U2的电压差值；
S2，根据电压差值，获取第一补偿量；
S3，通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
可选地，存储介质还被设置为存储用于执行以下步骤的程序代码：根据电压差值，获取第一补偿量包括：
S1，通过对电压差值进行滤波处理的方式，获取第一补偿量；或者，
S2，通过对电压差值进行限幅处理的方式，获取第一补偿量。
可选地，存储介质还被设置为存储用于执行以下步骤的程序代码：通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：
S1，在第一补偿量大于零的情况下，主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为第一补偿量，主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；
S2，在第一补偿量小于零的情况下，主边全桥电路的开关管Q1、Q4的补偿量为零，主边全桥电路的开关管Q2、Q3的补偿量为第一补偿量的绝对值。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本公开的实施例还提供了一种处理器，该处理器设置为运行程序，其中，该程序运行时执行上述任一项方法中的步骤。
可选地，在本实施例中，上述程序用于执行以下步骤：
可选地，在本实施例中，上述程序用于执行以下步骤：
S1，检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；
S2，根据U1和U2，对变换器中的变压器的偏磁进行抑制。
可选地，在本实施例中，上述程序用于执行以下步骤：根据U1和U2，对变换器中的变压器的偏磁进行抑制包括：
S1，根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；
S2，通过将获取的每个开关管的补偿量与相应的每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
可选地，在本实施例中，上述程序用于执行以下步骤：根据U1和U2，获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：
S1，获取U1和U2的电压差值；
S2，根据电压差值，获取第一补偿量；
S3，通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
可选地，在本实施例中，上述程序用于执行以下步骤：根据电压差值，获取第一补偿量包括：
S1，通过对电压差值进行滤波处理的方式，获取第一补偿量；或者，
S2，通过对电压差值进行限幅处理的方式，获取第一补偿量。
可选地，在本实施例中，上述程序用于执行以下步骤：通过对第一补偿量进行判断的方式获取变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：
S1，在第一补偿量大于零的情况下，主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为第一补偿量，主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；
S2，在第一补偿量小于零的情况下，主边全桥电路的开关管Q1、Q4的补偿量为零，主边全桥电路的开关管Q2、Q3的补偿量为第一补偿量的绝对值。
可选地，本实施例中的可选示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
本公开实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现上述偏磁抑制方法。
本领域的技术人员可以明白，上述的本公开的模块或步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成不同集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于随机存取存储器(RAM，Random Access Memory)、只读存储器(ROM，Read-Only Memory)、电可擦除只读存储器(EEPROM，Electrically Erasable Programmable Read-only Memory)、闪存或其他存储器技术、光盘只读存储器(CD-ROM，Compact Disc Read-Only Memory)、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本领域的普通技术人员可以理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。
工业实用性
通过本公开实施例，检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；根据U1和U2，对变换器中的变压器的偏磁进行抑制。由于根据变压器原有电路中检测副边全桥电路电流的电阻R1的电压值U1和变压器原有电路中检测副边全 桥电路电流的电阻R2的电压值U2，即可实现对变换器中的变压器的偏磁进行抑制，使得无需添加任何附加的元件，就可有效地抑制变压器的偏磁，因此，可以避免通过在变换器的电路中加入隔直电容来消除电路中变压器偏磁现象方式，导致电路的复杂度高以及变换器的体积大、成本高的情况，达到降低电路复杂度，减小变换器体积和成本效果。

Claims (12)

  1. 一种偏磁抑制方法，包括：
    检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；
    根据所述U1和所述U2，对所述变换器中的变压器的偏磁进行抑制。
  2. 根据权利要求1所述的方法，其中，根据所述U1和所述U2，对所述变换器中的变压器的偏磁进行抑制包括：
    根据所述U1和所述U2，获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；
    通过将获取的所述每个开关管的所述补偿量与相应的所述每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
  3. 根据权利要求2所述的方法，其中，根据所述U1和所述U2，获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：
    获取所述U1和所述U2的电压差值；
    根据所述电压差值，获取第一补偿量；
    通过对所述第一补偿量进行判断的方式获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
  4. 根据权利要求3所述的方法，其中，根据所述电压差值，获取第一补偿量包括：
    通过对所述电压差值进行滤波处理的方式，获取所述第一补偿量；或者，
    通过对所述电压差值进行限幅处理的方式，获取所述第一补偿量。
  5. 根据权利要求3所述的方法，其中，通过对所述第一补偿量进行判断的方式获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量包括：
    在所述第一补偿量大于零的情况下，所述主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为所述第一补偿量，所述主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；
    在所述第一补偿量小于零的情况下，所述主边全桥电路的开关管Q1、 Q4的补偿量为零，所述主边全桥电路的开关管Q2、Q3的补偿量为所述第一补偿量的绝对值。
  6. 一种偏磁抑制装置，包括：
    检测模块，设置为：检测变换器中用于检测副边全桥电路电流的电阻R1的电压值U1和用于检测副边全桥电路电流的电阻R2的电压值U2；
    抑制模块，设置为：根据所述U1和所述U2，对所述变换器中的变压器的偏磁进行抑制。
  7. 根据权利要求6所述的装置，所述抑制模块还设置为：根据所述U1和所述U2，获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量；以及通过将获取的所述每个开关管的所述补偿量与相应的所述每个开关管的占空比信息进行叠加的方式，对变换器中的变压器的偏磁进行抑制。
  8. 根据权利要求7所述的装置，所述抑制模块还设置为：获取所述U1和所述U2的电压差值；根据所述电压差值，获取第一补偿量；通过对所述第一补偿量进行判断的方式获取所述变换器中主边全桥电路的每个开关管的占空比信号所需的补偿量。
  9. 根据权利要求8所述的装置，所述抑制模块还设置为：通过对所述电压差值进行滤波处理的方式，获取所述第一补偿量；或者，通过对所述电压差值进行限幅处理的方式，获取所述第一补偿量。
  10. 根据权利要求8所述的装置，所述抑制模块还设置为：在所述第一补偿量大于零的情况下，所述主边全桥电路的变压器正向励磁方向开关管Q1、Q4的补偿量为所述第一补偿量，所述主边全桥电路的变压器负向励磁方向开关管Q2、Q3的补偿量为零；在所述第一补偿量小于零的情况下，所述主边全桥电路的开关管Q1、Q4的补偿量为零，所述主边全桥电路的开关管Q2、Q3的补偿量为所述第一补偿量的绝对值。
  11. 一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行权利要求1至5中任一项所述的方法。
  12. 一种处理器，所述处理器设置为运行程序，其中，所述程序运行时执行权利要求1至5中任一项所述的方法。
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