WO2018231866A1 - Hétérostructure à grille en tranchée et dispositifs actifs à double hétérostructure - Google Patents

Hétérostructure à grille en tranchée et dispositifs actifs à double hétérostructure Download PDF

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WO2018231866A1
WO2018231866A1 PCT/US2018/037154 US2018037154W WO2018231866A1 WO 2018231866 A1 WO2018231866 A1 WO 2018231866A1 US 2018037154 W US2018037154 W US 2018037154W WO 2018231866 A1 WO2018231866 A1 WO 2018231866A1
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semiconductor
conductivity
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semiconductor material
region
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Jun Zeng
Mohamed Darwish
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Maxpower Semiconductor, Inc.
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Definitions

  • the present application relates to power semiconductor switching devices, and more particularly to trench-gate devices with predominantly vertical current flow in wide-bandgap semiconductor materials.
  • SiC Silicon carbide
  • SiC Silicon carbide
  • the trench gate structure suffers a high electric field at the trench bottom corner due to the curvature of its geometry and the oxide thinning at the trench bottom and corner.
  • SiC trench gated devices this problem is worse than in a comparable silicon device because (for a given breakdown voltage rating) a higher epitaxial doping concentration is used in the SiC device; the higher epitaxial doping concentration results in a high bulk electric field in SiC drift region.
  • the high bulk field also leads to a higher electric field inside the gate oxide at the trench corner area when compared to the situation in Si device.
  • the gate oxide layer becomes much easier to breakdown at the trench bottom in SiC trench-gated device during off-state blocking operation.
  • the hot carrier injection becomes much severer. This is one of the most critical issues needed to be addressed in order to produce a reliable trench-gated SiC device.
  • the present application teaches, among other innovations, heterostmcture and double-heterostructure trench-gate devices, in which the substrate and/or the body are constructed of a narrower-bandgap semiconductor material than the uppermost portion of the drift region. Fabrication most preferably uses a process where gate dielectric anneal is performed after all other high-temperature steps have already been done.
  • the present application also discloses a fabrication process for manufacturing trench-gated power insulated-gate field-effect transistors to achieve doping modifications below at least some non-gate trenches.
  • the non-gate trenches are preferably and advantageously, but not necessarily, field plate trenches.
  • the disclosed process is especially advantageous with silicon carbide semiconductor materials.
  • the doping modification below the non-gate trenches is introduced in a self-aligned manner and activated before the gate oxide is grown on the gate trenches. Most preferably the gate dielectric growth is performed after all high temperature processes are finished; however, metal sputtering is used to form metal connections, and a transient annealing step ("RTA", or rapid thermal anneal) is optionally used for silicidation of front and back metallization (preferably simultaneously).
  • RTA transient annealing step
  • the doping modification can be chosen to provide merely a reduction in the doping below the non-gate trench. This reduces the peak field value below both the non-gate trenches and the gate trench, without significantly degrading the conductivity of the device.
  • Figure 1 schematically shows a trench-gate transistor which permits controllable vertical current flow through a silicon carbide semiconductor die.
  • Figures 2-11 show a sequence of process steps which result in fabrication of a completed transistor structure like that of Figure 12(a) or Figure 13(a).
  • Figure 12(b) shows a transistor structure which is generally similar to that of Figure 12(a), except that a tilted implant was used to produce shield extension regions.
  • Figure 13(b) shows a transistor structure which is generally similar to that of Figure 13(a), except that a tilted implant was used to produce shield extension regions.
  • Figures 14(a) and 14(b) show a transistor structure which is generally somewhat similar to that of Figure 12(a), except that no bottom oxide is present in the gate trench. Note that Figures 14(a) and 14(b) use different formation methods for modified doping regions 106 and 1061.
  • Figures 15-20 show a sequence of process steps which result in fabrication of a completed transistor structure like that of Figure 21(a) or Figure 21(b) or Figure 22. Note that Figures 21(a) and 21(b) use different formation methods for modified doping regions 106 and 1061. [0017] Figure 23 and Figure 24 show alternative devices which do not have the poly field plate in the source contact trench.
  • Figure 25 shows an example of an IGBT device which uses the disclosed innovations.
  • Figure 26(a) shows an example of a vertical trench-gated transistor in which the drift region and substrate are made of different semiconductor materials.
  • Figure 26(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 26(a).
  • Figure 27(a) shows an example of a vertical trench-gated transistor in which the drift region 102 is made of an epitaxial layer of silicon carbide (or alternatively an analogous wide-bandgap semiconductor), while the body region 144' is made of silicon (or an analogous semiconductor material which has a narrower bandgap than the epitaxial layer 102).
  • Figure 27(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 27(a).
  • Figure 28(a) shows an example of a double heterostructure vertical trench-gated transistor, which uses three different semiconductor materials.
  • Figure 28(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 28(a).
  • Figure 29(a) shows an example of a different double- heterostructure vertical trench-gated transistor.
  • Figure 29(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 29(a).
  • Figure 30 shows an example of a different double- heterostructure device.
  • Figure 31 shows an example of a more complex heterostructure device.
  • the present application discloses new device structures, and processes for making them, as applied to vertical-current-flow insulated- gate active devices in wide-bandgap semiconductor materials.
  • SiC Silicon carbide
  • SiC Silicon carbide
  • the trench gate structure suffers a high electric field at the trench bottom corner due to the curvature of its geometry and the oxide thinning at the trench bottom and corner.
  • SiC trench gated devices this problem is worse than in a comparable silicon device because (for a given breakdown voltage rating) a higher epitaxial doping concentration is used in the SiC device; the higher epitaxial doping concentration results in a high bulk electric field in SiC drift region.
  • the high bulk field also leads to a higher electric field inside the gate oxide at the trench corner area when compared to the situation in Si device.
  • the gate oxide layer becomes much easier to breakdown at the trench bottom in SiC trench-gated device during off-state blocking operation.
  • the hot carrier injection becomes much severer. This is one of the most critical issues needed to be addressed in order to produce a reliable trench-gated SiC device.
  • the present application discloses a fabrication process for manufacturing SiC material based trench-gated power MOSFET with doping modifications below non-gate trenches, e.g. like those disclosed in US patent 8,076,719.
  • Figure 1 shows a trench-gate transistor which permits controllable vertical current flow, e.g. from front to back of a device die.
  • Front-side current-carrying metallization 192 connects to n+ source region 142, and also to a p+ body contact region 143 (which connects to p-type body 144).
  • An interlevel dielectric 118 provides electrical insulation of the metallization from the gate electrode 112.
  • Back-side current-carrying metallization 194 connects to n+ substrate 100, which acts as the drain contact.
  • This example is an n-channel (NMOS) device.
  • NMOS n-channel
  • P-channel devices can be constructed on similar principles.
  • the drain terminal 194 is connected to a positive voltage (e.g. 1000V, with the source terminal 192 connected to ground): when the gate electrode 122 is raised to a sufficiently positive voltage, it will invert the nearest part of the body region 144 to form a channel.
  • the drift region includes a region 106 where the body doping has been modified; the function of this region will be discussed further below.
  • the gate voltage at which the channel forms is referred to as the "threshold" voltage. This may be e.g. 1V-6V, but the exact value of the threshold voltage will depend on body doping, channel doping, oxide fixed charge if any, work function differences, etc.
  • the gate trench 110 includes a buried oxide layer 114 below the gate electrode 112.
  • the non-gate trenches 120 include recessed field plates 122, which are typically tied to the source potential.
  • Table 1 shows an overview of a process flow for producing a device like that shown in Figure 1.
  • the sequence of operations includes: Starting with SiC N+ substrate 100, the N-buffer layer 101 and N- epitaxial layer 102 are grown. (It is important to note that the SiC starting material can also be grown on a Silicon substrate, as shown below, in order to reduce cost.)
  • a masked implant is optionally performed to modify the doping concentration of N- epitaxial layer 102, and thereby form the modified doping region 106. Most preferably this implant is of a donor dopant
  • the ambient temperature can be room temperature or a moderate higher temperature, such as 400°C-700°C. (This doping value will affect the threshold voltage, as will the channel doping introduced later in the process.)
  • N+ implant (using a donor dopant, e.g. such as P or N 2 ) is now performed in the locations where the n+ source regions 142 will be located.
  • a donor dopant e.g. such as P or N 2
  • a p-type implant using an acceptor dopant, such as Al or B
  • This high-temperature step activates the N+ and P+ implants, and will slightly shift the profile of the source region 142.
  • the N+ and P+ implants are preferably done at an elevated temperature (such as 600°C). This results in the structure shown in Figure 3.
  • a SiC etch is now carried out to form the gate trenches 110 and non-gate trenches 120. (These trenches are preferably identical at this point, but will be differentiated by later steps.) This produces the structure shown in Figure 4.
  • Another alternative to form the optional modified doping region 106 is by using a blanket implant to locally modify the doping concentration of N- epitaxial layer 102. Most preferably this is of a donor dopant (such as P 31 or N 2 ), in which case the modified doping region 106 has heavier doping, and hence higher conductivity, than the rest of the N- epitaxial layer 102.
  • the blanket implant can use an acceptor dopant, such as Al or B, to locally decrease the doping concentration of N- epitaxial layer 102. This provides some reduction in the peak field value near the bottom corners of the trenches, and hence can provide some additional protection against hot carrier injection. This can be advantageous in high-voltage and/or rad-hard applications. This results in the structure of Figure 5.
  • patterned resist 602 is used to protect the active gate trench 110, and then acceptor dopant (such as Al or B) is implanted into N/N- epitaxial layer 102 through the field plate trench 120, as shown in Figure 6.
  • This implant will form the P-Shield region 146 underneath the trenches 120.
  • the implantation can be adjusted properly to optimize the P- Shield profile along the field plate trench sidewall and the depth of P- Shield.
  • a high temperature process >1600°C
  • Ar ambient is carried out to anneal and activate all of implanted dopants with a carbon cap layer 702 in place for protection. This is depicted in Figure 7.
  • the BOX photo resist 602 is formed again to protect the active gate trench 110, and the oxide inside the field plate trench is completely etched. This leaves a BOX oxide 114 in place in the gate trenches 110, but not in the non-gate trenches 120, as shown in Figure 9.
  • the gate formation process begins. Initially a sacrificial oxide is preferably grown and stripped.
  • the gate oxide layer itself is preferably formed by dry thermal oxidation (or alternatively by a CVD process) along the trench sidewall as illustrated by Figure 10.
  • the gate oxide thickness is preferably between 400A (40nm) to 600A, and typically 500A.
  • Gate oxide formation is most preferably done in two steps: first, a layer of stoichiometric oxide is formed by CVD deposition or high temperature oxidation, in temperature range between 1100°C to 1300°C; secondly, a relatively high temperature anneal is performed in an oxidizing nitrogen-rich ambient (e.g. with 100% N 2 0 or NO). The anneal temperature, in this example, is between 1100°C to 1350°C. No high- temperature process steps should follow the gate oxide anneal.
  • the gate oxide can be partially converted to an oxynitride compound.
  • the net activity of nitrogen is increased by using an oxygen-nitrogen compound as the oxidizing component in the gas phase, and can be further increased by addition of N 2 or other nitrogen source.
  • This culminating gate oxide anneal maximizes the quality of the semiconductor-to-oxide interface. Surprisingly, this culminating anneal also provides improvement in the radiation-hardness of the final device.
  • Interlevel dielectric 118 is now formed, e.g. by CVD, and etched back to expose the non-gate trenches 120.
  • a recess etch is now performed to expose the n+ source and p+ body contact regions to the source metallization.
  • a thick metal layer 192 such as Aluminum, is now deposited on the front side of the device to form the Source electrode.
  • Another thick metal layer 194 similarly forms the Drain electrode. Electrical connection to the gate electrode 112 is formed similarly, but outside the area illustrated.
  • Figures 12(a) through 13(b) show a variety of final device structures produced by the above steps.
  • the modified-doping region 106 is an "N-reduced" region, resulting from the implantation of acceptors as an N-reduction implant at the stage of Figure 5.
  • Figures 12(a) and Figure 12(b) show examples where donors were blanket-implanted to make region 106 an "N- enhanced” region.
  • the "N-reduced” region can be utilized to further lessen the electric field at the trench bottom and corners.
  • the "N- enhanced” region can be used to reduce the device on-resistance and enhance forward current conduction.
  • the location of the P-shield 146 is expanded to include additional p-shield-extension regions 147 around the sides of the non- gate trenches 122.
  • the P body can either be connected to the P- Shield zone or disconnected from the P-Shield zone. Examples of this are shown in Figure 12(b) and Figure 13(b).
  • Figure 12(a) and Figure 13(a), by contrast, show examples where the P-Shield implant was not tilted (0 degrees tilt angle).
  • the dopings and thicknesses will depend on what operating voltage a device is designed for. For example, when the above device is optimized for 1200V operation, the epitaxial layer thickness is expected to be about 1 ⁇ , and its doping is expected to be about 6E15/cm . For a 650V implementation, the epitaxial layer thickness is expected to be about 5 ⁇ and its doping is about lE16/cm .
  • the P-body junction depth is preferably about 0.8 ⁇ and the trench depth is about ⁇ .
  • the shield region 146 is about 0.5 ⁇ to ⁇ thick, so the thickness of the epitaxial layer below the shield is expected to be about 9 ⁇ for 1200V device, and about 3 ⁇ for 650V device.
  • Table 2 summarizes the process flow for producing the device shown in Figures 14(a) or 14(b), in which the thick bottom oxide BOX is eliminated. Its process flow is similar to, but simpler than, the process sequence described in the previous paragraphs.
  • N+ implant (using a donor dopant, e.g. such as P or N 2 ) is now performed in the locations where the n+ source regions 142 will be.
  • a donor dopant e.g. such as P or N 2
  • These steps are preferably followed by p-type implants (using an acceptor dopant, such as Al or B), to form the P-body contact region 143.
  • p-type implants using an acceptor dopant, such as Al or B
  • This is followed by a high temperature furnace anneal process (>1600°C) in Ar ambient with a carbon cap layer 302 for protection.
  • This high-temperature step activates the N+ and P+ implants, and will slightly shift the profile of the source region 142.
  • N+ and P+ implants are preferably done at an elevated temperature (such as 600°C). This results in the structure shown in Figure 16.
  • a SiC etch is now carried out to form the gate trenches 110 and non-gate trenches 120. (This trenches are preferably identical at this point, but will be differentiated by later steps.) This produces the structure shown in Figure 17.
  • a blanket implant is now performed to locally modify the doping concentration of N- epitaxial layer 102, and thereby form the modified doping region 106. Most preferably this is of a donor dopant
  • the blanket implant can use an acceptor dopant, such as Al or B, to locally decrease the doping concentration of N- epitaxial layer 102. This provides some reduction in the peak field value near the bottom corners of the trenches, and hence can provide some additional protection against hot carrier injection. This can be advantageous in high-voltage and/or rad-hard applications. This results in the structure of Figure 18.
  • patterned resist 602 is used to protect the active gate trench 110, and then acceptor dopant (such as Al or B) is implanted into N/N- epitaxial layer 102 through the field plate trench 120, as shown in Figure 19.
  • acceptor dopant such as Al or B
  • This implant will form the P-Shield region 146 underneath the trenches 120.
  • the implantation can be adjusted to optimize the P-Shield profile along the field plate trench sidewall and the depth of P-Shield.
  • the gate formation process is done as described above, ending with a culminating anneal in an oxidizing nitrogen-rich ambient (e.g. with N 2 0 or NO).
  • the anneal temperature in this example, is between 1100°C to 1350°C. No high-temperature process steps should follow the gate oxide anneal.
  • This culminating gate oxide anneal maximizes the quality of the semiconductor-to-oxide interface. Surprisingly, this culminating anneal also provides improvement in the radiation-hardness of the final device.
  • the gate electrode 112 and field plate 122 are now formed, e.g. by deposition and CMP of n+ polysilicon. Following this interlevel dielectric is now formed and etched back. A recess etch is performed, front and backside contact metal layer are formed, and source, drain, and gate metal is deposited. This produces the final structure of Figure 21(a) or Figure 21(b) (if modified region 106 in Figure 21(a) or region 1061 in Figure 21(b) has enhanced doping), or the final structure of Figure 22 (if modified region 106 was partly counterdoped).
  • Figure 23 and Figure 24 show devices without the poly field plate in the source contact trench, but with only the P-Shield regions. Note also that a tilted implant was used to produce extended shield regions in these examples.
  • Figure 26(a) shows an example of a vertical trench-gated transistor in which the drift region 102 is made of an epitaxial layer of silicon carbide (or alternatively an analogous wide-bandgap semiconductor), while the substrate 100' is made of silicon (or an analogous semiconductor material which has a narrower bandgap than the epitaxial layer 102).
  • the epitaxial layer and substrate have a reasonably close lattice match; optionally, as shown, a buffer layer 101 can be included at this transition to reduce strain.
  • the buffer layer 101 will normally be n-type. This is a heterostructure device.
  • Figure 26(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 26(a). Note the presence of a P+ collector layer 199 next to the collector metallization 194, to provide minority carrier emission in the ON-state. (This provides lower on- resistance for the IGBT structure than for the corresponding transistor structure, but results in slower turnoff.)
  • Figure 27(a) shows an example of a vertical trench-gated transistor in which the drift region 102 is made of an epitaxial layer of silicon carbide (or alternatively an analogous wide-bandgap semiconductor), while the body region 144' is made of silicon (or an analogous semiconductor material which has a narrower bandgap than the epitaxial layer 102).
  • the SiC P-body region 144 By replacing the SiC P-body region 144 with silicon 144', the channel resistance is reduced significantly due to silicon's higher electron mobility.
  • the silicon P-body 144' can be formed over the SiC epitaxial layer by a further epitaxial deposition. This again leads a lower on-resistance for low voltage power MOSFET. This is a heterostructure device.
  • Figure 27(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 27(a). Note the use of a P+ substrate 100 next to the collector metallization 142, to provide minority carrier emission in the ON-state. (This provides lower on-resistance for the IGBT structure than for the corresponding transistor structure, but results in slower turnoff.) Double-Heterostructure Devices
  • Figure 28(a) shows an example of a double heterostructure device.
  • a vertical trench-gated transistor is modified to use three different semiconductor materials: 1) the drift region 102 is made of a heteroepitaxial layer of silicon carbide (or alternatively an analogous wide-bandgap semiconductor) over 2) a substrate 100' made of silicon (or an analogous semiconductor material which has a narrower bandgap than the epitaxial layer 102).
  • the body region 144' is made of silicon (or an analogous semiconductor material which has a higher carrier mobility than the epitaxial layer 102).
  • the silicon P-body 144' can be formed over the SiC epitaxial layer 102 by a further epitaxial deposition.
  • the mixed layer configuration in Figure 28(a) opens the possibility for SiC devices to penetrate into low voltage power MOSFET applications, with lower on-resistance compared to current pure Si based low voltage Power MOSFET.
  • Figure 28(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 28(a). Note the presence of a P+ minority carrier emission layer 199 next to the collector metallization 194, to provide minority carrier emission in the ON-state. (This provides lower on-resistance for the IGBT structure than for the corresponding transistor structure, but results in slower turnoff.)
  • Figure 29(a) shows an example of a different double- heterostructure vertical trench-gated transistor.
  • the body region 144" is formed from a III-N semiconductor (e.g. GaN).
  • the drift region 102 is made of an epitaxial layer of silicon carbide (or alternatively an analogous wide-bandgap semiconductor), while the substrate 100' is made of silicon (or an analogous semiconductor material which has a narrower bandgap than the epitaxial layer 102). It is believed that GaN on top of SiC layer has a reduced bulk defects, and as the result, the body diode of this device has a more reliable operation.
  • an n++ region 196 is used under the drain metallization 194, to reduce contact resistance.
  • using the GaN over SiC in the channel region can reduce the channel resistance significantly, since the channel carrier mobility of GaN is much higher than that of SiC.
  • Figure 29(b) shows an example of an IGBT device constructed similarly to the transistor of Figure 29(a). Note the presence of a P+ layer 199 next to the collector contact, to provide minority carrier emission in the ON-state. (This provides lower on-resistance for the IGBT structure structure, but results in slower turnoff.)
  • Figure 30 shows an example of a different double- heterostructure device.
  • This device has a fabrication sequence somewhat analogous to that of Figure 29(a), except that the III-N over IV heteroepitaxy step is performed to a greater thickness, so that the drift region 102' is formed in an epitaxial III-N layer (GaN in this example).
  • the superior mobility characteristics of GaN are believed to be advantageous is reducing on-state channel resistance.
  • the use of a SiC first layer 102" over a silicon substrate 100' still helps to provide a high breakdown voltage.
  • Figure 31 shows an example of a more complex heterostructure device.
  • Heterostructure and double-heterostructure trench-gate devices in which the substrate and/or the body are constructed of a narrower- bandgap semiconductor material than the uppermost portion of the drift region. Fabrication most preferably uses a process where gate dielectric anneal is performed after all other high-temperature steps have already been done.
  • a double-heterostructure semiconductor device structure comprising: at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material; wherein the first and third semiconductor materials are each different from the second semiconductor material; a first-conductivity-type source region surrounded by a second-conductivity-type body region, formed in the first semiconductor material; a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material; a gate which is positioned in a first trench within said semiconductor layer, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench; recessed field plates, positioned in proximity to and capacitively coupled to said semiconductor material; said recessed field plates being positioned in respective second trenches; wherein the first and second trenches both extend through the first semiconductor material down into the second semiconductor material;
  • a double-heterostructure semiconductor device structure comprising: at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material; wherein the first and third semiconductor materials are each different from the second semiconductor material; a first-conductivity-type source or emitter region surrounded by a second-conductivity-type body region, formed in the first semiconductor material; a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material; a gate which is positioned in a first trench within said semiconductor layer, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench.
  • a semiconductor device structure comprising: at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material which epitaxially overlies at least one layer of a fourth semiconductor material; wherein the first and third semiconductor materials are each different from the second semiconductor material, and the fourth semiconductor material is different from the third semiconductor material; a first-conductivity-type source or emitter region which is ohmically connected to a first current- carrying metallization, and which is surrounded by a second- conductivity-type body region, formed in the first semiconductor material; a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material; a gate which is positioned in a first trench within said semiconductor layer, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench, and thereby through portions of the drift region; a first semiconductor material epitaxially overlying at least one layer of a
  • a semiconductor device structure comprising: in a semiconductor mass consisting essentially, at upper portions thereof, of an uppermost epitaxial layer of a first semiconductor material overlying a layer of a second semiconductor material having a second bandgap which is larger than the bandgap of the first semiconductor material, a gate which is positioned in a first trench within said semiconductor layer, and is capacitively coupled to control vertical conduction from a first- conductivity-type source through second-conductivity-type portions of said layer near said trench; recessed field plates, positioned in proximity to and capacitively coupled to said semiconductor material; said recessed field plates being positioned in respective second trenches; a first additional diffusion component of a second conductivity type lying at least partially beneath said respective second trenches; and a second additional diffusion component of said first conductivity type lying at least partially within said second-conductivity-type portions of said layer; whereby said first additional diffusion component reduces depletion of said second-conductivity-type
  • a power semiconductor device fabrication process comprising: in a semiconductor mass consisting essentially of silicon carbide, forming, in any order, a first-conductivity-type source region, a second-conductivity-type body region which forms a junction with first- conductivity-type bulk material lying therebelow, first and second trenches, each extending deeper than the body region, a second- conductivity-type shield regions lying below said first trenches but not below said second trenches, and an additional doping modification component lying within the first-conductivity-type bulk material of the semiconductor mass; applying heat to activate dopants in the source region, the body region, the shield region, and the additional doping modification component; performing insulated gate fabrication, by forming a thin gate dielectric comprising a silicon oxide on sidewalls of the second trenches, annealing the thin gate dielectric at a temperature above 1000 degrees C in a nitrogen-rich oxidizing atmosphere, and forming a conductive gate electrode over
  • a power semiconductor device fabrication process comprising: in a semiconductor mass, forming, in any order, a first- conductivity-type carrier emission region, a second-conductivity-type body region which forms a junction with first-conductivity-type bulk material lying therebelow, a first and second trenches, each extending deeper than the body region, second-conductivity-type shield regions lying below said first trenches but not below said second trenches, and an additional doping modification component lying within the first- conductivity-type bulk material of the semiconductor mass; applying heat to activate dopants in the carrier emission region, the body region, the shield region, and the additional doping modification component; performing insulated gate fabrication, by forming a thin gate dielectric comprising a silicon oxide on sidewalls of the second trenches, annealing the thin gate dielectric at a temperature above 1000 degrees C in a nitrogen-rich oxidizing atmosphere, and forming a conductive gate electrode over the thin gate dielectric;
  • a silicon carbide (or comparable) trench transistor in which gate dielectric anneal, in an oxynitriding atmosphere, is performed after all other high-temperature steps have already been done.
  • a power semiconductor device fabrication process comprising: in a semiconductor mass, forming, in any order, a first- conductivity-type carrier emission region, a second-conductivity-type body region which forms a junction with first-conductivity-type bulk material lying therebelow, first and second trenches, each extending deeper than the body region, second-conductivity-type shield regions lying below said first trenches but not below said second trenches, and an additional doping modification component lying within the first- conductivity-type bulk material of the semiconductor mass; applying heat to activate dopants in the carrier emission region, the body region, the shield region, and the additional doping modification component; performing insulated gate fabrication, by forming a thin gate dielectric comprising a silicon oxide on sidewalls of the second trenches, annealing the thin gate dielectric in a nitrogen-rich oxidizing atmosphere, and forming a conductive gate electrode over the thin gate dielectric; and forming metallization to complete fabrication of
  • a power semiconductor device fabrication process comprising: a) in a semiconductor mass, forming, in any order, a first- conductivity-type carrier emission region, a second-conductivity-type body region which forms a junction with first-conductivity-type bulk material lying therebelow, first and second trenches, each extending deeper than the body region, and a second-conductivity-type shield regions lying below said first trenches but not below said second trench; b) applying heat to activate dopants in the carrier emission region, the body region, and the shield region; c) performing insulated gate fabrication, by forming a thin gate dielectric comprising a silicon oxide on sidewalls of the second trenches, annealing the thin gate dielectric at a temperature above 1000 degrees C in a nitrogen-rich oxidizing atmosphere, and forming a conductive gate electrode over the thin gate dielectric; and d) forming metallization to complete fabrication of an operative device; wherein no non-trans
  • a power semiconductor device fabrication process comprising: a) in a semiconductor mass, forming, in any order, a first- conductivity-type carrier emission region, a second-conductivity-type body region which forms a junction with first-conductivity-type bulk material lying therebelow, a first and second trenches, each extending deeper than the body region, and second-conductivity-type shield regions lying below said first trenches but not below said second trenches; b) applying heat to activate dopants in the carrier emission region, the body region, the shield region, and the additional doping modification component; c) performing insulated gate fabrication, by forming a thin gate dielectric comprising a silicon oxide on sidewalls of the second trenches, annealing the thin gate dielectric in a nitrogen-rich oxidizing atmosphere, and forming a conductive gate electrode over the thin gate dielectric; and d) forming metallization to complete fabrication of an operative device; wherein no
  • the preferred wide-bandgap semiconductor material is silicon carbide
  • other semiconductor materials can optionally be substituted.
  • a primary example of this is Group IV alloys, e.g. one of the SiGeC ternary semiconductor alloys.
  • the disclosed inventions can be adapted to other wide-bandgap semiconductor materials, such as diamond, GaN, AlGaN, or Ga 2 0 3 .
  • the devices fabricated are simple vertical-current-flow field-effect transistors.
  • the disclosed inventions can also be used to form other device types which include an insulated gate.
  • One example would be IGBTs (as in Figure 25), but other possibilities contemplated include MCTs and TMBSs (Trench MOS Barrier Schottky Rectifiers).

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Abstract

L'invention concerne une hétérostructure et des dispositifs à grille en tranchée à double hétérostructure, dans lesquels le substrat et/ou le corps sont construits dans un matériau semi-conducteur à bande interdite plus étroite que la partie la plus haute de la région de dérive. La fabrication met en oeuvre de préférence un procédé dans lequel un recuit diélectrique de grille est réalisé après que toutes les autres étapes à haute température ont été effectuées.
PCT/US2018/037154 2017-06-12 2018-06-12 Hétérostructure à grille en tranchée et dispositifs actifs à double hétérostructure WO2018231866A1 (fr)

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US20180366569A1 (en) * 2016-06-10 2018-12-20 Maxpower Semiconductor Inc. Trench-Gated Heterostructure and Double-Heterostructure Active Devices
CN115985943A (zh) * 2023-03-21 2023-04-18 晶艺半导体有限公司 Igbt半导体器件及其制作方法
TWI823771B (zh) * 2022-12-08 2023-11-21 美商達爾科技股份有限公司 垂直式半導體功率器件及其製造方法

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JP2008186925A (ja) * 2007-01-29 2008-08-14 Fuji Electric Device Technology Co Ltd 絶縁ゲート炭化珪素半導体装置とその製造方法
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US20140264564A1 (en) * 2013-03-13 2014-09-18 Cree, Inc. Field Effect Transistor Devices with Buried Well Protection Regions
US20160293743A1 (en) * 2010-07-06 2016-10-06 Maxpower Semiconductor, Inc. Power Semiconductor Devices, Structures, and Related Methods

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JP2008186925A (ja) * 2007-01-29 2008-08-14 Fuji Electric Device Technology Co Ltd 絶縁ゲート炭化珪素半導体装置とその製造方法
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US20180366569A1 (en) * 2016-06-10 2018-12-20 Maxpower Semiconductor Inc. Trench-Gated Heterostructure and Double-Heterostructure Active Devices
TWI823771B (zh) * 2022-12-08 2023-11-21 美商達爾科技股份有限公司 垂直式半導體功率器件及其製造方法
CN115985943A (zh) * 2023-03-21 2023-04-18 晶艺半导体有限公司 Igbt半导体器件及其制作方法

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