WO2018223932A1 - 一种基于gpp的5g终端通用平台优化方法及系统 - Google Patents

一种基于gpp的5g终端通用平台优化方法及系统 Download PDF

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WO2018223932A1
WO2018223932A1 PCT/CN2018/089837 CN2018089837W WO2018223932A1 WO 2018223932 A1 WO2018223932 A1 WO 2018223932A1 CN 2018089837 W CN2018089837 W CN 2018089837W WO 2018223932 A1 WO2018223932 A1 WO 2018223932A1
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task
gpp
tasks
subtasks
universal platform
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PCT/CN2018/089837
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English (en)
French (fr)
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唐彦波
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捷开通讯(深圳)有限公司
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Priority to US16/619,465 priority Critical patent/US20200183741A1/en
Priority to EP18812626.2A priority patent/EP3637830A4/en
Publication of WO2018223932A1 publication Critical patent/WO2018223932A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W24/00—Supervisory, monitoring or testing arrangements
    • H04W24/02—Arrangements for optimising operational condition
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/16—Central resource management; Negotiation of resources or communication parameters, e.g. negotiating bandwidth or QoS [Quality of Service]
    • H04W28/24—Negotiating SLA [Service Level Agreement]; Negotiating QoS [Quality of Service]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/48—Indexing scheme relating to G06F9/48
    • G06F2209/483—Multiproc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/48—Indexing scheme relating to G06F9/48
    • G06F2209/484—Precedence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5017—Task decomposition

Definitions

  • the present invention relates to the field of 5G technologies, and in particular, to a GPP-based 5G terminal universal platform optimization method and system.
  • an open 5G wireless system based on a purely software architecture implemented by a general-purpose processor can easily use a variety of sophisticated software engineering methods to improve software development efficiency and development quality;
  • the open architecture based on open pure software also faces many problems in software implementation, such as real-time processing of LTE and 5G protocol stack, HARQ feedback delay, and implementation of multi-terminal simulation, which brings great inconvenience.
  • the object of the present invention is to provide a GPP-based 5G terminal universal platform optimization method and system, which aims to solve the problem that the general-purpose 5G terminal general platform based on the general processor has low real-time performance and high delay.
  • an embodiment of the present invention provides a GPP-based 5G terminal universal platform optimization method, which includes:
  • Each subtask is assigned a time budget, and each subtask is marked with a time stamp in the processing flow, and the execution is terminated or prematurely terminated according to the comparison between the time stamp of each subtask and the allocated time budget.
  • the GPP-based 5G terminal universal platform optimization method supports static scheduling and dynamic scheduling.
  • the GPP-based 5G terminal universal platform optimization method the step of dividing a task into a plurality of subtasks according to attributes of each task, and assigning the plurality of subtasks to different threads further includes: The task and the priority of the thread are allocated.
  • the GPP-based 5G terminal universal platform optimization method the step of dividing a task into a plurality of subtasks according to attributes of each task, and assigning the plurality of subtasks to different threads further includes: The task is pre-processed.
  • the GPP-based 5G terminal common platform optimization method wherein each sub-task is assigned a time budget, and each sub-task is marked with a time stamp in the processing flow, according to the time stamp and the assigned time of each sub-task
  • the step of comparing the time budgets to the decision to continue or prematurely terminates includes monitoring the execution of the tasks by the task controller and interacting with the scheduler to increase or decrease the tasks processed by the physical layer.
  • the GPP-based 5G terminal universal platform optimization method uses an FPGA acceleration unit to build a heterogeneous computing platform, and accelerates the baseband signal through the FPGA to reduce the computational burden of the general-purpose processor; the DMA technology is adopted through the PCI-E interface.
  • the memory of the general server platform directly accesses the read and write data to realize high-speed data interaction between the general-purpose processor and the acceleration unit; the SIMD instruction supported by the general-purpose processor performs parallel processing of the single-instruction multi-channel data stream, wherein the instruction is based on the instruction
  • the set of software acceleration methods includes bit-level acceleration, symbol-level acceleration, and/or sample-level acceleration.
  • an embodiment of the present invention provides a GPP-based 5G terminal universal platform optimization method, which includes:
  • Different priorities are assigned to programs of different modules in the base station, wherein the control channel and the related procedures for controlling the processing flow have the highest priority; after the high-priority tasks are processed, the low-priority tasks are processed;
  • Each subtask is assigned a time budget, and each subtask is time stamped in the processing flow, and the execution or early termination is determined according to the time stamp of each subtask being compared with the allocated time budget.
  • the GPP-based 5G terminal universal platform optimization method wherein the GPP-based 5G terminal universal platform supports both static scheduling and dynamic scheduling.
  • the GPP-based 5G terminal common platform optimization method wherein the step of dividing a task into a plurality of subtasks according to an attribute of each task, and assigning the plurality of subtasks to different threads further includes:
  • the GPP-based 5G terminal common platform optimization method wherein the step of dividing a task into a plurality of subtasks according to an attribute of each task, and assigning the plurality of subtasks to different threads further includes:
  • the GPP-based 5G terminal universal platform optimization method wherein the sub-task is assigned a time budget, and each sub-task is marked with a time stamp in the processing flow, according to the time stamp and the assigned time of each sub-task
  • the steps of comparing the time budget to decide whether to continue or prematurely terminate include:
  • the task controller monitors the execution of the task and interacts with the scheduler to increase or decrease the tasks processed by the physical layer.
  • the GPP-based 5G terminal universal platform optimization method wherein the FPGA acceleration unit is used to build a heterogeneous computing platform, and the baseband signal is accelerated by the FPGA to reduce the computational burden of the general-purpose processor; the DMA is adopted through the PCI-E interface.
  • the technology directly accesses the read/write data of the memory of the general server platform to realize high-speed data interaction between the general-purpose processor and the acceleration unit; and performs parallel processing of the single-instruction multi-channel data stream by using the SIMD instruction supported by the general-purpose processor, wherein Instruction set based software acceleration methods include bit level acceleration, symbol level acceleration, and/or sample level acceleration.
  • a GPP-based 5G terminal universal platform optimization system which includes:
  • a priority module configured to assign different priorities to programs of different modules in the base station, wherein the control channel and the related program controlling the processing flow have the highest priority; and the programs of the different modules are processed in descending order of priority Corresponding task
  • a task segmentation allocation module configured to divide a task into a plurality of subtasks according to attributes of each task, and assign the plurality of subtasks to different threads;
  • a task execution module configured to allocate a time budget for each subtask, mark each subtask with a timestamp in the processing flow, and decide to continue execution according to the comparison result between the time stamp of each subtask and the allocated time budget. Early termination.
  • the GPP-based 5G terminal universal platform optimization system further comprising:
  • a pre-processing module for pre-processing tasks in a background thread For pre-processing tasks in a background thread.
  • the GPP-based 5G terminal universal platform optimization system further comprising:
  • the monitoring module is configured to monitor the execution of the task by the task controller, and communicate with the scheduler to increase or decrease the tasks processed by the physical layer.
  • the GPP-based 5G terminal universal platform optimization system wherein the FPGA acceleration unit is used to build a heterogeneous computing platform, and the baseband signal is accelerated by the FPGA to reduce the computational burden of the general-purpose processor; the DMA is adopted through the PCI-E interface.
  • the technology directly accesses the read/write data of the memory of the general server platform to realize high-speed data interaction between the general-purpose processor and the acceleration unit; and performs parallel processing of the single-instruction multi-channel data stream by using the SIMD instruction supported by the general-purpose processor, wherein Instruction set based software acceleration methods include bit level acceleration, symbol level acceleration, and/or sample level acceleration.
  • the GPP-based 5G terminal universal platform optimization method and system provided by the invention have high real-time processing and low HARQ feedback delay, which meets the strict requirements of high real-time and low delay in mobile communication, facilitates the realization of multi-terminal simulation, and greatly optimizes the present There is a universal platform that brings great convenience.
  • FIG. 1 is a flowchart of a method for optimizing a GPP-based 5G terminal universal platform according to the present invention.
  • FIG. 2 is a structural block diagram of a GPP-based 5G terminal universal platform optimization system provided by the present invention.
  • FIG. 3 is a schematic structural diagram of simulating a large number of terminals of a GPP-based 5G terminal universal platform optimization system according to the present invention.
  • the invention provides a GPP-based 5G terminal universal platform optimization method and system.
  • the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
  • the present invention provides a GPP-based 5G terminal universal platform optimization method, and the GPP-based 5G terminal universal platform optimization method includes:
  • S100 assign different priorities to programs of different modules in the base station, where the control channel and the related program of the control processing flow have the highest priority; and the tasks corresponding to the programs of the different modules are processed according to the order of priority from high to low, That is, after the high-priority task is processed, the low-priority task is processed;
  • the present invention is a software optimization method based on a GPP (General Purpose Processor) general-purpose processor platform.
  • the software architecture and traditional software of a base station based on the Intel general-purpose processor architecture are required due to the strict requirements of high real-time and low latency in mobile communication.
  • the architecture is different.
  • each subframe occupies 1 millisecond, which requires the software program at the base station to complete the decoding of the uplink channel and the ACK/NACK (acknowledgement/non-acknowledgement) to the UE (terminal) within 3 milliseconds.
  • the 5G NR occupies less than 1 millisecond per sub-frame.
  • HARQ Hybrid Automatic Repeat reQuest, a technology that combines forward error correction coding FEC and automatic retransmission request ARQ
  • the feedback time is more stringent than the LTE requirements.
  • base stations based on Intel general-purpose processor architectures differ from traditional digital signal processor-based base stations in software architecture.
  • DSP-based software radio implementations the latency of digital signal processing is almost fixed, so the process of program processing can be tightly controlled.
  • the program may experience jitter when processing the same functional module.
  • One solution is to bind the specified task to a core and let only a fixed program run on the core.
  • the design principle of the base station software architecture based on the Intel general processor architecture is to maximize the processing power of the multi-core processor based on the real-time requirements of the protocol.
  • programs of different modules in the base station are assigned different priorities.
  • the control channel and related procedures for controlling the processing flow must have the highest priority.
  • every effort is made to deal with the correlation operations of the data channel.
  • a dual-core processor and a quad-core processor can support 20MHz. TDD LTE protocol processing, but quad-core processors can provide higher data throughput.
  • the GPP-based 5G terminal universal platform supports both static scheduling and dynamic scheduling.
  • the task is divided into a plurality of subtasks according to the attributes of each task, and the subtasks are assigned to different threads.
  • the GPP-based 5G terminal universal platform of the present invention can quickly and efficiently segment tasks according to the attributes of each task when performing tasks, and flexibly assign tasks to different ones. the rout.
  • the step S200 further includes: S201, assigning priorities of tasks and threads. Specifically, regarding the priority assignment of tasks and threads. As mentioned earlier, the control channel handler needs to assign a higher priority. However, there are some tasks that do not have strict real-time requirements, so they can be assigned lower priority, and low-priority tasks can be processed after high-priority tasks are processed. For example, the response in the PRACH (Physical Random Access Channel) channel can be processed in a long period of time.
  • PRACH Physical Random Access Channel
  • each subtask is assigned a time budget, each subtask is time stamped in the processing flow, and the time stamp of each subtask is compared with the allocated time budget to decide to continue execution or early termination.
  • the task is divided into a plurality of subtasks and allocated, and then in step S300, a time budget is allocated to each subtask and the processing time of each subtask is recorded, and if the time budget is exceeded, the execution continues. Termination is terminated without exceeding the time budget.
  • the task manager needs to assign a time budget to each subtask. The software will time stamp the subtasks in the processing flow and compare them with the allocated time budget to decide whether to continue or prematurely terminate.
  • the software first processes high-priority tasks and then does its best to handle other tasks. For example, at the physical layer of the receiving end of the LTE terminal, the IFFT (Inverse Fast Fourier Transform) operation is first performed, and then the PDCCH (Physical Downlink Control Channel) is decoded one by one, and finally, according to the remaining time pair.
  • the data channel PDSCH Physical Downlink Shared Channel
  • the step S200 further includes:
  • S202 Pre-processing the task in a background thread.
  • tasks can be pre-processed in a background thread.
  • Many of the tasks of the sender can be calculated in advance.
  • the reference signals of the next 20 frames can be pre-calculated and stored in the memory.
  • there is no very strict real-time requirement for the transmission of new data in the PDSCH channel so the modulation and coding can be calculated and the scheduler decides when to transmit.
  • This pre-processing mechanism can reduce the occurrence of jitter and provide more space for tasks with high priority or limited time.
  • the step S300 further includes:
  • the task controller monitors the execution of the task and increases or decreases the tasks processed by the physical layer by interacting with the data of the scheduler. For example, when there are a large number of physical layer sending tasks that cannot be completed in the allocated time budget, the scheduler will assign fewer tasks to future uplink processing. Therefore, the throughput that can be supported on a particular platform will depend on the processing power of the processor. In addition, the task controller must also balance the load between the different cores. Mechanisms are also needed to prevent jitter generated during scheduling. This is the role of the intelligent scheduler and task controller in the general purpose processor platform of the present invention.
  • the GPP-based 5G terminal universal platform of the present invention has a cross-layer design of a physical layer, a MAC layer, and an RLC layer. These three layers are highly coupled in the LTE protocol, and although they have some independence from the functional point of view, they are coupled together from the perspective of task execution. In the traditional implementation, different layers use independent hardware structures, and the data transfer between layers causes unnecessary delay and waste. Terminals based on Intel's general-purpose processor architecture can easily implement cross-layer design because the entire protocol stack runs on one processor.
  • the GPP-based 5G terminal universal platform uses an FPGA acceleration unit to build a heterogeneous computing platform, and accelerates the baseband signal through the FPGA to reduce the computational burden of the general-purpose processor;
  • the -E interface uses DMA technology to directly access the read and write data of the memory of the general server platform to achieve high-speed data interaction between the general-purpose processor and the acceleration unit;
  • the SIMD instruction supported by the general-purpose processor is used to complete the single-instruction multi-channel data stream.
  • Parallel processing wherein the instruction set based software acceleration method includes bit level acceleration, symbol level acceleration, and/or sample level acceleration.
  • the FPGA acceleration unit is used to build a heterogeneous computing platform, and some baseband signals with relatively simple calculations and large calculations are accelerated by the FPGA, thereby reducing the general-purpose processor.
  • Calculating the burden designing the PCI-E interface, using DMA technology to directly access the read and write data of the memory of the general server platform, realizing high-speed data interaction between the general-purpose processor and the acceleration unit; the pre-transmission link RF and general-purpose server baseband processing interface adopts The mature CPRI interface is connected; the hardware architecture of the entire open 5G universal platform terminal simulator is given, and the software-defined physical layer, especially the baseband processing function, is implemented.
  • the SIMD instructions (MMX, SSE, SSE2, SSE3, SSE4, AVX, AVX2, etc.) supported by the general processor are used to complete the parallel processing of the single instruction multiple data streams.
  • the software acceleration method based on instruction set is as follows: 1) Bit level-Look UP Tables (LUT) Among them, the LUT is a compromise operation after considering the computational complexity and spatial complexity, and the LUT operation can greatly reduce the online processing delay instead of the conventional bit operation.
  • the CRC checksum and de-verification, scrambling code and descrambling code, rate matching and desmatching and other bit-level operations can be accelerated by the LUT method.
  • SIMD single instruction multiple data instructions
  • Intel CPU has a special multi-data instruction SIMD (Single Instruction multiple data)
  • SIMD Single Instruction multiple data
  • the symbol level operations such as modulation and demodulation, precoding, MIMO, and channel estimation can be performed by SIMD.
  • IPP Sample level-Intel Integrated Performance Primitives
  • IPP the comprehensive performance primitive IPP developed by Intel is a cross-platform, cross-operating software function library that can be implemented. Signal processing, image processing, multimedia, vector processing and other operations. IPP does not need to write assembly code, and small code changes can be greatly changed.
  • the FFT/IFFT operation is realized by IPP, and the test result shows that the online processing is completed by IPP, and the performance advantage is remarkable.
  • the FFT/IFFT can be accelerated in an IPP manner.
  • FIG. 2 is a schematic diagram of a GPP-based 5G terminal universal platform optimization system simulating a large number of terminals, and simulating a large number of terminals simultaneously on a common platform, based on Linux.
  • the low latency version of the real-time operating system naturally supports multi-threading technology.
  • Figure 2 shows the software architecture of the universal platform emulation multi-terminal, which will simulate the terminal per TTI [TTI refers to the transmission time interval, and each transport channel (TrCH) corresponds to a service, due to Different services have different delay requirements, so their transmission time interval (TTI) is different.
  • TTI refers to the transmission time interval
  • TrCH transport channel
  • TTI transmission time interval
  • the scheduling information that TTI can be 10ms, 20ms, 40ms or 80ms] is simplified and modular (such as UE).
  • Thread 0, shown by UE Thread 1 and other threads generates new threads to execute, guarantee efficiency, and respond in real time.
  • System System Information
  • Measurement nt Mobility Management
  • Mobility Management Mobility Management
  • the design of the entire system separates the real-time processing from the condition processing to ensure that each part can operate normally.
  • System The bus is a system bus.
  • the simulation of a large number of terminal architectures based on the GPP-based 5G terminal common platform provided by the present invention is as shown in FIG.
  • the present invention further provides a GPP-based 5G terminal universal platform optimization system.
  • the GPP-based 5G terminal universal platform optimization system includes:
  • a priority module 10 configured to allocate different priorities to programs of different modules in the base station, wherein the control channel and the related program for controlling the processing flow have the highest priority; processing the different modules according to the order of priority from highest to lowest a task corresponding to the program; specifically, as described in step S100;
  • the task segmentation and distribution module 20 is configured to divide the task into a plurality of subtasks according to the attributes of each task, and assign the plurality of subtasks to different threads; specifically, as described in step S200;
  • the task execution module 30 is configured to allocate a time budget for each subtask, mark each subtask with a time stamp in the processing flow, and decide to continue execution according to the comparison result between the time stamp of each subtask and the allocated time budget. Or terminate early; specifically as described in step S300.
  • the GPP-based 5G terminal universal platform supports both static scheduling and dynamic scheduling.
  • the GPP-based 5G terminal universal platform optimization system further includes:
  • a pre-processing module for pre-processing tasks in a background thread For pre-processing tasks in a background thread.
  • the GPP-based 5G terminal universal platform optimization system further includes:
  • the monitoring module is configured to monitor the execution of the task by the task controller, and communicate with the scheduler to increase or decrease the tasks processed by the physical layer.
  • the priority module 10 is further configured to allocate priorities of tasks and threads.
  • the GPP-based 5G terminal universal platform optimization system uses an FPGA acceleration unit to build a heterogeneous computing platform, and accelerates the baseband signal through the FPGA to reduce the computational burden of the general-purpose processor;
  • the DMA technology directly accesses the read and write data of the memory of the general server platform to realize high-speed data interaction between the general-purpose processor and the acceleration unit; and performs parallel processing of the single-instruction multi-channel data stream by using the SIMD instruction supported by the general-purpose processor, wherein
  • the instruction set based software acceleration methods include bit level acceleration, symbol level acceleration, and/or sample level acceleration.
  • the (or mobile terminal) program may be completed by a computer (or mobile terminal) program, and the computer (or mobile terminal) program may be stored in a computer.
  • the (or mobile terminal) can be read into the storage medium, and the program, when executed, can include the flow of an embodiment of each of the above methods.
  • the storage medium may be a magnetic disk, an optical disk, a read only memory (ROM) or a random access memory (RAM).
  • the present invention provides a GPP-based 5G terminal universal platform optimization method and system, which assigns different priorities to programs of different modules in a base station, wherein the control channel and the related procedures of the control processing flow have the highest priority.
  • Levels processing tasks corresponding to the programs of the different modules in descending order of priority; dividing the tasks into multiple subtasks according to the attributes of each task, and assigning the plurality of subtasks to different threads;
  • Assign a time budget to each subtask mark each subtask with a timestamp in the process flow, and decide to continue or prematurely terminate based on the comparison between the timestamp of each subtask and the assigned time budget;
  • Many problems faced by open architecture based on open software-only architecture such as real-time processing of LTE and 5G protocol stack, HARQ feedback delay, implementation of multi-terminal simulation, real-time processing, HARQ feedback Delayed, in line with the strict requirements of high real-time and low latency in mobile communication, convenient for multi-terminal simulation implementation, large Optimization of the

Abstract

一种基于GPP的5G终端通用平台优化方法通过为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；在高优先级的任务处理完毕后再处理低优先级的任务；根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据每个子任务的时间戳与分配的时间预算之间的比对结果来决定继续执行或提前终止。

Description

一种基于GPP的5G终端通用平台优化方法及系统
本申请要求于2017年6月05日提交中国专利局、申请号为201710415240.1、发明名称为“一种基于GPP的5G终端通用平台优化方法及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及5G技术领域，特别涉及一种基于GPP的5G终端通用平台优化方法及系统。
 背景技术
目前全球关于5G的技术研究正如火如荼的开展，但是3GPP标准化也还在同步进行，迄今为止还没有一个定型的版本。多数从事5G研究的厂商一致认为，到2020年前后，5G才能逐步进入商用阶段，并在全球范围内走进人们的生活。基于5G协议的不确定性，对测试终端的软件架构设计提出了挑战。与传统的基于FPGA、专用芯片或DSP的系统不同，基于通用处理器实现的纯软件架构的开放式5G无线系统可以方便地使用各种成熟的软件工程方法，提高软件开发效率与开发质量；但基于开放式纯软件的开放式架构在软件实现上也面临诸多问题，比如LTE和5G协议栈的实时性处理，HARQ反馈时延，多终端模拟的实现等问题，带来了大大的不便。
 技术问题
本发明的目的在于提供一种基于GPP的5G终端通用平台优化方法及系统，旨在解决现有基于通用处理器的5G终端通用平台实时性不高，时延高的问题。
 技术解决方案
第一方面，本发明实施例提供一种基于GPP的5G终端通用平台优化方法，其中，包括：
获取基站中多个程序的优先级信息，其中控制信道及控制处理流程的相关程序具有最高优先级；
按照优先级从高到低的顺序处理所述多个程序对应的任务；
根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
为每个子任务分配一个时间预算，在处理流程中为所述每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算之间的比对结果决定继续执行或提前终止。
所述的基于GPP的5G终端通用平台优化方法，所述基于的5G终端通用平台同时支持静态调度和动态调度。
所述的基于GPP的5G终端通用平台优化方法，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：对所述任务和所述线程的优先级进行分配。
所述的基于GPP的5G终端通用平台优化方法，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：在后台线程中预先处理所述任务。
所述的基于GPP的5G终端通用平台优化方法，所述为每个子任务分配一个时间预算，在处理流程中为所述每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算之间的比对结果决定继续执行或提前终止的步骤还包括：通过任务控制器对所述任务的执行情况进行监控，并与调度器交互来对物理层处理的任务进行增加或减少。
所述的基于GPP的5G终端通用平台优化方法，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
第二方面，本发明实施例提供一种基于GPP的5G终端通用平台优化方法，其中，包括：
为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；在高优先级的任务处理完毕后再处理低优先级的任务；
根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算进行比较来决定继续执行或提前终止。
所述的基于GPP的5G终端通用平台优化方法，其中，所述基于GPP的5G终端通用平台同时支持静态调度和动态调度。
所述的基于GPP的5G终端通用平台优化方法，其中，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：
对任务和线程的优先级进行分配。
所述的基于GPP的5G终端通用平台优化方法，其中，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：
在后台线程中预先处理任务。
所述的基于GPP的5G终端通用平台优化方法，其中，所述为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算进行比较来决定继续执行或提前终止的步骤还包括：
通过任务控制器对任务的执行情况进行监控，并与调度器交互来对物理层处理的任务进行增加或减少。
所述的基于GPP的5G终端通用平台优化方法，其中，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
一种基于GPP的5G终端通用平台优化系统，其中，包括：
优先级模块，用于为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；按照优先级从高到低的顺序处理所述不同模块的程序对应的任务；
任务切分分配模块，用于根据每个任务的属性对任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
任务执行模块，用于为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据每个子任务的时间戳与分配的时间预算之间的比对结果来决定继续执行或提前终止。
所述的基于GPP的5G终端通用平台优化系统，其中，还包括：
预先处理模块，用于在后台线程中预先处理任务。
所述的基于GPP的5G终端通用平台优化系统，其中，还包括：
监控模块，用于通过任务控制器对任务的执行情况进行监控，并与调度器沟通来对物理层处理的任务进行增加或减少。
所述的基于GPP的5G终端通用平台优化系统，其中，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
 有益效果
本发明提供的基于GPP的5G终端通用平台优化方法及系统，实时性处理高，HARQ反馈时延低，符合移动通信中高实时性低延迟的严格要求，方便多终端模拟的实现，大大优化了现有通用平台，带来了极大的方便。
 附图说明
图1为本发明提供的基于GPP的5G终端通用平台优化方法的方法流程图。
图2为本发明提供的基于GPP的5G终端通用平台优化系统的结构框图。
图3为本发明提供的基于GPP的5G终端通用平台优化系统模拟大量终端的架构示意图。
 本发明的最佳实施方式
本发明提供一种基于GPP的5G终端通用平台优化方法及系统。为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
请参阅图1，本发明了提供一种基于GPP的5G终端通用平台优化方法，所述基于GPP的5G终端通用平台优化方法，包括：
S100、为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序最高优先级；按照优先级从高到低的顺序处理所述不同模块的程序对应的任务，也即在高优先级的任务处理完毕后再处理低优先级的任务；
S200、根据每个任务的属性对任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
S300、为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，将每个子任务的时间戳与分配的时间预算进行比较来决定继续执行或提前终止，也即根据每个子任务的时间戳与分配的时间预算之间的比对结果来决定继续执行或提前终止。
下面结合具体的实施例对上述步骤进行详细的描述。
在所述步骤S100中，给基站中不同模块的程序分配不同的优先级，分配给控制信道及控制处理流程的相关程序最高优先级；按照优先级从高到低的顺序处理所述不同模块的程序对应的任务。具体来说，本发明是基于GPP（General Purpose Processor）通用处理器平台的软件优化方法，由于移动通信中高实时性低延迟的严格要求，基于Intel通用处理器架构的基站的软件架构与传统的软件架构不同。例如，在LTE标准中，每个子帧占用l毫秒时间，这就要求基站端的软件程序必须在3毫秒之内完成上行信道的解码以及对UE（终端）发送ACK／NACK（应答/非应答）的回应。而5G NR每子帧占用的时间远小于1毫秒时间，HARQ（混合自动重传请求，Hybrid Automatic Repeat reQuest，是一种将前向纠错编码FEC和自动重传请求ARQ相结合而形成的技术）的反馈时间比LTE要求更严格。
此外，基于Intel通用处理器架构的基站也与传统的基于数字信号处理器的基站在软件架构上有所不同。在基于DSP的软件无线电实现中，数字信号处理的延迟几乎是固定的，因此可以严格控制程序处理的流程。而在基于Intel架构的终端模拟仪中，由于操作系统多核、多线程的架构，使得程序在处理同一个功能模块时可能会出现抖动。一种解决方案是绑定指定的任务到某一个核上，让这个核上只运行固定的程序。
如何充分利用处理器中的多个核心是基于英特尔通用处理器架构的基站软件架构设计中的一个挑战。其软件架构必须具有可扩展性，能够支持不同的处理器以及任意个数的核。例如，在终端程序配置完成后，其可能在一个双核处理器上处理一个扇区的流量，也可能在一个四核处理器上处理三个扇区的流量。
基于英特尔通用处理器架构的基站软件架构的设计原则是在满足协议中对实时性要求的基础上，最大化的利用多核处理器的处理能力。为此，给基站中不同模块的程序分配不同的优先级。为了保证通信协议的正常运转，控制信道以及控制处理流程的相关程序必须具有最高的优先级。在此基础上，取决于处理器的能力，再尽最大的努力去处理数据信道的相关运算。这就意味着一个双核处理器和一个四核处理器都能够支持20MHz TDD LTE协议的处理，但是四核处理器可以提供更高的数据吞吐量。优选地，为了优化，所述基于GPP的5G终端通用平台同时支持静态调度和动态调度。
在所述步骤S200中，根据每个任务的属性将对任务进行切分多个子任务，并将所述子任务分配给不同的线程。具体来说，为了达到优化的目的，本发明的基于GPP的5G终端通用平台，在执行任务时，根据每个任务的属性可以快速高效地对任务进行切分，并且灵活地将任务分配给不同的线程。
优选地，所述步骤S200还包括：S201、对任务和线程的优先级进行分配。具体来说，关于任务和线程的优先级分配。如前文所述，控制信道处理程序需要分配较高的优先级。但也有一些任务并没有严格的实时性要求，因此可以给其分配较低的优先级，在高优先级的任务处理完毕后再处理低优先级的任务。例如，PRACH（Physical Random Access Channel，物理随机接入信道）信道中的响应就可以在一个较长的时间周期内去处理。
在步骤S300中，为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，将每个子任务的时间戳与分配的时间预算进行比较来决定继续执行或提前终止。具体来说，步骤S200中对任务进行切分为多个子任务并进行分配，然后在步骤S300中给每个子任务分配时间预算并记录每个子任务的处理时间，若超过时间预算则继续执行，若没有超过时间预算则提前终止。在实际应用时，任务管理器需要给每个子任务分配一个时间预算。软件在处理流程中会给子任务标记时间戳，并与分配的时间预算进行比较，以此来决定是继续执行还是提前终止。软件会首先处理高优先级的任务，然后在尽最大的努力处理其他任务。例如，在LTE终端接收端的物理层，首先进行IFFT（快速傅里叶反变换）运算，然后逐一对控制信道PDCCH（Physical Downlink Control Channel，物理下行控制信道）进行解码，最后再根据剩余的时间对数据信道PDSCH（Physical Downlink Shared Channel，物理下行共享信道）进行处理。
优选地，所述步骤S200还包括：
S202、在后台线程中预先处理任务。具体来说，就是任务可以在后台线程中进行预先处理。很多发送端的任务可以被事先计算完成，例如，接下来20帧的参考信号都可以被预先计算出来存放在内存中。此外，PDSCH信道中对新数据的发送也没有非常严格的实时性要求，因此可以将调制和编码实现计算完毕，而由调度器来决定何时发送。这种预先处理的机制能够减少抖动的出现，并给优先级高或者时间有限的任务提供了更多的空间。
优选地，所述步骤S300还包括：
S301、通过任务控制器对任务的执行情况进行监控，并与调度器交互来对物理层处理的任务进行增加或减少。具体来说，任务控制器会对任务的执行情况进行监控，并通过与调度器的进行数据的交互来对物理层处理的任务进行增加或减少。例如，当有大量的物理层发送任务不能在分配的时间预算中完成时，调度器会给未来的上行处理分配较少的任务。因此，在特定平台上能够支持的吞吐量将取决于处理器的处理能力。此外，任务控制器还必须平衡不同核之间的负载。还需提供机制防止调度时产生的抖动。这是本发明的通用处理器平台中智能调度器和任务控制器的作用。
在实际应用时，本发明的基于GPP的5G终端通用平台，其物理层、MAC层和RLC层的跨层设计。这三层在LTE协议中是高度耦合的，虽然从功能上看具有一定的独立性，但是从任务的执行角度来看是耦合在一起的。传统的实现方式中不同的层使用独立的硬件结构，各层之间数据的搬移造成了多余的延迟和浪费。基于Intel通用处理器架构的终端可以很方便地实现跨层设计，因为整个协议栈都运行在一个处理器上。
优选地，为了优化，在硬件方面，所述基于GPP的5G终端通用平台，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
具体来说，为了实现上述流程步骤对应的技术效果，一方面采用FPGA加速单元搭建异构计算平台，通过FPGA对某些计算相对简单但计算量大的基带信号进行加速处理，减少通用处理器的计算负担；设计PCI-E接口，采用DMA技术对通用服务器平台的内存进行直接访问读写数据，实现通用处理器与加速单元之间的高速数据交互；前传链路射频与通用服务器基带处理接口采用成熟的CPRI接口进行连接；给出整个开放式 5G通用平台终端模拟仪的硬件架构，实现软件自定义的物理层尤其基带处理功能。另一方面，结合Intel处理器的架构特点，采用通用处理器支持的SIMD指令（MMX，SSE，SSE2，SSE3，SSE4，AVX，AVX2等），完成单指令多路数据流的并行处理。基于指令集的软件加速方法如下：1）比特级加速：查表 (Bit level-Look UP Tables，LUT ) ；其中，LUT是考量计算复杂度和空间复杂度后进行的折中操作，LUT操作替代常规的比特操作能够大大降低线上处理时延。而CRC校验与去校验，扰码与解扰码，速率匹配与去匹配等比特级运算可采用LUT方式加速。2）符号级加速：单指令多数据指令(Symbol level-Single instruction multiple data，SIMD)，其中，Intel CPU有专门多数据指令SIMD(Single instruction multiple data)指令集来加速符号级运算的信号处理。SIMD主要针对符号级数据重复执行相同的操作。SIMD一条指令能处理几个操作，运算成本（计算资源）小，充分利用比特带宽，带来的好处是显著提升CPU效率。而调制解调，预编码，MIMO，信道估计等符号级运算可采用SIMD方式。3）采样级加速：Intel综合性能原语(Sample level-Intel Integrated Performance Primitives，IPP)，其中，Intel开发的综合性能原语IPP，是一套跨平台，跨操作系统的软件函数库，能够实现信号处理，图像处理，多媒体，向量处理等操作。IPP无需编写汇编代码，很小的代码改变就可得到极大的改变。利用IPP实现FFT/IFFT运算，测试结果显示利用IPP完成线上处理，性能优势显著。优选地，FFT/IFFT可采用IPP方式加速。这三种加速方式可分别采用或混合采用。
请参阅图2，本发明提供的基于GPP的5G终端通用平台优化系统模拟大量终端的架构示意图，关于在通用平台上同时模拟大量终端的实现，基于Linux low latency版本的实时操作系统天然支持多线程技术，图2是通用平台模拟多终端的软件架构，将模拟终端每TTI[TTI是指传输时间间隔，每个传输信道(TrCH)对应一个业务，由于各种业务对时延的要求不同，所以其传输时间间隔(TTI)是不同的，TTI可以是10ms、20ms、40ms或80ms]都要处理的调度信息精简并模块化（如UE Thread 0, UE Thread 1等线程所示）生成新的线程去执行，保证效率，和实时响应。对于一些需要5G系统协作执行的公共处理，比如系统消息（System Information），各种测量上报（Measurement nt）,移动性管理（Mobility Management）等以条件触发的方式在新线程上执行（System Information, Measurement nt, Mobility Management等）, 整个系统的设计将实时处理和条件处理的部分分开,保证各部分能够正常运行。System bus是系统总线，本发明提供的基于GPP的5G终端通用平台的模拟大量终端架构如图2所示，在模拟终端开机接入过程会产生大量的信令交互,如果所有模拟终端同时运行势必会导致信令突发,突发的信息可能会得不到及时的处理,又可能会导致信令重传,如此必然导致系统陷入恶性循环,所以需要控制终端接入时的运行顺序,通过各模拟终端线程通信,使终端的接入有序进行,模拟终端一个一个的接入,等到所有的终端都执行完成,可以达到多用户同时在线的目的. 然后根据5G网络的测试要求,随机的或是顺序的指示模拟终端上报自己的数据。
基于上述实施例提供的基于GPP的5G终端通用平台优化方法，本发明还提供一种基于GPP的5G终端通用平台优化系统。请参阅图3，所述基于GPP的5G终端通用平台优化系统包括：
优先级模块10，用于为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；按照优先级从高到低的顺序处理所述不同模块的程序对应的任务；具体如步骤S100所述；
任务切分分配模块20，用于根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；具体如步骤S200所述；
任务执行模块30，用于为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据每个子任务的时间戳与分配的时间预算之间的比对结果来决定继续执行或提前终止；具体如步骤S300所述。
进一步地，所述基于GPP的5G终端通用平台同时支持静态调度和动态调度。
进一步地，所述的基于GPP的5G终端通用平台优化系统，还包括：
预先处理模块，用于在后台线程中预先处理任务。
进一步地，所述的基于GPP的5G终端通用平台优化系统，还包括：
监控模块，用于通过任务控制器对任务的执行情况进行监控，并与调度器沟通来对物理层处理的任务进行增加或减少。
进一步地，所述优先级模块10还用于对任务和线程的优先级进行分配。
进一步地，所述的基于GPP的5G终端通用平台优化系统，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
由于所述基于GPP的5G终端通用平台优化系统的具体原理和详细技术特征在上述基于GPP的5G终端通用平台优化方法实施例中已详细阐述，在此不再赘述。
上述功能模块的划分仅用以举例说明，在实际应用中，可以根据需要将上述功能分配由不同的功能模块来完成，即划分成不同的功能模块，来完成上述描述的全部或部分功能。
本领域普通技术人员可以理解上述实施例方法中的全部或部分流程，是可以通过计算机（或移动终端）程序来指令相关的硬件完成，所述的计算机（或移动终端）程序可存储于一计算机（或移动终端）可读取存储介质中，程序在执行时，可包括上述各方法的实施例的流程。其中的存储介质可以为磁碟、光盘、只读存储记忆体（ROM）或随机存储记忆体（RAM）等。
综上所述，本发明提供的一种基于GPP的5G终端通用平台优化方法及系统，通过为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；按照优先级从高到低的顺序处理所述不同模块的程序对应的任务；根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；为每个子任务分配一个时间预算，在处理流程中为每个子任务标记时间戳，根据将每个子任务的时间戳与分配的时间预算之间的比对结果来决定继续执行或提前终止；优化了基于开放式纯软件的开放式架构在软件实现上面临的诸多问题，比如LTE和5G协议栈的实时性处理，HARQ反馈时延，多终端模拟的实现等问题，实时性处理高，HARQ反馈时延低，符合移动通信中高实时性低延迟的严格要求，方便多终端模拟的实现，大大优化了现有通用平台，带来了极大的方便。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (16)

  1. 一种基于GPP的5G终端通用平台优化方法，其中，包括：
    获取基站中多个程序的优先级信息，其中控制信道及控制处理流程的相关程序具有最高优先级；
    按照优先级从高到低的顺序处理所述多个程序对应的任务；
    根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
    为每个子任务分配一个时间预算，在处理流程中为所述每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算之间的比对结果决定继续执行或提前终止。
  2. 根据权利要求1所述的基于GPP的5G终端通用平台优化方法，其中，所述基于的5G终端通用平台同时支持静态调度和动态调度。
  3. 根据权利要求1所述的基于GPP的5G终端通用平台优化方法，其中，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：
    对所述任务和所述线程的优先级进行分配。
  4. 根据权利要求1所述的基于GPP的5G终端通用平台优化方法，其中，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：
    在后台线程中预先处理所述任务。
  5. 根据权利要求1所述的基于GPP的5G终端通用平台优化方法，其中，所述为每个子任务分配一个时间预算，在处理流程中为所述每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算之间的比对结果决定继续执行或提前终止的步骤还包括：
    通过任务控制器对所述任务的执行情况进行监控，并与调度器交互来对物理层处理的任务进行增加或减少。
  6. 根据权利要求1所述的基于GPP的5G终端通用平台优化方法，其中，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
  7. 一种基于GPP的5G终端通用平台优化方法，其中，包括：
    为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；在高优先级的任务处理完毕后再处理低优先级的任务；
    根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
    为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算进行比较来决定继续执行或提前终止。
  8. 根据权利要求7所述的基于GPP的5G终端通用平台优化方法，其中，所述基于GPP的5G终端通用平台同时支持静态调度和动态调度。
  9. 根据权利要求7所述的基于GPP的5G终端通用平台优化方法，其中，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：
    对所述任务和所述线程的优先级进行分配。
  10. 根据权利要求7所述的基于GPP的5G终端通用平台优化方法，其中，所述根据每个任务的属性将任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程的步骤还包括：
    在后台线程中预先处理所述任务。
  11. 根据权利要求7所述的基于GPP的5G终端通用平台优化方法，其中，所述为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据所述每个子任务的时间戳与分配的时间预算进行比较来决定继续执行或提前终止的步骤还包括：
    通过任务控制器对所述任务的执行情况进行监控，并与调度器交互来对物理层处理的任务进行增加或减少。
  12. 根据权利要求1所述的基于GPP的5G终端通用平台优化方法，其中，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
  13. 一种基于GPP的5G终端通用平台优化系统，其中，包括：
    优先级模块，用于为基站中不同模块的程序分配不同的优先级，其中控制信道及控制处理流程的相关程序具有最高优先级；按照优先级从高到低的顺序处理所述不同模块的程序对应的任务；
    任务切分分配模块，用于根据每个任务的属性对任务进行切分成多个子任务，并将所述多个子任务分配给不同的线程；
    任务执行模块，用于为每个子任务分配一个时间预算，在处理流程中给每个子任务标记时间戳，根据每个子任务的时间戳与分配的时间预算之间的比对结果来决定继续执行或提前终止。
  14. 根据权利要求13所述的基于GPP的5G终端通用平台优化系统，其中，还包括：
    预先处理模块，用于在后台线程中预先处理所述任务。
  15. 根据权利要求13所述的基于GPP的5G终端通用平台优化系统，其中，还包括：
    监控模块，用于通过任务控制器对任务的执行情况进行监控，并与调度器沟通来对物理层处理的任务进行增加或减少。
  16. 根据权利要求13所述的基于GPP的5G终端通用平台优化系统，其中，采用FPGA加速单元搭建异构计算平台，通过FPGA对基带信号进行加速处理，以减少通用处理器的计算负担；通过PCI-E接口采用DMA技术对通用服务器平台的内存进行直接访问读写数据，以实现通用处理器与加速单元之间的高速数据交互；采用通用处理器支持的SIMD指令完成单指令多路数据流的并行处理，其中，基于指令集的软件加速方法包括比特级加速、符号级加速和/或采样级加速。
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